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-rw-r--r--arch/powerpc/mm/mem.c20
1 files changed, 10 insertions, 10 deletions
diff --git a/arch/powerpc/mm/mem.c b/arch/powerpc/mm/mem.c
index d1c0758c5611..c85eda63d2b3 100644
--- a/arch/powerpc/mm/mem.c
+++ b/arch/powerpc/mm/mem.c
@@ -490,19 +490,19 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long address,
490 !cpu_has_feature(CPU_FTR_NOEXECUTE) && 490 !cpu_has_feature(CPU_FTR_NOEXECUTE) &&
491 pfn_valid(pfn)) { 491 pfn_valid(pfn)) {
492 struct page *page = pfn_to_page(pfn); 492 struct page *page = pfn_to_page(pfn);
493#ifdef CONFIG_8xx
494 /* On 8xx, cache control instructions (particularly
495 * "dcbst" from flush_dcache_icache) fault as write
496 * operation if there is an unpopulated TLB entry
497 * for the address in question. To workaround that,
498 * we invalidate the TLB here, thus avoiding dcbst
499 * misbehaviour.
500 */
501 _tlbie(address);
502#endif
493 if (!PageReserved(page) 503 if (!PageReserved(page)
494 && !test_bit(PG_arch_1, &page->flags)) { 504 && !test_bit(PG_arch_1, &page->flags)) {
495 if (vma->vm_mm == current->active_mm) { 505 if (vma->vm_mm == current->active_mm) {
496#ifdef CONFIG_8xx
497 /* On 8xx, cache control instructions (particularly
498 * "dcbst" from flush_dcache_icache) fault as write
499 * operation if there is an unpopulated TLB entry
500 * for the address in question. To workaround that,
501 * we invalidate the TLB here, thus avoiding dcbst
502 * misbehaviour.
503 */
504 _tlbie(address);
505#endif
506 __flush_dcache_icache((void *) address); 506 __flush_dcache_icache((void *) address);
507 } else 507 } else
508 flush_dcache_icache_page(page); 508 flush_dcache_icache_page(page);