diff options
Diffstat (limited to 'arch/powerpc/mm/hash_native_64.c')
-rw-r--r-- | arch/powerpc/mm/hash_native_64.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/powerpc/mm/hash_native_64.c b/arch/powerpc/mm/hash_native_64.c index dfd764896db0..90039bc64119 100644 --- a/arch/powerpc/mm/hash_native_64.c +++ b/arch/powerpc/mm/hash_native_64.c | |||
@@ -37,7 +37,7 @@ | |||
37 | 37 | ||
38 | #define HPTE_LOCK_BIT 3 | 38 | #define HPTE_LOCK_BIT 3 |
39 | 39 | ||
40 | static DEFINE_RAW_SPINLOCK(native_tlbie_lock); | 40 | DEFINE_RAW_SPINLOCK(native_tlbie_lock); |
41 | 41 | ||
42 | static inline void __tlbie(unsigned long va, int psize, int ssize) | 42 | static inline void __tlbie(unsigned long va, int psize, int ssize) |
43 | { | 43 | { |
@@ -51,7 +51,7 @@ static inline void __tlbie(unsigned long va, int psize, int ssize) | |||
51 | va &= ~0xffful; | 51 | va &= ~0xffful; |
52 | va |= ssize << 8; | 52 | va |= ssize << 8; |
53 | asm volatile(ASM_FTR_IFCLR("tlbie %0,0", PPC_TLBIE(%1,%0), %2) | 53 | asm volatile(ASM_FTR_IFCLR("tlbie %0,0", PPC_TLBIE(%1,%0), %2) |
54 | : : "r" (va), "r"(0), "i" (CPU_FTR_HVMODE_206) | 54 | : : "r" (va), "r"(0), "i" (CPU_FTR_ARCH_206) |
55 | : "memory"); | 55 | : "memory"); |
56 | break; | 56 | break; |
57 | default: | 57 | default: |
@@ -61,7 +61,7 @@ static inline void __tlbie(unsigned long va, int psize, int ssize) | |||
61 | va |= ssize << 8; | 61 | va |= ssize << 8; |
62 | va |= 1; /* L */ | 62 | va |= 1; /* L */ |
63 | asm volatile(ASM_FTR_IFCLR("tlbie %0,1", PPC_TLBIE(%1,%0), %2) | 63 | asm volatile(ASM_FTR_IFCLR("tlbie %0,1", PPC_TLBIE(%1,%0), %2) |
64 | : : "r" (va), "r"(0), "i" (CPU_FTR_HVMODE_206) | 64 | : : "r" (va), "r"(0), "i" (CPU_FTR_ARCH_206) |
65 | : "memory"); | 65 | : "memory"); |
66 | break; | 66 | break; |
67 | } | 67 | } |