1 files changed, 140 insertions, 4 deletions

diff --git a/arch/powerpc/mm/44x_mmu.c b/arch/powerpc/mm/44x_mmu.c
index 3986264b0993..d8c6efb32bc6 100644
--- a/arch/powerpc/mm/44x_mmu.c
+++ b/arch/powerpc/mm/44x_mmu.c
@@ -38,7 +38,9 @@ unsigned int tlb_44x_index; /* = 0 */
 unsigned int tlb_44x_hwater = PPC44x_TLB_SIZE - 1 - PPC44x_EARLY_TLBS;
 int icache_44x_need_flush;
 
-static void __init ppc44x_update_tlb_hwater(void)
+unsigned long tlb_47x_boltmap[1024/8];
+
+static void __cpuinit ppc44x_update_tlb_hwater(void)
 {
         extern unsigned int tlb_44x_patch_hwater_D[];
         extern unsigned int tlb_44x_patch_hwater_I[];
@@ -59,7 +61,7 @@ static void __init ppc44x_update_tlb_hwater(void)
 }
 
 /*
- * "Pins" a 256MB TLB entry in AS0 for kernel lowmem
+ * "Pins" a 256MB TLB entry in AS0 for kernel lowmem for 44x type MMU
  */
 static void __init ppc44x_pin_tlb(unsigned int virt, unsigned int phys)
 {
@@ -67,12 +69,18 @@ static void __init ppc44x_pin_tlb(unsigned int virt, unsigned int phys)
 
         ppc44x_update_tlb_hwater();
 
+        mtspr(SPRN_MMUCR, 0);
+
         __asm__ __volatile__(
                 "tlbwe  %2,%3,%4\n"
                 "tlbwe  %1,%3,%5\n"
                 "tlbwe  %0,%3,%6\n"
         :
+#ifdef CONFIG_PPC47x
+        : "r" (PPC47x_TLB2_S_RWX),
+#else
         : "r" (PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_SX | PPC44x_TLB_G),
+#endif
           "r" (phys),
           "r" (virt | PPC44x_TLB_VALID | PPC44x_TLB_256M),
           "r" (entry),
@@ -81,8 +89,93 @@ static void __init ppc44x_pin_tlb(unsigned int virt, unsigned int phys)
           "i" (PPC44x_TLB_ATTRIB));
 }
 
+static int __init ppc47x_find_free_bolted(void)
+{
+        unsigned int mmube0 = mfspr(SPRN_MMUBE0);
+        unsigned int mmube1 = mfspr(SPRN_MMUBE1);
+
+        if (!(mmube0 & MMUBE0_VBE0))
+                return 0;
+        if (!(mmube0 & MMUBE0_VBE1))
+                return 1;
+        if (!(mmube0 & MMUBE0_VBE2))
+                return 2;
+        if (!(mmube1 & MMUBE1_VBE3))
+                return 3;
+        if (!(mmube1 & MMUBE1_VBE4))
+                return 4;
+        if (!(mmube1 & MMUBE1_VBE5))
+                return 5;
+        return -1;
+}
+
+static void __init ppc47x_update_boltmap(void)
+{
+        unsigned int mmube0 = mfspr(SPRN_MMUBE0);
+        unsigned int mmube1 = mfspr(SPRN_MMUBE1);
+
+        if (mmube0 & MMUBE0_VBE0)
+                __set_bit((mmube0 >> MMUBE0_IBE0_SHIFT) & 0xff,
+                          tlb_47x_boltmap);
+        if (mmube0 & MMUBE0_VBE1)
+                __set_bit((mmube0 >> MMUBE0_IBE1_SHIFT) & 0xff,
+                          tlb_47x_boltmap);
+        if (mmube0 & MMUBE0_VBE2)
+                __set_bit((mmube0 >> MMUBE0_IBE2_SHIFT) & 0xff,
+                          tlb_47x_boltmap);
+        if (mmube1 & MMUBE1_VBE3)
+                __set_bit((mmube1 >> MMUBE1_IBE3_SHIFT) & 0xff,
+                          tlb_47x_boltmap);
+        if (mmube1 & MMUBE1_VBE4)
+                __set_bit((mmube1 >> MMUBE1_IBE4_SHIFT) & 0xff,
+                          tlb_47x_boltmap);
+        if (mmube1 & MMUBE1_VBE5)
+                __set_bit((mmube1 >> MMUBE1_IBE5_SHIFT) & 0xff,
+                          tlb_47x_boltmap);
+}
+
+/*
+ * "Pins" a 256MB TLB entry in AS0 for kernel lowmem for 47x type MMU
+ */
+static void __cpuinit ppc47x_pin_tlb(unsigned int virt, unsigned int phys)
+{
+        unsigned int rA;
+        int bolted;
+
+        /* Base rA is HW way select, way 0, bolted bit set */
+        rA = 0x88000000;
+
+        /* Look for a bolted entry slot */
+        bolted = ppc47x_find_free_bolted();
+        BUG_ON(bolted < 0);
+
+        /* Insert bolted slot number */
+        rA |= bolted << 24;
+
+        pr_debug("256M TLB entry for 0x%08x->0x%08x in bolt slot %d\n",
+                 virt, phys, bolted);
+
+        mtspr(SPRN_MMUCR, 0);
+
+        __asm__ __volatile__(
+                "tlbwe  %2,%3,0\n"
+                "tlbwe  %1,%3,1\n"
+                "tlbwe  %0,%3,2\n"
+                :
+                : "r" (PPC47x_TLB2_SW | PPC47x_TLB2_SR |
+                       PPC47x_TLB2_SX
+#ifdef CONFIG_SMP
+                       | PPC47x_TLB2_M
+#endif
+                       ),
+                  "r" (phys),
+                  "r" (virt | PPC47x_TLB0_VALID | PPC47x_TLB0_256M),
+                  "r" (rA));
+}
+
 void __init MMU_init_hw(void)
 {
+        /* This is not useful on 47x but won't hurt either */
         ppc44x_update_tlb_hwater();
 
         flush_instruction_cache();
@@ -95,8 +188,51 @@ unsigned long __init mmu_mapin_ram(unsigned long top)
         /* Pin in enough TLBs to cover any lowmem not covered by the
          * initial 256M mapping established in head_44x.S */
         for (addr = PPC_PIN_SIZE; addr < lowmem_end_addr;
-             addr += PPC_PIN_SIZE)
-                ppc44x_pin_tlb(addr + PAGE_OFFSET, addr);
+             addr += PPC_PIN_SIZE) {
+                if (mmu_has_feature(MMU_FTR_TYPE_47x))
+                        ppc47x_pin_tlb(addr + PAGE_OFFSET, addr);
+                else
+                        ppc44x_pin_tlb(addr + PAGE_OFFSET, addr);
+        }
+        if (mmu_has_feature(MMU_FTR_TYPE_47x)) {
+                ppc47x_update_boltmap();
 
+#ifdef DEBUG
+                {
+                        int i;
+
+                        printk(KERN_DEBUG "bolted entries: ");
+                        for (i = 0; i < 255; i++) {
+                                if (test_bit(i, tlb_47x_boltmap))
+                                        printk("%d ", i);
+                        }
+                        printk("\n");
+                }
+#endif /* DEBUG */
+        }
         return total_lowmem;
 }
+
+#ifdef CONFIG_SMP
+void __cpuinit mmu_init_secondary(int cpu)
+{
+        unsigned long addr;
+
+        /* Pin in enough TLBs to cover any lowmem not covered by the
+         * initial 256M mapping established in head_44x.S
+         *
+         * WARNING: This is called with only the first 256M of the
+         * linear mapping in the TLB and we can't take faults yet
+         * so beware of what this code uses. It runs off a temporary
+         * stack. current (r2) isn't initialized, smp_processor_id()
+         * will not work, current thread info isn't accessible, ...
+         */
+        for (addr = PPC_PIN_SIZE; addr < lowmem_end_addr;
+             addr += PPC_PIN_SIZE) {
+                if (mmu_has_feature(MMU_FTR_TYPE_47x))
+                        ppc47x_pin_tlb(addr + PAGE_OFFSET, addr);
+                else
+                        ppc44x_pin_tlb(addr + PAGE_OFFSET, addr);
+        }
+}
+#endif /* CONFIG_SMP */