diff options
Diffstat (limited to 'arch/powerpc/kvm')
-rw-r--r-- | arch/powerpc/kvm/book3s_hv.c | 147 |
1 files changed, 125 insertions, 22 deletions
diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c index e0a535cdf07b..a6d8f018180d 100644 --- a/arch/powerpc/kvm/book3s_hv.c +++ b/arch/powerpc/kvm/book3s_hv.c | |||
@@ -879,17 +879,6 @@ static int kvmppc_get_one_reg_hv(struct kvm_vcpu *vcpu, u64 id, | |||
879 | case KVM_REG_PPC_IAMR: | 879 | case KVM_REG_PPC_IAMR: |
880 | *val = get_reg_val(id, vcpu->arch.iamr); | 880 | *val = get_reg_val(id, vcpu->arch.iamr); |
881 | break; | 881 | break; |
882 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | ||
883 | case KVM_REG_PPC_TFHAR: | ||
884 | *val = get_reg_val(id, vcpu->arch.tfhar); | ||
885 | break; | ||
886 | case KVM_REG_PPC_TFIAR: | ||
887 | *val = get_reg_val(id, vcpu->arch.tfiar); | ||
888 | break; | ||
889 | case KVM_REG_PPC_TEXASR: | ||
890 | *val = get_reg_val(id, vcpu->arch.texasr); | ||
891 | break; | ||
892 | #endif | ||
893 | case KVM_REG_PPC_FSCR: | 882 | case KVM_REG_PPC_FSCR: |
894 | *val = get_reg_val(id, vcpu->arch.fscr); | 883 | *val = get_reg_val(id, vcpu->arch.fscr); |
895 | break; | 884 | break; |
@@ -970,6 +959,69 @@ static int kvmppc_get_one_reg_hv(struct kvm_vcpu *vcpu, u64 id, | |||
970 | case KVM_REG_PPC_PPR: | 959 | case KVM_REG_PPC_PPR: |
971 | *val = get_reg_val(id, vcpu->arch.ppr); | 960 | *val = get_reg_val(id, vcpu->arch.ppr); |
972 | break; | 961 | break; |
962 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | ||
963 | case KVM_REG_PPC_TFHAR: | ||
964 | *val = get_reg_val(id, vcpu->arch.tfhar); | ||
965 | break; | ||
966 | case KVM_REG_PPC_TFIAR: | ||
967 | *val = get_reg_val(id, vcpu->arch.tfiar); | ||
968 | break; | ||
969 | case KVM_REG_PPC_TEXASR: | ||
970 | *val = get_reg_val(id, vcpu->arch.texasr); | ||
971 | break; | ||
972 | case KVM_REG_PPC_TM_GPR0 ... KVM_REG_PPC_TM_GPR31: | ||
973 | i = id - KVM_REG_PPC_TM_GPR0; | ||
974 | *val = get_reg_val(id, vcpu->arch.gpr_tm[i]); | ||
975 | break; | ||
976 | case KVM_REG_PPC_TM_VSR0 ... KVM_REG_PPC_TM_VSR63: | ||
977 | { | ||
978 | int j; | ||
979 | i = id - KVM_REG_PPC_TM_VSR0; | ||
980 | if (i < 32) | ||
981 | for (j = 0; j < TS_FPRWIDTH; j++) | ||
982 | val->vsxval[j] = vcpu->arch.fp_tm.fpr[i][j]; | ||
983 | else { | ||
984 | if (cpu_has_feature(CPU_FTR_ALTIVEC)) | ||
985 | val->vval = vcpu->arch.vr_tm.vr[i-32]; | ||
986 | else | ||
987 | r = -ENXIO; | ||
988 | } | ||
989 | break; | ||
990 | } | ||
991 | case KVM_REG_PPC_TM_CR: | ||
992 | *val = get_reg_val(id, vcpu->arch.cr_tm); | ||
993 | break; | ||
994 | case KVM_REG_PPC_TM_LR: | ||
995 | *val = get_reg_val(id, vcpu->arch.lr_tm); | ||
996 | break; | ||
997 | case KVM_REG_PPC_TM_CTR: | ||
998 | *val = get_reg_val(id, vcpu->arch.ctr_tm); | ||
999 | break; | ||
1000 | case KVM_REG_PPC_TM_FPSCR: | ||
1001 | *val = get_reg_val(id, vcpu->arch.fp_tm.fpscr); | ||
1002 | break; | ||
1003 | case KVM_REG_PPC_TM_AMR: | ||
1004 | *val = get_reg_val(id, vcpu->arch.amr_tm); | ||
1005 | break; | ||
1006 | case KVM_REG_PPC_TM_PPR: | ||
1007 | *val = get_reg_val(id, vcpu->arch.ppr_tm); | ||
1008 | break; | ||
1009 | case KVM_REG_PPC_TM_VRSAVE: | ||
1010 | *val = get_reg_val(id, vcpu->arch.vrsave_tm); | ||
1011 | break; | ||
1012 | case KVM_REG_PPC_TM_VSCR: | ||
1013 | if (cpu_has_feature(CPU_FTR_ALTIVEC)) | ||
1014 | *val = get_reg_val(id, vcpu->arch.vr_tm.vscr.u[3]); | ||
1015 | else | ||
1016 | r = -ENXIO; | ||
1017 | break; | ||
1018 | case KVM_REG_PPC_TM_DSCR: | ||
1019 | *val = get_reg_val(id, vcpu->arch.dscr_tm); | ||
1020 | break; | ||
1021 | case KVM_REG_PPC_TM_TAR: | ||
1022 | *val = get_reg_val(id, vcpu->arch.tar_tm); | ||
1023 | break; | ||
1024 | #endif | ||
973 | case KVM_REG_PPC_ARCH_COMPAT: | 1025 | case KVM_REG_PPC_ARCH_COMPAT: |
974 | *val = get_reg_val(id, vcpu->arch.vcore->arch_compat); | 1026 | *val = get_reg_val(id, vcpu->arch.vcore->arch_compat); |
975 | break; | 1027 | break; |
@@ -1039,17 +1091,6 @@ static int kvmppc_set_one_reg_hv(struct kvm_vcpu *vcpu, u64 id, | |||
1039 | case KVM_REG_PPC_IAMR: | 1091 | case KVM_REG_PPC_IAMR: |
1040 | vcpu->arch.iamr = set_reg_val(id, *val); | 1092 | vcpu->arch.iamr = set_reg_val(id, *val); |
1041 | break; | 1093 | break; |
1042 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | ||
1043 | case KVM_REG_PPC_TFHAR: | ||
1044 | vcpu->arch.tfhar = set_reg_val(id, *val); | ||
1045 | break; | ||
1046 | case KVM_REG_PPC_TFIAR: | ||
1047 | vcpu->arch.tfiar = set_reg_val(id, *val); | ||
1048 | break; | ||
1049 | case KVM_REG_PPC_TEXASR: | ||
1050 | vcpu->arch.texasr = set_reg_val(id, *val); | ||
1051 | break; | ||
1052 | #endif | ||
1053 | case KVM_REG_PPC_FSCR: | 1094 | case KVM_REG_PPC_FSCR: |
1054 | vcpu->arch.fscr = set_reg_val(id, *val); | 1095 | vcpu->arch.fscr = set_reg_val(id, *val); |
1055 | break; | 1096 | break; |
@@ -1144,6 +1185,68 @@ static int kvmppc_set_one_reg_hv(struct kvm_vcpu *vcpu, u64 id, | |||
1144 | case KVM_REG_PPC_PPR: | 1185 | case KVM_REG_PPC_PPR: |
1145 | vcpu->arch.ppr = set_reg_val(id, *val); | 1186 | vcpu->arch.ppr = set_reg_val(id, *val); |
1146 | break; | 1187 | break; |
1188 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | ||
1189 | case KVM_REG_PPC_TFHAR: | ||
1190 | vcpu->arch.tfhar = set_reg_val(id, *val); | ||
1191 | break; | ||
1192 | case KVM_REG_PPC_TFIAR: | ||
1193 | vcpu->arch.tfiar = set_reg_val(id, *val); | ||
1194 | break; | ||
1195 | case KVM_REG_PPC_TEXASR: | ||
1196 | vcpu->arch.texasr = set_reg_val(id, *val); | ||
1197 | break; | ||
1198 | case KVM_REG_PPC_TM_GPR0 ... KVM_REG_PPC_TM_GPR31: | ||
1199 | i = id - KVM_REG_PPC_TM_GPR0; | ||
1200 | vcpu->arch.gpr_tm[i] = set_reg_val(id, *val); | ||
1201 | break; | ||
1202 | case KVM_REG_PPC_TM_VSR0 ... KVM_REG_PPC_TM_VSR63: | ||
1203 | { | ||
1204 | int j; | ||
1205 | i = id - KVM_REG_PPC_TM_VSR0; | ||
1206 | if (i < 32) | ||
1207 | for (j = 0; j < TS_FPRWIDTH; j++) | ||
1208 | vcpu->arch.fp_tm.fpr[i][j] = val->vsxval[j]; | ||
1209 | else | ||
1210 | if (cpu_has_feature(CPU_FTR_ALTIVEC)) | ||
1211 | vcpu->arch.vr_tm.vr[i-32] = val->vval; | ||
1212 | else | ||
1213 | r = -ENXIO; | ||
1214 | break; | ||
1215 | } | ||
1216 | case KVM_REG_PPC_TM_CR: | ||
1217 | vcpu->arch.cr_tm = set_reg_val(id, *val); | ||
1218 | break; | ||
1219 | case KVM_REG_PPC_TM_LR: | ||
1220 | vcpu->arch.lr_tm = set_reg_val(id, *val); | ||
1221 | break; | ||
1222 | case KVM_REG_PPC_TM_CTR: | ||
1223 | vcpu->arch.ctr_tm = set_reg_val(id, *val); | ||
1224 | break; | ||
1225 | case KVM_REG_PPC_TM_FPSCR: | ||
1226 | vcpu->arch.fp_tm.fpscr = set_reg_val(id, *val); | ||
1227 | break; | ||
1228 | case KVM_REG_PPC_TM_AMR: | ||
1229 | vcpu->arch.amr_tm = set_reg_val(id, *val); | ||
1230 | break; | ||
1231 | case KVM_REG_PPC_TM_PPR: | ||
1232 | vcpu->arch.ppr_tm = set_reg_val(id, *val); | ||
1233 | break; | ||
1234 | case KVM_REG_PPC_TM_VRSAVE: | ||
1235 | vcpu->arch.vrsave_tm = set_reg_val(id, *val); | ||
1236 | break; | ||
1237 | case KVM_REG_PPC_TM_VSCR: | ||
1238 | if (cpu_has_feature(CPU_FTR_ALTIVEC)) | ||
1239 | vcpu->arch.vr.vscr.u[3] = set_reg_val(id, *val); | ||
1240 | else | ||
1241 | r = - ENXIO; | ||
1242 | break; | ||
1243 | case KVM_REG_PPC_TM_DSCR: | ||
1244 | vcpu->arch.dscr_tm = set_reg_val(id, *val); | ||
1245 | break; | ||
1246 | case KVM_REG_PPC_TM_TAR: | ||
1247 | vcpu->arch.tar_tm = set_reg_val(id, *val); | ||
1248 | break; | ||
1249 | #endif | ||
1147 | case KVM_REG_PPC_ARCH_COMPAT: | 1250 | case KVM_REG_PPC_ARCH_COMPAT: |
1148 | r = kvmppc_set_arch_compat(vcpu, set_reg_val(id, *val)); | 1251 | r = kvmppc_set_arch_compat(vcpu, set_reg_val(id, *val)); |
1149 | break; | 1252 | break; |