diff options
Diffstat (limited to 'arch/powerpc/kvm/booke_interrupts.S')
-rw-r--r-- | arch/powerpc/kvm/booke_interrupts.S | 51 |
1 files changed, 34 insertions, 17 deletions
diff --git a/arch/powerpc/kvm/booke_interrupts.S b/arch/powerpc/kvm/booke_interrupts.S index 3e88dfa1dbe4..564ea32ecbac 100644 --- a/arch/powerpc/kvm/booke_interrupts.S +++ b/arch/powerpc/kvm/booke_interrupts.S | |||
@@ -335,7 +335,7 @@ lightweight_exit: | |||
335 | lwz r3, VCPU_PID(r4) | 335 | lwz r3, VCPU_PID(r4) |
336 | mtspr SPRN_PID, r3 | 336 | mtspr SPRN_PID, r3 |
337 | 337 | ||
338 | /* Prevent all TLB updates. */ | 338 | /* Prevent all asynchronous TLB updates. */ |
339 | mfmsr r5 | 339 | mfmsr r5 |
340 | lis r6, (MSR_EE|MSR_CE|MSR_ME|MSR_DE)@h | 340 | lis r6, (MSR_EE|MSR_CE|MSR_ME|MSR_DE)@h |
341 | ori r6, r6, (MSR_EE|MSR_CE|MSR_ME|MSR_DE)@l | 341 | ori r6, r6, (MSR_EE|MSR_CE|MSR_ME|MSR_DE)@l |
@@ -344,28 +344,45 @@ lightweight_exit: | |||
344 | 344 | ||
345 | /* Load the guest mappings, leaving the host's "pinned" kernel mappings | 345 | /* Load the guest mappings, leaving the host's "pinned" kernel mappings |
346 | * in place. */ | 346 | * in place. */ |
347 | /* XXX optimization: load only modified guest entries. */ | ||
348 | mfspr r10, SPRN_MMUCR /* Save host MMUCR. */ | 347 | mfspr r10, SPRN_MMUCR /* Save host MMUCR. */ |
349 | lis r8, tlb_44x_hwater@ha | 348 | li r5, PPC44x_TLB_SIZE |
350 | lwz r8, tlb_44x_hwater@l(r8) | 349 | lis r5, tlb_44x_hwater@ha |
351 | addi r9, r4, VCPU_SHADOW_TLB - 4 | 350 | lwz r5, tlb_44x_hwater@l(r5) |
352 | li r6, 0 | 351 | mtctr r5 |
352 | addi r9, r4, VCPU_SHADOW_TLB | ||
353 | addi r5, r4, VCPU_SHADOW_MOD | ||
354 | li r3, 0 | ||
353 | 1: | 355 | 1: |
356 | lbzx r7, r3, r5 | ||
357 | cmpwi r7, 0 | ||
358 | beq 3f | ||
359 | |||
354 | /* Load guest entry. */ | 360 | /* Load guest entry. */ |
355 | lwzu r7, 4(r9) | 361 | mulli r11, r3, TLBE_BYTES |
362 | add r11, r11, r9 | ||
363 | lwz r7, 0(r11) | ||
356 | mtspr SPRN_MMUCR, r7 | 364 | mtspr SPRN_MMUCR, r7 |
357 | lwzu r7, 4(r9) | 365 | lwz r7, 4(r11) |
358 | tlbwe r7, r6, PPC44x_TLB_PAGEID | 366 | tlbwe r7, r3, PPC44x_TLB_PAGEID |
359 | lwzu r7, 4(r9) | 367 | lwz r7, 8(r11) |
360 | tlbwe r7, r6, PPC44x_TLB_XLAT | 368 | tlbwe r7, r3, PPC44x_TLB_XLAT |
361 | lwzu r7, 4(r9) | 369 | lwz r7, 12(r11) |
362 | tlbwe r7, r6, PPC44x_TLB_ATTRIB | 370 | tlbwe r7, r3, PPC44x_TLB_ATTRIB |
363 | /* Increment index. */ | 371 | 3: |
364 | addi r6, r6, 1 | 372 | addi r3, r3, 1 /* Increment index. */ |
365 | cmpw r6, r8 | 373 | bdnz 1b |
366 | blt 1b | 374 | |
367 | mtspr SPRN_MMUCR, r10 /* Restore host MMUCR. */ | 375 | mtspr SPRN_MMUCR, r10 /* Restore host MMUCR. */ |
368 | 376 | ||
377 | /* Clear bitmap of modified TLB entries */ | ||
378 | li r5, PPC44x_TLB_SIZE>>2 | ||
379 | mtctr r5 | ||
380 | addi r5, r4, VCPU_SHADOW_MOD - 4 | ||
381 | li r6, 0 | ||
382 | 1: | ||
383 | stwu r6, 4(r5) | ||
384 | bdnz 1b | ||
385 | |||
369 | iccci 0, 0 /* XXX hack */ | 386 | iccci 0, 0 /* XXX hack */ |
370 | 387 | ||
371 | /* Load some guest volatiles. */ | 388 | /* Load some guest volatiles. */ |