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-rw-r--r--arch/powerpc/kernel/Makefile7
-rw-r--r--arch/powerpc/kernel/cputable.c2
-rw-r--r--arch/powerpc/kernel/e500-pmu.c129
-rw-r--r--arch/powerpc/kernel/head_64.S17
-rw-r--r--arch/powerpc/kernel/head_fsl_booke.S7
-rw-r--r--arch/powerpc/kernel/iommu.c7
-rw-r--r--arch/powerpc/kernel/legacy_serial.c2
-rw-r--r--arch/powerpc/kernel/paca.c93
-rw-r--r--arch/powerpc/kernel/pci-common.c15
-rw-r--r--arch/powerpc/kernel/perf_event.c29
-rw-r--r--arch/powerpc/kernel/perf_event_fsl_emb.c654
-rw-r--r--arch/powerpc/kernel/prom.c3
-rw-r--r--arch/powerpc/kernel/ptrace.c12
-rw-r--r--arch/powerpc/kernel/setup-common.c3
-rw-r--r--arch/powerpc/kernel/setup_32.c6
-rw-r--r--arch/powerpc/kernel/setup_64.c18
-rw-r--r--arch/powerpc/kernel/syscalls.c164
17 files changed, 923 insertions, 245 deletions
diff --git a/arch/powerpc/kernel/Makefile b/arch/powerpc/kernel/Makefile
index c002b0410219..877326320e74 100644
--- a/arch/powerpc/kernel/Makefile
+++ b/arch/powerpc/kernel/Makefile
@@ -98,11 +98,16 @@ obj64-$(CONFIG_AUDIT) += compat_audit.o
98 98
99obj-$(CONFIG_DYNAMIC_FTRACE) += ftrace.o 99obj-$(CONFIG_DYNAMIC_FTRACE) += ftrace.o
100obj-$(CONFIG_FUNCTION_GRAPH_TRACER) += ftrace.o 100obj-$(CONFIG_FUNCTION_GRAPH_TRACER) += ftrace.o
101obj-$(CONFIG_PPC_PERF_CTRS) += perf_event.o perf_callchain.o 101obj-$(CONFIG_PERF_EVENTS) += perf_callchain.o
102
103obj-$(CONFIG_PPC_PERF_CTRS) += perf_event.o
102obj64-$(CONFIG_PPC_PERF_CTRS) += power4-pmu.o ppc970-pmu.o power5-pmu.o \ 104obj64-$(CONFIG_PPC_PERF_CTRS) += power4-pmu.o ppc970-pmu.o power5-pmu.o \
103 power5+-pmu.o power6-pmu.o power7-pmu.o 105 power5+-pmu.o power6-pmu.o power7-pmu.o
104obj32-$(CONFIG_PPC_PERF_CTRS) += mpc7450-pmu.o 106obj32-$(CONFIG_PPC_PERF_CTRS) += mpc7450-pmu.o
105 107
108obj-$(CONFIG_FSL_EMB_PERF_EVENT) += perf_event_fsl_emb.o
109obj-$(CONFIG_FSL_EMB_PERF_EVENT_E500) += e500-pmu.o
110
106obj-$(CONFIG_8XX_MINIMAL_FPEMU) += softemu8xx.o 111obj-$(CONFIG_8XX_MINIMAL_FPEMU) += softemu8xx.o
107 112
108ifneq ($(CONFIG_PPC_INDIRECT_IO),y) 113ifneq ($(CONFIG_PPC_INDIRECT_IO),y)
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index 2fc82bac3bbc..8af4949434b2 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -1808,7 +1808,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
1808 .icache_bsize = 64, 1808 .icache_bsize = 64,
1809 .dcache_bsize = 64, 1809 .dcache_bsize = 64,
1810 .num_pmcs = 4, 1810 .num_pmcs = 4,
1811 .oprofile_cpu_type = "ppc/e500", /* xxx - galak, e500mc? */ 1811 .oprofile_cpu_type = "ppc/e500mc",
1812 .oprofile_type = PPC_OPROFILE_FSL_EMB, 1812 .oprofile_type = PPC_OPROFILE_FSL_EMB,
1813 .cpu_setup = __setup_cpu_e500mc, 1813 .cpu_setup = __setup_cpu_e500mc,
1814 .machine_check = machine_check_e500, 1814 .machine_check = machine_check_e500,
diff --git a/arch/powerpc/kernel/e500-pmu.c b/arch/powerpc/kernel/e500-pmu.c
new file mode 100644
index 000000000000..7c07de0d8943
--- /dev/null
+++ b/arch/powerpc/kernel/e500-pmu.c
@@ -0,0 +1,129 @@
1/*
2 * Performance counter support for e500 family processors.
3 *
4 * Copyright 2008-2009 Paul Mackerras, IBM Corporation.
5 * Copyright 2010 Freescale Semiconductor, Inc.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 */
12#include <linux/string.h>
13#include <linux/perf_event.h>
14#include <asm/reg.h>
15#include <asm/cputable.h>
16
17/*
18 * Map of generic hardware event types to hardware events
19 * Zero if unsupported
20 */
21static int e500_generic_events[] = {
22 [PERF_COUNT_HW_CPU_CYCLES] = 1,
23 [PERF_COUNT_HW_INSTRUCTIONS] = 2,
24 [PERF_COUNT_HW_CACHE_MISSES] = 41, /* Data L1 cache reloads */
25 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 12,
26 [PERF_COUNT_HW_BRANCH_MISSES] = 15,
27};
28
29#define C(x) PERF_COUNT_HW_CACHE_##x
30
31/*
32 * Table of generalized cache-related events.
33 * 0 means not supported, -1 means nonsensical, other values
34 * are event codes.
35 */
36static int e500_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
37 /*
38 * D-cache misses are not split into read/write/prefetch;
39 * use raw event 41.
40 */
41 [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
42 [C(OP_READ)] = { 27, 0 },
43 [C(OP_WRITE)] = { 28, 0 },
44 [C(OP_PREFETCH)] = { 29, 0 },
45 },
46 [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */
47 [C(OP_READ)] = { 2, 60 },
48 [C(OP_WRITE)] = { -1, -1 },
49 [C(OP_PREFETCH)] = { 0, 0 },
50 },
51 /*
52 * Assuming LL means L2, it's not a good match for this model.
53 * It allocates only on L1 castout or explicit prefetch, and
54 * does not have separate read/write events (but it does have
55 * separate instruction/data events).
56 */
57 [C(LL)] = { /* RESULT_ACCESS RESULT_MISS */
58 [C(OP_READ)] = { 0, 0 },
59 [C(OP_WRITE)] = { 0, 0 },
60 [C(OP_PREFETCH)] = { 0, 0 },
61 },
62 /*
63 * There are data/instruction MMU misses, but that's a miss on
64 * the chip's internal level-one TLB which is probably not
65 * what the user wants. Instead, unified level-two TLB misses
66 * are reported here.
67 */
68 [C(DTLB)] = { /* RESULT_ACCESS RESULT_MISS */
69 [C(OP_READ)] = { 26, 66 },
70 [C(OP_WRITE)] = { -1, -1 },
71 [C(OP_PREFETCH)] = { -1, -1 },
72 },
73 [C(BPU)] = { /* RESULT_ACCESS RESULT_MISS */
74 [C(OP_READ)] = { 12, 15 },
75 [C(OP_WRITE)] = { -1, -1 },
76 [C(OP_PREFETCH)] = { -1, -1 },
77 },
78};
79
80static int num_events = 128;
81
82/* Upper half of event id is PMLCb, for threshold events */
83static u64 e500_xlate_event(u64 event_id)
84{
85 u32 event_low = (u32)event_id;
86 u64 ret;
87
88 if (event_low >= num_events)
89 return 0;
90
91 ret = FSL_EMB_EVENT_VALID;
92
93 if (event_low >= 76 && event_low <= 81) {
94 ret |= FSL_EMB_EVENT_RESTRICTED;
95 ret |= event_id &
96 (FSL_EMB_EVENT_THRESHMUL | FSL_EMB_EVENT_THRESH);
97 } else if (event_id &
98 (FSL_EMB_EVENT_THRESHMUL | FSL_EMB_EVENT_THRESH)) {
99 /* Threshold requested on non-threshold event */
100 return 0;
101 }
102
103 return ret;
104}
105
106static struct fsl_emb_pmu e500_pmu = {
107 .name = "e500 family",
108 .n_counter = 4,
109 .n_restricted = 2,
110 .xlate_event = e500_xlate_event,
111 .n_generic = ARRAY_SIZE(e500_generic_events),
112 .generic_events = e500_generic_events,
113 .cache_events = &e500_cache_events,
114};
115
116static int init_e500_pmu(void)
117{
118 if (!cur_cpu_spec->oprofile_cpu_type)
119 return -ENODEV;
120
121 if (!strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc/e500mc"))
122 num_events = 256;
123 else if (strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc/e500"))
124 return -ENODEV;
125
126 return register_fsl_emb_pmu(&e500_pmu);
127}
128
129arch_initcall(init_e500_pmu);
diff --git a/arch/powerpc/kernel/head_64.S b/arch/powerpc/kernel/head_64.S
index 925807488022..bed9a29ee383 100644
--- a/arch/powerpc/kernel/head_64.S
+++ b/arch/powerpc/kernel/head_64.S
@@ -219,7 +219,8 @@ generic_secondary_common_init:
219 * physical cpu id in r24, we need to search the pacas to find 219 * physical cpu id in r24, we need to search the pacas to find
220 * which logical id maps to our physical one. 220 * which logical id maps to our physical one.
221 */ 221 */
222 LOAD_REG_ADDR(r13, paca) /* Get base vaddr of paca array */ 222 LOAD_REG_ADDR(r13, paca) /* Load paca pointer */
223 ld r13,0(r13) /* Get base vaddr of paca array */
223 li r5,0 /* logical cpu id */ 224 li r5,0 /* logical cpu id */
2241: lhz r6,PACAHWCPUID(r13) /* Load HW procid from paca */ 2251: lhz r6,PACAHWCPUID(r13) /* Load HW procid from paca */
225 cmpw r6,r24 /* Compare to our id */ 226 cmpw r6,r24 /* Compare to our id */
@@ -536,7 +537,8 @@ _GLOBAL(pmac_secondary_start)
536 mtmsrd r3 /* RI on */ 537 mtmsrd r3 /* RI on */
537 538
538 /* Set up a paca value for this processor. */ 539 /* Set up a paca value for this processor. */
539 LOAD_REG_ADDR(r4,paca) /* Get base vaddr of paca array */ 540 LOAD_REG_ADDR(r4,paca) /* Load paca pointer */
541 ld r4,0(r4) /* Get base vaddr of paca array */
540 mulli r13,r24,PACA_SIZE /* Calculate vaddr of right paca */ 542 mulli r13,r24,PACA_SIZE /* Calculate vaddr of right paca */
541 add r13,r13,r4 /* for this processor. */ 543 add r13,r13,r4 /* for this processor. */
542 mtspr SPRN_SPRG_PACA,r13 /* Save vaddr of paca in an SPRG*/ 544 mtspr SPRN_SPRG_PACA,r13 /* Save vaddr of paca in an SPRG*/
@@ -615,6 +617,17 @@ _GLOBAL(start_secondary_prolog)
615 std r3,0(r1) /* Zero the stack frame pointer */ 617 std r3,0(r1) /* Zero the stack frame pointer */
616 bl .start_secondary 618 bl .start_secondary
617 b . 619 b .
620/*
621 * Reset stack pointer and call start_secondary
622 * to continue with online operation when woken up
623 * from cede in cpu offline.
624 */
625_GLOBAL(start_secondary_resume)
626 ld r1,PACAKSAVE(r13) /* Reload kernel stack pointer */
627 li r3,0
628 std r3,0(r1) /* Zero the stack frame pointer */
629 bl .start_secondary
630 b .
618#endif 631#endif
619 632
620/* 633/*
diff --git a/arch/powerpc/kernel/head_fsl_booke.S b/arch/powerpc/kernel/head_fsl_booke.S
index 25793bb0e782..725526547994 100644
--- a/arch/powerpc/kernel/head_fsl_booke.S
+++ b/arch/powerpc/kernel/head_fsl_booke.S
@@ -747,9 +747,6 @@ finish_tlb_load:
747#else 747#else
748 rlwimi r12, r11, 26, 27, 31 /* extract WIMGE from pte */ 748 rlwimi r12, r11, 26, 27, 31 /* extract WIMGE from pte */
749#endif 749#endif
750#ifdef CONFIG_SMP
751 ori r12, r12, MAS2_M
752#endif
753 mtspr SPRN_MAS2, r12 750 mtspr SPRN_MAS2, r12
754 751
755#ifdef CONFIG_PTE_64BIT 752#ifdef CONFIG_PTE_64BIT
@@ -887,13 +884,17 @@ KernelSPE:
887 lwz r3,_MSR(r1) 884 lwz r3,_MSR(r1)
888 oris r3,r3,MSR_SPE@h 885 oris r3,r3,MSR_SPE@h
889 stw r3,_MSR(r1) /* enable use of SPE after return */ 886 stw r3,_MSR(r1) /* enable use of SPE after return */
887#ifdef CONFIG_PRINTK
890 lis r3,87f@h 888 lis r3,87f@h
891 ori r3,r3,87f@l 889 ori r3,r3,87f@l
892 mr r4,r2 /* current */ 890 mr r4,r2 /* current */
893 lwz r5,_NIP(r1) 891 lwz r5,_NIP(r1)
894 bl printk 892 bl printk
893#endif
895 b ret_from_except 894 b ret_from_except
895#ifdef CONFIG_PRINTK
89687: .string "SPE used in kernel (task=%p, pc=%x) \n" 89687: .string "SPE used in kernel (task=%p, pc=%x) \n"
897#endif
897 .align 4,0 898 .align 4,0
898 899
899#endif /* CONFIG_SPE */ 900#endif /* CONFIG_SPE */
diff --git a/arch/powerpc/kernel/iommu.c b/arch/powerpc/kernel/iommu.c
index 5547ae6e6b0b..ec94f906ea43 100644
--- a/arch/powerpc/kernel/iommu.c
+++ b/arch/powerpc/kernel/iommu.c
@@ -42,12 +42,7 @@
42 42
43#define DBG(...) 43#define DBG(...)
44 44
45#ifdef CONFIG_IOMMU_VMERGE 45static int novmerge;
46static int novmerge = 0;
47#else
48static int novmerge = 1;
49#endif
50
51static int protect4gb = 1; 46static int protect4gb = 1;
52 47
53static void __iommu_free(struct iommu_table *, dma_addr_t, unsigned int); 48static void __iommu_free(struct iommu_table *, dma_addr_t, unsigned int);
diff --git a/arch/powerpc/kernel/legacy_serial.c b/arch/powerpc/kernel/legacy_serial.c
index 9ddfaef1a184..035ada5443ee 100644
--- a/arch/powerpc/kernel/legacy_serial.c
+++ b/arch/powerpc/kernel/legacy_serial.c
@@ -469,7 +469,7 @@ static int __init serial_dev_init(void)
469 return -ENODEV; 469 return -ENODEV;
470 470
471 /* 471 /*
472 * Before we register the platfrom serial devices, we need 472 * Before we register the platform serial devices, we need
473 * to fixup their interrupts and their IO ports. 473 * to fixup their interrupts and their IO ports.
474 */ 474 */
475 DBG("Fixing serial ports interrupts and IO ports ...\n"); 475 DBG("Fixing serial ports interrupts and IO ports ...\n");
diff --git a/arch/powerpc/kernel/paca.c b/arch/powerpc/kernel/paca.c
index d16b1ea55d44..0c40c6f476fe 100644
--- a/arch/powerpc/kernel/paca.c
+++ b/arch/powerpc/kernel/paca.c
@@ -9,11 +9,15 @@
9 9
10#include <linux/threads.h> 10#include <linux/threads.h>
11#include <linux/module.h> 11#include <linux/module.h>
12#include <linux/lmb.h>
12 13
14#include <asm/firmware.h>
13#include <asm/lppaca.h> 15#include <asm/lppaca.h>
14#include <asm/paca.h> 16#include <asm/paca.h>
15#include <asm/sections.h> 17#include <asm/sections.h>
16#include <asm/pgtable.h> 18#include <asm/pgtable.h>
19#include <asm/iseries/lpar_map.h>
20#include <asm/iseries/hv_types.h>
17 21
18/* This symbol is provided by the linker - let it fill in the paca 22/* This symbol is provided by the linker - let it fill in the paca
19 * field correctly */ 23 * field correctly */
@@ -70,37 +74,82 @@ struct slb_shadow slb_shadow[] __cacheline_aligned = {
70 * processors. The processor VPD array needs one entry per physical 74 * processors. The processor VPD array needs one entry per physical
71 * processor (not thread). 75 * processor (not thread).
72 */ 76 */
73struct paca_struct paca[NR_CPUS]; 77struct paca_struct *paca;
74EXPORT_SYMBOL(paca); 78EXPORT_SYMBOL(paca);
75 79
76void __init initialise_pacas(void) 80struct paca_struct boot_paca;
77{
78 int cpu;
79 81
80 /* The TOC register (GPR2) points 32kB into the TOC, so that 64kB 82void __init initialise_paca(struct paca_struct *new_paca, int cpu)
81 * of the TOC can be addressed using a single machine instruction. 83{
82 */ 84 /* The TOC register (GPR2) points 32kB into the TOC, so that 64kB
85 * of the TOC can be addressed using a single machine instruction.
86 */
83 unsigned long kernel_toc = (unsigned long)(&__toc_start) + 0x8000UL; 87 unsigned long kernel_toc = (unsigned long)(&__toc_start) + 0x8000UL;
84 88
85 /* Can't use for_each_*_cpu, as they aren't functional yet */
86 for (cpu = 0; cpu < NR_CPUS; cpu++) {
87 struct paca_struct *new_paca = &paca[cpu];
88
89#ifdef CONFIG_PPC_BOOK3S 89#ifdef CONFIG_PPC_BOOK3S
90 new_paca->lppaca_ptr = &lppaca[cpu]; 90 new_paca->lppaca_ptr = &lppaca[cpu];
91#else 91#else
92 new_paca->kernel_pgd = swapper_pg_dir; 92 new_paca->kernel_pgd = swapper_pg_dir;
93#endif 93#endif
94 new_paca->lock_token = 0x8000; 94 new_paca->lock_token = 0x8000;
95 new_paca->paca_index = cpu; 95 new_paca->paca_index = cpu;
96 new_paca->kernel_toc = kernel_toc; 96 new_paca->kernel_toc = kernel_toc;
97 new_paca->kernelbase = (unsigned long) _stext; 97 new_paca->kernelbase = (unsigned long) _stext;
98 new_paca->kernel_msr = MSR_KERNEL; 98 new_paca->kernel_msr = MSR_KERNEL;
99 new_paca->hw_cpu_id = 0xffff; 99 new_paca->hw_cpu_id = 0xffff;
100 new_paca->__current = &init_task; 100 new_paca->__current = &init_task;
101#ifdef CONFIG_PPC_STD_MMU_64 101#ifdef CONFIG_PPC_STD_MMU_64
102 new_paca->slb_shadow_ptr = &slb_shadow[cpu]; 102 new_paca->slb_shadow_ptr = &slb_shadow[cpu];
103#endif /* CONFIG_PPC_STD_MMU_64 */ 103#endif /* CONFIG_PPC_STD_MMU_64 */
104}
105
106static int __initdata paca_size;
107
108void __init allocate_pacas(void)
109{
110 int nr_cpus, cpu, limit;
111
112 /*
113 * We can't take SLB misses on the paca, and we want to access them
114 * in real mode, so allocate them within the RMA and also within
115 * the first segment. On iSeries they must be within the area mapped
116 * by the HV, which is HvPagesToMap * HVPAGESIZE bytes.
117 */
118 limit = min(0x10000000ULL, lmb.rmo_size);
119 if (firmware_has_feature(FW_FEATURE_ISERIES))
120 limit = min(limit, HvPagesToMap * HVPAGESIZE);
121
122 nr_cpus = NR_CPUS;
123 /* On iSeries we know we can never have more than 64 cpus */
124 if (firmware_has_feature(FW_FEATURE_ISERIES))
125 nr_cpus = min(64, nr_cpus);
126
127 paca_size = PAGE_ALIGN(sizeof(struct paca_struct) * nr_cpus);
128
129 paca = __va(lmb_alloc_base(paca_size, PAGE_SIZE, limit));
130 memset(paca, 0, paca_size);
131
132 printk(KERN_DEBUG "Allocated %u bytes for %d pacas at %p\n",
133 paca_size, nr_cpus, paca);
134
135 /* Can't use for_each_*_cpu, as they aren't functional yet */
136 for (cpu = 0; cpu < nr_cpus; cpu++)
137 initialise_paca(&paca[cpu], cpu);
138}
139
140void __init free_unused_pacas(void)
141{
142 int new_size;
143
144 new_size = PAGE_ALIGN(sizeof(struct paca_struct) * num_possible_cpus());
145
146 if (new_size >= paca_size)
147 return;
148
149 lmb_free(__pa(paca) + new_size, paca_size - new_size);
150
151 printk(KERN_DEBUG "Freed %u bytes for unused pacas\n",
152 paca_size - new_size);
104 153
105 } 154 paca_size = new_size;
106} 155}
diff --git a/arch/powerpc/kernel/pci-common.c b/arch/powerpc/kernel/pci-common.c
index 2597f9545d8a..f3c42ce516e7 100644
--- a/arch/powerpc/kernel/pci-common.c
+++ b/arch/powerpc/kernel/pci-common.c
@@ -63,21 +63,6 @@ struct dma_map_ops *get_pci_dma_ops(void)
63} 63}
64EXPORT_SYMBOL(get_pci_dma_ops); 64EXPORT_SYMBOL(get_pci_dma_ops);
65 65
66int pci_set_dma_mask(struct pci_dev *dev, u64 mask)
67{
68 return dma_set_mask(&dev->dev, mask);
69}
70
71int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
72{
73 int rc;
74
75 rc = dma_set_mask(&dev->dev, mask);
76 dev->dev.coherent_dma_mask = dev->dma_mask;
77
78 return rc;
79}
80
81struct pci_controller *pcibios_alloc_controller(struct device_node *dev) 66struct pci_controller *pcibios_alloc_controller(struct device_node *dev)
82{ 67{
83 struct pci_controller *phb; 68 struct pci_controller *phb;
diff --git a/arch/powerpc/kernel/perf_event.c b/arch/powerpc/kernel/perf_event.c
index b6cf8f1f4d35..08460a2e9f41 100644
--- a/arch/powerpc/kernel/perf_event.c
+++ b/arch/powerpc/kernel/perf_event.c
@@ -1164,10 +1164,10 @@ static void record_and_restart(struct perf_event *event, unsigned long val,
1164 * Finally record data if requested. 1164 * Finally record data if requested.
1165 */ 1165 */
1166 if (record) { 1166 if (record) {
1167 struct perf_sample_data data = { 1167 struct perf_sample_data data;
1168 .addr = ~0ULL, 1168
1169 .period = event->hw.last_period, 1169 perf_sample_data_init(&data, ~0ULL);
1170 }; 1170 data.period = event->hw.last_period;
1171 1171
1172 if (event->attr.sample_type & PERF_SAMPLE_ADDR) 1172 if (event->attr.sample_type & PERF_SAMPLE_ADDR)
1173 perf_get_data_addr(regs, &data.addr); 1173 perf_get_data_addr(regs, &data.addr);
@@ -1287,7 +1287,7 @@ static void perf_event_interrupt(struct pt_regs *regs)
1287 irq_exit(); 1287 irq_exit();
1288} 1288}
1289 1289
1290void hw_perf_event_setup(int cpu) 1290static void power_pmu_setup(int cpu)
1291{ 1291{
1292 struct cpu_hw_events *cpuhw = &per_cpu(cpu_hw_events, cpu); 1292 struct cpu_hw_events *cpuhw = &per_cpu(cpu_hw_events, cpu);
1293 1293
@@ -1297,6 +1297,23 @@ void hw_perf_event_setup(int cpu)
1297 cpuhw->mmcr[0] = MMCR0_FC; 1297 cpuhw->mmcr[0] = MMCR0_FC;
1298} 1298}
1299 1299
1300static int __cpuinit
1301power_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
1302{
1303 unsigned int cpu = (long)hcpu;
1304
1305 switch (action & ~CPU_TASKS_FROZEN) {
1306 case CPU_UP_PREPARE:
1307 power_pmu_setup(cpu);
1308 break;
1309
1310 default:
1311 break;
1312 }
1313
1314 return NOTIFY_OK;
1315}
1316
1300int register_power_pmu(struct power_pmu *pmu) 1317int register_power_pmu(struct power_pmu *pmu)
1301{ 1318{
1302 if (ppmu) 1319 if (ppmu)
@@ -1314,5 +1331,7 @@ int register_power_pmu(struct power_pmu *pmu)
1314 freeze_events_kernel = MMCR0_FCHV; 1331 freeze_events_kernel = MMCR0_FCHV;
1315#endif /* CONFIG_PPC64 */ 1332#endif /* CONFIG_PPC64 */
1316 1333
1334 perf_cpu_notifier(power_pmu_notifier);
1335
1317 return 0; 1336 return 0;
1318} 1337}
diff --git a/arch/powerpc/kernel/perf_event_fsl_emb.c b/arch/powerpc/kernel/perf_event_fsl_emb.c
new file mode 100644
index 000000000000..369872f6cf78
--- /dev/null
+++ b/arch/powerpc/kernel/perf_event_fsl_emb.c
@@ -0,0 +1,654 @@
1/*
2 * Performance event support - Freescale Embedded Performance Monitor
3 *
4 * Copyright 2008-2009 Paul Mackerras, IBM Corporation.
5 * Copyright 2010 Freescale Semiconductor, Inc.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 */
12#include <linux/kernel.h>
13#include <linux/sched.h>
14#include <linux/perf_event.h>
15#include <linux/percpu.h>
16#include <linux/hardirq.h>
17#include <asm/reg_fsl_emb.h>
18#include <asm/pmc.h>
19#include <asm/machdep.h>
20#include <asm/firmware.h>
21#include <asm/ptrace.h>
22
23struct cpu_hw_events {
24 int n_events;
25 int disabled;
26 u8 pmcs_enabled;
27 struct perf_event *event[MAX_HWEVENTS];
28};
29static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
30
31static struct fsl_emb_pmu *ppmu;
32
33/* Number of perf_events counting hardware events */
34static atomic_t num_events;
35/* Used to avoid races in calling reserve/release_pmc_hardware */
36static DEFINE_MUTEX(pmc_reserve_mutex);
37
38/*
39 * If interrupts were soft-disabled when a PMU interrupt occurs, treat
40 * it as an NMI.
41 */
42static inline int perf_intr_is_nmi(struct pt_regs *regs)
43{
44#ifdef __powerpc64__
45 return !regs->softe;
46#else
47 return 0;
48#endif
49}
50
51static void perf_event_interrupt(struct pt_regs *regs);
52
53/*
54 * Read one performance monitor counter (PMC).
55 */
56static unsigned long read_pmc(int idx)
57{
58 unsigned long val;
59
60 switch (idx) {
61 case 0:
62 val = mfpmr(PMRN_PMC0);
63 break;
64 case 1:
65 val = mfpmr(PMRN_PMC1);
66 break;
67 case 2:
68 val = mfpmr(PMRN_PMC2);
69 break;
70 case 3:
71 val = mfpmr(PMRN_PMC3);
72 break;
73 default:
74 printk(KERN_ERR "oops trying to read PMC%d\n", idx);
75 val = 0;
76 }
77 return val;
78}
79
80/*
81 * Write one PMC.
82 */
83static void write_pmc(int idx, unsigned long val)
84{
85 switch (idx) {
86 case 0:
87 mtpmr(PMRN_PMC0, val);
88 break;
89 case 1:
90 mtpmr(PMRN_PMC1, val);
91 break;
92 case 2:
93 mtpmr(PMRN_PMC2, val);
94 break;
95 case 3:
96 mtpmr(PMRN_PMC3, val);
97 break;
98 default:
99 printk(KERN_ERR "oops trying to write PMC%d\n", idx);
100 }
101
102 isync();
103}
104
105/*
106 * Write one local control A register
107 */
108static void write_pmlca(int idx, unsigned long val)
109{
110 switch (idx) {
111 case 0:
112 mtpmr(PMRN_PMLCA0, val);
113 break;
114 case 1:
115 mtpmr(PMRN_PMLCA1, val);
116 break;
117 case 2:
118 mtpmr(PMRN_PMLCA2, val);
119 break;
120 case 3:
121 mtpmr(PMRN_PMLCA3, val);
122 break;
123 default:
124 printk(KERN_ERR "oops trying to write PMLCA%d\n", idx);
125 }
126
127 isync();
128}
129
130/*
131 * Write one local control B register
132 */
133static void write_pmlcb(int idx, unsigned long val)
134{
135 switch (idx) {
136 case 0:
137 mtpmr(PMRN_PMLCB0, val);
138 break;
139 case 1:
140 mtpmr(PMRN_PMLCB1, val);
141 break;
142 case 2:
143 mtpmr(PMRN_PMLCB2, val);
144 break;
145 case 3:
146 mtpmr(PMRN_PMLCB3, val);
147 break;
148 default:
149 printk(KERN_ERR "oops trying to write PMLCB%d\n", idx);
150 }
151
152 isync();
153}
154
155static void fsl_emb_pmu_read(struct perf_event *event)
156{
157 s64 val, delta, prev;
158
159 /*
160 * Performance monitor interrupts come even when interrupts
161 * are soft-disabled, as long as interrupts are hard-enabled.
162 * Therefore we treat them like NMIs.
163 */
164 do {
165 prev = atomic64_read(&event->hw.prev_count);
166 barrier();
167 val = read_pmc(event->hw.idx);
168 } while (atomic64_cmpxchg(&event->hw.prev_count, prev, val) != prev);
169
170 /* The counters are only 32 bits wide */
171 delta = (val - prev) & 0xfffffffful;
172 atomic64_add(delta, &event->count);
173 atomic64_sub(delta, &event->hw.period_left);
174}
175
176/*
177 * Disable all events to prevent PMU interrupts and to allow
178 * events to be added or removed.
179 */
180void hw_perf_disable(void)
181{
182 struct cpu_hw_events *cpuhw;
183 unsigned long flags;
184
185 local_irq_save(flags);
186 cpuhw = &__get_cpu_var(cpu_hw_events);
187
188 if (!cpuhw->disabled) {
189 cpuhw->disabled = 1;
190
191 /*
192 * Check if we ever enabled the PMU on this cpu.
193 */
194 if (!cpuhw->pmcs_enabled) {
195 ppc_enable_pmcs();
196 cpuhw->pmcs_enabled = 1;
197 }
198
199 if (atomic_read(&num_events)) {
200 /*
201 * Set the 'freeze all counters' bit, and disable
202 * interrupts. The barrier is to make sure the
203 * mtpmr has been executed and the PMU has frozen
204 * the events before we return.
205 */
206
207 mtpmr(PMRN_PMGC0, PMGC0_FAC);
208 isync();
209 }
210 }
211 local_irq_restore(flags);
212}
213
214/*
215 * Re-enable all events if disable == 0.
216 * If we were previously disabled and events were added, then
217 * put the new config on the PMU.
218 */
219void hw_perf_enable(void)
220{
221 struct cpu_hw_events *cpuhw;
222 unsigned long flags;
223
224 local_irq_save(flags);
225 cpuhw = &__get_cpu_var(cpu_hw_events);
226 if (!cpuhw->disabled)
227 goto out;
228
229 cpuhw->disabled = 0;
230 ppc_set_pmu_inuse(cpuhw->n_events != 0);
231
232 if (cpuhw->n_events > 0) {
233 mtpmr(PMRN_PMGC0, PMGC0_PMIE | PMGC0_FCECE);
234 isync();
235 }
236
237 out:
238 local_irq_restore(flags);
239}
240
241static int collect_events(struct perf_event *group, int max_count,
242 struct perf_event *ctrs[])
243{
244 int n = 0;
245 struct perf_event *event;
246
247 if (!is_software_event(group)) {
248 if (n >= max_count)
249 return -1;
250 ctrs[n] = group;
251 n++;
252 }
253 list_for_each_entry(event, &group->sibling_list, group_entry) {
254 if (!is_software_event(event) &&
255 event->state != PERF_EVENT_STATE_OFF) {
256 if (n >= max_count)
257 return -1;
258 ctrs[n] = event;
259 n++;
260 }
261 }
262 return n;
263}
264
265/* perf must be disabled, context locked on entry */
266static int fsl_emb_pmu_enable(struct perf_event *event)
267{
268 struct cpu_hw_events *cpuhw;
269 int ret = -EAGAIN;
270 int num_counters = ppmu->n_counter;
271 u64 val;
272 int i;
273
274 cpuhw = &get_cpu_var(cpu_hw_events);
275
276 if (event->hw.config & FSL_EMB_EVENT_RESTRICTED)
277 num_counters = ppmu->n_restricted;
278
279 /*
280 * Allocate counters from top-down, so that restricted-capable
281 * counters are kept free as long as possible.
282 */
283 for (i = num_counters - 1; i >= 0; i--) {
284 if (cpuhw->event[i])
285 continue;
286
287 break;
288 }
289
290 if (i < 0)
291 goto out;
292
293 event->hw.idx = i;
294 cpuhw->event[i] = event;
295 ++cpuhw->n_events;
296
297 val = 0;
298 if (event->hw.sample_period) {
299 s64 left = atomic64_read(&event->hw.period_left);
300 if (left < 0x80000000L)
301 val = 0x80000000L - left;
302 }
303 atomic64_set(&event->hw.prev_count, val);
304 write_pmc(i, val);
305 perf_event_update_userpage(event);
306
307 write_pmlcb(i, event->hw.config >> 32);
308 write_pmlca(i, event->hw.config_base);
309
310 ret = 0;
311 out:
312 put_cpu_var(cpu_hw_events);
313 return ret;
314}
315
316/* perf must be disabled, context locked on entry */
317static void fsl_emb_pmu_disable(struct perf_event *event)
318{
319 struct cpu_hw_events *cpuhw;
320 int i = event->hw.idx;
321
322 if (i < 0)
323 goto out;
324
325 fsl_emb_pmu_read(event);
326
327 cpuhw = &get_cpu_var(cpu_hw_events);
328
329 WARN_ON(event != cpuhw->event[event->hw.idx]);
330
331 write_pmlca(i, 0);
332 write_pmlcb(i, 0);
333 write_pmc(i, 0);
334
335 cpuhw->event[i] = NULL;
336 event->hw.idx = -1;
337
338 /*
339 * TODO: if at least one restricted event exists, and we
340 * just freed up a non-restricted-capable counter, and
341 * there is a restricted-capable counter occupied by
342 * a non-restricted event, migrate that event to the
343 * vacated counter.
344 */
345
346 cpuhw->n_events--;
347
348 out:
349 put_cpu_var(cpu_hw_events);
350}
351
352/*
353 * Re-enable interrupts on a event after they were throttled
354 * because they were coming too fast.
355 *
356 * Context is locked on entry, but perf is not disabled.
357 */
358static void fsl_emb_pmu_unthrottle(struct perf_event *event)
359{
360 s64 val, left;
361 unsigned long flags;
362
363 if (event->hw.idx < 0 || !event->hw.sample_period)
364 return;
365 local_irq_save(flags);
366 perf_disable();
367 fsl_emb_pmu_read(event);
368 left = event->hw.sample_period;
369 event->hw.last_period = left;
370 val = 0;
371 if (left < 0x80000000L)
372 val = 0x80000000L - left;
373 write_pmc(event->hw.idx, val);
374 atomic64_set(&event->hw.prev_count, val);
375 atomic64_set(&event->hw.period_left, left);
376 perf_event_update_userpage(event);
377 perf_enable();
378 local_irq_restore(flags);
379}
380
381static struct pmu fsl_emb_pmu = {
382 .enable = fsl_emb_pmu_enable,
383 .disable = fsl_emb_pmu_disable,
384 .read = fsl_emb_pmu_read,
385 .unthrottle = fsl_emb_pmu_unthrottle,
386};
387
388/*
389 * Release the PMU if this is the last perf_event.
390 */
391static void hw_perf_event_destroy(struct perf_event *event)
392{
393 if (!atomic_add_unless(&num_events, -1, 1)) {
394 mutex_lock(&pmc_reserve_mutex);
395 if (atomic_dec_return(&num_events) == 0)
396 release_pmc_hardware();
397 mutex_unlock(&pmc_reserve_mutex);
398 }
399}
400
401/*
402 * Translate a generic cache event_id config to a raw event_id code.
403 */
404static int hw_perf_cache_event(u64 config, u64 *eventp)
405{
406 unsigned long type, op, result;
407 int ev;
408
409 if (!ppmu->cache_events)
410 return -EINVAL;
411
412 /* unpack config */
413 type = config & 0xff;
414 op = (config >> 8) & 0xff;
415 result = (config >> 16) & 0xff;
416
417 if (type >= PERF_COUNT_HW_CACHE_MAX ||
418 op >= PERF_COUNT_HW_CACHE_OP_MAX ||
419 result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
420 return -EINVAL;
421
422 ev = (*ppmu->cache_events)[type][op][result];
423 if (ev == 0)
424 return -EOPNOTSUPP;
425 if (ev == -1)
426 return -EINVAL;
427 *eventp = ev;
428 return 0;
429}
430
431const struct pmu *hw_perf_event_init(struct perf_event *event)
432{
433 u64 ev;
434 struct perf_event *events[MAX_HWEVENTS];
435 int n;
436 int err;
437 int num_restricted;
438 int i;
439
440 switch (event->attr.type) {
441 case PERF_TYPE_HARDWARE:
442 ev = event->attr.config;
443 if (ev >= ppmu->n_generic || ppmu->generic_events[ev] == 0)
444 return ERR_PTR(-EOPNOTSUPP);
445 ev = ppmu->generic_events[ev];
446 break;
447
448 case PERF_TYPE_HW_CACHE:
449 err = hw_perf_cache_event(event->attr.config, &ev);
450 if (err)
451 return ERR_PTR(err);
452 break;
453
454 case PERF_TYPE_RAW:
455 ev = event->attr.config;
456 break;
457
458 default:
459 return ERR_PTR(-EINVAL);
460 }
461
462 event->hw.config = ppmu->xlate_event(ev);
463 if (!(event->hw.config & FSL_EMB_EVENT_VALID))
464 return ERR_PTR(-EINVAL);
465
466 /*
467 * If this is in a group, check if it can go on with all the
468 * other hardware events in the group. We assume the event
469 * hasn't been linked into its leader's sibling list at this point.
470 */
471 n = 0;
472 if (event->group_leader != event) {
473 n = collect_events(event->group_leader,
474 ppmu->n_counter - 1, events);
475 if (n < 0)
476 return ERR_PTR(-EINVAL);
477 }
478
479 if (event->hw.config & FSL_EMB_EVENT_RESTRICTED) {
480 num_restricted = 0;
481 for (i = 0; i < n; i++) {
482 if (events[i]->hw.config & FSL_EMB_EVENT_RESTRICTED)
483 num_restricted++;
484 }
485
486 if (num_restricted >= ppmu->n_restricted)
487 return ERR_PTR(-EINVAL);
488 }
489
490 event->hw.idx = -1;
491
492 event->hw.config_base = PMLCA_CE | PMLCA_FCM1 |
493 (u32)((ev << 16) & PMLCA_EVENT_MASK);
494
495 if (event->attr.exclude_user)
496 event->hw.config_base |= PMLCA_FCU;
497 if (event->attr.exclude_kernel)
498 event->hw.config_base |= PMLCA_FCS;
499 if (event->attr.exclude_idle)
500 return ERR_PTR(-ENOTSUPP);
501
502 event->hw.last_period = event->hw.sample_period;
503 atomic64_set(&event->hw.period_left, event->hw.last_period);
504
505 /*
506 * See if we need to reserve the PMU.
507 * If no events are currently in use, then we have to take a
508 * mutex to ensure that we don't race with another task doing
509 * reserve_pmc_hardware or release_pmc_hardware.
510 */
511 err = 0;
512 if (!atomic_inc_not_zero(&num_events)) {
513 mutex_lock(&pmc_reserve_mutex);
514 if (atomic_read(&num_events) == 0 &&
515 reserve_pmc_hardware(perf_event_interrupt))
516 err = -EBUSY;
517 else
518 atomic_inc(&num_events);
519 mutex_unlock(&pmc_reserve_mutex);
520
521 mtpmr(PMRN_PMGC0, PMGC0_FAC);
522 isync();
523 }
524 event->destroy = hw_perf_event_destroy;
525
526 if (err)
527 return ERR_PTR(err);
528 return &fsl_emb_pmu;
529}
530
531/*
532 * A counter has overflowed; update its count and record
533 * things if requested. Note that interrupts are hard-disabled
534 * here so there is no possibility of being interrupted.
535 */
536static void record_and_restart(struct perf_event *event, unsigned long val,
537 struct pt_regs *regs, int nmi)
538{
539 u64 period = event->hw.sample_period;
540 s64 prev, delta, left;
541 int record = 0;
542
543 /* we don't have to worry about interrupts here */
544 prev = atomic64_read(&event->hw.prev_count);
545 delta = (val - prev) & 0xfffffffful;
546 atomic64_add(delta, &event->count);
547
548 /*
549 * See if the total period for this event has expired,
550 * and update for the next period.
551 */
552 val = 0;
553 left = atomic64_read(&event->hw.period_left) - delta;
554 if (period) {
555 if (left <= 0) {
556 left += period;
557 if (left <= 0)
558 left = period;
559 record = 1;
560 }
561 if (left < 0x80000000LL)
562 val = 0x80000000LL - left;
563 }
564
565 /*
566 * Finally record data if requested.
567 */
568 if (record) {
569 struct perf_sample_data data = {
570 .period = event->hw.last_period,
571 };
572
573 if (perf_event_overflow(event, nmi, &data, regs)) {
574 /*
575 * Interrupts are coming too fast - throttle them
576 * by setting the event to 0, so it will be
577 * at least 2^30 cycles until the next interrupt
578 * (assuming each event counts at most 2 counts
579 * per cycle).
580 */
581 val = 0;
582 left = ~0ULL >> 1;
583 }
584 }
585
586 write_pmc(event->hw.idx, val);
587 atomic64_set(&event->hw.prev_count, val);
588 atomic64_set(&event->hw.period_left, left);
589 perf_event_update_userpage(event);
590}
591
592static void perf_event_interrupt(struct pt_regs *regs)
593{
594 int i;
595 struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events);
596 struct perf_event *event;
597 unsigned long val;
598 int found = 0;
599 int nmi;
600
601 nmi = perf_intr_is_nmi(regs);
602 if (nmi)
603 nmi_enter();
604 else
605 irq_enter();
606
607 for (i = 0; i < ppmu->n_counter; ++i) {
608 event = cpuhw->event[i];
609
610 val = read_pmc(i);
611 if ((int)val < 0) {
612 if (event) {
613 /* event has overflowed */
614 found = 1;
615 record_and_restart(event, val, regs, nmi);
616 } else {
617 /*
618 * Disabled counter is negative,
619 * reset it just in case.
620 */
621 write_pmc(i, 0);
622 }
623 }
624 }
625
626 /* PMM will keep counters frozen until we return from the interrupt. */
627 mtmsr(mfmsr() | MSR_PMM);
628 mtpmr(PMRN_PMGC0, PMGC0_PMIE | PMGC0_FCECE);
629 isync();
630
631 if (nmi)
632 nmi_exit();
633 else
634 irq_exit();
635}
636
637void hw_perf_event_setup(int cpu)
638{
639 struct cpu_hw_events *cpuhw = &per_cpu(cpu_hw_events, cpu);
640
641 memset(cpuhw, 0, sizeof(*cpuhw));
642}
643
644int register_fsl_emb_pmu(struct fsl_emb_pmu *pmu)
645{
646 if (ppmu)
647 return -EBUSY; /* something's already registered */
648
649 ppmu = pmu;
650 pr_info("%s performance monitor hardware support registered\n",
651 pmu->name);
652
653 return 0;
654}
diff --git a/arch/powerpc/kernel/prom.c b/arch/powerpc/kernel/prom.c
index 43238b2054b6..05131d634e73 100644
--- a/arch/powerpc/kernel/prom.c
+++ b/arch/powerpc/kernel/prom.c
@@ -43,6 +43,7 @@
43#include <asm/smp.h> 43#include <asm/smp.h>
44#include <asm/system.h> 44#include <asm/system.h>
45#include <asm/mmu.h> 45#include <asm/mmu.h>
46#include <asm/paca.h>
46#include <asm/pgtable.h> 47#include <asm/pgtable.h>
47#include <asm/pci.h> 48#include <asm/pci.h>
48#include <asm/iommu.h> 49#include <asm/iommu.h>
@@ -721,6 +722,8 @@ void __init early_init_devtree(void *params)
721 * FIXME .. and the initrd too? */ 722 * FIXME .. and the initrd too? */
722 move_device_tree(); 723 move_device_tree();
723 724
725 allocate_pacas();
726
724 DBG("Scanning CPUs ...\n"); 727 DBG("Scanning CPUs ...\n");
725 728
726 /* Retreive CPU related informations from the flat tree 729 /* Retreive CPU related informations from the flat tree
diff --git a/arch/powerpc/kernel/ptrace.c b/arch/powerpc/kernel/ptrace.c
index d9b05866615f..ed2cfe17d25e 100644
--- a/arch/powerpc/kernel/ptrace.c
+++ b/arch/powerpc/kernel/ptrace.c
@@ -940,7 +940,7 @@ static int del_instruction_bp(struct task_struct *child, int slot)
940{ 940{
941 switch (slot) { 941 switch (slot) {
942 case 1: 942 case 1:
943 if (child->thread.iac1 == 0) 943 if ((child->thread.dbcr0 & DBCR0_IAC1) == 0)
944 return -ENOENT; 944 return -ENOENT;
945 945
946 if (dbcr_iac_range(child) & DBCR_IAC12MODE) { 946 if (dbcr_iac_range(child) & DBCR_IAC12MODE) {
@@ -952,7 +952,7 @@ static int del_instruction_bp(struct task_struct *child, int slot)
952 child->thread.dbcr0 &= ~DBCR0_IAC1; 952 child->thread.dbcr0 &= ~DBCR0_IAC1;
953 break; 953 break;
954 case 2: 954 case 2:
955 if (child->thread.iac2 == 0) 955 if ((child->thread.dbcr0 & DBCR0_IAC2) == 0)
956 return -ENOENT; 956 return -ENOENT;
957 957
958 if (dbcr_iac_range(child) & DBCR_IAC12MODE) 958 if (dbcr_iac_range(child) & DBCR_IAC12MODE)
@@ -963,7 +963,7 @@ static int del_instruction_bp(struct task_struct *child, int slot)
963 break; 963 break;
964#if CONFIG_PPC_ADV_DEBUG_IACS > 2 964#if CONFIG_PPC_ADV_DEBUG_IACS > 2
965 case 3: 965 case 3:
966 if (child->thread.iac3 == 0) 966 if ((child->thread.dbcr0 & DBCR0_IAC3) == 0)
967 return -ENOENT; 967 return -ENOENT;
968 968
969 if (dbcr_iac_range(child) & DBCR_IAC34MODE) { 969 if (dbcr_iac_range(child) & DBCR_IAC34MODE) {
@@ -975,7 +975,7 @@ static int del_instruction_bp(struct task_struct *child, int slot)
975 child->thread.dbcr0 &= ~DBCR0_IAC3; 975 child->thread.dbcr0 &= ~DBCR0_IAC3;
976 break; 976 break;
977 case 4: 977 case 4:
978 if (child->thread.iac4 == 0) 978 if ((child->thread.dbcr0 & DBCR0_IAC4) == 0)
979 return -ENOENT; 979 return -ENOENT;
980 980
981 if (dbcr_iac_range(child) & DBCR_IAC34MODE) 981 if (dbcr_iac_range(child) & DBCR_IAC34MODE)
@@ -1054,7 +1054,7 @@ static int set_dac(struct task_struct *child, struct ppc_hw_breakpoint *bp_info)
1054static int del_dac(struct task_struct *child, int slot) 1054static int del_dac(struct task_struct *child, int slot)
1055{ 1055{
1056 if (slot == 1) { 1056 if (slot == 1) {
1057 if (child->thread.dac1 == 0) 1057 if ((dbcr_dac(child) & (DBCR_DAC1R | DBCR_DAC1W)) == 0)
1058 return -ENOENT; 1058 return -ENOENT;
1059 1059
1060 child->thread.dac1 = 0; 1060 child->thread.dac1 = 0;
@@ -1070,7 +1070,7 @@ static int del_dac(struct task_struct *child, int slot)
1070 child->thread.dvc1 = 0; 1070 child->thread.dvc1 = 0;
1071#endif 1071#endif
1072 } else if (slot == 2) { 1072 } else if (slot == 2) {
1073 if (child->thread.dac1 == 0) 1073 if ((dbcr_dac(child) & (DBCR_DAC2R | DBCR_DAC2W)) == 0)
1074 return -ENOENT; 1074 return -ENOENT;
1075 1075
1076#ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE 1076#ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
diff --git a/arch/powerpc/kernel/setup-common.c b/arch/powerpc/kernel/setup-common.c
index 03dd6a248198..48f0a008b20b 100644
--- a/arch/powerpc/kernel/setup-common.c
+++ b/arch/powerpc/kernel/setup-common.c
@@ -36,6 +36,7 @@
36#include <linux/lmb.h> 36#include <linux/lmb.h>
37#include <linux/of_platform.h> 37#include <linux/of_platform.h>
38#include <asm/io.h> 38#include <asm/io.h>
39#include <asm/paca.h>
39#include <asm/prom.h> 40#include <asm/prom.h>
40#include <asm/processor.h> 41#include <asm/processor.h>
41#include <asm/vdso_datapage.h> 42#include <asm/vdso_datapage.h>
@@ -493,6 +494,8 @@ void __init smp_setup_cpu_maps(void)
493 * here will have to be reworked 494 * here will have to be reworked
494 */ 495 */
495 cpu_init_thread_core_maps(nthreads); 496 cpu_init_thread_core_maps(nthreads);
497
498 free_unused_pacas();
496} 499}
497#endif /* CONFIG_SMP */ 500#endif /* CONFIG_SMP */
498 501
diff --git a/arch/powerpc/kernel/setup_32.c b/arch/powerpc/kernel/setup_32.c
index b152de3e64d4..8f58986c2ad9 100644
--- a/arch/powerpc/kernel/setup_32.c
+++ b/arch/powerpc/kernel/setup_32.c
@@ -39,7 +39,6 @@
39#include <asm/serial.h> 39#include <asm/serial.h>
40#include <asm/udbg.h> 40#include <asm/udbg.h>
41#include <asm/mmu_context.h> 41#include <asm/mmu_context.h>
42#include <asm/swiotlb.h>
43 42
44#include "setup.h" 43#include "setup.h"
45 44
@@ -343,11 +342,6 @@ void __init setup_arch(char **cmdline_p)
343 ppc_md.setup_arch(); 342 ppc_md.setup_arch();
344 if ( ppc_md.progress ) ppc_md.progress("arch: exit", 0x3eab); 343 if ( ppc_md.progress ) ppc_md.progress("arch: exit", 0x3eab);
345 344
346#ifdef CONFIG_SWIOTLB
347 if (ppc_swiotlb_enable)
348 swiotlb_init(1);
349#endif
350
351 paging_init(); 345 paging_init();
352 346
353 /* Initialize the MMU context management stuff */ 347 /* Initialize the MMU context management stuff */
diff --git a/arch/powerpc/kernel/setup_64.c b/arch/powerpc/kernel/setup_64.c
index 6568406b2a30..914389158a9b 100644
--- a/arch/powerpc/kernel/setup_64.c
+++ b/arch/powerpc/kernel/setup_64.c
@@ -61,7 +61,6 @@
61#include <asm/xmon.h> 61#include <asm/xmon.h>
62#include <asm/udbg.h> 62#include <asm/udbg.h>
63#include <asm/kexec.h> 63#include <asm/kexec.h>
64#include <asm/swiotlb.h>
65#include <asm/mmu_context.h> 64#include <asm/mmu_context.h>
66 65
67#include "setup.h" 66#include "setup.h"
@@ -144,9 +143,9 @@ early_param("smt-enabled", early_smt_enabled);
144#endif /* CONFIG_SMP */ 143#endif /* CONFIG_SMP */
145 144
146/* Put the paca pointer into r13 and SPRG_PACA */ 145/* Put the paca pointer into r13 and SPRG_PACA */
147void __init setup_paca(int cpu) 146static void __init setup_paca(struct paca_struct *new_paca)
148{ 147{
149 local_paca = &paca[cpu]; 148 local_paca = new_paca;
150 mtspr(SPRN_SPRG_PACA, local_paca); 149 mtspr(SPRN_SPRG_PACA, local_paca);
151#ifdef CONFIG_PPC_BOOK3E 150#ifdef CONFIG_PPC_BOOK3E
152 mtspr(SPRN_SPRG_TLB_EXFRAME, local_paca->extlb); 151 mtspr(SPRN_SPRG_TLB_EXFRAME, local_paca->extlb);
@@ -176,14 +175,12 @@ void __init early_setup(unsigned long dt_ptr)
176{ 175{
177 /* -------- printk is _NOT_ safe to use here ! ------- */ 176 /* -------- printk is _NOT_ safe to use here ! ------- */
178 177
179 /* Fill in any unititialised pacas */
180 initialise_pacas();
181
182 /* Identify CPU type */ 178 /* Identify CPU type */
183 identify_cpu(0, mfspr(SPRN_PVR)); 179 identify_cpu(0, mfspr(SPRN_PVR));
184 180
185 /* Assume we're on cpu 0 for now. Don't write to the paca yet! */ 181 /* Assume we're on cpu 0 for now. Don't write to the paca yet! */
186 setup_paca(0); 182 initialise_paca(&boot_paca, 0);
183 setup_paca(&boot_paca);
187 184
188 /* Initialize lockdep early or else spinlocks will blow */ 185 /* Initialize lockdep early or else spinlocks will blow */
189 lockdep_init(); 186 lockdep_init();
@@ -203,7 +200,7 @@ void __init early_setup(unsigned long dt_ptr)
203 early_init_devtree(__va(dt_ptr)); 200 early_init_devtree(__va(dt_ptr));
204 201
205 /* Now we know the logical id of our boot cpu, setup the paca. */ 202 /* Now we know the logical id of our boot cpu, setup the paca. */
206 setup_paca(boot_cpuid); 203 setup_paca(&paca[boot_cpuid]);
207 204
208 /* Fix up paca fields required for the boot cpu */ 205 /* Fix up paca fields required for the boot cpu */
209 get_paca()->cpu_start = 1; 206 get_paca()->cpu_start = 1;
@@ -543,11 +540,6 @@ void __init setup_arch(char **cmdline_p)
543 if (ppc_md.setup_arch) 540 if (ppc_md.setup_arch)
544 ppc_md.setup_arch(); 541 ppc_md.setup_arch();
545 542
546#ifdef CONFIG_SWIOTLB
547 if (ppc_swiotlb_enable)
548 swiotlb_init(1);
549#endif
550
551 paging_init(); 543 paging_init();
552 544
553 /* Initialize the MMU context management stuff */ 545 /* Initialize the MMU context management stuff */
diff --git a/arch/powerpc/kernel/syscalls.c b/arch/powerpc/kernel/syscalls.c
index 3370e62e43d4..f2496f2faecc 100644
--- a/arch/powerpc/kernel/syscalls.c
+++ b/arch/powerpc/kernel/syscalls.c
@@ -42,100 +42,6 @@
42#include <asm/time.h> 42#include <asm/time.h>
43#include <asm/unistd.h> 43#include <asm/unistd.h>
44 44
45/*
46 * sys_ipc() is the de-multiplexer for the SysV IPC calls..
47 *
48 * This is really horribly ugly.
49 */
50int sys_ipc(uint call, int first, unsigned long second, long third,
51 void __user *ptr, long fifth)
52{
53 int version, ret;
54
55 version = call >> 16; /* hack for backward compatibility */
56 call &= 0xffff;
57
58 ret = -ENOSYS;
59 switch (call) {
60 case SEMOP:
61 ret = sys_semtimedop(first, (struct sembuf __user *)ptr,
62 (unsigned)second, NULL);
63 break;
64 case SEMTIMEDOP:
65 ret = sys_semtimedop(first, (struct sembuf __user *)ptr,
66 (unsigned)second,
67 (const struct timespec __user *) fifth);
68 break;
69 case SEMGET:
70 ret = sys_semget (first, (int)second, third);
71 break;
72 case SEMCTL: {
73 union semun fourth;
74
75 ret = -EINVAL;
76 if (!ptr)
77 break;
78 if ((ret = get_user(fourth.__pad, (void __user * __user *)ptr)))
79 break;
80 ret = sys_semctl(first, (int)second, third, fourth);
81 break;
82 }
83 case MSGSND:
84 ret = sys_msgsnd(first, (struct msgbuf __user *)ptr,
85 (size_t)second, third);
86 break;
87 case MSGRCV:
88 switch (version) {
89 case 0: {
90 struct ipc_kludge tmp;
91
92 ret = -EINVAL;
93 if (!ptr)
94 break;
95 if ((ret = copy_from_user(&tmp,
96 (struct ipc_kludge __user *) ptr,
97 sizeof (tmp)) ? -EFAULT : 0))
98 break;
99 ret = sys_msgrcv(first, tmp.msgp, (size_t) second,
100 tmp.msgtyp, third);
101 break;
102 }
103 default:
104 ret = sys_msgrcv (first, (struct msgbuf __user *) ptr,
105 (size_t)second, fifth, third);
106 break;
107 }
108 break;
109 case MSGGET:
110 ret = sys_msgget((key_t)first, (int)second);
111 break;
112 case MSGCTL:
113 ret = sys_msgctl(first, (int)second,
114 (struct msqid_ds __user *)ptr);
115 break;
116 case SHMAT: {
117 ulong raddr;
118 ret = do_shmat(first, (char __user *)ptr, (int)second, &raddr);
119 if (ret)
120 break;
121 ret = put_user(raddr, (ulong __user *) third);
122 break;
123 }
124 case SHMDT:
125 ret = sys_shmdt((char __user *)ptr);
126 break;
127 case SHMGET:
128 ret = sys_shmget(first, (size_t)second, third);
129 break;
130 case SHMCTL:
131 ret = sys_shmctl(first, (int)second,
132 (struct shmid_ds __user *)ptr);
133 break;
134 }
135
136 return ret;
137}
138
139static inline unsigned long do_mmap2(unsigned long addr, size_t len, 45static inline unsigned long do_mmap2(unsigned long addr, size_t len,
140 unsigned long prot, unsigned long flags, 46 unsigned long prot, unsigned long flags,
141 unsigned long fd, unsigned long off, int shift) 47 unsigned long fd, unsigned long off, int shift)
@@ -210,76 +116,6 @@ long ppc64_personality(unsigned long personality)
210} 116}
211#endif 117#endif
212 118
213#ifdef CONFIG_PPC64
214#define OVERRIDE_MACHINE (personality(current->personality) == PER_LINUX32)
215#else
216#define OVERRIDE_MACHINE 0
217#endif
218
219static inline int override_machine(char __user *mach)
220{
221 if (OVERRIDE_MACHINE) {
222 /* change ppc64 to ppc */
223 if (__put_user(0, mach+3) || __put_user(0, mach+4))
224 return -EFAULT;
225 }
226 return 0;
227}
228
229long ppc_newuname(struct new_utsname __user * name)
230{
231 int err = 0;
232
233 down_read(&uts_sem);
234 if (copy_to_user(name, utsname(), sizeof(*name)))
235 err = -EFAULT;
236 up_read(&uts_sem);
237 if (!err)
238 err = override_machine(name->machine);
239 return err;
240}
241
242int sys_uname(struct old_utsname __user *name)
243{
244 int err = 0;
245
246 down_read(&uts_sem);
247 if (copy_to_user(name, utsname(), sizeof(*name)))
248 err = -EFAULT;
249 up_read(&uts_sem);
250 if (!err)
251 err = override_machine(name->machine);
252 return err;
253}
254
255int sys_olduname(struct oldold_utsname __user *name)
256{
257 int error;
258
259 if (!access_ok(VERIFY_WRITE, name, sizeof(struct oldold_utsname)))
260 return -EFAULT;
261
262 down_read(&uts_sem);
263 error = __copy_to_user(&name->sysname, &utsname()->sysname,
264 __OLD_UTS_LEN);
265 error |= __put_user(0, name->sysname + __OLD_UTS_LEN);
266 error |= __copy_to_user(&name->nodename, &utsname()->nodename,
267 __OLD_UTS_LEN);
268 error |= __put_user(0, name->nodename + __OLD_UTS_LEN);
269 error |= __copy_to_user(&name->release, &utsname()->release,
270 __OLD_UTS_LEN);
271 error |= __put_user(0, name->release + __OLD_UTS_LEN);
272 error |= __copy_to_user(&name->version, &utsname()->version,
273 __OLD_UTS_LEN);
274 error |= __put_user(0, name->version + __OLD_UTS_LEN);
275 error |= __copy_to_user(&name->machine, &utsname()->machine,
276 __OLD_UTS_LEN);
277 error |= override_machine(name->machine);
278 up_read(&uts_sem);
279
280 return error? -EFAULT: 0;
281}
282
283long ppc_fadvise64_64(int fd, int advice, u32 offset_high, u32 offset_low, 119long ppc_fadvise64_64(int fd, int advice, u32 offset_high, u32 offset_low,
284 u32 len_high, u32 len_low) 120 u32 len_high, u32 len_low)
285{ 121{
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-23 21:04:16 -0500