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-rw-r--r--arch/powerpc/kernel/swsusp_32.S2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/powerpc/kernel/swsusp_32.S b/arch/powerpc/kernel/swsusp_32.S
index b0754e237438..ba4dee3d233f 100644
--- a/arch/powerpc/kernel/swsusp_32.S
+++ b/arch/powerpc/kernel/swsusp_32.S
@@ -143,7 +143,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
143 143
144 /* Disable MSR:DR to make sure we don't take a TLB or 144 /* Disable MSR:DR to make sure we don't take a TLB or
145 * hash miss during the copy, as our hash table will 145 * hash miss during the copy, as our hash table will
146 * for a while be unuseable. For .text, we assume we are 146 * for a while be unusable. For .text, we assume we are
147 * covered by a BAT. This works only for non-G5 at this 147 * covered by a BAT. This works only for non-G5 at this
148 * point. G5 will need a better approach, possibly using 148 * point. G5 will need a better approach, possibly using
149 * a small temporary hash table filled with large mappings, 149 * a small temporary hash table filled with large mappings,