diff options
Diffstat (limited to 'arch/powerpc/kernel/power5-pmu.c')
| -rw-r--r-- | arch/powerpc/kernel/power5-pmu.c | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/arch/powerpc/kernel/power5-pmu.c b/arch/powerpc/kernel/power5-pmu.c index 1b44c5fca189..670cf10b91e8 100644 --- a/arch/powerpc/kernel/power5-pmu.c +++ b/arch/powerpc/kernel/power5-pmu.c | |||
| @@ -556,6 +556,46 @@ static int power5_generic_events[] = { | |||
| 556 | [PERF_COUNT_BRANCH_MISSES] = 0x230e5, /* BR_MPRED_CR */ | 556 | [PERF_COUNT_BRANCH_MISSES] = 0x230e5, /* BR_MPRED_CR */ |
| 557 | }; | 557 | }; |
| 558 | 558 | ||
| 559 | #define C(x) PERF_COUNT_HW_CACHE_##x | ||
| 560 | |||
| 561 | /* | ||
| 562 | * Table of generalized cache-related events. | ||
| 563 | * 0 means not supported, -1 means nonsensical, other values | ||
| 564 | * are event codes. | ||
| 565 | */ | ||
| 566 | static int power5_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { | ||
| 567 | [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */ | ||
| 568 | [C(OP_READ)] = { 0x4c1090, 0x3c1088 }, | ||
| 569 | [C(OP_WRITE)] = { 0x3c1090, 0xc10c3 }, | ||
| 570 | [C(OP_PREFETCH)] = { 0xc70e7, 0 }, | ||
| 571 | }, | ||
| 572 | [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */ | ||
| 573 | [C(OP_READ)] = { 0, 0 }, | ||
| 574 | [C(OP_WRITE)] = { -1, -1 }, | ||
| 575 | [C(OP_PREFETCH)] = { 0, 0 }, | ||
| 576 | }, | ||
| 577 | [C(L2)] = { /* RESULT_ACCESS RESULT_MISS */ | ||
| 578 | [C(OP_READ)] = { 0, 0x3c309b }, | ||
| 579 | [C(OP_WRITE)] = { 0, 0 }, | ||
| 580 | [C(OP_PREFETCH)] = { 0xc50c3, 0 }, | ||
| 581 | }, | ||
| 582 | [C(DTLB)] = { /* RESULT_ACCESS RESULT_MISS */ | ||
| 583 | [C(OP_READ)] = { 0x2c4090, 0x800c4 }, | ||
| 584 | [C(OP_WRITE)] = { -1, -1 }, | ||
| 585 | [C(OP_PREFETCH)] = { -1, -1 }, | ||
| 586 | }, | ||
| 587 | [C(ITLB)] = { /* RESULT_ACCESS RESULT_MISS */ | ||
| 588 | [C(OP_READ)] = { 0, 0x800c0 }, | ||
| 589 | [C(OP_WRITE)] = { -1, -1 }, | ||
| 590 | [C(OP_PREFETCH)] = { -1, -1 }, | ||
| 591 | }, | ||
| 592 | [C(BPU)] = { /* RESULT_ACCESS RESULT_MISS */ | ||
| 593 | [C(OP_READ)] = { 0x230e4, 0x230e5 }, | ||
| 594 | [C(OP_WRITE)] = { -1, -1 }, | ||
| 595 | [C(OP_PREFETCH)] = { -1, -1 }, | ||
| 596 | }, | ||
| 597 | }; | ||
| 598 | |||
| 559 | struct power_pmu power5_pmu = { | 599 | struct power_pmu power5_pmu = { |
| 560 | .n_counter = 6, | 600 | .n_counter = 6, |
| 561 | .max_alternatives = MAX_ALT, | 601 | .max_alternatives = MAX_ALT, |
| @@ -567,4 +607,5 @@ struct power_pmu power5_pmu = { | |||
| 567 | .disable_pmc = power5_disable_pmc, | 607 | .disable_pmc = power5_disable_pmc, |
| 568 | .n_generic = ARRAY_SIZE(power5_generic_events), | 608 | .n_generic = ARRAY_SIZE(power5_generic_events), |
| 569 | .generic_events = power5_generic_events, | 609 | .generic_events = power5_generic_events, |
| 610 | .cache_events = &power5_cache_events, | ||
| 570 | }; | 611 | }; |