1 files changed, 41 insertions, 38 deletions

diff --git a/arch/powerpc/kernel/power5+-pmu.c b/arch/powerpc/kernel/power5+-pmu.c
index 41e5d2d958d4..aef144d503b0 100644
--- a/arch/powerpc/kernel/power5+-pmu.c
+++ b/arch/powerpc/kernel/power5+-pmu.c
@@ -126,20 +126,21 @@ static const int grsel_shift[8] = {
 };
 
 /* Masks and values for using events from the various units */
-static u64 unit_cons[PM_LASTUNIT+1][2] = {
-        [PM_FPU] =   { 0x3200000000ull, 0x0100000000ull },
-        [PM_ISU0] =  { 0x0200000000ull, 0x0080000000ull },
-        [PM_ISU1] =  { 0x3200000000ull, 0x3100000000ull },
-        [PM_IFU] =   { 0x3200000000ull, 0x2100000000ull },
-        [PM_IDU] =   { 0x0e00000000ull, 0x0040000000ull },
-        [PM_GRS] =   { 0x0e00000000ull, 0x0c40000000ull },
+static unsigned long unit_cons[PM_LASTUNIT+1][2] = {
+        [PM_FPU] =   { 0x3200000000ul, 0x0100000000ul },
+        [PM_ISU0] =  { 0x0200000000ul, 0x0080000000ul },
+        [PM_ISU1] =  { 0x3200000000ul, 0x3100000000ul },
+        [PM_IFU] =   { 0x3200000000ul, 0x2100000000ul },
+        [PM_IDU] =   { 0x0e00000000ul, 0x0040000000ul },
+        [PM_GRS] =   { 0x0e00000000ul, 0x0c40000000ul },
 };
 
-static int power5p_get_constraint(u64 event, u64 *maskp, u64 *valp)
+static int power5p_get_constraint(u64 event, unsigned long *maskp,
+                                  unsigned long *valp)
 {
         int pmc, byte, unit, sh;
         int bit, fmask;
-        u64 mask = 0, value = 0;
+        unsigned long mask = 0, value = 0;
 
         pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
         if (pmc) {
@@ -171,17 +172,18 @@ static int power5p_get_constraint(u64 event, u64 *maskp, u64 *valp)
                         bit = event & 7;
                         fmask = (bit == 6)? 7: 3;
                         sh = grsel_shift[bit];
-                        mask |= (u64)fmask << sh;
-                        value |= (u64)((event >> PM_GRS_SH) & fmask) << sh;
+                        mask |= (unsigned long)fmask << sh;
+                        value |= (unsigned long)((event >> PM_GRS_SH) & fmask)
+                                << sh;
                 }
                 /* Set byte lane select field */
-                mask  |= 0xfULL << (24 - 4 * byte);
-                value |= (u64)unit << (24 - 4 * byte);
+                mask  |= 0xfUL << (24 - 4 * byte);
+                value |= (unsigned long)unit << (24 - 4 * byte);
         }
         if (pmc < 5) {
                 /* need a counter from PMC1-4 set */
-                mask  |= 0x8000000000000ull;
-                value |= 0x1000000000000ull;
+                mask  |= 0x8000000000000ul;
+                value |= 0x1000000000000ul;
         }
         *maskp = mask;
         *valp = value;
@@ -452,10 +454,10 @@ static int power5p_marked_instr_event(u64 event)
 }
 
 static int power5p_compute_mmcr(u64 event[], int n_ev,
-                                unsigned int hwc[], u64 mmcr[])
+                                unsigned int hwc[], unsigned long mmcr[])
 {
-        u64 mmcr1 = 0;
-        u64 mmcra = 0;
+        unsigned long mmcr1 = 0;
+        unsigned long mmcra = 0;
         unsigned int pmc, unit, byte, psel;
         unsigned int ttm;
         int i, isbus, bit, grsel;
@@ -517,7 +519,7 @@ static int power5p_compute_mmcr(u64 event[], int n_ev,
                         continue;
                 if (ttmuse++)
                         return -1;
-                mmcr1 |= (u64)i << MMCR1_TTM0SEL_SH;
+                mmcr1 |= (unsigned long)i << MMCR1_TTM0SEL_SH;
         }
         ttmuse = 0;
         for (; i <= PM_GRS; ++i) {
@@ -525,7 +527,7 @@ static int power5p_compute_mmcr(u64 event[], int n_ev,
                         continue;
                 if (ttmuse++)
                         return -1;
-                mmcr1 |= (u64)(i & 3) << MMCR1_TTM1SEL_SH;
+                mmcr1 |= (unsigned long)(i & 3) << MMCR1_TTM1SEL_SH;
         }
         if (ttmuse > 1)
                 return -1;
@@ -540,10 +542,11 @@ static int power5p_compute_mmcr(u64 event[], int n_ev,
                         unit = PM_ISU0_ALT;
                 } else if (unit == PM_LSU1 + 1) {
                         /* select lower word of LSU1 for this byte */
-                        mmcr1 |= 1ull << (MMCR1_TTM3SEL_SH + 3 - byte);
+                        mmcr1 |= 1ul << (MMCR1_TTM3SEL_SH + 3 - byte);
                 }
                 ttm = unit >> 2;
-                mmcr1 |= (u64)ttm << (MMCR1_TD_CP_DBG0SEL_SH - 2 * byte);
+                mmcr1 |= (unsigned long)ttm
+                        << (MMCR1_TD_CP_DBG0SEL_SH - 2 * byte);
         }
 
         /* Second pass: assign PMCs, set PMCxSEL and PMCx_ADDER_SEL fields */
@@ -568,7 +571,7 @@ static int power5p_compute_mmcr(u64 event[], int n_ev,
                         if (isbus && (byte & 2) &&
                             (psel == 8 || psel == 0x10 || psel == 0x28))
                                 /* add events on higher-numbered bus */
-                                mmcr1 |= 1ull << (MMCR1_PMC1_ADDER_SEL_SH - pmc);
+                                mmcr1 |= 1ul << (MMCR1_PMC1_ADDER_SEL_SH - pmc);
                 } else {
                         /* Instructions or run cycles on PMC5/6 */
                         --pmc;
@@ -576,7 +579,7 @@ static int power5p_compute_mmcr(u64 event[], int n_ev,
                 if (isbus && unit == PM_GRS) {
                         bit = psel & 7;
                         grsel = (event[i] >> PM_GRS_SH) & PM_GRS_MSK;
-                        mmcr1 |= (u64)grsel << grsel_shift[bit];
+                        mmcr1 |= (unsigned long)grsel << grsel_shift[bit];
                 }
                 if (power5p_marked_instr_event(event[i]))
                         mmcra |= MMCRA_SAMPLE_ENABLE;
@@ -599,7 +602,7 @@ static int power5p_compute_mmcr(u64 event[], int n_ev,
         return 0;
 }
 
-static void power5p_disable_pmc(unsigned int pmc, u64 mmcr[])
+static void power5p_disable_pmc(unsigned int pmc, unsigned long mmcr[])
 {
         if (pmc <= 3)
                 mmcr[1] &= ~(0x7fUL << MMCR1_PMCSEL_SH(pmc));
@@ -655,17 +658,17 @@ static int power5p_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
 };
 
 struct power_pmu power5p_pmu = {
-        .n_counter = 6,
-        .max_alternatives = MAX_ALT,
-        .add_fields = 0x7000000000055ull,
-        .test_adder = 0x3000040000000ull,
-        .compute_mmcr = power5p_compute_mmcr,
-        .get_constraint = power5p_get_constraint,
-        .get_alternatives = power5p_get_alternatives,
-        .disable_pmc = power5p_disable_pmc,
-        .limited_pmc_event = power5p_limited_pmc_event,
-        .flags = PPMU_LIMITED_PMC5_6,
-        .n_generic = ARRAY_SIZE(power5p_generic_events),
-        .generic_events = power5p_generic_events,
-        .cache_events = &power5p_cache_events,
+        .n_counter              = 6,
+        .max_alternatives       = MAX_ALT,
+        .add_fields             = 0x7000000000055ul,
+        .test_adder             = 0x3000040000000ul,
+        .compute_mmcr           = power5p_compute_mmcr,
+        .get_constraint         = power5p_get_constraint,
+        .get_alternatives       = power5p_get_alternatives,
+        .disable_pmc            = power5p_disable_pmc,
+        .limited_pmc_event      = power5p_limited_pmc_event,
+        .flags                  = PPMU_LIMITED_PMC5_6,
+        .n_generic              = ARRAY_SIZE(power5p_generic_events),
+        .generic_events         = power5p_generic_events,
+        .cache_events           = &power5p_cache_events,
 };