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Diffstat (limited to 'arch/powerpc/kernel/pci_64.c')
-rw-r--r--arch/powerpc/kernel/pci_64.c444
1 files changed, 58 insertions, 386 deletions
diff --git a/arch/powerpc/kernel/pci_64.c b/arch/powerpc/kernel/pci_64.c
index 9f63bdcb0bdf..52750745edfd 100644
--- a/arch/powerpc/kernel/pci_64.c
+++ b/arch/powerpc/kernel/pci_64.c
@@ -31,7 +31,6 @@
31#include <asm/byteorder.h> 31#include <asm/byteorder.h>
32#include <asm/machdep.h> 32#include <asm/machdep.h>
33#include <asm/ppc-pci.h> 33#include <asm/ppc-pci.h>
34#include <asm/firmware.h>
35 34
36#ifdef DEBUG 35#ifdef DEBUG
37#include <asm/udbg.h> 36#include <asm/udbg.h>
@@ -41,10 +40,6 @@
41#endif 40#endif
42 41
43unsigned long pci_probe_only = 1; 42unsigned long pci_probe_only = 1;
44int pci_assign_all_buses = 0;
45
46static void fixup_resource(struct resource *res, struct pci_dev *dev);
47static void do_bus_setup(struct pci_bus *bus);
48 43
49/* pci_io_base -- the base address from which io bars are offsets. 44/* pci_io_base -- the base address from which io bars are offsets.
50 * This is the lowest I/O base address (so bar values are always positive), 45 * This is the lowest I/O base address (so bar values are always positive),
@@ -70,139 +65,31 @@ struct dma_mapping_ops *get_pci_dma_ops(void)
70} 65}
71EXPORT_SYMBOL(get_pci_dma_ops); 66EXPORT_SYMBOL(get_pci_dma_ops);
72 67
73static void fixup_broken_pcnet32(struct pci_dev* dev)
74{
75 if ((dev->class>>8 == PCI_CLASS_NETWORK_ETHERNET)) {
76 dev->vendor = PCI_VENDOR_ID_AMD;
77 pci_write_config_word(dev, PCI_VENDOR_ID, PCI_VENDOR_ID_AMD);
78 }
79}
80DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TRIDENT, PCI_ANY_ID, fixup_broken_pcnet32);
81 68
82void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, 69int pci_set_dma_mask(struct pci_dev *dev, u64 mask)
83 struct resource *res)
84{ 70{
85 unsigned long offset = 0; 71 return dma_set_mask(&dev->dev, mask);
86 struct pci_controller *hose = pci_bus_to_host(dev->bus);
87
88 if (!hose)
89 return;
90
91 if (res->flags & IORESOURCE_IO)
92 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
93
94 if (res->flags & IORESOURCE_MEM)
95 offset = hose->pci_mem_offset;
96
97 region->start = res->start - offset;
98 region->end = res->end - offset;
99} 72}
100 73
101void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, 74int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
102 struct pci_bus_region *region)
103{ 75{
104 unsigned long offset = 0; 76 int rc;
105 struct pci_controller *hose = pci_bus_to_host(dev->bus);
106
107 if (!hose)
108 return;
109 77
110 if (res->flags & IORESOURCE_IO) 78 rc = dma_set_mask(&dev->dev, mask);
111 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 79 dev->dev.coherent_dma_mask = dev->dma_mask;
112 80
113 if (res->flags & IORESOURCE_MEM) 81 return rc;
114 offset = hose->pci_mem_offset;
115
116 res->start = region->start + offset;
117 res->end = region->end + offset;
118} 82}
119 83
120#ifdef CONFIG_HOTPLUG 84static void fixup_broken_pcnet32(struct pci_dev* dev)
121EXPORT_SYMBOL(pcibios_resource_to_bus);
122EXPORT_SYMBOL(pcibios_bus_to_resource);
123#endif
124
125/*
126 * We need to avoid collisions with `mirrored' VGA ports
127 * and other strange ISA hardware, so we always want the
128 * addresses to be allocated in the 0x000-0x0ff region
129 * modulo 0x400.
130 *
131 * Why? Because some silly external IO cards only decode
132 * the low 10 bits of the IO address. The 0x00-0xff region
133 * is reserved for motherboard devices that decode all 16
134 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
135 * but we want to try to avoid allocating at 0x2900-0x2bff
136 * which might have be mirrored at 0x0100-0x03ff..
137 */
138void pcibios_align_resource(void *data, struct resource *res,
139 resource_size_t size, resource_size_t align)
140{
141 struct pci_dev *dev = data;
142 struct pci_controller *hose = pci_bus_to_host(dev->bus);
143 resource_size_t start = res->start;
144 unsigned long alignto;
145
146 if (res->flags & IORESOURCE_IO) {
147 unsigned long offset = (unsigned long)hose->io_base_virt -
148 _IO_BASE;
149 /* Make sure we start at our min on all hoses */
150 if (start - offset < PCIBIOS_MIN_IO)
151 start = PCIBIOS_MIN_IO + offset;
152
153 /*
154 * Put everything into 0x00-0xff region modulo 0x400
155 */
156 if (start & 0x300)
157 start = (start + 0x3ff) & ~0x3ff;
158
159 } else if (res->flags & IORESOURCE_MEM) {
160 /* Make sure we start at our min on all hoses */
161 if (start - hose->pci_mem_offset < PCIBIOS_MIN_MEM)
162 start = PCIBIOS_MIN_MEM + hose->pci_mem_offset;
163
164 /* Align to multiple of size of minimum base. */
165 alignto = max(0x1000UL, align);
166 start = ALIGN(start, alignto);
167 }
168
169 res->start = start;
170}
171
172void __devinit pcibios_claim_one_bus(struct pci_bus *b)
173{ 85{
174 struct pci_dev *dev; 86 if ((dev->class>>8 == PCI_CLASS_NETWORK_ETHERNET)) {
175 struct pci_bus *child_bus; 87 dev->vendor = PCI_VENDOR_ID_AMD;
176 88 pci_write_config_word(dev, PCI_VENDOR_ID, PCI_VENDOR_ID_AMD);
177 list_for_each_entry(dev, &b->devices, bus_list) {
178 int i;
179
180 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
181 struct resource *r = &dev->resource[i];
182
183 if (r->parent || !r->start || !r->flags)
184 continue;
185 pci_claim_resource(dev, i);
186 }
187 } 89 }
188
189 list_for_each_entry(child_bus, &b->children, node)
190 pcibios_claim_one_bus(child_bus);
191} 90}
192#ifdef CONFIG_HOTPLUG 91DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TRIDENT, PCI_ANY_ID, fixup_broken_pcnet32);
193EXPORT_SYMBOL_GPL(pcibios_claim_one_bus);
194#endif
195
196static void __init pcibios_claim_of_setup(void)
197{
198 struct pci_bus *b;
199
200 if (firmware_has_feature(FW_FEATURE_ISERIES))
201 return;
202 92
203 list_for_each_entry(b, &pci_root_buses, node)
204 pcibios_claim_one_bus(b);
205}
206 93
207static u32 get_int_prop(struct device_node *np, const char *name, u32 def) 94static u32 get_int_prop(struct device_node *np, const char *name, u32 def)
208{ 95{
@@ -270,7 +157,6 @@ static void pci_parse_of_addrs(struct device_node *node, struct pci_dev *dev)
270 res->end = base + size - 1; 157 res->end = base + size - 1;
271 res->flags = flags; 158 res->flags = flags;
272 res->name = pci_name(dev); 159 res->name = pci_name(dev);
273 fixup_resource(res, dev);
274 } 160 }
275} 161}
276 162
@@ -339,16 +225,17 @@ struct pci_dev *of_create_pci_dev(struct device_node *node,
339EXPORT_SYMBOL(of_create_pci_dev); 225EXPORT_SYMBOL(of_create_pci_dev);
340 226
341void __devinit of_scan_bus(struct device_node *node, 227void __devinit of_scan_bus(struct device_node *node,
342 struct pci_bus *bus) 228 struct pci_bus *bus)
343{ 229{
344 struct device_node *child = NULL; 230 struct device_node *child;
345 const u32 *reg; 231 const u32 *reg;
346 int reglen, devfn; 232 int reglen, devfn;
347 struct pci_dev *dev; 233 struct pci_dev *dev;
348 234
349 DBG("of_scan_bus(%s) bus no %d... \n", node->full_name, bus->number); 235 DBG("of_scan_bus(%s) bus no %d... \n", node->full_name, bus->number);
350 236
351 while ((child = of_get_next_child(node, child)) != NULL) { 237 /* Scan direct children */
238 for_each_child_of_node(node, child) {
352 DBG(" * %s\n", child->full_name); 239 DBG(" * %s\n", child->full_name);
353 reg = of_get_property(child, "reg", &reglen); 240 reg = of_get_property(child, "reg", &reglen);
354 if (reg == NULL || reglen < 20) 241 if (reg == NULL || reglen < 20)
@@ -359,19 +246,26 @@ void __devinit of_scan_bus(struct device_node *node,
359 dev = of_create_pci_dev(child, bus, devfn); 246 dev = of_create_pci_dev(child, bus, devfn);
360 if (!dev) 247 if (!dev)
361 continue; 248 continue;
362 DBG("dev header type: %x\n", dev->hdr_type); 249 DBG(" dev header type: %x\n", dev->hdr_type);
250 }
363 251
252 /* Ally all fixups */
253 pcibios_fixup_of_probed_bus(bus);
254
255 /* Now scan child busses */
256 list_for_each_entry(dev, &bus->devices, bus_list) {
364 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || 257 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
365 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS) 258 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS) {
366 of_scan_pci_bridge(child, dev); 259 struct device_node *child = pci_device_to_OF_node(dev);
260 if (dev)
261 of_scan_pci_bridge(child, dev);
262 }
367 } 263 }
368
369 do_bus_setup(bus);
370} 264}
371EXPORT_SYMBOL(of_scan_bus); 265EXPORT_SYMBOL(of_scan_bus);
372 266
373void __devinit of_scan_pci_bridge(struct device_node *node, 267void __devinit of_scan_pci_bridge(struct device_node *node,
374 struct pci_dev *dev) 268 struct pci_dev *dev)
375{ 269{
376 struct pci_bus *bus; 270 struct pci_bus *bus;
377 const u32 *busrange, *ranges; 271 const u32 *busrange, *ranges;
@@ -441,7 +335,6 @@ void __devinit of_scan_pci_bridge(struct device_node *node,
441 res->start = of_read_number(&ranges[1], 2); 335 res->start = of_read_number(&ranges[1], 2);
442 res->end = res->start + size - 1; 336 res->end = res->start + size - 1;
443 res->flags = flags; 337 res->flags = flags;
444 fixup_resource(res, dev);
445 } 338 }
446 sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus), 339 sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
447 bus->number); 340 bus->number);
@@ -462,12 +355,12 @@ EXPORT_SYMBOL(of_scan_pci_bridge);
462void __devinit scan_phb(struct pci_controller *hose) 355void __devinit scan_phb(struct pci_controller *hose)
463{ 356{
464 struct pci_bus *bus; 357 struct pci_bus *bus;
465 struct device_node *node = hose->arch_data; 358 struct device_node *node = hose->dn;
466 int i, mode; 359 int i, mode;
467 struct resource *res;
468 360
469 DBG("Scanning PHB %s\n", node ? node->full_name : "<NO NAME>"); 361 DBG("PCI: Scanning PHB %s\n", node ? node->full_name : "<NO NAME>");
470 362
363 /* Create an empty bus for the toplevel */
471 bus = pci_create_bus(hose->parent, hose->first_busno, hose->ops, node); 364 bus = pci_create_bus(hose->parent, hose->first_busno, hose->ops, node);
472 if (bus == NULL) { 365 if (bus == NULL) {
473 printk(KERN_ERR "Failed to create bus for PCI domain %04x\n", 366 printk(KERN_ERR "Failed to create bus for PCI domain %04x\n",
@@ -477,27 +370,27 @@ void __devinit scan_phb(struct pci_controller *hose)
477 bus->secondary = hose->first_busno; 370 bus->secondary = hose->first_busno;
478 hose->bus = bus; 371 hose->bus = bus;
479 372
480 if (!firmware_has_feature(FW_FEATURE_ISERIES)) 373 /* Get some IO space for the new PHB */
481 pcibios_map_io_space(bus); 374 pcibios_map_io_space(bus);
482
483 bus->resource[0] = res = &hose->io_resource;
484 if (res->flags && request_resource(&ioport_resource, res)) {
485 printk(KERN_ERR "Failed to request PCI IO region "
486 "on PCI domain %04x\n", hose->global_number);
487 DBG("res->start = 0x%016lx, res->end = 0x%016lx\n",
488 res->start, res->end);
489 }
490 375
376 /* Wire up PHB bus resources */
377 DBG("PCI: PHB IO resource = %016lx-%016lx [%lx]\n",
378 hose->io_resource.start, hose->io_resource.end,
379 hose->io_resource.flags);
380 bus->resource[0] = &hose->io_resource;
491 for (i = 0; i < 3; ++i) { 381 for (i = 0; i < 3; ++i) {
492 res = &hose->mem_resources[i]; 382 DBG("PCI: PHB MEM resource %d = %016lx-%016lx [%lx]\n", i,
493 bus->resource[i+1] = res; 383 hose->mem_resources[i].start,
494 if (res->flags && request_resource(&iomem_resource, res)) 384 hose->mem_resources[i].end,
495 printk(KERN_ERR "Failed to request PCI memory region " 385 hose->mem_resources[i].flags);
496 "on PCI domain %04x\n", hose->global_number); 386 bus->resource[i+1] = &hose->mem_resources[i];
497 } 387 }
388 DBG("PCI: PHB MEM offset = %016lx\n", hose->pci_mem_offset);
389 DBG("PCI: PHB IO offset = %08lx\n",
390 (unsigned long)hose->io_base_virt - _IO_BASE);
498 391
392 /* Get probe mode and perform scan */
499 mode = PCI_PROBE_NORMAL; 393 mode = PCI_PROBE_NORMAL;
500
501 if (node && ppc_md.pci_probe_mode) 394 if (node && ppc_md.pci_probe_mode)
502 mode = ppc_md.pci_probe_mode(bus); 395 mode = ppc_md.pci_probe_mode(bus);
503 DBG(" probe mode: %d\n", mode); 396 DBG(" probe mode: %d\n", mode);
@@ -514,15 +407,15 @@ static int __init pcibios_init(void)
514{ 407{
515 struct pci_controller *hose, *tmp; 408 struct pci_controller *hose, *tmp;
516 409
410 printk(KERN_INFO "PCI: Probing PCI hardware\n");
411
517 /* For now, override phys_mem_access_prot. If we need it, 412 /* For now, override phys_mem_access_prot. If we need it,
518 * later, we may move that initialization to each ppc_md 413 * later, we may move that initialization to each ppc_md
519 */ 414 */
520 ppc_md.phys_mem_access_prot = pci_phys_mem_access_prot; 415 ppc_md.phys_mem_access_prot = pci_phys_mem_access_prot;
521 416
522 if (firmware_has_feature(FW_FEATURE_ISERIES)) 417 if (pci_probe_only)
523 iSeries_pcibios_init(); 418 ppc_pci_flags |= PPC_PCI_PROBE_ONLY;
524
525 printk(KERN_DEBUG "PCI: Probing PCI hardware\n");
526 419
527 /* Scan all of the recorded PCI controllers. */ 420 /* Scan all of the recorded PCI controllers. */
528 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 421 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
@@ -530,19 +423,8 @@ static int __init pcibios_init(void)
530 pci_bus_add_devices(hose->bus); 423 pci_bus_add_devices(hose->bus);
531 } 424 }
532 425
533 if (!firmware_has_feature(FW_FEATURE_ISERIES)) { 426 /* Call common code to handle resource allocation */
534 if (pci_probe_only) 427 pcibios_resource_survey();
535 pcibios_claim_of_setup();
536 else
537 /* FIXME: `else' will be removed when
538 pci_assign_unassigned_resources() is able to work
539 correctly with [partially] allocated PCI tree. */
540 pci_assign_unassigned_resources();
541 }
542
543 /* Call machine dependent final fixup */
544 if (ppc_md.pcibios_fixup)
545 ppc_md.pcibios_fixup();
546 428
547 printk(KERN_DEBUG "PCI: Probing PCI hardware done\n"); 429 printk(KERN_DEBUG "PCI: Probing PCI hardware done\n");
548 430
@@ -551,141 +433,6 @@ static int __init pcibios_init(void)
551 433
552subsys_initcall(pcibios_init); 434subsys_initcall(pcibios_init);
553 435
554int pcibios_enable_device(struct pci_dev *dev, int mask)
555{
556 u16 cmd, oldcmd;
557 int i;
558
559 pci_read_config_word(dev, PCI_COMMAND, &cmd);
560 oldcmd = cmd;
561
562 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
563 struct resource *res = &dev->resource[i];
564
565 /* Only set up the requested stuff */
566 if (!(mask & (1<<i)))
567 continue;
568
569 if (res->flags & IORESOURCE_IO)
570 cmd |= PCI_COMMAND_IO;
571 if (res->flags & IORESOURCE_MEM)
572 cmd |= PCI_COMMAND_MEMORY;
573 }
574
575 if (cmd != oldcmd) {
576 printk(KERN_DEBUG "PCI: Enabling device: (%s), cmd %x\n",
577 pci_name(dev), cmd);
578 /* Enable the appropriate bits in the PCI command register. */
579 pci_write_config_word(dev, PCI_COMMAND, cmd);
580 }
581 return 0;
582}
583
584/* Decide whether to display the domain number in /proc */
585int pci_proc_domain(struct pci_bus *bus)
586{
587 if (firmware_has_feature(FW_FEATURE_ISERIES))
588 return 0;
589 else {
590 struct pci_controller *hose = pci_bus_to_host(bus);
591 return hose->buid != 0;
592 }
593}
594
595void __devinit pci_process_bridge_OF_ranges(struct pci_controller *hose,
596 struct device_node *dev, int prim)
597{
598 const unsigned int *ranges;
599 unsigned int pci_space;
600 unsigned long size;
601 int rlen = 0;
602 int memno = 0;
603 struct resource *res;
604 int np, na = of_n_addr_cells(dev);
605 unsigned long pci_addr, cpu_phys_addr;
606
607 np = na + 5;
608
609 /* From "PCI Binding to 1275"
610 * The ranges property is laid out as an array of elements,
611 * each of which comprises:
612 * cells 0 - 2: a PCI address
613 * cells 3 or 3+4: a CPU physical address
614 * (size depending on dev->n_addr_cells)
615 * cells 4+5 or 5+6: the size of the range
616 */
617 ranges = of_get_property(dev, "ranges", &rlen);
618 if (ranges == NULL)
619 return;
620 hose->io_base_phys = 0;
621 while ((rlen -= np * sizeof(unsigned int)) >= 0) {
622 res = NULL;
623 pci_space = ranges[0];
624 pci_addr = ((unsigned long)ranges[1] << 32) | ranges[2];
625 cpu_phys_addr = of_translate_address(dev, &ranges[3]);
626 size = ((unsigned long)ranges[na+3] << 32) | ranges[na+4];
627 ranges += np;
628 if (size == 0)
629 continue;
630
631 /* Now consume following elements while they are contiguous */
632 while (rlen >= np * sizeof(unsigned int)) {
633 unsigned long addr, phys;
634
635 if (ranges[0] != pci_space)
636 break;
637 addr = ((unsigned long)ranges[1] << 32) | ranges[2];
638 phys = ranges[3];
639 if (na >= 2)
640 phys = (phys << 32) | ranges[4];
641 if (addr != pci_addr + size ||
642 phys != cpu_phys_addr + size)
643 break;
644
645 size += ((unsigned long)ranges[na+3] << 32)
646 | ranges[na+4];
647 ranges += np;
648 rlen -= np * sizeof(unsigned int);
649 }
650
651 switch ((pci_space >> 24) & 0x3) {
652 case 1: /* I/O space */
653 hose->io_base_phys = cpu_phys_addr - pci_addr;
654 /* handle from 0 to top of I/O window */
655 hose->pci_io_size = pci_addr + size;
656
657 res = &hose->io_resource;
658 res->flags = IORESOURCE_IO;
659 res->start = pci_addr;
660 DBG("phb%d: IO 0x%lx -> 0x%lx\n", hose->global_number,
661 res->start, res->start + size - 1);
662 break;
663 case 2: /* memory space */
664 memno = 0;
665 while (memno < 3 && hose->mem_resources[memno].flags)
666 ++memno;
667
668 if (memno == 0)
669 hose->pci_mem_offset = cpu_phys_addr - pci_addr;
670 if (memno < 3) {
671 res = &hose->mem_resources[memno];
672 res->flags = IORESOURCE_MEM;
673 res->start = cpu_phys_addr;
674 DBG("phb%d: MEM 0x%lx -> 0x%lx\n", hose->global_number,
675 res->start, res->start + size - 1);
676 }
677 break;
678 }
679 if (res != NULL) {
680 res->name = dev->full_name;
681 res->end = res->start + size - 1;
682 res->parent = NULL;
683 res->sibling = NULL;
684 res->child = NULL;
685 }
686 }
687}
688
689#ifdef CONFIG_HOTPLUG 436#ifdef CONFIG_HOTPLUG
690 437
691int pcibios_unmap_io_space(struct pci_bus *bus) 438int pcibios_unmap_io_space(struct pci_bus *bus)
@@ -719,8 +466,7 @@ int pcibios_unmap_io_space(struct pci_bus *bus)
719 if (hose->io_base_alloc == 0) 466 if (hose->io_base_alloc == 0)
720 return 0; 467 return 0;
721 468
722 DBG("IO unmapping for PHB %s\n", 469 DBG("IO unmapping for PHB %s\n", hose->dn->full_name);
723 ((struct device_node *)hose->arch_data)->full_name);
724 DBG(" alloc=0x%p\n", hose->io_base_alloc); 470 DBG(" alloc=0x%p\n", hose->io_base_alloc);
725 471
726 /* This is a PHB, we fully unmap the IO area */ 472 /* This is a PHB, we fully unmap the IO area */
@@ -779,8 +525,7 @@ int __devinit pcibios_map_io_space(struct pci_bus *bus)
779 hose->io_base_virt = (void __iomem *)(area->addr + 525 hose->io_base_virt = (void __iomem *)(area->addr +
780 hose->io_base_phys - phys_page); 526 hose->io_base_phys - phys_page);
781 527
782 DBG("IO mapping for PHB %s\n", 528 DBG("IO mapping for PHB %s\n", hose->dn->full_name);
783 ((struct device_node *)hose->arch_data)->full_name);
784 DBG(" phys=0x%016lx, virt=0x%p (alloc=0x%p)\n", 529 DBG(" phys=0x%016lx, virt=0x%p (alloc=0x%p)\n",
785 hose->io_base_phys, hose->io_base_virt, hose->io_base_alloc); 530 hose->io_base_phys, hose->io_base_virt, hose->io_base_alloc);
786 DBG(" size=0x%016lx (alloc=0x%016lx)\n", 531 DBG(" size=0x%016lx (alloc=0x%016lx)\n",
@@ -803,51 +548,13 @@ int __devinit pcibios_map_io_space(struct pci_bus *bus)
803} 548}
804EXPORT_SYMBOL_GPL(pcibios_map_io_space); 549EXPORT_SYMBOL_GPL(pcibios_map_io_space);
805 550
806static void __devinit fixup_resource(struct resource *res, struct pci_dev *dev)
807{
808 struct pci_controller *hose = pci_bus_to_host(dev->bus);
809 unsigned long offset;
810
811 if (res->flags & IORESOURCE_IO) {
812 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
813 res->start += offset;
814 res->end += offset;
815 } else if (res->flags & IORESOURCE_MEM) {
816 res->start += hose->pci_mem_offset;
817 res->end += hose->pci_mem_offset;
818 }
819}
820
821void __devinit pcibios_fixup_device_resources(struct pci_dev *dev,
822 struct pci_bus *bus)
823{
824 /* Update device resources. */
825 int i;
826
827 DBG("%s: Fixup resources:\n", pci_name(dev));
828 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
829 struct resource *res = &dev->resource[i];
830 if (!res->flags)
831 continue;
832
833 DBG(" 0x%02x < %08lx:0x%016lx...0x%016lx\n",
834 i, res->flags, res->start, res->end);
835
836 fixup_resource(res, dev);
837
838 DBG(" > %08lx:0x%016lx...0x%016lx\n",
839 res->flags, res->start, res->end);
840 }
841}
842EXPORT_SYMBOL(pcibios_fixup_device_resources);
843
844void __devinit pcibios_setup_new_device(struct pci_dev *dev) 551void __devinit pcibios_setup_new_device(struct pci_dev *dev)
845{ 552{
846 struct dev_archdata *sd = &dev->dev.archdata; 553 struct dev_archdata *sd = &dev->dev.archdata;
847 554
848 sd->of_node = pci_device_to_OF_node(dev); 555 sd->of_node = pci_device_to_OF_node(dev);
849 556
850 DBG("PCI device %s OF node: %s\n", pci_name(dev), 557 DBG("PCI: device %s OF node: %s\n", pci_name(dev),
851 sd->of_node ? sd->of_node->full_name : "<none>"); 558 sd->of_node ? sd->of_node->full_name : "<none>");
852 559
853 sd->dma_ops = pci_dma_ops; 560 sd->dma_ops = pci_dma_ops;
@@ -861,7 +568,7 @@ void __devinit pcibios_setup_new_device(struct pci_dev *dev)
861} 568}
862EXPORT_SYMBOL(pcibios_setup_new_device); 569EXPORT_SYMBOL(pcibios_setup_new_device);
863 570
864static void __devinit do_bus_setup(struct pci_bus *bus) 571void __devinit pcibios_do_bus_setup(struct pci_bus *bus)
865{ 572{
866 struct pci_dev *dev; 573 struct pci_dev *dev;
867 574
@@ -870,42 +577,7 @@ static void __devinit do_bus_setup(struct pci_bus *bus)
870 577
871 list_for_each_entry(dev, &bus->devices, bus_list) 578 list_for_each_entry(dev, &bus->devices, bus_list)
872 pcibios_setup_new_device(dev); 579 pcibios_setup_new_device(dev);
873
874 /* Read default IRQs and fixup if necessary */
875 list_for_each_entry(dev, &bus->devices, bus_list) {
876 pci_read_irq_line(dev);
877 if (ppc_md.pci_irq_fixup)
878 ppc_md.pci_irq_fixup(dev);
879 }
880}
881
882void __devinit pcibios_fixup_bus(struct pci_bus *bus)
883{
884 struct pci_dev *dev = bus->self;
885 struct device_node *np;
886
887 np = pci_bus_to_OF_node(bus);
888
889 DBG("pcibios_fixup_bus(%s)\n", np ? np->full_name : "<???>");
890
891 if (dev && pci_probe_only &&
892 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
893 /* This is a subordinate bridge */
894
895 pci_read_bridge_bases(bus);
896 pcibios_fixup_device_resources(dev, bus);
897 }
898
899 do_bus_setup(bus);
900
901 if (!pci_probe_only)
902 return;
903
904 list_for_each_entry(dev, &bus->devices, bus_list)
905 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
906 pcibios_fixup_device_resources(dev, bus);
907} 580}
908EXPORT_SYMBOL(pcibios_fixup_bus);
909 581
910unsigned long pci_address_to_pio(phys_addr_t address) 582unsigned long pci_address_to_pio(phys_addr_t address)
911{ 583{