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-rw-r--r--arch/powerpc/kernel/pci-common.c774
1 files changed, 746 insertions, 28 deletions
diff --git a/arch/powerpc/kernel/pci-common.c b/arch/powerpc/kernel/pci-common.c
index 2ae3b6f778a3..980fe32895c0 100644
--- a/arch/powerpc/kernel/pci-common.c
+++ b/arch/powerpc/kernel/pci-common.c
@@ -48,32 +48,26 @@
48static DEFINE_SPINLOCK(hose_spinlock); 48static DEFINE_SPINLOCK(hose_spinlock);
49 49
50/* XXX kill that some day ... */ 50/* XXX kill that some day ... */
51int global_phb_number; /* Global phb counter */ 51static int global_phb_number; /* Global phb counter */
52 52
53extern struct list_head hose_list; 53/* ISA Memory physical address */
54resource_size_t isa_mem_base;
54 55
55/* 56/* Default PCI flags is 0 */
56 * pci_controller(phb) initialized common variables. 57unsigned int ppc_pci_flags;
57 */
58static void __devinit pci_setup_pci_controller(struct pci_controller *hose)
59{
60 memset(hose, 0, sizeof(struct pci_controller));
61
62 spin_lock(&hose_spinlock);
63 hose->global_number = global_phb_number++;
64 list_add_tail(&hose->list_node, &hose_list);
65 spin_unlock(&hose_spinlock);
66}
67 58
68struct pci_controller * pcibios_alloc_controller(struct device_node *dev) 59struct pci_controller *pcibios_alloc_controller(struct device_node *dev)
69{ 60{
70 struct pci_controller *phb; 61 struct pci_controller *phb;
71 62
72 phb = alloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL); 63 phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL);
73 if (phb == NULL) 64 if (phb == NULL)
74 return NULL; 65 return NULL;
75 pci_setup_pci_controller(phb); 66 spin_lock(&hose_spinlock);
76 phb->arch_data = dev; 67 phb->global_number = global_phb_number++;
68 list_add_tail(&phb->list_node, &hose_list);
69 spin_unlock(&hose_spinlock);
70 phb->dn = dev;
77 phb->is_dynamic = mem_init_done; 71 phb->is_dynamic = mem_init_done;
78#ifdef CONFIG_PPC64 72#ifdef CONFIG_PPC64
79 if (dev) { 73 if (dev) {
@@ -126,15 +120,10 @@ int pcibios_vaddr_is_ioport(void __iomem *address)
126 */ 120 */
127int pci_domain_nr(struct pci_bus *bus) 121int pci_domain_nr(struct pci_bus *bus)
128{ 122{
129 if (firmware_has_feature(FW_FEATURE_ISERIES)) 123 struct pci_controller *hose = pci_bus_to_host(bus);
130 return 0;
131 else {
132 struct pci_controller *hose = pci_bus_to_host(bus);
133 124
134 return hose->global_number; 125 return hose->global_number;
135 }
136} 126}
137
138EXPORT_SYMBOL(pci_domain_nr); 127EXPORT_SYMBOL(pci_domain_nr);
139 128
140#ifdef CONFIG_PPC_OF 129#ifdef CONFIG_PPC_OF
@@ -153,7 +142,7 @@ struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node)
153 while(node) { 142 while(node) {
154 struct pci_controller *hose, *tmp; 143 struct pci_controller *hose, *tmp;
155 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) 144 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
156 if (hose->arch_data == node) 145 if (hose->dn == node)
157 return hose; 146 return hose;
158 node = node->parent; 147 node = node->parent;
159 } 148 }
@@ -201,6 +190,20 @@ int pci_read_irq_line(struct pci_dev *pci_dev)
201 struct of_irq oirq; 190 struct of_irq oirq;
202 unsigned int virq; 191 unsigned int virq;
203 192
193 /* The current device-tree that iSeries generates from the HV
194 * PCI informations doesn't contain proper interrupt routing,
195 * and all the fallback would do is print out crap, so we
196 * don't attempt to resolve the interrupts here at all, some
197 * iSeries specific fixup does it.
198 *
199 * In the long run, we will hopefully fix the generated device-tree
200 * instead.
201 */
202#ifdef CONFIG_PPC_ISERIES
203 if (firmware_has_feature(FW_FEATURE_ISERIES))
204 return -1;
205#endif
206
204 DBG("Try to map irq for %s...\n", pci_name(pci_dev)); 207 DBG("Try to map irq for %s...\n", pci_name(pci_dev));
205 208
206#ifdef DEBUG 209#ifdef DEBUG
@@ -222,10 +225,11 @@ int pci_read_irq_line(struct pci_dev *pci_dev)
222 if (pin == 0) 225 if (pin == 0)
223 return -1; 226 return -1;
224 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) || 227 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) ||
225 line == 0xff) { 228 line == 0xff || line == 0) {
226 return -1; 229 return -1;
227 } 230 }
228 DBG(" -> no map ! Using irq line %d from PCI config\n", line); 231 DBG(" -> no map ! Using line %d (pin %d) from PCI config\n",
232 line, pin);
229 233
230 virq = irq_create_mapping(NULL, line); 234 virq = irq_create_mapping(NULL, line);
231 if (virq != NO_IRQ) 235 if (virq != NO_IRQ)
@@ -475,3 +479,717 @@ void pci_resource_to_user(const struct pci_dev *dev, int bar,
475 *start = rsrc->start - offset; 479 *start = rsrc->start - offset;
476 *end = rsrc->end - offset; 480 *end = rsrc->end - offset;
477} 481}
482
483/**
484 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
485 * @hose: newly allocated pci_controller to be setup
486 * @dev: device node of the host bridge
487 * @primary: set if primary bus (32 bits only, soon to be deprecated)
488 *
489 * This function will parse the "ranges" property of a PCI host bridge device
490 * node and setup the resource mapping of a pci controller based on its
491 * content.
492 *
493 * Life would be boring if it wasn't for a few issues that we have to deal
494 * with here:
495 *
496 * - We can only cope with one IO space range and up to 3 Memory space
497 * ranges. However, some machines (thanks Apple !) tend to split their
498 * space into lots of small contiguous ranges. So we have to coalesce.
499 *
500 * - We can only cope with all memory ranges having the same offset
501 * between CPU addresses and PCI addresses. Unfortunately, some bridges
502 * are setup for a large 1:1 mapping along with a small "window" which
503 * maps PCI address 0 to some arbitrary high address of the CPU space in
504 * order to give access to the ISA memory hole.
505 * The way out of here that I've chosen for now is to always set the
506 * offset based on the first resource found, then override it if we
507 * have a different offset and the previous was set by an ISA hole.
508 *
509 * - Some busses have IO space not starting at 0, which causes trouble with
510 * the way we do our IO resource renumbering. The code somewhat deals with
511 * it for 64 bits but I would expect problems on 32 bits.
512 *
513 * - Some 32 bits platforms such as 4xx can have physical space larger than
514 * 32 bits so we need to use 64 bits values for the parsing
515 */
516void __devinit pci_process_bridge_OF_ranges(struct pci_controller *hose,
517 struct device_node *dev,
518 int primary)
519{
520 const u32 *ranges;
521 int rlen;
522 int pna = of_n_addr_cells(dev);
523 int np = pna + 5;
524 int memno = 0, isa_hole = -1;
525 u32 pci_space;
526 unsigned long long pci_addr, cpu_addr, pci_next, cpu_next, size;
527 unsigned long long isa_mb = 0;
528 struct resource *res;
529
530 printk(KERN_INFO "PCI host bridge %s %s ranges:\n",
531 dev->full_name, primary ? "(primary)" : "");
532
533 /* Get ranges property */
534 ranges = of_get_property(dev, "ranges", &rlen);
535 if (ranges == NULL)
536 return;
537
538 /* Parse it */
539 while ((rlen -= np * 4) >= 0) {
540 /* Read next ranges element */
541 pci_space = ranges[0];
542 pci_addr = of_read_number(ranges + 1, 2);
543 cpu_addr = of_translate_address(dev, ranges + 3);
544 size = of_read_number(ranges + pna + 3, 2);
545 ranges += np;
546 if (cpu_addr == OF_BAD_ADDR || size == 0)
547 continue;
548
549 /* Now consume following elements while they are contiguous */
550 for (; rlen >= np * sizeof(u32);
551 ranges += np, rlen -= np * 4) {
552 if (ranges[0] != pci_space)
553 break;
554 pci_next = of_read_number(ranges + 1, 2);
555 cpu_next = of_translate_address(dev, ranges + 3);
556 if (pci_next != pci_addr + size ||
557 cpu_next != cpu_addr + size)
558 break;
559 size += of_read_number(ranges + pna + 3, 2);
560 }
561
562 /* Act based on address space type */
563 res = NULL;
564 switch ((pci_space >> 24) & 0x3) {
565 case 1: /* PCI IO space */
566 printk(KERN_INFO
567 " IO 0x%016llx..0x%016llx -> 0x%016llx\n",
568 cpu_addr, cpu_addr + size - 1, pci_addr);
569
570 /* We support only one IO range */
571 if (hose->pci_io_size) {
572 printk(KERN_INFO
573 " \\--> Skipped (too many) !\n");
574 continue;
575 }
576#ifdef CONFIG_PPC32
577 /* On 32 bits, limit I/O space to 16MB */
578 if (size > 0x01000000)
579 size = 0x01000000;
580
581 /* 32 bits needs to map IOs here */
582 hose->io_base_virt = ioremap(cpu_addr, size);
583
584 /* Expect trouble if pci_addr is not 0 */
585 if (primary)
586 isa_io_base =
587 (unsigned long)hose->io_base_virt;
588#endif /* CONFIG_PPC32 */
589 /* pci_io_size and io_base_phys always represent IO
590 * space starting at 0 so we factor in pci_addr
591 */
592 hose->pci_io_size = pci_addr + size;
593 hose->io_base_phys = cpu_addr - pci_addr;
594
595 /* Build resource */
596 res = &hose->io_resource;
597 res->flags = IORESOURCE_IO;
598 res->start = pci_addr;
599 break;
600 case 2: /* PCI Memory space */
601 printk(KERN_INFO
602 " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
603 cpu_addr, cpu_addr + size - 1, pci_addr,
604 (pci_space & 0x40000000) ? "Prefetch" : "");
605
606 /* We support only 3 memory ranges */
607 if (memno >= 3) {
608 printk(KERN_INFO
609 " \\--> Skipped (too many) !\n");
610 continue;
611 }
612 /* Handles ISA memory hole space here */
613 if (pci_addr == 0) {
614 isa_mb = cpu_addr;
615 isa_hole = memno;
616 if (primary || isa_mem_base == 0)
617 isa_mem_base = cpu_addr;
618 }
619
620 /* We get the PCI/Mem offset from the first range or
621 * the, current one if the offset came from an ISA
622 * hole. If they don't match, bugger.
623 */
624 if (memno == 0 ||
625 (isa_hole >= 0 && pci_addr != 0 &&
626 hose->pci_mem_offset == isa_mb))
627 hose->pci_mem_offset = cpu_addr - pci_addr;
628 else if (pci_addr != 0 &&
629 hose->pci_mem_offset != cpu_addr - pci_addr) {
630 printk(KERN_INFO
631 " \\--> Skipped (offset mismatch) !\n");
632 continue;
633 }
634
635 /* Build resource */
636 res = &hose->mem_resources[memno++];
637 res->flags = IORESOURCE_MEM;
638 if (pci_space & 0x40000000)
639 res->flags |= IORESOURCE_PREFETCH;
640 res->start = cpu_addr;
641 break;
642 }
643 if (res != NULL) {
644 res->name = dev->full_name;
645 res->end = res->start + size - 1;
646 res->parent = NULL;
647 res->sibling = NULL;
648 res->child = NULL;
649 }
650 }
651
652 /* Out of paranoia, let's put the ISA hole last if any */
653 if (isa_hole >= 0 && memno > 0 && isa_hole != (memno-1)) {
654 struct resource tmp = hose->mem_resources[isa_hole];
655 hose->mem_resources[isa_hole] = hose->mem_resources[memno-1];
656 hose->mem_resources[memno-1] = tmp;
657 }
658}
659
660/* Decide whether to display the domain number in /proc */
661int pci_proc_domain(struct pci_bus *bus)
662{
663 struct pci_controller *hose = pci_bus_to_host(bus);
664#ifdef CONFIG_PPC64
665 return hose->buid != 0;
666#else
667 if (!(ppc_pci_flags & PPC_PCI_ENABLE_PROC_DOMAINS))
668 return 0;
669 if (ppc_pci_flags & PPC_PCI_COMPAT_DOMAIN_0)
670 return hose->global_number != 0;
671 return 1;
672#endif
673}
674
675void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
676 struct resource *res)
677{
678 resource_size_t offset = 0, mask = (resource_size_t)-1;
679 struct pci_controller *hose = pci_bus_to_host(dev->bus);
680
681 if (!hose)
682 return;
683 if (res->flags & IORESOURCE_IO) {
684 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
685 mask = 0xffffffffu;
686 } else if (res->flags & IORESOURCE_MEM)
687 offset = hose->pci_mem_offset;
688
689 region->start = (res->start - offset) & mask;
690 region->end = (res->end - offset) & mask;
691}
692EXPORT_SYMBOL(pcibios_resource_to_bus);
693
694void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
695 struct pci_bus_region *region)
696{
697 resource_size_t offset = 0, mask = (resource_size_t)-1;
698 struct pci_controller *hose = pci_bus_to_host(dev->bus);
699
700 if (!hose)
701 return;
702 if (res->flags & IORESOURCE_IO) {
703 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
704 mask = 0xffffffffu;
705 } else if (res->flags & IORESOURCE_MEM)
706 offset = hose->pci_mem_offset;
707 res->start = (region->start + offset) & mask;
708 res->end = (region->end + offset) & mask;
709}
710EXPORT_SYMBOL(pcibios_bus_to_resource);
711
712/* Fixup a bus resource into a linux resource */
713static void __devinit fixup_resource(struct resource *res, struct pci_dev *dev)
714{
715 struct pci_controller *hose = pci_bus_to_host(dev->bus);
716 resource_size_t offset = 0, mask = (resource_size_t)-1;
717
718 if (res->flags & IORESOURCE_IO) {
719 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
720 mask = 0xffffffffu;
721 } else if (res->flags & IORESOURCE_MEM)
722 offset = hose->pci_mem_offset;
723
724 res->start = (res->start + offset) & mask;
725 res->end = (res->end + offset) & mask;
726
727 pr_debug("PCI:%s %016llx-%016llx\n",
728 pci_name(dev),
729 (unsigned long long)res->start,
730 (unsigned long long)res->end);
731}
732
733
734/* This header fixup will do the resource fixup for all devices as they are
735 * probed, but not for bridge ranges
736 */
737static void __devinit pcibios_fixup_resources(struct pci_dev *dev)
738{
739 struct pci_controller *hose = pci_bus_to_host(dev->bus);
740 int i;
741
742 if (!hose) {
743 printk(KERN_ERR "No host bridge for PCI dev %s !\n",
744 pci_name(dev));
745 return;
746 }
747 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
748 struct resource *res = dev->resource + i;
749 if (!res->flags)
750 continue;
751 if (res->end == 0xffffffff) {
752 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] is unassigned\n",
753 pci_name(dev), i,
754 (unsigned long long)res->start,
755 (unsigned long long)res->end,
756 (unsigned int)res->flags);
757 res->end -= res->start;
758 res->start = 0;
759 res->flags |= IORESOURCE_UNSET;
760 continue;
761 }
762
763 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] fixup...\n",
764 pci_name(dev), i,
765 (unsigned long long)res->start,\
766 (unsigned long long)res->end,
767 (unsigned int)res->flags);
768
769 fixup_resource(res, dev);
770 }
771
772 /* Call machine specific resource fixup */
773 if (ppc_md.pcibios_fixup_resources)
774 ppc_md.pcibios_fixup_resources(dev);
775}
776DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
777
778static void __devinit __pcibios_fixup_bus(struct pci_bus *bus)
779{
780 struct pci_controller *hose = pci_bus_to_host(bus);
781 struct pci_dev *dev = bus->self;
782
783 pr_debug("PCI: Fixup bus %d (%s)\n", bus->number, dev ? pci_name(dev) : "PHB");
784
785 /* Fixup PCI<->PCI bridges. Host bridges are handled separately, for
786 * now differently between 32 and 64 bits.
787 */
788 if (dev != NULL) {
789 struct resource *res;
790 int i;
791
792 for (i = 0; i < PCI_BUS_NUM_RESOURCES; ++i) {
793 if ((res = bus->resource[i]) == NULL)
794 continue;
795 if (!res->flags)
796 continue;
797 if (i >= 3 && bus->self->transparent)
798 continue;
799 /* On PowerMac, Apple leaves bridge windows open over
800 * an inaccessible region of memory space (0...fffff)
801 * which is somewhat bogus, but that's what they think
802 * means disabled...
803 *
804 * We clear those to force them to be reallocated later
805 *
806 * We detect such regions by the fact that the base is
807 * equal to the pci_mem_offset of the host bridge and
808 * their size is smaller than 1M.
809 */
810 if (res->flags & IORESOURCE_MEM &&
811 res->start == hose->pci_mem_offset &&
812 res->end < 0x100000) {
813 printk(KERN_INFO
814 "PCI: Closing bogus Apple Firmware"
815 " region %d on bus 0x%02x\n",
816 i, bus->number);
817 res->flags = 0;
818 continue;
819 }
820
821 pr_debug("PCI:%s Bus rsrc %d %016llx-%016llx [%x] fixup...\n",
822 pci_name(dev), i,
823 (unsigned long long)res->start,\
824 (unsigned long long)res->end,
825 (unsigned int)res->flags);
826
827 fixup_resource(res, dev);
828 }
829 }
830
831 /* Additional setup that is different between 32 and 64 bits for now */
832 pcibios_do_bus_setup(bus);
833
834 /* Platform specific bus fixups */
835 if (ppc_md.pcibios_fixup_bus)
836 ppc_md.pcibios_fixup_bus(bus);
837
838 /* Read default IRQs and fixup if necessary */
839 list_for_each_entry(dev, &bus->devices, bus_list) {
840 pci_read_irq_line(dev);
841 if (ppc_md.pci_irq_fixup)
842 ppc_md.pci_irq_fixup(dev);
843 }
844}
845
846void __devinit pcibios_fixup_bus(struct pci_bus *bus)
847{
848 /* When called from the generic PCI probe, read PCI<->PCI bridge
849 * bases before proceeding
850 */
851 if (bus->self != NULL)
852 pci_read_bridge_bases(bus);
853 __pcibios_fixup_bus(bus);
854}
855EXPORT_SYMBOL(pcibios_fixup_bus);
856
857/* When building a bus from the OF tree rather than probing, we need a
858 * slightly different version of the fixup which doesn't read the
859 * bridge bases using config space accesses
860 */
861void __devinit pcibios_fixup_of_probed_bus(struct pci_bus *bus)
862{
863 __pcibios_fixup_bus(bus);
864}
865
866static int skip_isa_ioresource_align(struct pci_dev *dev)
867{
868 if ((ppc_pci_flags & PPC_PCI_CAN_SKIP_ISA_ALIGN) &&
869 !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA))
870 return 1;
871 return 0;
872}
873
874/*
875 * We need to avoid collisions with `mirrored' VGA ports
876 * and other strange ISA hardware, so we always want the
877 * addresses to be allocated in the 0x000-0x0ff region
878 * modulo 0x400.
879 *
880 * Why? Because some silly external IO cards only decode
881 * the low 10 bits of the IO address. The 0x00-0xff region
882 * is reserved for motherboard devices that decode all 16
883 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
884 * but we want to try to avoid allocating at 0x2900-0x2bff
885 * which might have be mirrored at 0x0100-0x03ff..
886 */
887void pcibios_align_resource(void *data, struct resource *res,
888 resource_size_t size, resource_size_t align)
889{
890 struct pci_dev *dev = data;
891
892 if (res->flags & IORESOURCE_IO) {
893 resource_size_t start = res->start;
894
895 if (skip_isa_ioresource_align(dev))
896 return;
897 if (start & 0x300) {
898 start = (start + 0x3ff) & ~0x3ff;
899 res->start = start;
900 }
901 }
902}
903EXPORT_SYMBOL(pcibios_align_resource);
904
905/*
906 * Reparent resource children of pr that conflict with res
907 * under res, and make res replace those children.
908 */
909static int __init reparent_resources(struct resource *parent,
910 struct resource *res)
911{
912 struct resource *p, **pp;
913 struct resource **firstpp = NULL;
914
915 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
916 if (p->end < res->start)
917 continue;
918 if (res->end < p->start)
919 break;
920 if (p->start < res->start || p->end > res->end)
921 return -1; /* not completely contained */
922 if (firstpp == NULL)
923 firstpp = pp;
924 }
925 if (firstpp == NULL)
926 return -1; /* didn't find any conflicting entries? */
927 res->parent = parent;
928 res->child = *firstpp;
929 res->sibling = *pp;
930 *firstpp = res;
931 *pp = NULL;
932 for (p = res->child; p != NULL; p = p->sibling) {
933 p->parent = res;
934 DBG(KERN_INFO "PCI: reparented %s [%llx..%llx] under %s\n",
935 p->name,
936 (unsigned long long)p->start,
937 (unsigned long long)p->end, res->name);
938 }
939 return 0;
940}
941
942/*
943 * Handle resources of PCI devices. If the world were perfect, we could
944 * just allocate all the resource regions and do nothing more. It isn't.
945 * On the other hand, we cannot just re-allocate all devices, as it would
946 * require us to know lots of host bridge internals. So we attempt to
947 * keep as much of the original configuration as possible, but tweak it
948 * when it's found to be wrong.
949 *
950 * Known BIOS problems we have to work around:
951 * - I/O or memory regions not configured
952 * - regions configured, but not enabled in the command register
953 * - bogus I/O addresses above 64K used
954 * - expansion ROMs left enabled (this may sound harmless, but given
955 * the fact the PCI specs explicitly allow address decoders to be
956 * shared between expansion ROMs and other resource regions, it's
957 * at least dangerous)
958 *
959 * Our solution:
960 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
961 * This gives us fixed barriers on where we can allocate.
962 * (2) Allocate resources for all enabled devices. If there is
963 * a collision, just mark the resource as unallocated. Also
964 * disable expansion ROMs during this step.
965 * (3) Try to allocate resources for disabled devices. If the
966 * resources were assigned correctly, everything goes well,
967 * if they weren't, they won't disturb allocation of other
968 * resources.
969 * (4) Assign new addresses to resources which were either
970 * not configured at all or misconfigured. If explicitly
971 * requested by the user, configure expansion ROM address
972 * as well.
973 */
974
975static void __init pcibios_allocate_bus_resources(struct list_head *bus_list)
976{
977 struct pci_bus *bus;
978 int i;
979 struct resource *res, *pr;
980
981 /* Depth-First Search on bus tree */
982 list_for_each_entry(bus, bus_list, node) {
983 for (i = 0; i < PCI_BUS_NUM_RESOURCES; ++i) {
984 if ((res = bus->resource[i]) == NULL || !res->flags
985 || res->start > res->end)
986 continue;
987 if (bus->parent == NULL)
988 pr = (res->flags & IORESOURCE_IO) ?
989 &ioport_resource : &iomem_resource;
990 else {
991 /* Don't bother with non-root busses when
992 * re-assigning all resources. We clear the
993 * resource flags as if they were colliding
994 * and as such ensure proper re-allocation
995 * later.
996 */
997 if (ppc_pci_flags & PPC_PCI_REASSIGN_ALL_RSRC)
998 goto clear_resource;
999 pr = pci_find_parent_resource(bus->self, res);
1000 if (pr == res) {
1001 /* this happens when the generic PCI
1002 * code (wrongly) decides that this
1003 * bridge is transparent -- paulus
1004 */
1005 continue;
1006 }
1007 }
1008
1009 DBG("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx "
1010 "[0x%x], parent %p (%s)\n",
1011 bus->self ? pci_name(bus->self) : "PHB",
1012 bus->number, i,
1013 (unsigned long long)res->start,
1014 (unsigned long long)res->end,
1015 (unsigned int)res->flags,
1016 pr, (pr && pr->name) ? pr->name : "nil");
1017
1018 if (pr && !(pr->flags & IORESOURCE_UNSET)) {
1019 if (request_resource(pr, res) == 0)
1020 continue;
1021 /*
1022 * Must be a conflict with an existing entry.
1023 * Move that entry (or entries) under the
1024 * bridge resource and try again.
1025 */
1026 if (reparent_resources(pr, res) == 0)
1027 continue;
1028 }
1029 printk(KERN_WARNING
1030 "PCI: Cannot allocate resource region "
1031 "%d of PCI bridge %d, will remap\n",
1032 i, bus->number);
1033clear_resource:
1034 res->flags = 0;
1035 }
1036 pcibios_allocate_bus_resources(&bus->children);
1037 }
1038}
1039
1040static inline void __devinit alloc_resource(struct pci_dev *dev, int idx)
1041{
1042 struct resource *pr, *r = &dev->resource[idx];
1043
1044 DBG("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n",
1045 pci_name(dev), idx,
1046 (unsigned long long)r->start,
1047 (unsigned long long)r->end,
1048 (unsigned int)r->flags);
1049
1050 pr = pci_find_parent_resource(dev, r);
1051 if (!pr || (pr->flags & IORESOURCE_UNSET) ||
1052 request_resource(pr, r) < 0) {
1053 printk(KERN_WARNING "PCI: Cannot allocate resource region %d"
1054 " of device %s, will remap\n", idx, pci_name(dev));
1055 if (pr)
1056 DBG("PCI: parent is %p: %016llx-%016llx [%x]\n", pr,
1057 (unsigned long long)pr->start,
1058 (unsigned long long)pr->end,
1059 (unsigned int)pr->flags);
1060 /* We'll assign a new address later */
1061 r->flags |= IORESOURCE_UNSET;
1062 r->end -= r->start;
1063 r->start = 0;
1064 }
1065}
1066
1067static void __init pcibios_allocate_resources(int pass)
1068{
1069 struct pci_dev *dev = NULL;
1070 int idx, disabled;
1071 u16 command;
1072 struct resource *r;
1073
1074 for_each_pci_dev(dev) {
1075 pci_read_config_word(dev, PCI_COMMAND, &command);
1076 for (idx = 0; idx < 6; idx++) {
1077 r = &dev->resource[idx];
1078 if (r->parent) /* Already allocated */
1079 continue;
1080 if (!r->flags || (r->flags & IORESOURCE_UNSET))
1081 continue; /* Not assigned at all */
1082 if (r->flags & IORESOURCE_IO)
1083 disabled = !(command & PCI_COMMAND_IO);
1084 else
1085 disabled = !(command & PCI_COMMAND_MEMORY);
1086 if (pass == disabled)
1087 alloc_resource(dev, idx);
1088 }
1089 if (pass)
1090 continue;
1091 r = &dev->resource[PCI_ROM_RESOURCE];
1092 if (r->flags & IORESOURCE_ROM_ENABLE) {
1093 /* Turn the ROM off, leave the resource region,
1094 * but keep it unregistered.
1095 */
1096 u32 reg;
1097 DBG("PCI: Switching off ROM of %s\n", pci_name(dev));
1098 r->flags &= ~IORESOURCE_ROM_ENABLE;
1099 pci_read_config_dword(dev, dev->rom_base_reg, &reg);
1100 pci_write_config_dword(dev, dev->rom_base_reg,
1101 reg & ~PCI_ROM_ADDRESS_ENABLE);
1102 }
1103 }
1104}
1105
1106void __init pcibios_resource_survey(void)
1107{
1108 /* Allocate and assign resources. If we re-assign everything, then
1109 * we skip the allocate phase
1110 */
1111 pcibios_allocate_bus_resources(&pci_root_buses);
1112
1113 if (!(ppc_pci_flags & PPC_PCI_REASSIGN_ALL_RSRC)) {
1114 pcibios_allocate_resources(0);
1115 pcibios_allocate_resources(1);
1116 }
1117
1118 if (!(ppc_pci_flags & PPC_PCI_PROBE_ONLY)) {
1119 DBG("PCI: Assigning unassigned resouces...\n");
1120 pci_assign_unassigned_resources();
1121 }
1122
1123 /* Call machine dependent fixup */
1124 if (ppc_md.pcibios_fixup)
1125 ppc_md.pcibios_fixup();
1126}
1127
1128#ifdef CONFIG_HOTPLUG
1129/* This is used by the pSeries hotplug driver to allocate resource
1130 * of newly plugged busses. We can try to consolidate with the
1131 * rest of the code later, for now, keep it as-is
1132 */
1133void __devinit pcibios_claim_one_bus(struct pci_bus *bus)
1134{
1135 struct pci_dev *dev;
1136 struct pci_bus *child_bus;
1137
1138 list_for_each_entry(dev, &bus->devices, bus_list) {
1139 int i;
1140
1141 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1142 struct resource *r = &dev->resource[i];
1143
1144 if (r->parent || !r->start || !r->flags)
1145 continue;
1146 pci_claim_resource(dev, i);
1147 }
1148 }
1149
1150 list_for_each_entry(child_bus, &bus->children, node)
1151 pcibios_claim_one_bus(child_bus);
1152}
1153EXPORT_SYMBOL_GPL(pcibios_claim_one_bus);
1154#endif /* CONFIG_HOTPLUG */
1155
1156int pcibios_enable_device(struct pci_dev *dev, int mask)
1157{
1158 u16 cmd, old_cmd;
1159 int idx;
1160 struct resource *r;
1161
1162 if (ppc_md.pcibios_enable_device_hook)
1163 if (ppc_md.pcibios_enable_device_hook(dev))
1164 return -EINVAL;
1165
1166 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1167 old_cmd = cmd;
1168 for (idx = 0; idx < PCI_NUM_RESOURCES; idx++) {
1169 /* Only set up the requested stuff */
1170 if (!(mask & (1 << idx)))
1171 continue;
1172 r = &dev->resource[idx];
1173 if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
1174 continue;
1175 if ((idx == PCI_ROM_RESOURCE) &&
1176 (!(r->flags & IORESOURCE_ROM_ENABLE)))
1177 continue;
1178 if (r->parent == NULL) {
1179 printk(KERN_ERR "PCI: Device %s not available because"
1180 " of resource collisions\n", pci_name(dev));
1181 return -EINVAL;
1182 }
1183 if (r->flags & IORESOURCE_IO)
1184 cmd |= PCI_COMMAND_IO;
1185 if (r->flags & IORESOURCE_MEM)
1186 cmd |= PCI_COMMAND_MEMORY;
1187 }
1188 if (cmd != old_cmd) {
1189 printk("PCI: Enabling device %s (%04x -> %04x)\n",
1190 pci_name(dev), old_cmd, cmd);
1191 pci_write_config_word(dev, PCI_COMMAND, cmd);
1192 }
1193 return 0;
1194}
1195
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-20 07:41:04 -0500