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-rw-r--r--arch/powerpc/kernel/misc_64.S124
1 files changed, 0 insertions, 124 deletions
diff --git a/arch/powerpc/kernel/misc_64.S b/arch/powerpc/kernel/misc_64.S
index c70e20708a1f..21fd2c662a99 100644
--- a/arch/powerpc/kernel/misc_64.S
+++ b/arch/powerpc/kernel/misc_64.S
@@ -246,130 +246,6 @@ _GLOBAL(__flush_dcache_icache)
246 isync 246 isync
247 blr 247 blr
248 248
249/*
250 * identify_cpu and calls setup_cpu
251 * In: r3 = base of the cpu_specs array
252 * r4 = address of cur_cpu_spec
253 * r5 = relocation offset
254 */
255_GLOBAL(identify_cpu)
256 mfpvr r7
2571:
258 lwz r8,CPU_SPEC_PVR_MASK(r3)
259 and r8,r8,r7
260 lwz r9,CPU_SPEC_PVR_VALUE(r3)
261 cmplw 0,r9,r8
262 beq 1f
263 addi r3,r3,CPU_SPEC_ENTRY_SIZE
264 b 1b
2651:
266 sub r0,r3,r5
267 std r0,0(r4)
268 ld r4,CPU_SPEC_SETUP(r3)
269 cmpdi 0,r4,0
270 add r4,r4,r5
271 beqlr
272 ld r4,0(r4)
273 add r4,r4,r5
274 mtctr r4
275 /* Calling convention for cpu setup is r3=offset, r4=cur_cpu_spec */
276 mr r4,r3
277 mr r3,r5
278 bctr
279
280/*
281 * do_cpu_ftr_fixups - goes through the list of CPU feature fixups
282 * and writes nop's over sections of code that don't apply for this cpu.
283 * r3 = data offset (not changed)
284 */
285_GLOBAL(do_cpu_ftr_fixups)
286 /* Get CPU 0 features */
287 LOAD_REG_IMMEDIATE(r6,cur_cpu_spec)
288 sub r6,r6,r3
289 ld r4,0(r6)
290 sub r4,r4,r3
291 ld r4,CPU_SPEC_FEATURES(r4)
292 /* Get the fixup table */
293 LOAD_REG_IMMEDIATE(r6,__start___ftr_fixup)
294 sub r6,r6,r3
295 LOAD_REG_IMMEDIATE(r7,__stop___ftr_fixup)
296 sub r7,r7,r3
297 /* Do the fixup */
2981: cmpld r6,r7
299 bgelr
300 addi r6,r6,32
301 ld r8,-32(r6) /* mask */
302 and r8,r8,r4
303 ld r9,-24(r6) /* value */
304 cmpld r8,r9
305 beq 1b
306 ld r8,-16(r6) /* section begin */
307 ld r9,-8(r6) /* section end */
308 subf. r9,r8,r9
309 beq 1b
310 /* write nops over the section of code */
311 /* todo: if large section, add a branch at the start of it */
312 srwi r9,r9,2
313 mtctr r9
314 sub r8,r8,r3
315 lis r0,0x60000000@h /* nop */
3163: stw r0,0(r8)
317 andi. r10,r4,CPU_FTR_SPLIT_ID_CACHE@l
318 beq 2f
319 dcbst 0,r8 /* suboptimal, but simpler */
320 sync
321 icbi 0,r8
3222: addi r8,r8,4
323 bdnz 3b
324 sync /* additional sync needed on g4 */
325 isync
326 b 1b
327
328/*
329 * do_fw_ftr_fixups - goes through the list of firmware feature fixups
330 * and writes nop's over sections of code that don't apply for this firmware.
331 * r3 = data offset (not changed)
332 */
333_GLOBAL(do_fw_ftr_fixups)
334 /* Get firmware features */
335 LOAD_REG_IMMEDIATE(r6,powerpc_firmware_features)
336 sub r6,r6,r3
337 ld r4,0(r6)
338 /* Get the fixup table */
339 LOAD_REG_IMMEDIATE(r6,__start___fw_ftr_fixup)
340 sub r6,r6,r3
341 LOAD_REG_IMMEDIATE(r7,__stop___fw_ftr_fixup)
342 sub r7,r7,r3
343 /* Do the fixup */
3441: cmpld r6,r7
345 bgelr
346 addi r6,r6,32
347 ld r8,-32(r6) /* mask */
348 and r8,r8,r4
349 ld r9,-24(r6) /* value */
350 cmpld r8,r9
351 beq 1b
352 ld r8,-16(r6) /* section begin */
353 ld r9,-8(r6) /* section end */
354 subf. r9,r8,r9
355 beq 1b
356 /* write nops over the section of code */
357 /* todo: if large section, add a branch at the start of it */
358 srwi r9,r9,2
359 mtctr r9
360 sub r8,r8,r3
361 lis r0,0x60000000@h /* nop */
3623: stw r0,0(r8)
363BEGIN_FTR_SECTION
364 dcbst 0,r8 /* suboptimal, but simpler */
365 sync
366 icbi 0,r8
367END_FTR_SECTION_IFSET(CPU_FTR_SPLIT_ID_CACHE)
368 addi r8,r8,4
369 bdnz 3b
370 sync /* additional sync needed on g4 */
371 isync
372 b 1b
373 249
374#if defined(CONFIG_PPC_PMAC) || defined(CONFIG_PPC_MAPLE) 250#if defined(CONFIG_PPC_PMAC) || defined(CONFIG_PPC_MAPLE)
375/* 251/*