diff options
Diffstat (limited to 'arch/powerpc/kernel/misc_32.S')
-rw-r--r-- | arch/powerpc/kernel/misc_32.S | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/powerpc/kernel/misc_32.S b/arch/powerpc/kernel/misc_32.S index 98decf8ebff4..e708ab7ca9e8 100644 --- a/arch/powerpc/kernel/misc_32.S +++ b/arch/powerpc/kernel/misc_32.S | |||
@@ -392,7 +392,7 @@ BEGIN_FTR_SECTION | |||
392 | mtspr SPRN_L1CSR0,r3 | 392 | mtspr SPRN_L1CSR0,r3 |
393 | isync | 393 | isync |
394 | blr | 394 | blr |
395 | END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE) | 395 | END_FTR_SECTION_IFSET(CPU_FTR_UNIFIED_ID_CACHE) |
396 | mfspr r3,SPRN_L1CSR1 | 396 | mfspr r3,SPRN_L1CSR1 |
397 | ori r3,r3,L1CSR1_ICFI|L1CSR1_ICLFR | 397 | ori r3,r3,L1CSR1_ICFI|L1CSR1_ICLFR |
398 | mtspr SPRN_L1CSR1,r3 | 398 | mtspr SPRN_L1CSR1,r3 |
@@ -419,7 +419,7 @@ END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE) | |||
419 | _GLOBAL(__flush_icache_range) | 419 | _GLOBAL(__flush_icache_range) |
420 | BEGIN_FTR_SECTION | 420 | BEGIN_FTR_SECTION |
421 | blr /* for 601, do nothing */ | 421 | blr /* for 601, do nothing */ |
422 | END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE) | 422 | END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE) |
423 | li r5,L1_CACHE_BYTES-1 | 423 | li r5,L1_CACHE_BYTES-1 |
424 | andc r3,r3,r5 | 424 | andc r3,r3,r5 |
425 | subf r4,r3,r4 | 425 | subf r4,r3,r4 |
@@ -514,8 +514,8 @@ _GLOBAL(invalidate_dcache_range) | |||
514 | */ | 514 | */ |
515 | _GLOBAL(__flush_dcache_icache) | 515 | _GLOBAL(__flush_dcache_icache) |
516 | BEGIN_FTR_SECTION | 516 | BEGIN_FTR_SECTION |
517 | blr /* for 601, do nothing */ | 517 | blr |
518 | END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE) | 518 | END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE) |
519 | rlwinm r3,r3,0,0,19 /* Get page base address */ | 519 | rlwinm r3,r3,0,0,19 /* Get page base address */ |
520 | li r4,4096/L1_CACHE_BYTES /* Number of lines in a page */ | 520 | li r4,4096/L1_CACHE_BYTES /* Number of lines in a page */ |
521 | mtctr r4 | 521 | mtctr r4 |
@@ -543,7 +543,7 @@ END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE) | |||
543 | _GLOBAL(__flush_dcache_icache_phys) | 543 | _GLOBAL(__flush_dcache_icache_phys) |
544 | BEGIN_FTR_SECTION | 544 | BEGIN_FTR_SECTION |
545 | blr /* for 601, do nothing */ | 545 | blr /* for 601, do nothing */ |
546 | END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE) | 546 | END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE) |
547 | mfmsr r10 | 547 | mfmsr r10 |
548 | rlwinm r0,r10,0,28,26 /* clear DR */ | 548 | rlwinm r0,r10,0,28,26 /* clear DR */ |
549 | mtmsr r0 | 549 | mtmsr r0 |