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-rw-r--r--arch/powerpc/kernel/head_fsl_booke.S44
1 files changed, 35 insertions, 9 deletions
diff --git a/arch/powerpc/kernel/head_fsl_booke.S b/arch/powerpc/kernel/head_fsl_booke.S
index d9cc2c288d9e..4ff744143566 100644
--- a/arch/powerpc/kernel/head_fsl_booke.S
+++ b/arch/powerpc/kernel/head_fsl_booke.S
@@ -68,7 +68,9 @@ _ENTRY(_start);
68 mr r29,r5 68 mr r29,r5
69 mr r28,r6 69 mr r28,r6
70 mr r27,r7 70 mr r27,r7
71 li r25,0 /* phys kernel start (low) */
71 li r24,0 /* CPU number */ 72 li r24,0 /* CPU number */
73 li r23,0 /* phys kernel start (high) */
72 74
73/* We try to not make any assumptions about how the boot loader 75/* We try to not make any assumptions about how the boot loader
74 * setup or used the TLBs. We invalidate all mappings from the 76 * setup or used the TLBs. We invalidate all mappings from the
@@ -167,7 +169,28 @@ skpinv: addi r6,r6,1 /* Increment */
167 mtspr SPRN_MAS0,r7 169 mtspr SPRN_MAS0,r7
168 tlbre 170 tlbre
169 171
170 /* Just modify the entry ID, EPN and RPN for the temp mapping */ 172 /* grab and fixup the RPN */
173 mfspr r6,SPRN_MAS1 /* extract MAS1[SIZE] */
174 rlwinm r6,r6,25,27,30
175 li r8,-1
176 addi r6,r6,10
177 slw r6,r8,r6 /* convert to mask */
178
179 bl 1f /* Find our address */
1801: mflr r7
181
182 mfspr r8,SPRN_MAS3
183#ifdef CONFIG_PHYS_64BIT
184 mfspr r23,SPRN_MAS7
185#endif
186 and r8,r6,r8
187 subfic r9,r6,-4096
188 and r9,r9,r7
189
190 or r25,r8,r9
191 ori r8,r25,(MAS3_SX|MAS3_SW|MAS3_SR)
192
193 /* Just modify the entry ID and EPN for the temp mapping */
171 lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */ 194 lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
172 rlwimi r7,r5,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r5) */ 195 rlwimi r7,r5,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r5) */
173 mtspr SPRN_MAS0,r7 196 mtspr SPRN_MAS0,r7
@@ -177,12 +200,10 @@ skpinv: addi r6,r6,1 /* Increment */
177 ori r6,r6,(MAS1_TSIZE(BOOKE_PAGESZ_4K))@l 200 ori r6,r6,(MAS1_TSIZE(BOOKE_PAGESZ_4K))@l
178 mtspr SPRN_MAS1,r6 201 mtspr SPRN_MAS1,r6
179 mfspr r6,SPRN_MAS2 202 mfspr r6,SPRN_MAS2
180 lis r7,PHYSICAL_START@h 203 li r7,0 /* temp EPN = 0 */
181 rlwimi r7,r6,0,20,31 204 rlwimi r7,r6,0,20,31
182 mtspr SPRN_MAS2,r7 205 mtspr SPRN_MAS2,r7
183 mfspr r6,SPRN_MAS3 206 mtspr SPRN_MAS3,r8
184 rlwimi r7,r6,0,20,31
185 mtspr SPRN_MAS3,r7
186 tlbwe 207 tlbwe
187 208
188 xori r6,r4,1 209 xori r6,r4,1
@@ -232,8 +253,7 @@ skpinv: addi r6,r6,1 /* Increment */
232 ori r6,r6,PAGE_OFFSET@l 253 ori r6,r6,PAGE_OFFSET@l
233 rlwimi r6,r7,0,20,31 254 rlwimi r6,r7,0,20,31
234 mtspr SPRN_MAS2,r6 255 mtspr SPRN_MAS2,r6
235 li r7,(MAS3_SX|MAS3_SW|MAS3_SR) 256 mtspr SPRN_MAS3,r8
236 mtspr SPRN_MAS3,r7
237 tlbwe 257 tlbwe
238 258
239/* 7. Jump to KERNELBASE mapping */ 259/* 7. Jump to KERNELBASE mapping */
@@ -283,7 +303,10 @@ skpinv: addi r6,r6,1 /* Increment */
283 SET_IVOR(12, WatchdogTimer); 303 SET_IVOR(12, WatchdogTimer);
284 SET_IVOR(13, DataTLBError); 304 SET_IVOR(13, DataTLBError);
285 SET_IVOR(14, InstructionTLBError); 305 SET_IVOR(14, InstructionTLBError);
286 SET_IVOR(15, Debug); 306 SET_IVOR(15, DebugDebug);
307#if defined(CONFIG_E500)
308 SET_IVOR(15, DebugCrit);
309#endif
287 SET_IVOR(32, SPEUnavailable); 310 SET_IVOR(32, SPEUnavailable);
288 SET_IVOR(33, SPEFloatingPointData); 311 SET_IVOR(33, SPEFloatingPointData);
289 SET_IVOR(34, SPEFloatingPointRound); 312 SET_IVOR(34, SPEFloatingPointRound);
@@ -718,7 +741,10 @@ interrupt_base:
718 741
719 742
720 /* Debug Interrupt */ 743 /* Debug Interrupt */
721 DEBUG_EXCEPTION 744 DEBUG_DEBUG_EXCEPTION
745#if defined(CONFIG_E500)
746 DEBUG_CRIT_EXCEPTION
747#endif
722 748
723/* 749/*
724 * Local functions 750 * Local functions