diff options
Diffstat (limited to 'arch/powerpc/kernel/head_fsl_booke.S')
-rw-r--r-- | arch/powerpc/kernel/head_fsl_booke.S | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/arch/powerpc/kernel/head_fsl_booke.S b/arch/powerpc/kernel/head_fsl_booke.S index 7c2b65380658..c4268500e856 100644 --- a/arch/powerpc/kernel/head_fsl_booke.S +++ b/arch/powerpc/kernel/head_fsl_booke.S | |||
@@ -39,6 +39,7 @@ | |||
39 | #include <asm/thread_info.h> | 39 | #include <asm/thread_info.h> |
40 | #include <asm/ppc_asm.h> | 40 | #include <asm/ppc_asm.h> |
41 | #include <asm/asm-offsets.h> | 41 | #include <asm/asm-offsets.h> |
42 | #include <asm/cache.h> | ||
42 | #include "head_booke.h" | 43 | #include "head_booke.h" |
43 | 44 | ||
44 | /* As with the other PowerPC ports, it is expected that when code | 45 | /* As with the other PowerPC ports, it is expected that when code |
@@ -1071,6 +1072,52 @@ _GLOBAL(set_context) | |||
1071 | isync /* Force context change */ | 1072 | isync /* Force context change */ |
1072 | blr | 1073 | blr |
1073 | 1074 | ||
1075 | _GLOBAL(flush_dcache_L1) | ||
1076 | mfspr r3,SPRN_L1CFG0 | ||
1077 | |||
1078 | rlwinm r5,r3,9,3 /* Extract cache block size */ | ||
1079 | twlgti r5,1 /* Only 32 and 64 byte cache blocks | ||
1080 | * are currently defined. | ||
1081 | */ | ||
1082 | li r4,32 | ||
1083 | subfic r6,r5,2 /* r6 = log2(1KiB / cache block size) - | ||
1084 | * log2(number of ways) | ||
1085 | */ | ||
1086 | slw r5,r4,r5 /* r5 = cache block size */ | ||
1087 | |||
1088 | rlwinm r7,r3,0,0xff /* Extract number of KiB in the cache */ | ||
1089 | mulli r7,r7,13 /* An 8-way cache will require 13 | ||
1090 | * loads per set. | ||
1091 | */ | ||
1092 | slw r7,r7,r6 | ||
1093 | |||
1094 | /* save off HID0 and set DCFA */ | ||
1095 | mfspr r8,SPRN_HID0 | ||
1096 | ori r9,r8,HID0_DCFA@l | ||
1097 | mtspr SPRN_HID0,r9 | ||
1098 | isync | ||
1099 | |||
1100 | lis r4,KERNELBASE@h | ||
1101 | mtctr r7 | ||
1102 | |||
1103 | 1: lwz r3,0(r4) /* Load... */ | ||
1104 | add r4,r4,r5 | ||
1105 | bdnz 1b | ||
1106 | |||
1107 | msync | ||
1108 | lis r4,KERNELBASE@h | ||
1109 | mtctr r7 | ||
1110 | |||
1111 | 1: dcbf 0,r4 /* ...and flush. */ | ||
1112 | add r4,r4,r5 | ||
1113 | bdnz 1b | ||
1114 | |||
1115 | /* restore HID0 */ | ||
1116 | mtspr SPRN_HID0,r8 | ||
1117 | isync | ||
1118 | |||
1119 | blr | ||
1120 | |||
1074 | /* | 1121 | /* |
1075 | * We put a few things here that have to be page-aligned. This stuff | 1122 | * We put a few things here that have to be page-aligned. This stuff |
1076 | * goes at the beginning of the data segment, which is page-aligned. | 1123 | * goes at the beginning of the data segment, which is page-aligned. |