diff options
Diffstat (limited to 'arch/powerpc/kernel/head_32.S')
-rw-r--r-- | arch/powerpc/kernel/head_32.S | 31 |
1 files changed, 21 insertions, 10 deletions
diff --git a/arch/powerpc/kernel/head_32.S b/arch/powerpc/kernel/head_32.S index 0c326823c6d4..a1c4cfd25ded 100644 --- a/arch/powerpc/kernel/head_32.S +++ b/arch/powerpc/kernel/head_32.S | |||
@@ -31,6 +31,7 @@ | |||
31 | #include <asm/ppc_asm.h> | 31 | #include <asm/ppc_asm.h> |
32 | #include <asm/asm-offsets.h> | 32 | #include <asm/asm-offsets.h> |
33 | #include <asm/ptrace.h> | 33 | #include <asm/ptrace.h> |
34 | #include <asm/bug.h> | ||
34 | 35 | ||
35 | /* 601 only have IBAT; cr0.eq is set on 601 when using this macro */ | 36 | /* 601 only have IBAT; cr0.eq is set on 601 when using this macro */ |
36 | #define LOAD_BAT(n, reg, RA, RB) \ | 37 | #define LOAD_BAT(n, reg, RA, RB) \ |
@@ -182,7 +183,8 @@ __after_mmu_off: | |||
182 | bl reloc_offset | 183 | bl reloc_offset |
183 | mr r26,r3 | 184 | mr r26,r3 |
184 | addis r4,r3,KERNELBASE@h /* current address of _start */ | 185 | addis r4,r3,KERNELBASE@h /* current address of _start */ |
185 | cmpwi 0,r4,0 /* are we already running at 0? */ | 186 | lis r5,PHYSICAL_START@h |
187 | cmplw 0,r4,r5 /* already running at PHYSICAL_START? */ | ||
186 | bne relocate_kernel | 188 | bne relocate_kernel |
187 | /* | 189 | /* |
188 | * we now have the 1st 16M of ram mapped with the bats. | 190 | * we now have the 1st 16M of ram mapped with the bats. |
@@ -810,13 +812,13 @@ giveup_altivec: | |||
810 | 812 | ||
811 | /* | 813 | /* |
812 | * This code is jumped to from the startup code to copy | 814 | * This code is jumped to from the startup code to copy |
813 | * the kernel image to physical address 0. | 815 | * the kernel image to physical address PHYSICAL_START. |
814 | */ | 816 | */ |
815 | relocate_kernel: | 817 | relocate_kernel: |
816 | addis r9,r26,klimit@ha /* fetch klimit */ | 818 | addis r9,r26,klimit@ha /* fetch klimit */ |
817 | lwz r25,klimit@l(r9) | 819 | lwz r25,klimit@l(r9) |
818 | addis r25,r25,-KERNELBASE@h | 820 | addis r25,r25,-KERNELBASE@h |
819 | li r3,0 /* Destination base address */ | 821 | lis r3,PHYSICAL_START@h /* Destination base address */ |
820 | li r6,0 /* Destination offset */ | 822 | li r6,0 /* Destination offset */ |
821 | li r5,0x4000 /* # bytes of memory to copy */ | 823 | li r5,0x4000 /* # bytes of memory to copy */ |
822 | bl copy_and_flush /* copy the first 0x4000 bytes */ | 824 | bl copy_and_flush /* copy the first 0x4000 bytes */ |
@@ -989,12 +991,12 @@ load_up_mmu: | |||
989 | LOAD_BAT(1,r3,r4,r5) | 991 | LOAD_BAT(1,r3,r4,r5) |
990 | LOAD_BAT(2,r3,r4,r5) | 992 | LOAD_BAT(2,r3,r4,r5) |
991 | LOAD_BAT(3,r3,r4,r5) | 993 | LOAD_BAT(3,r3,r4,r5) |
992 | BEGIN_FTR_SECTION | 994 | BEGIN_MMU_FTR_SECTION |
993 | LOAD_BAT(4,r3,r4,r5) | 995 | LOAD_BAT(4,r3,r4,r5) |
994 | LOAD_BAT(5,r3,r4,r5) | 996 | LOAD_BAT(5,r3,r4,r5) |
995 | LOAD_BAT(6,r3,r4,r5) | 997 | LOAD_BAT(6,r3,r4,r5) |
996 | LOAD_BAT(7,r3,r4,r5) | 998 | LOAD_BAT(7,r3,r4,r5) |
997 | END_FTR_SECTION_IFSET(CPU_FTR_HAS_HIGH_BATS) | 999 | END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS) |
998 | blr | 1000 | blr |
999 | 1001 | ||
1000 | /* | 1002 | /* |
@@ -1070,9 +1072,14 @@ start_here: | |||
1070 | RFI | 1072 | RFI |
1071 | 1073 | ||
1072 | /* | 1074 | /* |
1075 | * void switch_mmu_context(struct mm_struct *prev, struct mm_struct *next); | ||
1076 | * | ||
1073 | * Set up the segment registers for a new context. | 1077 | * Set up the segment registers for a new context. |
1074 | */ | 1078 | */ |
1075 | _ENTRY(set_context) | 1079 | _ENTRY(switch_mmu_context) |
1080 | lwz r3,MMCONTEXTID(r4) | ||
1081 | cmpwi cr0,r3,0 | ||
1082 | blt- 4f | ||
1076 | mulli r3,r3,897 /* multiply context by skew factor */ | 1083 | mulli r3,r3,897 /* multiply context by skew factor */ |
1077 | rlwinm r3,r3,4,8,27 /* VSID = (context & 0xfffff) << 4 */ | 1084 | rlwinm r3,r3,4,8,27 /* VSID = (context & 0xfffff) << 4 */ |
1078 | addis r3,r3,0x6000 /* Set Ks, Ku bits */ | 1085 | addis r3,r3,0x6000 /* Set Ks, Ku bits */ |
@@ -1083,6 +1090,7 @@ _ENTRY(set_context) | |||
1083 | /* Context switch the PTE pointer for the Abatron BDI2000. | 1090 | /* Context switch the PTE pointer for the Abatron BDI2000. |
1084 | * The PGDIR is passed as second argument. | 1091 | * The PGDIR is passed as second argument. |
1085 | */ | 1092 | */ |
1093 | lwz r4,MM_PGD(r4) | ||
1086 | lis r5, KERNELBASE@h | 1094 | lis r5, KERNELBASE@h |
1087 | lwz r5, 0xf0(r5) | 1095 | lwz r5, 0xf0(r5) |
1088 | stw r4, 0x4(r5) | 1096 | stw r4, 0x4(r5) |
@@ -1098,6 +1106,9 @@ _ENTRY(set_context) | |||
1098 | sync | 1106 | sync |
1099 | isync | 1107 | isync |
1100 | blr | 1108 | blr |
1109 | 4: trap | ||
1110 | EMIT_BUG_ENTRY 4b,__FILE__,__LINE__,0 | ||
1111 | blr | ||
1101 | 1112 | ||
1102 | /* | 1113 | /* |
1103 | * An undocumented "feature" of 604e requires that the v bit | 1114 | * An undocumented "feature" of 604e requires that the v bit |
@@ -1131,7 +1142,7 @@ clear_bats: | |||
1131 | mtspr SPRN_IBAT2L,r10 | 1142 | mtspr SPRN_IBAT2L,r10 |
1132 | mtspr SPRN_IBAT3U,r10 | 1143 | mtspr SPRN_IBAT3U,r10 |
1133 | mtspr SPRN_IBAT3L,r10 | 1144 | mtspr SPRN_IBAT3L,r10 |
1134 | BEGIN_FTR_SECTION | 1145 | BEGIN_MMU_FTR_SECTION |
1135 | /* Here's a tweak: at this point, CPU setup have | 1146 | /* Here's a tweak: at this point, CPU setup have |
1136 | * not been called yet, so HIGH_BAT_EN may not be | 1147 | * not been called yet, so HIGH_BAT_EN may not be |
1137 | * set in HID0 for the 745x processors. However, it | 1148 | * set in HID0 for the 745x processors. However, it |
@@ -1154,7 +1165,7 @@ BEGIN_FTR_SECTION | |||
1154 | mtspr SPRN_IBAT6L,r10 | 1165 | mtspr SPRN_IBAT6L,r10 |
1155 | mtspr SPRN_IBAT7U,r10 | 1166 | mtspr SPRN_IBAT7U,r10 |
1156 | mtspr SPRN_IBAT7L,r10 | 1167 | mtspr SPRN_IBAT7L,r10 |
1157 | END_FTR_SECTION_IFSET(CPU_FTR_HAS_HIGH_BATS) | 1168 | END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS) |
1158 | blr | 1169 | blr |
1159 | 1170 | ||
1160 | flush_tlbs: | 1171 | flush_tlbs: |
@@ -1178,11 +1189,11 @@ mmu_off: | |||
1178 | 1189 | ||
1179 | /* | 1190 | /* |
1180 | * Use the first pair of BAT registers to map the 1st 16MB | 1191 | * Use the first pair of BAT registers to map the 1st 16MB |
1181 | * of RAM to KERNELBASE. From this point on we can't safely | 1192 | * of RAM to PAGE_OFFSET. From this point on we can't safely |
1182 | * call OF any more. | 1193 | * call OF any more. |
1183 | */ | 1194 | */ |
1184 | initial_bats: | 1195 | initial_bats: |
1185 | lis r11,KERNELBASE@h | 1196 | lis r11,PAGE_OFFSET@h |
1186 | mfspr r9,SPRN_PVR | 1197 | mfspr r9,SPRN_PVR |
1187 | rlwinm r9,r9,16,16,31 /* r9 = 1 for 601, 4 for 604 */ | 1198 | rlwinm r9,r9,16,16,31 /* r9 = 1 for 601, 4 for 604 */ |
1188 | cmpwi 0,r9,1 | 1199 | cmpwi 0,r9,1 |