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-rw-r--r--arch/powerpc/kernel/cputable.c13
1 files changed, 12 insertions, 1 deletions
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index 7dcc01be4b09..83f9ab139d4c 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -237,6 +237,11 @@ struct cpu_spec cpu_specs[] = {
237 .num_pmcs = 6, 237 .num_pmcs = 6,
238 .oprofile_cpu_type = "ppc64/power5", 238 .oprofile_cpu_type = "ppc64/power5",
239 .oprofile_type = PPC_OPROFILE_POWER4, 239 .oprofile_type = PPC_OPROFILE_POWER4,
240 /* SIHV / SIPR bits are implemented on POWER4+ (GQ)
241 * and above but only works on POWER5 and above
242 */
243 .oprofile_mmcra_sihv = MMCRA_SIHV,
244 .oprofile_mmcra_sipr = MMCRA_SIPR,
240 .platform = "power5", 245 .platform = "power5",
241 }, 246 },
242 { /* Power5 GS */ 247 { /* Power5 GS */
@@ -250,6 +255,8 @@ struct cpu_spec cpu_specs[] = {
250 .num_pmcs = 6, 255 .num_pmcs = 6,
251 .oprofile_cpu_type = "ppc64/power5+", 256 .oprofile_cpu_type = "ppc64/power5+",
252 .oprofile_type = PPC_OPROFILE_POWER4, 257 .oprofile_type = PPC_OPROFILE_POWER4,
258 .oprofile_mmcra_sihv = MMCRA_SIHV,
259 .oprofile_mmcra_sipr = MMCRA_SIPR,
253 .platform = "power5+", 260 .platform = "power5+",
254 }, 261 },
255 { /* Power6 */ 262 { /* Power6 */
@@ -260,9 +267,13 @@ struct cpu_spec cpu_specs[] = {
260 .cpu_user_features = COMMON_USER_POWER6, 267 .cpu_user_features = COMMON_USER_POWER6,
261 .icache_bsize = 128, 268 .icache_bsize = 128,
262 .dcache_bsize = 128, 269 .dcache_bsize = 128,
263 .num_pmcs = 6, 270 .num_pmcs = 8,
264 .oprofile_cpu_type = "ppc64/power6", 271 .oprofile_cpu_type = "ppc64/power6",
265 .oprofile_type = PPC_OPROFILE_POWER4, 272 .oprofile_type = PPC_OPROFILE_POWER4,
273 .oprofile_mmcra_sihv = POWER6_MMCRA_SIHV,
274 .oprofile_mmcra_sipr = POWER6_MMCRA_SIPR,
275 .oprofile_mmcra_clear = POWER6_MMCRA_THRM |
276 POWER6_MMCRA_OTHER,
266 .platform = "power6", 277 .platform = "power6",
267 }, 278 },
268 { /* Cell Broadband Engine */ 279 { /* Cell Broadband Engine */