1 files changed, 24 insertions, 75 deletions
diff --git a/arch/powerpc/kernel/cpu_setup_ppc970.S b/arch/powerpc/kernel/cpu_setup_ppc970.S
index f69af2c5d7b3..f619932794e8 100644
--- a/arch/powerpc/kernel/cpu_setup_ppc970.S
+++ b/arch/powerpc/kernel/cpu_setup_ppc970.S
@@ -16,27 +16,12 @@
 #include <asm/asm-offsets.h>
 #include <asm/cache.h>
-_GLOBAL(__970_cpu_preinit)
+_GLOBAL(__cpu_preinit_ppc970)
-        /*
+        /* Do nothing if not running in HV mode */
-         * Do nothing if not running in HV mode
-         */
        mfmsr   r0
        rldicl. r0,r0,4,63
        beqlr
-        /*
-         * Deal only with PPC970 and PPC970FX.
-         */
-        mfspr   r0,SPRN_PVR
-        srwi    r0,r0,16
-        cmpwi   r0,0x39
-        beq     1f
-        cmpwi   r0,0x3c
-        beq     1f
-        cmpwi   r0,0x44
-        bnelr
-1:
        /* Make sure HID4:rm_ci is off before MMU is turned off, that large
         * pages are enabled with HID4:61 and clear HID5:DCBZ_size and
         * HID5:DCBZ32_ill
@@ -72,21 +57,6 @@ _GLOBAL(__970_cpu_preinit)
        isync
        blr
-_GLOBAL(__setup_cpu_ppc970)
-        mfspr   r0,SPRN_HID0
-        li      r11,5                   /* clear DOZE and SLEEP */
-        rldimi  r0,r11,52,8             /* set NAP and DPM */
-        mtspr   SPRN_HID0,r0
-        mfspr   r0,SPRN_HID0
-        mfspr   r0,SPRN_HID0
-        mfspr   r0,SPRN_HID0
-        mfspr   r0,SPRN_HID0
-        mfspr   r0,SPRN_HID0
-        mfspr   r0,SPRN_HID0
-        sync
-        isync
-        blr
 /* Definitions for the table use to save CPU states */
 #define CS_HID0         0
 #define CS_HID1         8
@@ -101,33 +71,28 @@ cpu_state_storage:
        .balign L1_CACHE_BYTES,0
        .text
-/* Called in normal context to backup CPU 0 state. This
- * does not include cache settings. This function is also
- * called for machine sleep. This does not include the MMU
- * setup, BATs, etc... but rather the "special" registers
- * like HID0, HID1, HID4, etc...
- */
-_GLOBAL(__save_cpu_setup)
-        /* Some CR fields are volatile, we back it up all */
-        mfcr    r7
-        /* Get storage ptr */
-        LOAD_REG_IMMEDIATE(r5,cpu_state_storage)
-        /* We only deal with 970 for now */
+_GLOBAL(__setup_cpu_ppc970)
-        mfspr   r0,SPRN_PVR
+        /* Do nothing if not running in HV mode */
-        srwi    r0,r0,16
-        cmpwi   r0,0x39
-        beq     1f
-        cmpwi   r0,0x3c
-        beq     1f
-        cmpwi   r0,0x44
-        bne     2f
-1:      /* skip if not running in HV mode */
        mfmsr   r0
        rldicl. r0,r0,4,63
-        beq     2f
+        beqlr
+        mfspr   r0,SPRN_HID0
+        li      r11,5                   /* clear DOZE and SLEEP */
+        rldimi  r0,r11,52,8             /* set NAP and DPM */
+        mtspr   SPRN_HID0,r0
+        mfspr   r0,SPRN_HID0
+        mfspr   r0,SPRN_HID0
+        mfspr   r0,SPRN_HID0
+        mfspr   r0,SPRN_HID0
+        mfspr   r0,SPRN_HID0
+        mfspr   r0,SPRN_HID0
+        sync
+        isync
+        /* Save away cpu state */
+        LOAD_REG_IMMEDIATE(r5,cpu_state_storage)
        /* Save HID0,1,4 and 5 */
        mfspr   r3,SPRN_HID0
@@ -139,35 +104,19 @@ _GLOBAL(__save_cpu_setup)
        mfspr   r3,SPRN_HID5
        std     r3,CS_HID5(r5)
-2:
-        mtcr    r7
        blr
 /* Called with no MMU context (typically MSR:IR/DR off) to
 * restore CPU state as backed up by the previous
 * function. This does not include cache setting
 */
-_GLOBAL(__restore_cpu_setup)
+_GLOBAL(__restore_cpu_ppc970)
-        /* Get storage ptr (FIXME when using anton reloc as we
+        /* Do nothing if not running in HV mode */
-         * are running with translation disabled here
-         */
-        LOAD_REG_IMMEDIATE(r5,cpu_state_storage)
-        /* We only deal with 970 for now */
-        mfspr   r0,SPRN_PVR
-        srwi    r0,r0,16
-        cmpwi   r0,0x39
-        beq     1f
-        cmpwi   r0,0x3c
-        beq     1f
-        cmpwi   r0,0x44
-        bnelr
-1:      /* skip if not running in HV mode */
        mfmsr   r0
        rldicl. r0,r0,4,63
        beqlr
+        LOAD_REG_IMMEDIATE(r5,cpu_state_storage)
        /* Before accessing memory, we make sure rm_ci is clear */
        li      r0,0
        mfspr   r3,SPRN_HID4

diff --git a/arch/powerpc/kernel/cpu_setup_ppc970.S b/arch/powerpc/kernel/cpu_setup_ppc970.S index f69af2c5d7b3..f619932794e8 100644 --- a/arch/powerpc/kernel/cpu_setup_ppc970.S +++ b/arch/powerpc/kernel/cpu_setup_ppc970.S
@@ -16,27 +16,12 @@
16	#include <asm/asm-offsets.h>	16	#include <asm/asm-offsets.h>
17	#include <asm/cache.h>	17	#include <asm/cache.h>
18		18
19	_GLOBAL(__970_cpu_preinit)	19	_GLOBAL(__cpu_preinit_ppc970)
20	/*	20	/* Do nothing if not running in HV mode */
21	* Do nothing if not running in HV mode
22	*/
23	mfmsr r0	21	mfmsr r0
24	rldicl. r0,r0,4,63	22	rldicl. r0,r0,4,63
25	beqlr	23	beqlr
26		24
27	/*
28	* Deal only with PPC970 and PPC970FX.
29	*/
30	mfspr r0,SPRN_PVR
31	srwi r0,r0,16
32	cmpwi r0,0x39
33	beq 1f
34	cmpwi r0,0x3c
35	beq 1f
36	cmpwi r0,0x44
37	bnelr
38	1:
39
40	/* Make sure HID4:rm_ci is off before MMU is turned off, that large	25	/* Make sure HID4:rm_ci is off before MMU is turned off, that large
41	* pages are enabled with HID4:61 and clear HID5:DCBZ_size and	26	* pages are enabled with HID4:61 and clear HID5:DCBZ_size and
42	* HID5:DCBZ32_ill	27	* HID5:DCBZ32_ill
@@ -72,21 +57,6 @@ _GLOBAL(__970_cpu_preinit)
72	isync	57	isync
73	blr	58	blr
74		59
75	_GLOBAL(__setup_cpu_ppc970)
76	mfspr r0,SPRN_HID0
77	li r11,5 /* clear DOZE and SLEEP */
78	rldimi r0,r11,52,8 /* set NAP and DPM */
79	mtspr SPRN_HID0,r0
80	mfspr r0,SPRN_HID0
81	mfspr r0,SPRN_HID0
82	mfspr r0,SPRN_HID0
83	mfspr r0,SPRN_HID0
84	mfspr r0,SPRN_HID0
85	mfspr r0,SPRN_HID0
86	sync
87	isync
88	blr
89
90	/* Definitions for the table use to save CPU states */	60	/* Definitions for the table use to save CPU states */
91	#define CS_HID0 0	61	#define CS_HID0 0
92	#define CS_HID1 8	62	#define CS_HID1 8
@@ -101,33 +71,28 @@ cpu_state_storage:
101	.balign L1_CACHE_BYTES,0	71	.balign L1_CACHE_BYTES,0
102	.text	72	.text
103		73
104	/* Called in normal context to backup CPU 0 state. This
105	* does not include cache settings. This function is also
106	* called for machine sleep. This does not include the MMU
107	* setup, BATs, etc... but rather the "special" registers
108	* like HID0, HID1, HID4, etc...
109	*/
110	_GLOBAL(__save_cpu_setup)
111	/* Some CR fields are volatile, we back it up all */
112	mfcr r7
113
114	/* Get storage ptr */
115	LOAD_REG_IMMEDIATE(r5,cpu_state_storage)
116		74
117	/* We only deal with 970 for now */	75	_GLOBAL(__setup_cpu_ppc970)
118	mfspr r0,SPRN_PVR	76	/* Do nothing if not running in HV mode */
119	srwi r0,r0,16
120	cmpwi r0,0x39
121	beq 1f
122	cmpwi r0,0x3c
123	beq 1f
124	cmpwi r0,0x44
125	bne 2f
126
127	1: /* skip if not running in HV mode */
128	mfmsr r0	77	mfmsr r0
129	rldicl. r0,r0,4,63	78	rldicl. r0,r0,4,63
130	beq 2f	79	beqlr
		80
		81	mfspr r0,SPRN_HID0
		82	li r11,5 /* clear DOZE and SLEEP */
		83	rldimi r0,r11,52,8 /* set NAP and DPM */
		84	mtspr SPRN_HID0,r0
		85	mfspr r0,SPRN_HID0
		86	mfspr r0,SPRN_HID0
		87	mfspr r0,SPRN_HID0
		88	mfspr r0,SPRN_HID0
		89	mfspr r0,SPRN_HID0
		90	mfspr r0,SPRN_HID0
		91	sync
		92	isync
		93
		94	/* Save away cpu state */
		95	LOAD_REG_IMMEDIATE(r5,cpu_state_storage)
131		96
132	/* Save HID0,1,4 and 5 */	97	/* Save HID0,1,4 and 5 */
133	mfspr r3,SPRN_HID0	98	mfspr r3,SPRN_HID0
@@ -139,35 +104,19 @@ _GLOBAL(__save_cpu_setup)
139	mfspr r3,SPRN_HID5	104	mfspr r3,SPRN_HID5
140	std r3,CS_HID5(r5)	105	std r3,CS_HID5(r5)
141		106
142	2:
143	mtcr r7
144	blr	107	blr
145		108
146	/* Called with no MMU context (typically MSR:IR/DR off) to	109	/* Called with no MMU context (typically MSR:IR/DR off) to
147	* restore CPU state as backed up by the previous	110	* restore CPU state as backed up by the previous
148	* function. This does not include cache setting	111	* function. This does not include cache setting
149	*/	112	*/
150	_GLOBAL(__restore_cpu_setup)	113	_GLOBAL(__restore_cpu_ppc970)
151	/* Get storage ptr (FIXME when using anton reloc as we	114	/* Do nothing if not running in HV mode */
152	* are running with translation disabled here
153	*/
154	LOAD_REG_IMMEDIATE(r5,cpu_state_storage)
155
156	/* We only deal with 970 for now */
157	mfspr r0,SPRN_PVR
158	srwi r0,r0,16
159	cmpwi r0,0x39
160	beq 1f
161	cmpwi r0,0x3c
162	beq 1f
163	cmpwi r0,0x44
164	bnelr
165
166	1: /* skip if not running in HV mode */
167	mfmsr r0	115	mfmsr r0
168	rldicl. r0,r0,4,63	116	rldicl. r0,r0,4,63
169	beqlr	117	beqlr
170		118
		119	LOAD_REG_IMMEDIATE(r5,cpu_state_storage)
171	/* Before accessing memory, we make sure rm_ci is clear */	120	/* Before accessing memory, we make sure rm_ci is clear */
172	li r0,0	121	li r0,0
173	mfspr r3,SPRN_HID4	122	mfspr r3,SPRN_HID4