diff options
Diffstat (limited to 'arch/powerpc/kernel/align.c')
-rw-r--r-- | arch/powerpc/kernel/align.c | 20 |
1 files changed, 16 insertions, 4 deletions
diff --git a/arch/powerpc/kernel/align.c b/arch/powerpc/kernel/align.c index 5ffcfaa77d6a..a5b632e52fae 100644 --- a/arch/powerpc/kernel/align.c +++ b/arch/powerpc/kernel/align.c | |||
@@ -24,6 +24,7 @@ | |||
24 | #include <asm/system.h> | 24 | #include <asm/system.h> |
25 | #include <asm/cache.h> | 25 | #include <asm/cache.h> |
26 | #include <asm/cputable.h> | 26 | #include <asm/cputable.h> |
27 | #include <asm/emulated_ops.h> | ||
27 | 28 | ||
28 | struct aligninfo { | 29 | struct aligninfo { |
29 | unsigned char len; | 30 | unsigned char len; |
@@ -730,8 +731,10 @@ int fix_alignment(struct pt_regs *regs) | |||
730 | areg = dsisr & 0x1f; /* register to update */ | 731 | areg = dsisr & 0x1f; /* register to update */ |
731 | 732 | ||
732 | #ifdef CONFIG_SPE | 733 | #ifdef CONFIG_SPE |
733 | if ((instr >> 26) == 0x4) | 734 | if ((instr >> 26) == 0x4) { |
735 | PPC_WARN_EMULATED(spe); | ||
734 | return emulate_spe(regs, reg, instr); | 736 | return emulate_spe(regs, reg, instr); |
737 | } | ||
735 | #endif | 738 | #endif |
736 | 739 | ||
737 | instr = (dsisr >> 10) & 0x7f; | 740 | instr = (dsisr >> 10) & 0x7f; |
@@ -783,23 +786,28 @@ int fix_alignment(struct pt_regs *regs) | |||
783 | flags |= SPLT; | 786 | flags |= SPLT; |
784 | nb = 8; | 787 | nb = 8; |
785 | } | 788 | } |
789 | PPC_WARN_EMULATED(vsx); | ||
786 | return emulate_vsx(addr, reg, areg, regs, flags, nb); | 790 | return emulate_vsx(addr, reg, areg, regs, flags, nb); |
787 | } | 791 | } |
788 | #endif | 792 | #endif |
789 | /* A size of 0 indicates an instruction we don't support, with | 793 | /* A size of 0 indicates an instruction we don't support, with |
790 | * the exception of DCBZ which is handled as a special case here | 794 | * the exception of DCBZ which is handled as a special case here |
791 | */ | 795 | */ |
792 | if (instr == DCBZ) | 796 | if (instr == DCBZ) { |
797 | PPC_WARN_EMULATED(dcbz); | ||
793 | return emulate_dcbz(regs, addr); | 798 | return emulate_dcbz(regs, addr); |
799 | } | ||
794 | if (unlikely(nb == 0)) | 800 | if (unlikely(nb == 0)) |
795 | return 0; | 801 | return 0; |
796 | 802 | ||
797 | /* Load/Store Multiple instructions are handled in their own | 803 | /* Load/Store Multiple instructions are handled in their own |
798 | * function | 804 | * function |
799 | */ | 805 | */ |
800 | if (flags & M) | 806 | if (flags & M) { |
807 | PPC_WARN_EMULATED(multiple); | ||
801 | return emulate_multiple(regs, addr, reg, nb, | 808 | return emulate_multiple(regs, addr, reg, nb, |
802 | flags, instr, swiz); | 809 | flags, instr, swiz); |
810 | } | ||
803 | 811 | ||
804 | /* Verify the address of the operand */ | 812 | /* Verify the address of the operand */ |
805 | if (unlikely(user_mode(regs) && | 813 | if (unlikely(user_mode(regs) && |
@@ -816,8 +824,12 @@ int fix_alignment(struct pt_regs *regs) | |||
816 | } | 824 | } |
817 | 825 | ||
818 | /* Special case for 16-byte FP loads and stores */ | 826 | /* Special case for 16-byte FP loads and stores */ |
819 | if (nb == 16) | 827 | if (nb == 16) { |
828 | PPC_WARN_EMULATED(fp_pair); | ||
820 | return emulate_fp_pair(addr, reg, flags); | 829 | return emulate_fp_pair(addr, reg, flags); |
830 | } | ||
831 | |||
832 | PPC_WARN_EMULATED(unaligned); | ||
821 | 833 | ||
822 | /* If we are loading, get the data from user space, else | 834 | /* If we are loading, get the data from user space, else |
823 | * get it from register values | 835 | * get it from register values |