aboutsummaryrefslogtreecommitdiffstats
path: root/arch/powerpc/include
diff options
context:
space:
mode:
Diffstat (limited to 'arch/powerpc/include')
-rw-r--r--arch/powerpc/include/asm/Kbuild5
-rw-r--r--arch/powerpc/include/asm/archrandom.h18
-rw-r--r--arch/powerpc/include/asm/compat.h9
-rw-r--r--arch/powerpc/include/asm/cputable.h6
-rw-r--r--arch/powerpc/include/asm/exception-64e.h15
-rw-r--r--arch/powerpc/include/asm/exception-64s.h8
-rw-r--r--arch/powerpc/include/asm/fsl_ifc.h838
-rw-r--r--arch/powerpc/include/asm/hvcall.h5
-rw-r--r--arch/powerpc/include/asm/kvm_book3s.h5
-rw-r--r--arch/powerpc/include/asm/kvm_book3s_64.h12
-rw-r--r--arch/powerpc/include/asm/kvm_book3s_asm.h2
-rw-r--r--arch/powerpc/include/asm/kvm_booke_hv_asm.h17
-rw-r--r--arch/powerpc/include/asm/kvm_ppc.h2
-rw-r--r--arch/powerpc/include/asm/machdep.h7
-rw-r--r--arch/powerpc/include/asm/mce.h3
-rw-r--r--arch/powerpc/include/asm/mmu-book3e.h9
-rw-r--r--arch/powerpc/include/asm/opal.h66
-rw-r--r--arch/powerpc/include/asm/paca.h9
-rw-r--r--arch/powerpc/include/asm/perf_event_server.h1
-rw-r--r--arch/powerpc/include/asm/processor.h1
-rw-r--r--arch/powerpc/include/asm/ptrace.h16
-rw-r--r--arch/powerpc/include/asm/reg.h19
-rw-r--r--arch/powerpc/include/asm/rtas.h1
-rw-r--r--arch/powerpc/include/asm/smp.h2
-rw-r--r--arch/powerpc/include/asm/time.h1
-rw-r--r--arch/powerpc/include/asm/tm.h4
-rw-r--r--arch/powerpc/include/asm/topology.h1
27 files changed, 197 insertions, 885 deletions
diff --git a/arch/powerpc/include/asm/Kbuild b/arch/powerpc/include/asm/Kbuild
index 6c0a955a1b06..3fb1bc432f4f 100644
--- a/arch/powerpc/include/asm/Kbuild
+++ b/arch/powerpc/include/asm/Kbuild
@@ -1,7 +1,8 @@
1 1
2generic-y += clkdev.h 2generic-y += clkdev.h
3generic-y += hash.h
4generic-y += mcs_spinlock.h
5generic-y += preempt.h
3generic-y += rwsem.h 6generic-y += rwsem.h
4generic-y += trace_clock.h 7generic-y += trace_clock.h
5generic-y += preempt.h
6generic-y += vtime.h 8generic-y += vtime.h
7generic-y += hash.h
diff --git a/arch/powerpc/include/asm/archrandom.h b/arch/powerpc/include/asm/archrandom.h
index d853d163ba47..bde531103638 100644
--- a/arch/powerpc/include/asm/archrandom.h
+++ b/arch/powerpc/include/asm/archrandom.h
@@ -25,8 +25,26 @@ static inline int arch_get_random_int(unsigned int *v)
25 return rc; 25 return rc;
26} 26}
27 27
28static inline int arch_has_random(void)
29{
30 return !!ppc_md.get_random_long;
31}
32
28int powernv_get_random_long(unsigned long *v); 33int powernv_get_random_long(unsigned long *v);
29 34
35static inline int arch_get_random_seed_long(unsigned long *v)
36{
37 return 0;
38}
39static inline int arch_get_random_seed_int(unsigned int *v)
40{
41 return 0;
42}
43static inline int arch_has_random_seed(void)
44{
45 return 0;
46}
47
30#endif /* CONFIG_ARCH_RANDOM */ 48#endif /* CONFIG_ARCH_RANDOM */
31 49
32#endif /* _ASM_POWERPC_ARCHRANDOM_H */ 50#endif /* _ASM_POWERPC_ARCHRANDOM_H */
diff --git a/arch/powerpc/include/asm/compat.h b/arch/powerpc/include/asm/compat.h
index 84fdf6857c31..b142b8e0ed9e 100644
--- a/arch/powerpc/include/asm/compat.h
+++ b/arch/powerpc/include/asm/compat.h
@@ -8,7 +8,11 @@
8#include <linux/sched.h> 8#include <linux/sched.h>
9 9
10#define COMPAT_USER_HZ 100 10#define COMPAT_USER_HZ 100
11#ifdef __BIG_ENDIAN__
11#define COMPAT_UTS_MACHINE "ppc\0\0" 12#define COMPAT_UTS_MACHINE "ppc\0\0"
13#else
14#define COMPAT_UTS_MACHINE "ppcle\0\0"
15#endif
12 16
13typedef u32 compat_size_t; 17typedef u32 compat_size_t;
14typedef s32 compat_ssize_t; 18typedef s32 compat_ssize_t;
@@ -200,10 +204,11 @@ static inline void __user *arch_compat_alloc_user_space(long len)
200 204
201 /* 205 /*
202 * We can't access below the stack pointer in the 32bit ABI and 206 * We can't access below the stack pointer in the 32bit ABI and
203 * can access 288 bytes in the 64bit ABI 207 * can access 288 bytes in the 64bit big-endian ABI,
208 * or 512 bytes with the new ELFv2 little-endian ABI.
204 */ 209 */
205 if (!is_32bit_task()) 210 if (!is_32bit_task())
206 usp -= 288; 211 usp -= USER_REDZONE_SIZE;
207 212
208 return (void __user *) (usp - len); 213 return (void __user *) (usp - len);
209} 214}
diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h
index 617cc767c076..bc2347774f0a 100644
--- a/arch/powerpc/include/asm/cputable.h
+++ b/arch/powerpc/include/asm/cputable.h
@@ -189,6 +189,7 @@ extern const char *powerpc_base_platform;
189#define CPU_FTR_HAS_PPR LONG_ASM_CONST(0x0200000000000000) 189#define CPU_FTR_HAS_PPR LONG_ASM_CONST(0x0200000000000000)
190#define CPU_FTR_DAWR LONG_ASM_CONST(0x0400000000000000) 190#define CPU_FTR_DAWR LONG_ASM_CONST(0x0400000000000000)
191#define CPU_FTR_DABRX LONG_ASM_CONST(0x0800000000000000) 191#define CPU_FTR_DABRX LONG_ASM_CONST(0x0800000000000000)
192#define CPU_FTR_PMAO_BUG LONG_ASM_CONST(0x1000000000000000)
192 193
193#ifndef __ASSEMBLY__ 194#ifndef __ASSEMBLY__
194 195
@@ -445,6 +446,7 @@ extern const char *powerpc_base_platform;
445 CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \ 446 CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
446 CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_DAWR | \ 447 CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_DAWR | \
447 CPU_FTR_ARCH_207S | CPU_FTR_TM_COMP) 448 CPU_FTR_ARCH_207S | CPU_FTR_TM_COMP)
449#define CPU_FTRS_POWER8E (CPU_FTRS_POWER8 | CPU_FTR_PMAO_BUG)
448#define CPU_FTRS_CELL (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ 450#define CPU_FTRS_CELL (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
449 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ 451 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
450 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \ 452 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
@@ -466,8 +468,8 @@ extern const char *powerpc_base_platform;
466#define CPU_FTRS_POSSIBLE \ 468#define CPU_FTRS_POSSIBLE \
467 (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 | \ 469 (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 | \
468 CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 | \ 470 CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 | \
469 CPU_FTRS_POWER7 | CPU_FTRS_POWER8 | CPU_FTRS_CELL | \ 471 CPU_FTRS_POWER7 | CPU_FTRS_POWER8E | CPU_FTRS_POWER8 | \
470 CPU_FTRS_PA6T | CPU_FTR_VSX) 472 CPU_FTRS_CELL | CPU_FTRS_PA6T | CPU_FTR_VSX)
471#endif 473#endif
472#else 474#else
473enum { 475enum {
diff --git a/arch/powerpc/include/asm/exception-64e.h b/arch/powerpc/include/asm/exception-64e.h
index 51fa43e536b9..a563d9afd179 100644
--- a/arch/powerpc/include/asm/exception-64e.h
+++ b/arch/powerpc/include/asm/exception-64e.h
@@ -46,9 +46,8 @@
46#define EX_CR (1 * 8) 46#define EX_CR (1 * 8)
47#define EX_R10 (2 * 8) 47#define EX_R10 (2 * 8)
48#define EX_R11 (3 * 8) 48#define EX_R11 (3 * 8)
49#define EX_R13 (4 * 8) 49#define EX_R14 (4 * 8)
50#define EX_R14 (5 * 8) 50#define EX_R15 (5 * 8)
51#define EX_R15 (6 * 8)
52 51
53/* 52/*
54 * The TLB miss exception uses different slots. 53 * The TLB miss exception uses different slots.
@@ -173,16 +172,6 @@ exc_##label##_book3e:
173 ld r9,EX_TLB_R9(r12); \ 172 ld r9,EX_TLB_R9(r12); \
174 ld r8,EX_TLB_R8(r12); \ 173 ld r8,EX_TLB_R8(r12); \
175 mtlr r16; 174 mtlr r16;
176#define TLB_MISS_PROLOG_STATS_BOLTED \
177 mflr r10; \
178 std r8,PACA_EXTLB+EX_TLB_R8(r13); \
179 std r9,PACA_EXTLB+EX_TLB_R9(r13); \
180 std r10,PACA_EXTLB+EX_TLB_LR(r13);
181#define TLB_MISS_RESTORE_STATS_BOLTED \
182 ld r16,PACA_EXTLB+EX_TLB_LR(r13); \
183 ld r9,PACA_EXTLB+EX_TLB_R9(r13); \
184 ld r8,PACA_EXTLB+EX_TLB_R8(r13); \
185 mtlr r16;
186#define TLB_MISS_STATS_D(name) \ 175#define TLB_MISS_STATS_D(name) \
187 addi r9,r13,MMSTAT_DSTATS+name; \ 176 addi r9,r13,MMSTAT_DSTATS+name; \
188 bl .tlb_stat_inc; 177 bl .tlb_stat_inc;
diff --git a/arch/powerpc/include/asm/exception-64s.h b/arch/powerpc/include/asm/exception-64s.h
index 66830618cc19..aeaa56cd9b54 100644
--- a/arch/powerpc/include/asm/exception-64s.h
+++ b/arch/powerpc/include/asm/exception-64s.h
@@ -147,6 +147,14 @@ BEGIN_FTR_SECTION_NESTED(943) \
147END_FTR_SECTION_NESTED(ftr,ftr,943) 147END_FTR_SECTION_NESTED(ftr,ftr,943)
148 148
149/* 149/*
150 * Set an SPR from a register if the CPU has the given feature
151 */
152#define OPT_SET_SPR(ra, spr, ftr) \
153BEGIN_FTR_SECTION_NESTED(943) \
154 mtspr spr,ra; \
155END_FTR_SECTION_NESTED(ftr,ftr,943)
156
157/*
150 * Save a register to the PACA if the CPU has the given feature 158 * Save a register to the PACA if the CPU has the given feature
151 */ 159 */
152#define OPT_SAVE_REG_TO_PACA(offset, ra, ftr) \ 160#define OPT_SAVE_REG_TO_PACA(offset, ra, ftr) \
diff --git a/arch/powerpc/include/asm/fsl_ifc.h b/arch/powerpc/include/asm/fsl_ifc.h
deleted file mode 100644
index f49ddb1b2273..000000000000
--- a/arch/powerpc/include/asm/fsl_ifc.h
+++ /dev/null
@@ -1,838 +0,0 @@
1/* Freescale Integrated Flash Controller
2 *
3 * Copyright 2011 Freescale Semiconductor, Inc
4 *
5 * Author: Dipen Dudhat <dipen.dudhat@freescale.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#ifndef __ASM_FSL_IFC_H
23#define __ASM_FSL_IFC_H
24
25#include <linux/compiler.h>
26#include <linux/types.h>
27#include <linux/io.h>
28
29#include <linux/of_platform.h>
30#include <linux/interrupt.h>
31
32#define FSL_IFC_BANK_COUNT 4
33
34/*
35 * CSPR - Chip Select Property Register
36 */
37#define CSPR_BA 0xFFFF0000
38#define CSPR_BA_SHIFT 16
39#define CSPR_PORT_SIZE 0x00000180
40#define CSPR_PORT_SIZE_SHIFT 7
41/* Port Size 8 bit */
42#define CSPR_PORT_SIZE_8 0x00000080
43/* Port Size 16 bit */
44#define CSPR_PORT_SIZE_16 0x00000100
45/* Port Size 32 bit */
46#define CSPR_PORT_SIZE_32 0x00000180
47/* Write Protect */
48#define CSPR_WP 0x00000040
49#define CSPR_WP_SHIFT 6
50/* Machine Select */
51#define CSPR_MSEL 0x00000006
52#define CSPR_MSEL_SHIFT 1
53/* NOR */
54#define CSPR_MSEL_NOR 0x00000000
55/* NAND */
56#define CSPR_MSEL_NAND 0x00000002
57/* GPCM */
58#define CSPR_MSEL_GPCM 0x00000004
59/* Bank Valid */
60#define CSPR_V 0x00000001
61#define CSPR_V_SHIFT 0
62
63/*
64 * Address Mask Register
65 */
66#define IFC_AMASK_MASK 0xFFFF0000
67#define IFC_AMASK_SHIFT 16
68#define IFC_AMASK(n) (IFC_AMASK_MASK << \
69 (__ilog2(n) - IFC_AMASK_SHIFT))
70
71/*
72 * Chip Select Option Register IFC_NAND Machine
73 */
74/* Enable ECC Encoder */
75#define CSOR_NAND_ECC_ENC_EN 0x80000000
76#define CSOR_NAND_ECC_MODE_MASK 0x30000000
77/* 4 bit correction per 520 Byte sector */
78#define CSOR_NAND_ECC_MODE_4 0x00000000
79/* 8 bit correction per 528 Byte sector */
80#define CSOR_NAND_ECC_MODE_8 0x10000000
81/* Enable ECC Decoder */
82#define CSOR_NAND_ECC_DEC_EN 0x04000000
83/* Row Address Length */
84#define CSOR_NAND_RAL_MASK 0x01800000
85#define CSOR_NAND_RAL_SHIFT 20
86#define CSOR_NAND_RAL_1 0x00000000
87#define CSOR_NAND_RAL_2 0x00800000
88#define CSOR_NAND_RAL_3 0x01000000
89#define CSOR_NAND_RAL_4 0x01800000
90/* Page Size 512b, 2k, 4k */
91#define CSOR_NAND_PGS_MASK 0x00180000
92#define CSOR_NAND_PGS_SHIFT 16
93#define CSOR_NAND_PGS_512 0x00000000
94#define CSOR_NAND_PGS_2K 0x00080000
95#define CSOR_NAND_PGS_4K 0x00100000
96#define CSOR_NAND_PGS_8K 0x00180000
97/* Spare region Size */
98#define CSOR_NAND_SPRZ_MASK 0x0000E000
99#define CSOR_NAND_SPRZ_SHIFT 13
100#define CSOR_NAND_SPRZ_16 0x00000000
101#define CSOR_NAND_SPRZ_64 0x00002000
102#define CSOR_NAND_SPRZ_128 0x00004000
103#define CSOR_NAND_SPRZ_210 0x00006000
104#define CSOR_NAND_SPRZ_218 0x00008000
105#define CSOR_NAND_SPRZ_224 0x0000A000
106#define CSOR_NAND_SPRZ_CSOR_EXT 0x0000C000
107/* Pages Per Block */
108#define CSOR_NAND_PB_MASK 0x00000700
109#define CSOR_NAND_PB_SHIFT 8
110#define CSOR_NAND_PB(n) ((__ilog2(n) - 5) << CSOR_NAND_PB_SHIFT)
111/* Time for Read Enable High to Output High Impedance */
112#define CSOR_NAND_TRHZ_MASK 0x0000001C
113#define CSOR_NAND_TRHZ_SHIFT 2
114#define CSOR_NAND_TRHZ_20 0x00000000
115#define CSOR_NAND_TRHZ_40 0x00000004
116#define CSOR_NAND_TRHZ_60 0x00000008
117#define CSOR_NAND_TRHZ_80 0x0000000C
118#define CSOR_NAND_TRHZ_100 0x00000010
119/* Buffer control disable */
120#define CSOR_NAND_BCTLD 0x00000001
121
122/*
123 * Chip Select Option Register - NOR Flash Mode
124 */
125/* Enable Address shift Mode */
126#define CSOR_NOR_ADM_SHFT_MODE_EN 0x80000000
127/* Page Read Enable from NOR device */
128#define CSOR_NOR_PGRD_EN 0x10000000
129/* AVD Toggle Enable during Burst Program */
130#define CSOR_NOR_AVD_TGL_PGM_EN 0x01000000
131/* Address Data Multiplexing Shift */
132#define CSOR_NOR_ADM_MASK 0x0003E000
133#define CSOR_NOR_ADM_SHIFT_SHIFT 13
134#define CSOR_NOR_ADM_SHIFT(n) ((n) << CSOR_NOR_ADM_SHIFT_SHIFT)
135/* Type of the NOR device hooked */
136#define CSOR_NOR_NOR_MODE_AYSNC_NOR 0x00000000
137#define CSOR_NOR_NOR_MODE_AVD_NOR 0x00000020
138/* Time for Read Enable High to Output High Impedance */
139#define CSOR_NOR_TRHZ_MASK 0x0000001C
140#define CSOR_NOR_TRHZ_SHIFT 2
141#define CSOR_NOR_TRHZ_20 0x00000000
142#define CSOR_NOR_TRHZ_40 0x00000004
143#define CSOR_NOR_TRHZ_60 0x00000008
144#define CSOR_NOR_TRHZ_80 0x0000000C
145#define CSOR_NOR_TRHZ_100 0x00000010
146/* Buffer control disable */
147#define CSOR_NOR_BCTLD 0x00000001
148
149/*
150 * Chip Select Option Register - GPCM Mode
151 */
152/* GPCM Mode - Normal */
153#define CSOR_GPCM_GPMODE_NORMAL 0x00000000
154/* GPCM Mode - GenericASIC */
155#define CSOR_GPCM_GPMODE_ASIC 0x80000000
156/* Parity Mode odd/even */
157#define CSOR_GPCM_PARITY_EVEN 0x40000000
158/* Parity Checking enable/disable */
159#define CSOR_GPCM_PAR_EN 0x20000000
160/* GPCM Timeout Count */
161#define CSOR_GPCM_GPTO_MASK 0x0F000000
162#define CSOR_GPCM_GPTO_SHIFT 24
163#define CSOR_GPCM_GPTO(n) ((__ilog2(n) - 8) << CSOR_GPCM_GPTO_SHIFT)
164/* GPCM External Access Termination mode for read access */
165#define CSOR_GPCM_RGETA_EXT 0x00080000
166/* GPCM External Access Termination mode for write access */
167#define CSOR_GPCM_WGETA_EXT 0x00040000
168/* Address Data Multiplexing Shift */
169#define CSOR_GPCM_ADM_MASK 0x0003E000
170#define CSOR_GPCM_ADM_SHIFT_SHIFT 13
171#define CSOR_GPCM_ADM_SHIFT(n) ((n) << CSOR_GPCM_ADM_SHIFT_SHIFT)
172/* Generic ASIC Parity error indication delay */
173#define CSOR_GPCM_GAPERRD_MASK 0x00000180
174#define CSOR_GPCM_GAPERRD_SHIFT 7
175#define CSOR_GPCM_GAPERRD(n) (((n) - 1) << CSOR_GPCM_GAPERRD_SHIFT)
176/* Time for Read Enable High to Output High Impedance */
177#define CSOR_GPCM_TRHZ_MASK 0x0000001C
178#define CSOR_GPCM_TRHZ_20 0x00000000
179#define CSOR_GPCM_TRHZ_40 0x00000004
180#define CSOR_GPCM_TRHZ_60 0x00000008
181#define CSOR_GPCM_TRHZ_80 0x0000000C
182#define CSOR_GPCM_TRHZ_100 0x00000010
183/* Buffer control disable */
184#define CSOR_GPCM_BCTLD 0x00000001
185
186/*
187 * Ready Busy Status Register (RB_STAT)
188 */
189/* CSn is READY */
190#define IFC_RB_STAT_READY_CS0 0x80000000
191#define IFC_RB_STAT_READY_CS1 0x40000000
192#define IFC_RB_STAT_READY_CS2 0x20000000
193#define IFC_RB_STAT_READY_CS3 0x10000000
194
195/*
196 * General Control Register (GCR)
197 */
198#define IFC_GCR_MASK 0x8000F800
199/* reset all IFC hardware */
200#define IFC_GCR_SOFT_RST_ALL 0x80000000
201/* Turnaroud Time of external buffer */
202#define IFC_GCR_TBCTL_TRN_TIME 0x0000F800
203#define IFC_GCR_TBCTL_TRN_TIME_SHIFT 11
204
205/*
206 * Common Event and Error Status Register (CM_EVTER_STAT)
207 */
208/* Chip select error */
209#define IFC_CM_EVTER_STAT_CSER 0x80000000
210
211/*
212 * Common Event and Error Enable Register (CM_EVTER_EN)
213 */
214/* Chip select error checking enable */
215#define IFC_CM_EVTER_EN_CSEREN 0x80000000
216
217/*
218 * Common Event and Error Interrupt Enable Register (CM_EVTER_INTR_EN)
219 */
220/* Chip select error interrupt enable */
221#define IFC_CM_EVTER_INTR_EN_CSERIREN 0x80000000
222
223/*
224 * Common Transfer Error Attribute Register-0 (CM_ERATTR0)
225 */
226/* transaction type of error Read/Write */
227#define IFC_CM_ERATTR0_ERTYP_READ 0x80000000
228#define IFC_CM_ERATTR0_ERAID 0x0FF00000
229#define IFC_CM_ERATTR0_ERAID_SHIFT 20
230#define IFC_CM_ERATTR0_ESRCID 0x0000FF00
231#define IFC_CM_ERATTR0_ESRCID_SHIFT 8
232
233/*
234 * Clock Control Register (CCR)
235 */
236#define IFC_CCR_MASK 0x0F0F8800
237/* Clock division ratio */
238#define IFC_CCR_CLK_DIV_MASK 0x0F000000
239#define IFC_CCR_CLK_DIV_SHIFT 24
240#define IFC_CCR_CLK_DIV(n) ((n-1) << IFC_CCR_CLK_DIV_SHIFT)
241/* IFC Clock Delay */
242#define IFC_CCR_CLK_DLY_MASK 0x000F0000
243#define IFC_CCR_CLK_DLY_SHIFT 16
244#define IFC_CCR_CLK_DLY(n) ((n) << IFC_CCR_CLK_DLY_SHIFT)
245/* Invert IFC clock before sending out */
246#define IFC_CCR_INV_CLK_EN 0x00008000
247/* Fedback IFC Clock */
248#define IFC_CCR_FB_IFC_CLK_SEL 0x00000800
249
250/*
251 * Clock Status Register (CSR)
252 */
253/* Clk is stable */
254#define IFC_CSR_CLK_STAT_STABLE 0x80000000
255
256/*
257 * IFC_NAND Machine Specific Registers
258 */
259/*
260 * NAND Configuration Register (NCFGR)
261 */
262/* Auto Boot Mode */
263#define IFC_NAND_NCFGR_BOOT 0x80000000
264/* Addressing Mode-ROW0+n/COL0 */
265#define IFC_NAND_NCFGR_ADDR_MODE_RC0 0x00000000
266/* Addressing Mode-ROW0+n/COL0+n */
267#define IFC_NAND_NCFGR_ADDR_MODE_RC1 0x00400000
268/* Number of loop iterations of FIR sequences for multi page operations */
269#define IFC_NAND_NCFGR_NUM_LOOP_MASK 0x0000F000
270#define IFC_NAND_NCFGR_NUM_LOOP_SHIFT 12
271#define IFC_NAND_NCFGR_NUM_LOOP(n) ((n) << IFC_NAND_NCFGR_NUM_LOOP_SHIFT)
272/* Number of wait cycles */
273#define IFC_NAND_NCFGR_NUM_WAIT_MASK 0x000000FF
274#define IFC_NAND_NCFGR_NUM_WAIT_SHIFT 0
275
276/*
277 * NAND Flash Command Registers (NAND_FCR0/NAND_FCR1)
278 */
279/* General purpose FCM flash command bytes CMD0-CMD7 */
280#define IFC_NAND_FCR0_CMD0 0xFF000000
281#define IFC_NAND_FCR0_CMD0_SHIFT 24
282#define IFC_NAND_FCR0_CMD1 0x00FF0000
283#define IFC_NAND_FCR0_CMD1_SHIFT 16
284#define IFC_NAND_FCR0_CMD2 0x0000FF00
285#define IFC_NAND_FCR0_CMD2_SHIFT 8
286#define IFC_NAND_FCR0_CMD3 0x000000FF
287#define IFC_NAND_FCR0_CMD3_SHIFT 0
288#define IFC_NAND_FCR1_CMD4 0xFF000000
289#define IFC_NAND_FCR1_CMD4_SHIFT 24
290#define IFC_NAND_FCR1_CMD5 0x00FF0000
291#define IFC_NAND_FCR1_CMD5_SHIFT 16
292#define IFC_NAND_FCR1_CMD6 0x0000FF00
293#define IFC_NAND_FCR1_CMD6_SHIFT 8
294#define IFC_NAND_FCR1_CMD7 0x000000FF
295#define IFC_NAND_FCR1_CMD7_SHIFT 0
296
297/*
298 * Flash ROW and COL Address Register (ROWn, COLn)
299 */
300/* Main/spare region locator */
301#define IFC_NAND_COL_MS 0x80000000
302/* Column Address */
303#define IFC_NAND_COL_CA_MASK 0x00000FFF
304
305/*
306 * NAND Flash Byte Count Register (NAND_BC)
307 */
308/* Byte Count for read/Write */
309#define IFC_NAND_BC 0x000001FF
310
311/*
312 * NAND Flash Instruction Registers (NAND_FIR0/NAND_FIR1/NAND_FIR2)
313 */
314/* NAND Machine specific opcodes OP0-OP14*/
315#define IFC_NAND_FIR0_OP0 0xFC000000
316#define IFC_NAND_FIR0_OP0_SHIFT 26
317#define IFC_NAND_FIR0_OP1 0x03F00000
318#define IFC_NAND_FIR0_OP1_SHIFT 20
319#define IFC_NAND_FIR0_OP2 0x000FC000
320#define IFC_NAND_FIR0_OP2_SHIFT 14
321#define IFC_NAND_FIR0_OP3 0x00003F00
322#define IFC_NAND_FIR0_OP3_SHIFT 8
323#define IFC_NAND_FIR0_OP4 0x000000FC
324#define IFC_NAND_FIR0_OP4_SHIFT 2
325#define IFC_NAND_FIR1_OP5 0xFC000000
326#define IFC_NAND_FIR1_OP5_SHIFT 26
327#define IFC_NAND_FIR1_OP6 0x03F00000
328#define IFC_NAND_FIR1_OP6_SHIFT 20
329#define IFC_NAND_FIR1_OP7 0x000FC000
330#define IFC_NAND_FIR1_OP7_SHIFT 14
331#define IFC_NAND_FIR1_OP8 0x00003F00
332#define IFC_NAND_FIR1_OP8_SHIFT 8
333#define IFC_NAND_FIR1_OP9 0x000000FC
334#define IFC_NAND_FIR1_OP9_SHIFT 2
335#define IFC_NAND_FIR2_OP10 0xFC000000
336#define IFC_NAND_FIR2_OP10_SHIFT 26
337#define IFC_NAND_FIR2_OP11 0x03F00000
338#define IFC_NAND_FIR2_OP11_SHIFT 20
339#define IFC_NAND_FIR2_OP12 0x000FC000
340#define IFC_NAND_FIR2_OP12_SHIFT 14
341#define IFC_NAND_FIR2_OP13 0x00003F00
342#define IFC_NAND_FIR2_OP13_SHIFT 8
343#define IFC_NAND_FIR2_OP14 0x000000FC
344#define IFC_NAND_FIR2_OP14_SHIFT 2
345
346/*
347 * Instruction opcodes to be programmed
348 * in FIR registers- 6bits
349 */
350enum ifc_nand_fir_opcodes {
351 IFC_FIR_OP_NOP,
352 IFC_FIR_OP_CA0,
353 IFC_FIR_OP_CA1,
354 IFC_FIR_OP_CA2,
355 IFC_FIR_OP_CA3,
356 IFC_FIR_OP_RA0,
357 IFC_FIR_OP_RA1,
358 IFC_FIR_OP_RA2,
359 IFC_FIR_OP_RA3,
360 IFC_FIR_OP_CMD0,
361 IFC_FIR_OP_CMD1,
362 IFC_FIR_OP_CMD2,
363 IFC_FIR_OP_CMD3,
364 IFC_FIR_OP_CMD4,
365 IFC_FIR_OP_CMD5,
366 IFC_FIR_OP_CMD6,
367 IFC_FIR_OP_CMD7,
368 IFC_FIR_OP_CW0,
369 IFC_FIR_OP_CW1,
370 IFC_FIR_OP_CW2,
371 IFC_FIR_OP_CW3,
372 IFC_FIR_OP_CW4,
373 IFC_FIR_OP_CW5,
374 IFC_FIR_OP_CW6,
375 IFC_FIR_OP_CW7,
376 IFC_FIR_OP_WBCD,
377 IFC_FIR_OP_RBCD,
378 IFC_FIR_OP_BTRD,
379 IFC_FIR_OP_RDSTAT,
380 IFC_FIR_OP_NWAIT,
381 IFC_FIR_OP_WFR,
382 IFC_FIR_OP_SBRD,
383 IFC_FIR_OP_UA,
384 IFC_FIR_OP_RB,
385};
386
387/*
388 * NAND Chip Select Register (NAND_CSEL)
389 */
390#define IFC_NAND_CSEL 0x0C000000
391#define IFC_NAND_CSEL_SHIFT 26
392#define IFC_NAND_CSEL_CS0 0x00000000
393#define IFC_NAND_CSEL_CS1 0x04000000
394#define IFC_NAND_CSEL_CS2 0x08000000
395#define IFC_NAND_CSEL_CS3 0x0C000000
396
397/*
398 * NAND Operation Sequence Start (NANDSEQ_STRT)
399 */
400/* NAND Flash Operation Start */
401#define IFC_NAND_SEQ_STRT_FIR_STRT 0x80000000
402/* Automatic Erase */
403#define IFC_NAND_SEQ_STRT_AUTO_ERS 0x00800000
404/* Automatic Program */
405#define IFC_NAND_SEQ_STRT_AUTO_PGM 0x00100000
406/* Automatic Copyback */
407#define IFC_NAND_SEQ_STRT_AUTO_CPB 0x00020000
408/* Automatic Read Operation */
409#define IFC_NAND_SEQ_STRT_AUTO_RD 0x00004000
410/* Automatic Status Read */
411#define IFC_NAND_SEQ_STRT_AUTO_STAT_RD 0x00000800
412
413/*
414 * NAND Event and Error Status Register (NAND_EVTER_STAT)
415 */
416/* Operation Complete */
417#define IFC_NAND_EVTER_STAT_OPC 0x80000000
418/* Flash Timeout Error */
419#define IFC_NAND_EVTER_STAT_FTOER 0x08000000
420/* Write Protect Error */
421#define IFC_NAND_EVTER_STAT_WPER 0x04000000
422/* ECC Error */
423#define IFC_NAND_EVTER_STAT_ECCER 0x02000000
424/* RCW Load Done */
425#define IFC_NAND_EVTER_STAT_RCW_DN 0x00008000
426/* Boot Loadr Done */
427#define IFC_NAND_EVTER_STAT_BOOT_DN 0x00004000
428/* Bad Block Indicator search select */
429#define IFC_NAND_EVTER_STAT_BBI_SRCH_SE 0x00000800
430
431/*
432 * NAND Flash Page Read Completion Event Status Register
433 * (PGRDCMPL_EVT_STAT)
434 */
435#define PGRDCMPL_EVT_STAT_MASK 0xFFFF0000
436/* Small Page 0-15 Done */
437#define PGRDCMPL_EVT_STAT_SECTION_SP(n) (1 << (31 - (n)))
438/* Large Page(2K) 0-3 Done */
439#define PGRDCMPL_EVT_STAT_LP_2K(n) (0xF << (28 - (n)*4))
440/* Large Page(4K) 0-1 Done */
441#define PGRDCMPL_EVT_STAT_LP_4K(n) (0xFF << (24 - (n)*8))
442
443/*
444 * NAND Event and Error Enable Register (NAND_EVTER_EN)
445 */
446/* Operation complete event enable */
447#define IFC_NAND_EVTER_EN_OPC_EN 0x80000000
448/* Page read complete event enable */
449#define IFC_NAND_EVTER_EN_PGRDCMPL_EN 0x20000000
450/* Flash Timeout error enable */
451#define IFC_NAND_EVTER_EN_FTOER_EN 0x08000000
452/* Write Protect error enable */
453#define IFC_NAND_EVTER_EN_WPER_EN 0x04000000
454/* ECC error logging enable */
455#define IFC_NAND_EVTER_EN_ECCER_EN 0x02000000
456
457/*
458 * NAND Event and Error Interrupt Enable Register (NAND_EVTER_INTR_EN)
459 */
460/* Enable interrupt for operation complete */
461#define IFC_NAND_EVTER_INTR_OPCIR_EN 0x80000000
462/* Enable interrupt for Page read complete */
463#define IFC_NAND_EVTER_INTR_PGRDCMPLIR_EN 0x20000000
464/* Enable interrupt for Flash timeout error */
465#define IFC_NAND_EVTER_INTR_FTOERIR_EN 0x08000000
466/* Enable interrupt for Write protect error */
467#define IFC_NAND_EVTER_INTR_WPERIR_EN 0x04000000
468/* Enable interrupt for ECC error*/
469#define IFC_NAND_EVTER_INTR_ECCERIR_EN 0x02000000
470
471/*
472 * NAND Transfer Error Attribute Register-0 (NAND_ERATTR0)
473 */
474#define IFC_NAND_ERATTR0_MASK 0x0C080000
475/* Error on CS0-3 for NAND */
476#define IFC_NAND_ERATTR0_ERCS_CS0 0x00000000
477#define IFC_NAND_ERATTR0_ERCS_CS1 0x04000000
478#define IFC_NAND_ERATTR0_ERCS_CS2 0x08000000
479#define IFC_NAND_ERATTR0_ERCS_CS3 0x0C000000
480/* Transaction type of error Read/Write */
481#define IFC_NAND_ERATTR0_ERTTYPE_READ 0x00080000
482
483/*
484 * NAND Flash Status Register (NAND_FSR)
485 */
486/* First byte of data read from read status op */
487#define IFC_NAND_NFSR_RS0 0xFF000000
488/* Second byte of data read from read status op */
489#define IFC_NAND_NFSR_RS1 0x00FF0000
490
491/*
492 * ECC Error Status Registers (ECCSTAT0-ECCSTAT3)
493 */
494/* Number of ECC errors on sector n (n = 0-15) */
495#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_MASK 0x0F000000
496#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_SHIFT 24
497#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_MASK 0x000F0000
498#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_SHIFT 16
499#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_MASK 0x00000F00
500#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_SHIFT 8
501#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_MASK 0x0000000F
502#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_SHIFT 0
503#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_MASK 0x0F000000
504#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_SHIFT 24
505#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_MASK 0x000F0000
506#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_SHIFT 16
507#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_MASK 0x00000F00
508#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_SHIFT 8
509#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_MASK 0x0000000F
510#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_SHIFT 0
511#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_MASK 0x0F000000
512#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_SHIFT 24
513#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_MASK 0x000F0000
514#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_SHIFT 16
515#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_MASK 0x00000F00
516#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_SHIFT 8
517#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_MASK 0x0000000F
518#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_SHIFT 0
519#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_MASK 0x0F000000
520#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_SHIFT 24
521#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_MASK 0x000F0000
522#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_SHIFT 16
523#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_MASK 0x00000F00
524#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_SHIFT 8
525#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_MASK 0x0000000F
526#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_SHIFT 0
527
528/*
529 * NAND Control Register (NANDCR)
530 */
531#define IFC_NAND_NCR_FTOCNT_MASK 0x1E000000
532#define IFC_NAND_NCR_FTOCNT_SHIFT 25
533#define IFC_NAND_NCR_FTOCNT(n) ((_ilog2(n) - 8) << IFC_NAND_NCR_FTOCNT_SHIFT)
534
535/*
536 * NAND_AUTOBOOT_TRGR
537 */
538/* Trigger RCW load */
539#define IFC_NAND_AUTOBOOT_TRGR_RCW_LD 0x80000000
540/* Trigget Auto Boot */
541#define IFC_NAND_AUTOBOOT_TRGR_BOOT_LD 0x20000000
542
543/*
544 * NAND_MDR
545 */
546/* 1st read data byte when opcode SBRD */
547#define IFC_NAND_MDR_RDATA0 0xFF000000
548/* 2nd read data byte when opcode SBRD */
549#define IFC_NAND_MDR_RDATA1 0x00FF0000
550
551/*
552 * NOR Machine Specific Registers
553 */
554/*
555 * NOR Event and Error Status Register (NOR_EVTER_STAT)
556 */
557/* NOR Command Sequence Operation Complete */
558#define IFC_NOR_EVTER_STAT_OPC_NOR 0x80000000
559/* Write Protect Error */
560#define IFC_NOR_EVTER_STAT_WPER 0x04000000
561/* Command Sequence Timeout Error */
562#define IFC_NOR_EVTER_STAT_STOER 0x01000000
563
564/*
565 * NOR Event and Error Enable Register (NOR_EVTER_EN)
566 */
567/* NOR Command Seq complete event enable */
568#define IFC_NOR_EVTER_EN_OPCEN_NOR 0x80000000
569/* Write Protect Error Checking Enable */
570#define IFC_NOR_EVTER_EN_WPEREN 0x04000000
571/* Timeout Error Enable */
572#define IFC_NOR_EVTER_EN_STOEREN 0x01000000
573
574/*
575 * NOR Event and Error Interrupt Enable Register (NOR_EVTER_INTR_EN)
576 */
577/* Enable interrupt for OPC complete */
578#define IFC_NOR_EVTER_INTR_OPCEN_NOR 0x80000000
579/* Enable interrupt for write protect error */
580#define IFC_NOR_EVTER_INTR_WPEREN 0x04000000
581/* Enable interrupt for timeout error */
582#define IFC_NOR_EVTER_INTR_STOEREN 0x01000000
583
584/*
585 * NOR Transfer Error Attribute Register-0 (NOR_ERATTR0)
586 */
587/* Source ID for error transaction */
588#define IFC_NOR_ERATTR0_ERSRCID 0xFF000000
589/* AXI ID for error transation */
590#define IFC_NOR_ERATTR0_ERAID 0x000FF000
591/* Chip select corresponds to NOR error */
592#define IFC_NOR_ERATTR0_ERCS_CS0 0x00000000
593#define IFC_NOR_ERATTR0_ERCS_CS1 0x00000010
594#define IFC_NOR_ERATTR0_ERCS_CS2 0x00000020
595#define IFC_NOR_ERATTR0_ERCS_CS3 0x00000030
596/* Type of transaction read/write */
597#define IFC_NOR_ERATTR0_ERTYPE_READ 0x00000001
598
599/*
600 * NOR Transfer Error Attribute Register-2 (NOR_ERATTR2)
601 */
602#define IFC_NOR_ERATTR2_ER_NUM_PHASE_EXP 0x000F0000
603#define IFC_NOR_ERATTR2_ER_NUM_PHASE_PER 0x00000F00
604
605/*
606 * NOR Control Register (NORCR)
607 */
608#define IFC_NORCR_MASK 0x0F0F0000
609/* No. of Address/Data Phase */
610#define IFC_NORCR_NUM_PHASE_MASK 0x0F000000
611#define IFC_NORCR_NUM_PHASE_SHIFT 24
612#define IFC_NORCR_NUM_PHASE(n) ((n-1) << IFC_NORCR_NUM_PHASE_SHIFT)
613/* Sequence Timeout Count */
614#define IFC_NORCR_STOCNT_MASK 0x000F0000
615#define IFC_NORCR_STOCNT_SHIFT 16
616#define IFC_NORCR_STOCNT(n) ((__ilog2(n) - 8) << IFC_NORCR_STOCNT_SHIFT)
617
618/*
619 * GPCM Machine specific registers
620 */
621/*
622 * GPCM Event and Error Status Register (GPCM_EVTER_STAT)
623 */
624/* Timeout error */
625#define IFC_GPCM_EVTER_STAT_TOER 0x04000000
626/* Parity error */
627#define IFC_GPCM_EVTER_STAT_PER 0x01000000
628
629/*
630 * GPCM Event and Error Enable Register (GPCM_EVTER_EN)
631 */
632/* Timeout error enable */
633#define IFC_GPCM_EVTER_EN_TOER_EN 0x04000000
634/* Parity error enable */
635#define IFC_GPCM_EVTER_EN_PER_EN 0x01000000
636
637/*
638 * GPCM Event and Error Interrupt Enable Register (GPCM_EVTER_INTR_EN)
639 */
640/* Enable Interrupt for timeout error */
641#define IFC_GPCM_EEIER_TOERIR_EN 0x04000000
642/* Enable Interrupt for Parity error */
643#define IFC_GPCM_EEIER_PERIR_EN 0x01000000
644
645/*
646 * GPCM Transfer Error Attribute Register-0 (GPCM_ERATTR0)
647 */
648/* Source ID for error transaction */
649#define IFC_GPCM_ERATTR0_ERSRCID 0xFF000000
650/* AXI ID for error transaction */
651#define IFC_GPCM_ERATTR0_ERAID 0x000FF000
652/* Chip select corresponds to GPCM error */
653#define IFC_GPCM_ERATTR0_ERCS_CS0 0x00000000
654#define IFC_GPCM_ERATTR0_ERCS_CS1 0x00000040
655#define IFC_GPCM_ERATTR0_ERCS_CS2 0x00000080
656#define IFC_GPCM_ERATTR0_ERCS_CS3 0x000000C0
657/* Type of transaction read/Write */
658#define IFC_GPCM_ERATTR0_ERTYPE_READ 0x00000001
659
660/*
661 * GPCM Transfer Error Attribute Register-2 (GPCM_ERATTR2)
662 */
663/* On which beat of address/data parity error is observed */
664#define IFC_GPCM_ERATTR2_PERR_BEAT 0x00000C00
665/* Parity Error on byte */
666#define IFC_GPCM_ERATTR2_PERR_BYTE 0x000000F0
667/* Parity Error reported in addr or data phase */
668#define IFC_GPCM_ERATTR2_PERR_DATA_PHASE 0x00000001
669
670/*
671 * GPCM Status Register (GPCM_STAT)
672 */
673#define IFC_GPCM_STAT_BSY 0x80000000 /* GPCM is busy */
674
675/*
676 * IFC Controller NAND Machine registers
677 */
678struct fsl_ifc_nand {
679 __be32 ncfgr;
680 u32 res1[0x4];
681 __be32 nand_fcr0;
682 __be32 nand_fcr1;
683 u32 res2[0x8];
684 __be32 row0;
685 u32 res3;
686 __be32 col0;
687 u32 res4;
688 __be32 row1;
689 u32 res5;
690 __be32 col1;
691 u32 res6;
692 __be32 row2;
693 u32 res7;
694 __be32 col2;
695 u32 res8;
696 __be32 row3;
697 u32 res9;
698 __be32 col3;
699 u32 res10[0x24];
700 __be32 nand_fbcr;
701 u32 res11;
702 __be32 nand_fir0;
703 __be32 nand_fir1;
704 __be32 nand_fir2;
705 u32 res12[0x10];
706 __be32 nand_csel;
707 u32 res13;
708 __be32 nandseq_strt;
709 u32 res14;
710 __be32 nand_evter_stat;
711 u32 res15;
712 __be32 pgrdcmpl_evt_stat;
713 u32 res16[0x2];
714 __be32 nand_evter_en;
715 u32 res17[0x2];
716 __be32 nand_evter_intr_en;
717 u32 res18[0x2];
718 __be32 nand_erattr0;
719 __be32 nand_erattr1;
720 u32 res19[0x10];
721 __be32 nand_fsr;
722 u32 res20;
723 __be32 nand_eccstat[4];
724 u32 res21[0x20];
725 __be32 nanndcr;
726 u32 res22[0x2];
727 __be32 nand_autoboot_trgr;
728 u32 res23;
729 __be32 nand_mdr;
730 u32 res24[0x5C];
731};
732
733/*
734 * IFC controller NOR Machine registers
735 */
736struct fsl_ifc_nor {
737 __be32 nor_evter_stat;
738 u32 res1[0x2];
739 __be32 nor_evter_en;
740 u32 res2[0x2];
741 __be32 nor_evter_intr_en;
742 u32 res3[0x2];
743 __be32 nor_erattr0;
744 __be32 nor_erattr1;
745 __be32 nor_erattr2;
746 u32 res4[0x4];
747 __be32 norcr;
748 u32 res5[0xEF];
749};
750
751/*
752 * IFC controller GPCM Machine registers
753 */
754struct fsl_ifc_gpcm {
755 __be32 gpcm_evter_stat;
756 u32 res1[0x2];
757 __be32 gpcm_evter_en;
758 u32 res2[0x2];
759 __be32 gpcm_evter_intr_en;
760 u32 res3[0x2];
761 __be32 gpcm_erattr0;
762 __be32 gpcm_erattr1;
763 __be32 gpcm_erattr2;
764 __be32 gpcm_stat;
765 u32 res4[0x1F3];
766};
767
768/*
769 * IFC Controller Registers
770 */
771struct fsl_ifc_regs {
772 __be32 ifc_rev;
773 u32 res1[0x2];
774 struct {
775 __be32 cspr_ext;
776 __be32 cspr;
777 u32 res2;
778 } cspr_cs[FSL_IFC_BANK_COUNT];
779 u32 res3[0x19];
780 struct {
781 __be32 amask;
782 u32 res4[0x2];
783 } amask_cs[FSL_IFC_BANK_COUNT];
784 u32 res5[0x17];
785 struct {
786 __be32 csor_ext;
787 __be32 csor;
788 u32 res6;
789 } csor_cs[FSL_IFC_BANK_COUNT];
790 u32 res7[0x19];
791 struct {
792 __be32 ftim[4];
793 u32 res8[0x8];
794 } ftim_cs[FSL_IFC_BANK_COUNT];
795 u32 res9[0x60];
796 __be32 rb_stat;
797 u32 res10[0x2];
798 __be32 ifc_gcr;
799 u32 res11[0x2];
800 __be32 cm_evter_stat;
801 u32 res12[0x2];
802 __be32 cm_evter_en;
803 u32 res13[0x2];
804 __be32 cm_evter_intr_en;
805 u32 res14[0x2];
806 __be32 cm_erattr0;
807 __be32 cm_erattr1;
808 u32 res15[0x2];
809 __be32 ifc_ccr;
810 __be32 ifc_csr;
811 u32 res16[0x2EB];
812 struct fsl_ifc_nand ifc_nand;
813 struct fsl_ifc_nor ifc_nor;
814 struct fsl_ifc_gpcm ifc_gpcm;
815};
816
817extern unsigned int convert_ifc_address(phys_addr_t addr_base);
818extern int fsl_ifc_find(phys_addr_t addr_base);
819
820/* overview of the fsl ifc controller */
821
822struct fsl_ifc_ctrl {
823 /* device info */
824 struct device *dev;
825 struct fsl_ifc_regs __iomem *regs;
826 int irq;
827 int nand_irq;
828 spinlock_t lock;
829 void *nand;
830
831 u32 nand_stat;
832 wait_queue_head_t nand_wait;
833};
834
835extern struct fsl_ifc_ctrl *fsl_ifc_ctrl_dev;
836
837
838#endif /* __ASM_FSL_IFC_H */
diff --git a/arch/powerpc/include/asm/hvcall.h b/arch/powerpc/include/asm/hvcall.h
index d8b600b3f058..5dbbb29f5c3e 100644
--- a/arch/powerpc/include/asm/hvcall.h
+++ b/arch/powerpc/include/asm/hvcall.h
@@ -274,6 +274,11 @@
274/* Platform specific hcalls, used by KVM */ 274/* Platform specific hcalls, used by KVM */
275#define H_RTAS 0xf000 275#define H_RTAS 0xf000
276 276
277/* "Platform specific hcalls", provided by PHYP */
278#define H_GET_24X7_CATALOG_PAGE 0xF078
279#define H_GET_24X7_DATA 0xF07C
280#define H_GET_PERF_COUNTER_INFO 0xF080
281
277#ifndef __ASSEMBLY__ 282#ifndef __ASSEMBLY__
278 283
279/** 284/**
diff --git a/arch/powerpc/include/asm/kvm_book3s.h b/arch/powerpc/include/asm/kvm_book3s.h
index 83851aabfdc8..bb1e38a23ac7 100644
--- a/arch/powerpc/include/asm/kvm_book3s.h
+++ b/arch/powerpc/include/asm/kvm_book3s.h
@@ -304,6 +304,11 @@ static inline ulong kvmppc_get_fault_dar(struct kvm_vcpu *vcpu)
304 return vcpu->arch.fault_dar; 304 return vcpu->arch.fault_dar;
305} 305}
306 306
307static inline bool is_kvmppc_resume_guest(int r)
308{
309 return (r == RESUME_GUEST || r == RESUME_GUEST_NV);
310}
311
307/* Magic register values loaded into r3 and r4 before the 'sc' assembly 312/* Magic register values loaded into r3 and r4 before the 'sc' assembly
308 * instruction for the OSI hypercalls */ 313 * instruction for the OSI hypercalls */
309#define OSI_SC_MAGIC_R3 0x113724FA 314#define OSI_SC_MAGIC_R3 0x113724FA
diff --git a/arch/powerpc/include/asm/kvm_book3s_64.h b/arch/powerpc/include/asm/kvm_book3s_64.h
index bf0fa8b0a883..51388befeddb 100644
--- a/arch/powerpc/include/asm/kvm_book3s_64.h
+++ b/arch/powerpc/include/asm/kvm_book3s_64.h
@@ -289,6 +289,18 @@ static inline void note_hpte_modification(struct kvm *kvm,
289 if (atomic_read(&kvm->arch.hpte_mod_interest)) 289 if (atomic_read(&kvm->arch.hpte_mod_interest))
290 rev->guest_rpte |= HPTE_GR_MODIFIED; 290 rev->guest_rpte |= HPTE_GR_MODIFIED;
291} 291}
292
293/*
294 * Like kvm_memslots(), but for use in real mode when we can't do
295 * any RCU stuff (since the secondary threads are offline from the
296 * kernel's point of view), and we can't print anything.
297 * Thus we use rcu_dereference_raw() rather than rcu_dereference_check().
298 */
299static inline struct kvm_memslots *kvm_memslots_raw(struct kvm *kvm)
300{
301 return rcu_dereference_raw_notrace(kvm->memslots);
302}
303
292#endif /* CONFIG_KVM_BOOK3S_HV_POSSIBLE */ 304#endif /* CONFIG_KVM_BOOK3S_HV_POSSIBLE */
293 305
294#endif /* __ASM_KVM_BOOK3S_64_H__ */ 306#endif /* __ASM_KVM_BOOK3S_64_H__ */
diff --git a/arch/powerpc/include/asm/kvm_book3s_asm.h b/arch/powerpc/include/asm/kvm_book3s_asm.h
index f3a91dc02c98..821725c1bf46 100644
--- a/arch/powerpc/include/asm/kvm_book3s_asm.h
+++ b/arch/powerpc/include/asm/kvm_book3s_asm.h
@@ -94,7 +94,7 @@ struct kvmppc_host_state {
94 unsigned long xics_phys; 94 unsigned long xics_phys;
95 u32 saved_xirr; 95 u32 saved_xirr;
96 u64 dabr; 96 u64 dabr;
97 u64 host_mmcr[3]; 97 u64 host_mmcr[7]; /* MMCR 0,1,A, SIAR, SDAR, MMCR2, SIER */
98 u32 host_pmc[8]; 98 u32 host_pmc[8];
99 u64 host_purr; 99 u64 host_purr;
100 u64 host_spurr; 100 u64 host_spurr;
diff --git a/arch/powerpc/include/asm/kvm_booke_hv_asm.h b/arch/powerpc/include/asm/kvm_booke_hv_asm.h
index 3a79f5325712..e5f048bbcb7c 100644
--- a/arch/powerpc/include/asm/kvm_booke_hv_asm.h
+++ b/arch/powerpc/include/asm/kvm_booke_hv_asm.h
@@ -36,26 +36,21 @@
36 * *(r8 + GPR11) = saved r11 36 * *(r8 + GPR11) = saved r11
37 * 37 *
38 * 64-bit host 38 * 64-bit host
39 * Expected inputs (GEN/GDBELL/DBG/MC exception types): 39 * Expected inputs (GEN/GDBELL/DBG/CRIT/MC exception types):
40 * r10 = saved CR 40 * r10 = saved CR
41 * r13 = PACA_POINTER 41 * r13 = PACA_POINTER
42 * *(r13 + PACA_EX##type + EX_R10) = saved r10 42 * *(r13 + PACA_EX##type + EX_R10) = saved r10
43 * *(r13 + PACA_EX##type + EX_R11) = saved r11 43 * *(r13 + PACA_EX##type + EX_R11) = saved r11
44 * SPRN_SPRG_##type##_SCRATCH = saved r13 44 * SPRN_SPRG_##type##_SCRATCH = saved r13
45 * 45 *
46 * Expected inputs (CRIT exception type):
47 * r10 = saved CR
48 * r13 = PACA_POINTER
49 * *(r13 + PACA_EX##type + EX_R10) = saved r10
50 * *(r13 + PACA_EX##type + EX_R11) = saved r11
51 * *(r13 + PACA_EX##type + EX_R13) = saved r13
52 *
53 * Expected inputs (TLB exception type): 46 * Expected inputs (TLB exception type):
54 * r10 = saved CR 47 * r10 = saved CR
48 * r12 = extlb pointer
55 * r13 = PACA_POINTER 49 * r13 = PACA_POINTER
56 * *(r13 + PACA_EX##type + EX_TLB_R10) = saved r10 50 * *(r12 + EX_TLB_R10) = saved r10
57 * *(r13 + PACA_EX##type + EX_TLB_R11) = saved r11 51 * *(r12 + EX_TLB_R11) = saved r11
58 * SPRN_SPRG_GEN_SCRATCH = saved r13 52 * *(r12 + EX_TLB_R13) = saved r13
53 * SPRN_SPRG_GEN_SCRATCH = saved r12
59 * 54 *
60 * Only the bolted version of TLB miss exception handlers is supported now. 55 * Only the bolted version of TLB miss exception handlers is supported now.
61 */ 56 */
diff --git a/arch/powerpc/include/asm/kvm_ppc.h b/arch/powerpc/include/asm/kvm_ppc.h
index fcd53f0d34ba..4096f16502a9 100644
--- a/arch/powerpc/include/asm/kvm_ppc.h
+++ b/arch/powerpc/include/asm/kvm_ppc.h
@@ -129,6 +129,8 @@ extern long kvm_vm_ioctl_create_spapr_tce(struct kvm *kvm,
129 struct kvm_create_spapr_tce *args); 129 struct kvm_create_spapr_tce *args);
130extern long kvmppc_h_put_tce(struct kvm_vcpu *vcpu, unsigned long liobn, 130extern long kvmppc_h_put_tce(struct kvm_vcpu *vcpu, unsigned long liobn,
131 unsigned long ioba, unsigned long tce); 131 unsigned long ioba, unsigned long tce);
132extern long kvmppc_h_get_tce(struct kvm_vcpu *vcpu, unsigned long liobn,
133 unsigned long ioba);
132extern struct kvm_rma_info *kvm_alloc_rma(void); 134extern struct kvm_rma_info *kvm_alloc_rma(void);
133extern void kvm_release_rma(struct kvm_rma_info *ri); 135extern void kvm_release_rma(struct kvm_rma_info *ri);
134extern struct page *kvm_alloc_hpt(unsigned long nr_pages); 136extern struct page *kvm_alloc_hpt(unsigned long nr_pages);
diff --git a/arch/powerpc/include/asm/machdep.h b/arch/powerpc/include/asm/machdep.h
index ad3025d0880b..5b6c03f1058f 100644
--- a/arch/powerpc/include/asm/machdep.h
+++ b/arch/powerpc/include/asm/machdep.h
@@ -170,6 +170,9 @@ struct machdep_calls {
170 int (*system_reset_exception)(struct pt_regs *regs); 170 int (*system_reset_exception)(struct pt_regs *regs);
171 int (*machine_check_exception)(struct pt_regs *regs); 171 int (*machine_check_exception)(struct pt_regs *regs);
172 172
173 /* Called during machine check exception to retrive fixup address. */
174 bool (*mce_check_early_recovery)(struct pt_regs *regs);
175
173 /* Motherboard/chipset features. This is a kind of general purpose 176 /* Motherboard/chipset features. This is a kind of general purpose
174 * hook used to control some machine specific features (like reset 177 * hook used to control some machine specific features (like reset
175 * lines, chip power control, etc...). 178 * lines, chip power control, etc...).
@@ -279,6 +282,10 @@ struct machdep_calls {
279#ifdef CONFIG_ARCH_RANDOM 282#ifdef CONFIG_ARCH_RANDOM
280 int (*get_random_long)(unsigned long *v); 283 int (*get_random_long)(unsigned long *v);
281#endif 284#endif
285
286#ifdef CONFIG_MEMORY_HOTREMOVE
287 int (*remove_memory)(u64, u64);
288#endif
282}; 289};
283 290
284extern void e500_idle(void); 291extern void e500_idle(void);
diff --git a/arch/powerpc/include/asm/mce.h b/arch/powerpc/include/asm/mce.h
index 8e99edf6d966..f97d8cb6bdf6 100644
--- a/arch/powerpc/include/asm/mce.h
+++ b/arch/powerpc/include/asm/mce.h
@@ -187,7 +187,8 @@ struct mce_error_info {
187#define MCE_EVENT_DONTRELEASE false 187#define MCE_EVENT_DONTRELEASE false
188 188
189extern void save_mce_event(struct pt_regs *regs, long handled, 189extern void save_mce_event(struct pt_regs *regs, long handled,
190 struct mce_error_info *mce_err, uint64_t addr); 190 struct mce_error_info *mce_err, uint64_t nip,
191 uint64_t addr);
191extern int get_mce_event(struct machine_check_event *mce, bool release); 192extern int get_mce_event(struct machine_check_event *mce, bool release);
192extern void release_mce_event(void); 193extern void release_mce_event(void);
193extern void machine_check_queue_event(void); 194extern void machine_check_queue_event(void);
diff --git a/arch/powerpc/include/asm/mmu-book3e.h b/arch/powerpc/include/asm/mmu-book3e.h
index 89b785d16846..901dac6b6cb7 100644
--- a/arch/powerpc/include/asm/mmu-book3e.h
+++ b/arch/powerpc/include/asm/mmu-book3e.h
@@ -287,11 +287,14 @@ extern int mmu_linear_psize;
287extern int mmu_vmemmap_psize; 287extern int mmu_vmemmap_psize;
288 288
289struct tlb_core_data { 289struct tlb_core_data {
290 /*
291 * Per-core spinlock for e6500 TLB handlers (no tlbsrx.)
292 * Must be the first struct element.
293 */
294 u8 lock;
295
290 /* For software way selection, as on Freescale TLB1 */ 296 /* For software way selection, as on Freescale TLB1 */
291 u8 esel_next, esel_max, esel_first; 297 u8 esel_next, esel_max, esel_first;
292
293 /* Per-core spinlock for e6500 TLB handlers (no tlbsrx.) */
294 u8 lock;
295}; 298};
296 299
297#ifdef CONFIG_PPC64 300#ifdef CONFIG_PPC64
diff --git a/arch/powerpc/include/asm/opal.h b/arch/powerpc/include/asm/opal.h
index 40157e2ca691..fe2aa0b48d2b 100644
--- a/arch/powerpc/include/asm/opal.h
+++ b/arch/powerpc/include/asm/opal.h
@@ -83,6 +83,8 @@ extern int opal_enter_rtas(struct rtas_args *args,
83#define OPAL_INTERNAL_ERROR -11 83#define OPAL_INTERNAL_ERROR -11
84#define OPAL_BUSY_EVENT -12 84#define OPAL_BUSY_EVENT -12
85#define OPAL_HARDWARE_FROZEN -13 85#define OPAL_HARDWARE_FROZEN -13
86#define OPAL_WRONG_STATE -14
87#define OPAL_ASYNC_COMPLETION -15
86 88
87/* API Tokens (in r0) */ 89/* API Tokens (in r0) */
88#define OPAL_CONSOLE_WRITE 1 90#define OPAL_CONSOLE_WRITE 1
@@ -151,12 +153,27 @@ extern int opal_enter_rtas(struct rtas_args *args,
151#define OPAL_LPC_READ 67 153#define OPAL_LPC_READ 67
152#define OPAL_LPC_WRITE 68 154#define OPAL_LPC_WRITE 68
153#define OPAL_RETURN_CPU 69 155#define OPAL_RETURN_CPU 69
156#define OPAL_ELOG_READ 71
157#define OPAL_ELOG_WRITE 72
158#define OPAL_ELOG_ACK 73
159#define OPAL_ELOG_RESEND 74
160#define OPAL_ELOG_SIZE 75
154#define OPAL_FLASH_VALIDATE 76 161#define OPAL_FLASH_VALIDATE 76
155#define OPAL_FLASH_MANAGE 77 162#define OPAL_FLASH_MANAGE 77
156#define OPAL_FLASH_UPDATE 78 163#define OPAL_FLASH_UPDATE 78
164#define OPAL_RESYNC_TIMEBASE 79
165#define OPAL_DUMP_INIT 81
166#define OPAL_DUMP_INFO 82
167#define OPAL_DUMP_READ 83
168#define OPAL_DUMP_ACK 84
157#define OPAL_GET_MSG 85 169#define OPAL_GET_MSG 85
158#define OPAL_CHECK_ASYNC_COMPLETION 86 170#define OPAL_CHECK_ASYNC_COMPLETION 86
159#define OPAL_SYNC_HOST_REBOOT 87 171#define OPAL_SYNC_HOST_REBOOT 87
172#define OPAL_SENSOR_READ 88
173#define OPAL_GET_PARAM 89
174#define OPAL_SET_PARAM 90
175#define OPAL_DUMP_RESEND 91
176#define OPAL_DUMP_INFO2 94
160 177
161#ifndef __ASSEMBLY__ 178#ifndef __ASSEMBLY__
162 179
@@ -237,11 +254,14 @@ enum OpalPendingState {
237 OPAL_EVENT_EPOW = 0x80, 254 OPAL_EVENT_EPOW = 0x80,
238 OPAL_EVENT_LED_STATUS = 0x100, 255 OPAL_EVENT_LED_STATUS = 0x100,
239 OPAL_EVENT_PCI_ERROR = 0x200, 256 OPAL_EVENT_PCI_ERROR = 0x200,
257 OPAL_EVENT_DUMP_AVAIL = 0x400,
240 OPAL_EVENT_MSG_PENDING = 0x800, 258 OPAL_EVENT_MSG_PENDING = 0x800,
241}; 259};
242 260
243enum OpalMessageType { 261enum OpalMessageType {
244 OPAL_MSG_ASYNC_COMP = 0, 262 OPAL_MSG_ASYNC_COMP = 0, /* params[0] = token, params[1] = rc,
263 * additional params function-specific
264 */
245 OPAL_MSG_MEM_ERR, 265 OPAL_MSG_MEM_ERR,
246 OPAL_MSG_EPOW, 266 OPAL_MSG_EPOW,
247 OPAL_MSG_SHUTDOWN, 267 OPAL_MSG_SHUTDOWN,
@@ -394,6 +414,13 @@ enum OpalLPCAddressType {
394 OPAL_LPC_FW = 2, 414 OPAL_LPC_FW = 2,
395}; 415};
396 416
417/* System parameter permission */
418enum OpalSysparamPerm {
419 OPAL_SYSPARAM_READ = 0x1,
420 OPAL_SYSPARAM_WRITE = 0x2,
421 OPAL_SYSPARAM_RW = (OPAL_SYSPARAM_READ | OPAL_SYSPARAM_WRITE),
422};
423
397struct opal_msg { 424struct opal_msg {
398 uint32_t msg_type; 425 uint32_t msg_type;
399 uint32_t reserved; 426 uint32_t reserved;
@@ -816,23 +843,44 @@ int64_t opal_pci_next_error(uint64_t phb_id, uint64_t *first_frozen_pe,
816int64_t opal_pci_poll(uint64_t phb_id); 843int64_t opal_pci_poll(uint64_t phb_id);
817int64_t opal_return_cpu(void); 844int64_t opal_return_cpu(void);
818 845
819int64_t opal_xscom_read(uint32_t gcid, uint32_t pcb_addr, __be64 *val); 846int64_t opal_xscom_read(uint32_t gcid, uint64_t pcb_addr, __be64 *val);
820int64_t opal_xscom_write(uint32_t gcid, uint32_t pcb_addr, uint64_t val); 847int64_t opal_xscom_write(uint32_t gcid, uint64_t pcb_addr, uint64_t val);
821 848
822int64_t opal_lpc_write(uint32_t chip_id, enum OpalLPCAddressType addr_type, 849int64_t opal_lpc_write(uint32_t chip_id, enum OpalLPCAddressType addr_type,
823 uint32_t addr, uint32_t data, uint32_t sz); 850 uint32_t addr, uint32_t data, uint32_t sz);
824int64_t opal_lpc_read(uint32_t chip_id, enum OpalLPCAddressType addr_type, 851int64_t opal_lpc_read(uint32_t chip_id, enum OpalLPCAddressType addr_type,
825 uint32_t addr, __be32 *data, uint32_t sz); 852 uint32_t addr, __be32 *data, uint32_t sz);
853
854int64_t opal_read_elog(uint64_t buffer, size_t size, uint64_t log_id);
855int64_t opal_get_elog_size(uint64_t *log_id, size_t *size, uint64_t *elog_type);
856int64_t opal_write_elog(uint64_t buffer, uint64_t size, uint64_t offset);
857int64_t opal_send_ack_elog(uint64_t log_id);
858void opal_resend_pending_logs(void);
859
826int64_t opal_validate_flash(uint64_t buffer, uint32_t *size, uint32_t *result); 860int64_t opal_validate_flash(uint64_t buffer, uint32_t *size, uint32_t *result);
827int64_t opal_manage_flash(uint8_t op); 861int64_t opal_manage_flash(uint8_t op);
828int64_t opal_update_flash(uint64_t blk_list); 862int64_t opal_update_flash(uint64_t blk_list);
863int64_t opal_dump_init(uint8_t dump_type);
864int64_t opal_dump_info(uint32_t *dump_id, uint32_t *dump_size);
865int64_t opal_dump_info2(uint32_t *dump_id, uint32_t *dump_size, uint32_t *dump_type);
866int64_t opal_dump_read(uint32_t dump_id, uint64_t buffer);
867int64_t opal_dump_ack(uint32_t dump_id);
868int64_t opal_dump_resend_notification(void);
829 869
830int64_t opal_get_msg(uint64_t buffer, size_t size); 870int64_t opal_get_msg(uint64_t buffer, size_t size);
831int64_t opal_check_completion(uint64_t buffer, size_t size, uint64_t token); 871int64_t opal_check_completion(uint64_t buffer, size_t size, uint64_t token);
832int64_t opal_sync_host_reboot(void); 872int64_t opal_sync_host_reboot(void);
873int64_t opal_get_param(uint64_t token, uint32_t param_id, uint64_t buffer,
874 size_t length);
875int64_t opal_set_param(uint64_t token, uint32_t param_id, uint64_t buffer,
876 size_t length);
877int64_t opal_sensor_read(uint32_t sensor_hndl, int token,
878 uint32_t *sensor_data);
833 879
834/* Internal functions */ 880/* Internal functions */
835extern int early_init_dt_scan_opal(unsigned long node, const char *uname, int depth, void *data); 881extern int early_init_dt_scan_opal(unsigned long node, const char *uname, int depth, void *data);
882extern int early_init_dt_scan_recoverable_ranges(unsigned long node,
883 const char *uname, int depth, void *data);
836 884
837extern int opal_get_chars(uint32_t vtermno, char *buf, int count); 885extern int opal_get_chars(uint32_t vtermno, char *buf, int count);
838extern int opal_put_chars(uint32_t vtermno, const char *buf, int total_len); 886extern int opal_put_chars(uint32_t vtermno, const char *buf, int total_len);
@@ -853,6 +901,13 @@ extern void opal_notifier_update_evt(uint64_t evt_mask, uint64_t evt_val);
853extern int opal_get_chars(uint32_t vtermno, char *buf, int count); 901extern int opal_get_chars(uint32_t vtermno, char *buf, int count);
854extern int opal_put_chars(uint32_t vtermno, const char *buf, int total_len); 902extern int opal_put_chars(uint32_t vtermno, const char *buf, int total_len);
855 903
904extern int __opal_async_get_token(void);
905extern int opal_async_get_token_interruptible(void);
906extern int __opal_async_release_token(int token);
907extern int opal_async_release_token(int token);
908extern int opal_async_wait_response(uint64_t token, struct opal_msg *msg);
909extern int opal_get_sensor_data(u32 sensor_hndl, u32 *sensor_data);
910
856extern void hvc_opal_init_early(void); 911extern void hvc_opal_init_early(void);
857 912
858struct rtc_time; 913struct rtc_time;
@@ -861,10 +916,15 @@ extern void opal_get_rtc_time(struct rtc_time *tm);
861extern unsigned long opal_get_boot_time(void); 916extern unsigned long opal_get_boot_time(void);
862extern void opal_nvram_init(void); 917extern void opal_nvram_init(void);
863extern void opal_flash_init(void); 918extern void opal_flash_init(void);
919extern int opal_elog_init(void);
920extern void opal_platform_dump_init(void);
921extern void opal_sys_param_init(void);
864 922
865extern int opal_machine_check(struct pt_regs *regs); 923extern int opal_machine_check(struct pt_regs *regs);
924extern bool opal_mce_check_early_recovery(struct pt_regs *regs);
866 925
867extern void opal_shutdown(void); 926extern void opal_shutdown(void);
927extern int opal_resync_timebase(void);
868 928
869extern void opal_lpc_init(void); 929extern void opal_lpc_init(void);
870 930
diff --git a/arch/powerpc/include/asm/paca.h b/arch/powerpc/include/asm/paca.h
index 9c5dbc3833fb..8e956a0b6e85 100644
--- a/arch/powerpc/include/asm/paca.h
+++ b/arch/powerpc/include/asm/paca.h
@@ -116,8 +116,11 @@ struct paca_struct {
116 /* Shared by all threads of a core -- points to tcd of first thread */ 116 /* Shared by all threads of a core -- points to tcd of first thread */
117 struct tlb_core_data *tcd_ptr; 117 struct tlb_core_data *tcd_ptr;
118 118
119 /* We can have up to 3 levels of reentrancy in the TLB miss handler */ 119 /*
120 u64 extlb[3][EX_TLB_SIZE / sizeof(u64)]; 120 * We can have up to 3 levels of reentrancy in the TLB miss handler,
121 * in each of four exception levels (normal, crit, mcheck, debug).
122 */
123 u64 extlb[12][EX_TLB_SIZE / sizeof(u64)];
121 u64 exmc[8]; /* used for machine checks */ 124 u64 exmc[8]; /* used for machine checks */
122 u64 excrit[8]; /* used for crit interrupts */ 125 u64 excrit[8]; /* used for crit interrupts */
123 u64 exdbg[8]; /* used for debug interrupts */ 126 u64 exdbg[8]; /* used for debug interrupts */
@@ -146,7 +149,7 @@ struct paca_struct {
146 u8 io_sync; /* writel() needs spin_unlock sync */ 149 u8 io_sync; /* writel() needs spin_unlock sync */
147 u8 irq_work_pending; /* IRQ_WORK interrupt while soft-disable */ 150 u8 irq_work_pending; /* IRQ_WORK interrupt while soft-disable */
148 u8 nap_state_lost; /* NV GPR values lost in power7_idle */ 151 u8 nap_state_lost; /* NV GPR values lost in power7_idle */
149 u64 sprg3; /* Saved user-visible sprg */ 152 u64 sprg_vdso; /* Saved user-visible sprg */
150#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 153#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
151 u64 tm_scratch; /* TM scratch area for reclaim */ 154 u64 tm_scratch; /* TM scratch area for reclaim */
152#endif 155#endif
diff --git a/arch/powerpc/include/asm/perf_event_server.h b/arch/powerpc/include/asm/perf_event_server.h
index 3fd2f1b6f906..9ed737146dbb 100644
--- a/arch/powerpc/include/asm/perf_event_server.h
+++ b/arch/powerpc/include/asm/perf_event_server.h
@@ -14,6 +14,7 @@
14#include <linux/device.h> 14#include <linux/device.h>
15#include <uapi/asm/perf_event.h> 15#include <uapi/asm/perf_event.h>
16 16
17/* Update perf_event_print_debug() if this changes */
17#define MAX_HWEVENTS 8 18#define MAX_HWEVENTS 8
18#define MAX_EVENT_ALTERNATIVES 8 19#define MAX_EVENT_ALTERNATIVES 8
19#define MAX_LIMITED_HWCOUNTERS 2 20#define MAX_LIMITED_HWCOUNTERS 2
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index b62de43ae5f3..d660dc36831a 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -450,6 +450,7 @@ enum idle_boot_override {IDLE_NO_OVERRIDE = 0, IDLE_POWERSAVE_OFF};
450 450
451extern int powersave_nap; /* set if nap mode can be used in idle loop */ 451extern int powersave_nap; /* set if nap mode can be used in idle loop */
452extern void power7_nap(void); 452extern void power7_nap(void);
453extern void power7_sleep(void);
453extern void flush_instruction_cache(void); 454extern void flush_instruction_cache(void);
454extern void hard_reset_now(void); 455extern void hard_reset_now(void);
455extern void poweroff_now(void); 456extern void poweroff_now(void);
diff --git a/arch/powerpc/include/asm/ptrace.h b/arch/powerpc/include/asm/ptrace.h
index becc08e6a65c..279b80f3bb29 100644
--- a/arch/powerpc/include/asm/ptrace.h
+++ b/arch/powerpc/include/asm/ptrace.h
@@ -28,11 +28,23 @@
28 28
29#ifdef __powerpc64__ 29#ifdef __powerpc64__
30 30
31/*
32 * Size of redzone that userspace is allowed to use below the stack
33 * pointer. This is 288 in the 64-bit big-endian ELF ABI, and 512 in
34 * the new ELFv2 little-endian ABI, so we allow the larger amount.
35 *
36 * For kernel code we allow a 288-byte redzone, in order to conserve
37 * kernel stack space; gcc currently only uses 288 bytes, and will
38 * hopefully allow explicit control of the redzone size in future.
39 */
40#define USER_REDZONE_SIZE 512
41#define KERNEL_REDZONE_SIZE 288
42
31#define STACK_FRAME_OVERHEAD 112 /* size of minimum stack frame */ 43#define STACK_FRAME_OVERHEAD 112 /* size of minimum stack frame */
32#define STACK_FRAME_LR_SAVE 2 /* Location of LR in stack frame */ 44#define STACK_FRAME_LR_SAVE 2 /* Location of LR in stack frame */
33#define STACK_FRAME_REGS_MARKER ASM_CONST(0x7265677368657265) 45#define STACK_FRAME_REGS_MARKER ASM_CONST(0x7265677368657265)
34#define STACK_INT_FRAME_SIZE (sizeof(struct pt_regs) + \ 46#define STACK_INT_FRAME_SIZE (sizeof(struct pt_regs) + \
35 STACK_FRAME_OVERHEAD + 288) 47 STACK_FRAME_OVERHEAD + KERNEL_REDZONE_SIZE)
36#define STACK_FRAME_MARKER 12 48#define STACK_FRAME_MARKER 12
37 49
38/* Size of dummy stack frame allocated when calling signal handler. */ 50/* Size of dummy stack frame allocated when calling signal handler. */
@@ -41,6 +53,8 @@
41 53
42#else /* __powerpc64__ */ 54#else /* __powerpc64__ */
43 55
56#define USER_REDZONE_SIZE 0
57#define KERNEL_REDZONE_SIZE 0
44#define STACK_FRAME_OVERHEAD 16 /* size of minimum stack frame */ 58#define STACK_FRAME_OVERHEAD 16 /* size of minimum stack frame */
45#define STACK_FRAME_LR_SAVE 1 /* Location of LR in stack frame */ 59#define STACK_FRAME_LR_SAVE 1 /* Location of LR in stack frame */
46#define STACK_FRAME_REGS_MARKER ASM_CONST(0x72656773) 60#define STACK_FRAME_REGS_MARKER ASM_CONST(0x72656773)
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index 90c06ec6eff5..0dcc48af25a3 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -213,6 +213,7 @@
213#define SPRN_ACOP 0x1F /* Available Coprocessor Register */ 213#define SPRN_ACOP 0x1F /* Available Coprocessor Register */
214#define SPRN_TFIAR 0x81 /* Transaction Failure Inst Addr */ 214#define SPRN_TFIAR 0x81 /* Transaction Failure Inst Addr */
215#define SPRN_TEXASR 0x82 /* Transaction EXception & Summary */ 215#define SPRN_TEXASR 0x82 /* Transaction EXception & Summary */
216#define TEXASR_FS __MASK(63-36) /* Transaction Failure Summary */
216#define SPRN_TEXASRU 0x83 /* '' '' '' Upper 32 */ 217#define SPRN_TEXASRU 0x83 /* '' '' '' Upper 32 */
217#define SPRN_TFHAR 0x80 /* Transaction Failure Handler Addr */ 218#define SPRN_TFHAR 0x80 /* Transaction Failure Handler Addr */
218#define SPRN_CTRLF 0x088 219#define SPRN_CTRLF 0x088
@@ -577,9 +578,13 @@
577#define SPRN_SPRG3 0x113 /* Special Purpose Register General 3 */ 578#define SPRN_SPRG3 0x113 /* Special Purpose Register General 3 */
578#define SPRN_USPRG3 0x103 /* SPRG3 userspace read */ 579#define SPRN_USPRG3 0x103 /* SPRG3 userspace read */
579#define SPRN_SPRG4 0x114 /* Special Purpose Register General 4 */ 580#define SPRN_SPRG4 0x114 /* Special Purpose Register General 4 */
581#define SPRN_USPRG4 0x104 /* SPRG4 userspace read */
580#define SPRN_SPRG5 0x115 /* Special Purpose Register General 5 */ 582#define SPRN_SPRG5 0x115 /* Special Purpose Register General 5 */
583#define SPRN_USPRG5 0x105 /* SPRG5 userspace read */
581#define SPRN_SPRG6 0x116 /* Special Purpose Register General 6 */ 584#define SPRN_SPRG6 0x116 /* Special Purpose Register General 6 */
585#define SPRN_USPRG6 0x106 /* SPRG6 userspace read */
582#define SPRN_SPRG7 0x117 /* Special Purpose Register General 7 */ 586#define SPRN_SPRG7 0x117 /* Special Purpose Register General 7 */
587#define SPRN_USPRG7 0x107 /* SPRG7 userspace read */
583#define SPRN_SRR0 0x01A /* Save/Restore Register 0 */ 588#define SPRN_SRR0 0x01A /* Save/Restore Register 0 */
584#define SPRN_SRR1 0x01B /* Save/Restore Register 1 */ 589#define SPRN_SRR1 0x01B /* Save/Restore Register 1 */
585#define SRR1_ISI_NOPT 0x40000000 /* ISI: Not found in hash */ 590#define SRR1_ISI_NOPT 0x40000000 /* ISI: Not found in hash */
@@ -664,12 +669,14 @@
664#define MMCR0_PMXE 0x04000000UL /* performance monitor exception enable */ 669#define MMCR0_PMXE 0x04000000UL /* performance monitor exception enable */
665#define MMCR0_FCECE 0x02000000UL /* freeze ctrs on enabled cond or event */ 670#define MMCR0_FCECE 0x02000000UL /* freeze ctrs on enabled cond or event */
666#define MMCR0_TBEE 0x00400000UL /* time base exception enable */ 671#define MMCR0_TBEE 0x00400000UL /* time base exception enable */
672#define MMCR0_BHRBA 0x00200000UL /* BHRB Access allowed in userspace */
667#define MMCR0_EBE 0x00100000UL /* Event based branch enable */ 673#define MMCR0_EBE 0x00100000UL /* Event based branch enable */
668#define MMCR0_PMCC 0x000c0000UL /* PMC control */ 674#define MMCR0_PMCC 0x000c0000UL /* PMC control */
669#define MMCR0_PMCC_U6 0x00080000UL /* PMC1-6 are R/W by user (PR) */ 675#define MMCR0_PMCC_U6 0x00080000UL /* PMC1-6 are R/W by user (PR) */
670#define MMCR0_PMC1CE 0x00008000UL /* PMC1 count enable*/ 676#define MMCR0_PMC1CE 0x00008000UL /* PMC1 count enable*/
671#define MMCR0_PMCjCE 0x00004000UL /* PMCj count enable*/ 677#define MMCR0_PMCjCE 0x00004000UL /* PMCj count enable*/
672#define MMCR0_TRIGGER 0x00002000UL /* TRIGGER enable */ 678#define MMCR0_TRIGGER 0x00002000UL /* TRIGGER enable */
679#define MMCR0_PMAO_SYNC 0x00000800UL /* PMU interrupt is synchronous */
673#define MMCR0_PMAO 0x00000080UL /* performance monitor alert has occurred, set to 0 after handling exception */ 680#define MMCR0_PMAO 0x00000080UL /* performance monitor alert has occurred, set to 0 after handling exception */
674#define MMCR0_SHRFC 0x00000040UL /* SHRre freeze conditions between threads */ 681#define MMCR0_SHRFC 0x00000040UL /* SHRre freeze conditions between threads */
675#define MMCR0_FC56 0x00000010UL /* freeze counters 5 and 6 */ 682#define MMCR0_FC56 0x00000010UL /* freeze counters 5 and 6 */
@@ -703,6 +710,7 @@
703#define SPRN_EBBHR 804 /* Event based branch handler register */ 710#define SPRN_EBBHR 804 /* Event based branch handler register */
704#define SPRN_EBBRR 805 /* Event based branch return register */ 711#define SPRN_EBBRR 805 /* Event based branch return register */
705#define SPRN_BESCR 806 /* Branch event status and control register */ 712#define SPRN_BESCR 806 /* Branch event status and control register */
713#define BESCR_GE 0x8000000000000000ULL /* Global Enable */
706#define SPRN_WORT 895 /* Workload optimization register - thread */ 714#define SPRN_WORT 895 /* Workload optimization register - thread */
707 715
708#define SPRN_PMC1 787 716#define SPRN_PMC1 787
@@ -879,11 +887,10 @@
879 * 64-bit embedded 887 * 64-bit embedded
880 * - SPRG0 generic exception scratch 888 * - SPRG0 generic exception scratch
881 * - SPRG2 TLB exception stack 889 * - SPRG2 TLB exception stack
882 * - SPRG3 critical exception scratch and 890 * - SPRG3 critical exception scratch (user visible, sorry!)
883 * CPU and NUMA node for VDSO getcpu (user visible)
884 * - SPRG4 unused (user visible) 891 * - SPRG4 unused (user visible)
885 * - SPRG6 TLB miss scratch (user visible, sorry !) 892 * - SPRG6 TLB miss scratch (user visible, sorry !)
886 * - SPRG7 critical exception scratch 893 * - SPRG7 CPU and NUMA node for VDSO getcpu (user visible)
887 * - SPRG8 machine check exception scratch 894 * - SPRG8 machine check exception scratch
888 * - SPRG9 debug exception scratch 895 * - SPRG9 debug exception scratch
889 * 896 *
@@ -940,6 +947,8 @@
940#define SPRN_SPRG_SCRATCH0 SPRN_SPRG2 947#define SPRN_SPRG_SCRATCH0 SPRN_SPRG2
941#define SPRN_SPRG_HPACA SPRN_HSPRG0 948#define SPRN_SPRG_HPACA SPRN_HSPRG0
942#define SPRN_SPRG_HSCRATCH0 SPRN_HSPRG1 949#define SPRN_SPRG_HSCRATCH0 SPRN_HSPRG1
950#define SPRN_SPRG_VDSO_READ SPRN_USPRG3
951#define SPRN_SPRG_VDSO_WRITE SPRN_SPRG3
943 952
944#define GET_PACA(rX) \ 953#define GET_PACA(rX) \
945 BEGIN_FTR_SECTION_NESTED(66); \ 954 BEGIN_FTR_SECTION_NESTED(66); \
@@ -983,6 +992,8 @@
983#define SPRN_SPRG_TLB_SCRATCH SPRN_SPRG6 992#define SPRN_SPRG_TLB_SCRATCH SPRN_SPRG6
984#define SPRN_SPRG_GEN_SCRATCH SPRN_SPRG0 993#define SPRN_SPRG_GEN_SCRATCH SPRN_SPRG0
985#define SPRN_SPRG_GDBELL_SCRATCH SPRN_SPRG_GEN_SCRATCH 994#define SPRN_SPRG_GDBELL_SCRATCH SPRN_SPRG_GEN_SCRATCH
995#define SPRN_SPRG_VDSO_READ SPRN_USPRG7
996#define SPRN_SPRG_VDSO_WRITE SPRN_SPRG7
986 997
987#define SET_PACA(rX) mtspr SPRN_SPRG_PACA,rX 998#define SET_PACA(rX) mtspr SPRN_SPRG_PACA,rX
988#define GET_PACA(rX) mfspr rX,SPRN_SPRG_PACA 999#define GET_PACA(rX) mfspr rX,SPRN_SPRG_PACA
@@ -1102,6 +1113,8 @@
1102#define PVR_8560 0x80200000 1113#define PVR_8560 0x80200000
1103#define PVR_VER_E500V1 0x8020 1114#define PVR_VER_E500V1 0x8020
1104#define PVR_VER_E500V2 0x8021 1115#define PVR_VER_E500V2 0x8021
1116#define PVR_VER_E500MC 0x8023
1117#define PVR_VER_E5500 0x8024
1105#define PVR_VER_E6500 0x8040 1118#define PVR_VER_E6500 0x8040
1106 1119
1107/* 1120/*
diff --git a/arch/powerpc/include/asm/rtas.h b/arch/powerpc/include/asm/rtas.h
index 9bd52c65e66f..a0e1add01ef5 100644
--- a/arch/powerpc/include/asm/rtas.h
+++ b/arch/powerpc/include/asm/rtas.h
@@ -283,6 +283,7 @@ extern void pSeries_log_error(char *buf, unsigned int err_type, int fatal);
283 283
284#ifdef CONFIG_PPC_PSERIES 284#ifdef CONFIG_PPC_PSERIES
285extern int pseries_devicetree_update(s32 scope); 285extern int pseries_devicetree_update(s32 scope);
286extern void post_mobility_fixup(void);
286#endif 287#endif
287 288
288#ifdef CONFIG_PPC_RTAS_DAEMON 289#ifdef CONFIG_PPC_RTAS_DAEMON
diff --git a/arch/powerpc/include/asm/smp.h b/arch/powerpc/include/asm/smp.h
index 084e0807db98..ff51046b6466 100644
--- a/arch/powerpc/include/asm/smp.h
+++ b/arch/powerpc/include/asm/smp.h
@@ -120,7 +120,7 @@ extern int cpu_to_core_id(int cpu);
120 * in /proc/interrupts will be wrong!!! --Troy */ 120 * in /proc/interrupts will be wrong!!! --Troy */
121#define PPC_MSG_CALL_FUNCTION 0 121#define PPC_MSG_CALL_FUNCTION 0
122#define PPC_MSG_RESCHEDULE 1 122#define PPC_MSG_RESCHEDULE 1
123#define PPC_MSG_CALL_FUNC_SINGLE 2 123#define PPC_MSG_TICK_BROADCAST 2
124#define PPC_MSG_DEBUGGER_BREAK 3 124#define PPC_MSG_DEBUGGER_BREAK 3
125 125
126/* for irq controllers that have dedicated ipis per message (4) */ 126/* for irq controllers that have dedicated ipis per message (4) */
diff --git a/arch/powerpc/include/asm/time.h b/arch/powerpc/include/asm/time.h
index c1f267694acb..1d428e6007ca 100644
--- a/arch/powerpc/include/asm/time.h
+++ b/arch/powerpc/include/asm/time.h
@@ -28,6 +28,7 @@ extern struct clock_event_device decrementer_clockevent;
28struct rtc_time; 28struct rtc_time;
29extern void to_tm(int tim, struct rtc_time * tm); 29extern void to_tm(int tim, struct rtc_time * tm);
30extern void GregorianDay(struct rtc_time *tm); 30extern void GregorianDay(struct rtc_time *tm);
31extern void tick_broadcast_ipi_handler(void);
31 32
32extern void generic_calibrate_decr(void); 33extern void generic_calibrate_decr(void);
33 34
diff --git a/arch/powerpc/include/asm/tm.h b/arch/powerpc/include/asm/tm.h
index 0c9f8b74dd97..c22d704b6d41 100644
--- a/arch/powerpc/include/asm/tm.h
+++ b/arch/powerpc/include/asm/tm.h
@@ -7,6 +7,8 @@
7 7
8#include <uapi/asm/tm.h> 8#include <uapi/asm/tm.h>
9 9
10#ifndef __ASSEMBLY__
11
10#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 12#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
11extern void do_load_up_transact_fpu(struct thread_struct *thread); 13extern void do_load_up_transact_fpu(struct thread_struct *thread);
12extern void do_load_up_transact_altivec(struct thread_struct *thread); 14extern void do_load_up_transact_altivec(struct thread_struct *thread);
@@ -21,3 +23,5 @@ extern void tm_recheckpoint(struct thread_struct *thread,
21extern void tm_abort(uint8_t cause); 23extern void tm_abort(uint8_t cause);
22extern void tm_save_sprs(struct thread_struct *thread); 24extern void tm_save_sprs(struct thread_struct *thread);
23extern void tm_restore_sprs(struct thread_struct *thread); 25extern void tm_restore_sprs(struct thread_struct *thread);
26
27#endif /* __ASSEMBLY__ */
diff --git a/arch/powerpc/include/asm/topology.h b/arch/powerpc/include/asm/topology.h
index d0b5fca6b077..c9202151079f 100644
--- a/arch/powerpc/include/asm/topology.h
+++ b/arch/powerpc/include/asm/topology.h
@@ -99,7 +99,6 @@ static inline int prrn_is_enabled(void)
99 99
100#ifdef CONFIG_SMP 100#ifdef CONFIG_SMP
101#include <asm/cputable.h> 101#include <asm/cputable.h>
102#define smt_capable() (cpu_has_feature(CPU_FTR_SMT))
103 102
104#ifdef CONFIG_PPC64 103#ifdef CONFIG_PPC64
105#include <asm/smp.h> 104#include <asm/smp.h>
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-15 20:23:49 -0500