diff options
Diffstat (limited to 'arch/powerpc/include')
-rw-r--r-- | arch/powerpc/include/asm/processor.h | 4 | ||||
-rw-r--r-- | arch/powerpc/include/asm/reg.h | 31 | ||||
-rw-r--r-- | arch/powerpc/include/asm/switch_to.h | 9 |
3 files changed, 33 insertions, 11 deletions
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index 47a35b08b963..e378cccfca55 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h | |||
@@ -247,6 +247,10 @@ struct thread_struct { | |||
247 | unsigned long tm_orig_msr; /* Thread's MSR on ctx switch */ | 247 | unsigned long tm_orig_msr; /* Thread's MSR on ctx switch */ |
248 | struct pt_regs ckpt_regs; /* Checkpointed registers */ | 248 | struct pt_regs ckpt_regs; /* Checkpointed registers */ |
249 | 249 | ||
250 | unsigned long tm_tar; | ||
251 | unsigned long tm_ppr; | ||
252 | unsigned long tm_dscr; | ||
253 | |||
250 | /* | 254 | /* |
251 | * Transactional FP and VSX 0-31 register set. | 255 | * Transactional FP and VSX 0-31 register set. |
252 | * NOTE: the sense of these is the opposite of the integer ckpt_regs! | 256 | * NOTE: the sense of these is the opposite of the integer ckpt_regs! |
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h index 64264bf601f5..dc10bf549635 100644 --- a/arch/powerpc/include/asm/reg.h +++ b/arch/powerpc/include/asm/reg.h | |||
@@ -254,19 +254,28 @@ | |||
254 | #define SPRN_HRMOR 0x139 /* Real mode offset register */ | 254 | #define SPRN_HRMOR 0x139 /* Real mode offset register */ |
255 | #define SPRN_HSRR0 0x13A /* Hypervisor Save/Restore 0 */ | 255 | #define SPRN_HSRR0 0x13A /* Hypervisor Save/Restore 0 */ |
256 | #define SPRN_HSRR1 0x13B /* Hypervisor Save/Restore 1 */ | 256 | #define SPRN_HSRR1 0x13B /* Hypervisor Save/Restore 1 */ |
257 | /* HFSCR and FSCR bit numbers are the same */ | ||
258 | #define FSCR_TAR_LG 8 /* Enable Target Address Register */ | ||
259 | #define FSCR_EBB_LG 7 /* Enable Event Based Branching */ | ||
260 | #define FSCR_TM_LG 5 /* Enable Transactional Memory */ | ||
261 | #define FSCR_PM_LG 4 /* Enable prob/priv access to PMU SPRs */ | ||
262 | #define FSCR_BHRB_LG 3 /* Enable Branch History Rolling Buffer*/ | ||
263 | #define FSCR_DSCR_LG 2 /* Enable Data Stream Control Register */ | ||
264 | #define FSCR_VECVSX_LG 1 /* Enable VMX/VSX */ | ||
265 | #define FSCR_FP_LG 0 /* Enable Floating Point */ | ||
257 | #define SPRN_FSCR 0x099 /* Facility Status & Control Register */ | 266 | #define SPRN_FSCR 0x099 /* Facility Status & Control Register */ |
258 | #define FSCR_TAR (1 << (63-55)) /* Enable Target Address Register */ | 267 | #define FSCR_TAR __MASK(FSCR_TAR_LG) |
259 | #define FSCR_EBB (1 << (63-56)) /* Enable Event Based Branching */ | 268 | #define FSCR_EBB __MASK(FSCR_EBB_LG) |
260 | #define FSCR_DSCR (1 << (63-61)) /* Enable Data Stream Control Register */ | 269 | #define FSCR_DSCR __MASK(FSCR_DSCR_LG) |
261 | #define SPRN_HFSCR 0xbe /* HV=1 Facility Status & Control Register */ | 270 | #define SPRN_HFSCR 0xbe /* HV=1 Facility Status & Control Register */ |
262 | #define HFSCR_TAR (1 << (63-55)) /* Enable Target Address Register */ | 271 | #define HFSCR_TAR __MASK(FSCR_TAR_LG) |
263 | #define HFSCR_EBB (1 << (63-56)) /* Enable Event Based Branching */ | 272 | #define HFSCR_EBB __MASK(FSCR_EBB_LG) |
264 | #define HFSCR_TM (1 << (63-58)) /* Enable Transactional Memory */ | 273 | #define HFSCR_TM __MASK(FSCR_TM_LG) |
265 | #define HFSCR_PM (1 << (63-60)) /* Enable prob/priv access to PMU SPRs */ | 274 | #define HFSCR_PM __MASK(FSCR_PM_LG) |
266 | #define HFSCR_BHRB (1 << (63-59)) /* Enable Branch History Rolling Buffer*/ | 275 | #define HFSCR_BHRB __MASK(FSCR_BHRB_LG) |
267 | #define HFSCR_DSCR (1 << (63-61)) /* Enable Data Stream Control Register */ | 276 | #define HFSCR_DSCR __MASK(FSCR_DSCR_LG) |
268 | #define HFSCR_VECVSX (1 << (63-62)) /* Enable VMX/VSX */ | 277 | #define HFSCR_VECVSX __MASK(FSCR_VECVSX_LG) |
269 | #define HFSCR_FP (1 << (63-63)) /* Enable Floating Point */ | 278 | #define HFSCR_FP __MASK(FSCR_FP_LG) |
270 | #define SPRN_TAR 0x32f /* Target Address Register */ | 279 | #define SPRN_TAR 0x32f /* Target Address Register */ |
271 | #define SPRN_LPCR 0x13E /* LPAR Control Register */ | 280 | #define SPRN_LPCR 0x13E /* LPAR Control Register */ |
272 | #define LPCR_VPM0 (1ul << (63-0)) | 281 | #define LPCR_VPM0 (1ul << (63-0)) |
diff --git a/arch/powerpc/include/asm/switch_to.h b/arch/powerpc/include/asm/switch_to.h index 2c7edde8f1bb..2be5618cdec6 100644 --- a/arch/powerpc/include/asm/switch_to.h +++ b/arch/powerpc/include/asm/switch_to.h | |||
@@ -15,6 +15,15 @@ extern struct task_struct *__switch_to(struct task_struct *, | |||
15 | struct thread_struct; | 15 | struct thread_struct; |
16 | extern struct task_struct *_switch(struct thread_struct *prev, | 16 | extern struct task_struct *_switch(struct thread_struct *prev, |
17 | struct thread_struct *next); | 17 | struct thread_struct *next); |
18 | #ifdef CONFIG_PPC_BOOK3S_64 | ||
19 | static inline void save_tar(struct thread_struct *prev) | ||
20 | { | ||
21 | if (cpu_has_feature(CPU_FTR_ARCH_207S)) | ||
22 | prev->tar = mfspr(SPRN_TAR); | ||
23 | } | ||
24 | #else | ||
25 | static inline void save_tar(struct thread_struct *prev) {} | ||
26 | #endif | ||
18 | 27 | ||
19 | extern void load_up_fpu(void); | 28 | extern void load_up_fpu(void); |
20 | extern void enable_kernel_fp(void); | 29 | extern void enable_kernel_fp(void); |