diff options
Diffstat (limited to 'arch/powerpc/include')
-rw-r--r-- | arch/powerpc/include/asm/8xx_immap.h | 4 | ||||
-rw-r--r-- | arch/powerpc/include/asm/uninorth.h | 2 |
2 files changed, 3 insertions, 3 deletions
diff --git a/arch/powerpc/include/asm/8xx_immap.h b/arch/powerpc/include/asm/8xx_immap.h index 6b6dc20b0beb..bdf0563ba423 100644 --- a/arch/powerpc/include/asm/8xx_immap.h +++ b/arch/powerpc/include/asm/8xx_immap.h | |||
@@ -393,8 +393,8 @@ typedef struct fec { | |||
393 | uint fec_addr_low; /* lower 32 bits of station address */ | 393 | uint fec_addr_low; /* lower 32 bits of station address */ |
394 | ushort fec_addr_high; /* upper 16 bits of station address */ | 394 | ushort fec_addr_high; /* upper 16 bits of station address */ |
395 | ushort res1; /* reserved */ | 395 | ushort res1; /* reserved */ |
396 | uint fec_hash_table_high; /* upper 32-bits of hash table */ | 396 | uint fec_grp_hash_table_high; /* upper 32-bits of hash table */ |
397 | uint fec_hash_table_low; /* lower 32-bits of hash table */ | 397 | uint fec_grp_hash_table_low; /* lower 32-bits of hash table */ |
398 | uint fec_r_des_start; /* beginning of Rx descriptor ring */ | 398 | uint fec_r_des_start; /* beginning of Rx descriptor ring */ |
399 | uint fec_x_des_start; /* beginning of Tx descriptor ring */ | 399 | uint fec_x_des_start; /* beginning of Tx descriptor ring */ |
400 | uint fec_r_buff_size; /* Rx buffer size */ | 400 | uint fec_r_buff_size; /* Rx buffer size */ |
diff --git a/arch/powerpc/include/asm/uninorth.h b/arch/powerpc/include/asm/uninorth.h index ae9c899c8a6d..d12b11d7641e 100644 --- a/arch/powerpc/include/asm/uninorth.h +++ b/arch/powerpc/include/asm/uninorth.h | |||
@@ -60,7 +60,7 @@ | |||
60 | * | 60 | * |
61 | * Obviously, the GART is not cache coherent and so any change to it | 61 | * Obviously, the GART is not cache coherent and so any change to it |
62 | * must be flushed to memory (or maybe just make the GART space non | 62 | * must be flushed to memory (or maybe just make the GART space non |
63 | * cachable). AGP memory itself does't seem to be cache coherent neither. | 63 | * cachable). AGP memory itself doesn't seem to be cache coherent neither. |
64 | * | 64 | * |
65 | * In order to invalidate the GART (which is probably necessary to inval | 65 | * In order to invalidate the GART (which is probably necessary to inval |
66 | * the bridge internal TLBs), the following sequence has to be written, | 66 | * the bridge internal TLBs), the following sequence has to be written, |