1 files changed, 307 insertions, 0 deletions
diff --git a/arch/powerpc/include/uapi/asm/elf.h b/arch/powerpc/include/uapi/asm/elf.h
new file mode 100644
index 000000000000..05b8d560cfba
--- /dev/null
+++ b/arch/powerpc/include/uapi/asm/elf.h
@@ -0,0 +1,307 @@
+/*
+ * ELF register definitions..
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#ifndef _UAPI_ASM_POWERPC_ELF_H
+#define _UAPI_ASM_POWERPC_ELF_H
+#include <linux/types.h>
+#include <asm/ptrace.h>
+#include <asm/cputable.h>
+#include <asm/auxvec.h>
+/* PowerPC relocations defined by the ABIs */
+#define R_PPC_NONE              0
+#define R_PPC_ADDR32            1       /* 32bit absolute address */
+#define R_PPC_ADDR24            2       /* 26bit address, 2 bits ignored.  */
+#define R_PPC_ADDR16            3       /* 16bit absolute address */
+#define R_PPC_ADDR16_LO         4       /* lower 16bit of absolute address */
+#define R_PPC_ADDR16_HI         5       /* high 16bit of absolute address */
+#define R_PPC_ADDR16_HA         6       /* adjusted high 16bit */
+#define R_PPC_ADDR14            7       /* 16bit address, 2 bits ignored */
+#define R_PPC_ADDR14_BRTAKEN    8
+#define R_PPC_ADDR14_BRNTAKEN   9
+#define R_PPC_REL24             10      /* PC relative 26 bit */
+#define R_PPC_REL14             11      /* PC relative 16 bit */
+#define R_PPC_REL14_BRTAKEN     12
+#define R_PPC_REL14_BRNTAKEN    13
+#define R_PPC_GOT16             14
+#define R_PPC_GOT16_LO          15
+#define R_PPC_GOT16_HI          16
+#define R_PPC_GOT16_HA          17
+#define R_PPC_PLTREL24          18
+#define R_PPC_COPY              19
+#define R_PPC_GLOB_DAT          20
+#define R_PPC_JMP_SLOT          21
+#define R_PPC_RELATIVE          22
+#define R_PPC_LOCAL24PC         23
+#define R_PPC_UADDR32           24
+#define R_PPC_UADDR16           25
+#define R_PPC_REL32             26
+#define R_PPC_PLT32             27
+#define R_PPC_PLTREL32          28
+#define R_PPC_PLT16_LO          29
+#define R_PPC_PLT16_HI          30
+#define R_PPC_PLT16_HA          31
+#define R_PPC_SDAREL16          32
+#define R_PPC_SECTOFF           33
+#define R_PPC_SECTOFF_LO        34
+#define R_PPC_SECTOFF_HI        35
+#define R_PPC_SECTOFF_HA        36
+/* PowerPC relocations defined for the TLS access ABI.  */
+#define R_PPC_TLS               67 /* none      (sym+add)@tls */
+#define R_PPC_DTPMOD32          68 /* word32    (sym+add)@dtpmod */
+#define R_PPC_TPREL16           69 /* half16*   (sym+add)@tprel */
+#define R_PPC_TPREL16_LO        70 /* half16    (sym+add)@tprel@l */
+#define R_PPC_TPREL16_HI        71 /* half16    (sym+add)@tprel@h */
+#define R_PPC_TPREL16_HA        72 /* half16    (sym+add)@tprel@ha */
+#define R_PPC_TPREL32           73 /* word32    (sym+add)@tprel */
+#define R_PPC_DTPREL16          74 /* half16*   (sym+add)@dtprel */
+#define R_PPC_DTPREL16_LO       75 /* half16    (sym+add)@dtprel@l */
+#define R_PPC_DTPREL16_HI       76 /* half16    (sym+add)@dtprel@h */
+#define R_PPC_DTPREL16_HA       77 /* half16    (sym+add)@dtprel@ha */
+#define R_PPC_DTPREL32          78 /* word32    (sym+add)@dtprel */
+#define R_PPC_GOT_TLSGD16       79 /* half16*   (sym+add)@got@tlsgd */
+#define R_PPC_GOT_TLSGD16_LO    80 /* half16    (sym+add)@got@tlsgd@l */
+#define R_PPC_GOT_TLSGD16_HI    81 /* half16    (sym+add)@got@tlsgd@h */
+#define R_PPC_GOT_TLSGD16_HA    82 /* half16    (sym+add)@got@tlsgd@ha */
+#define R_PPC_GOT_TLSLD16       83 /* half16*   (sym+add)@got@tlsld */
+#define R_PPC_GOT_TLSLD16_LO    84 /* half16    (sym+add)@got@tlsld@l */
+#define R_PPC_GOT_TLSLD16_HI    85 /* half16    (sym+add)@got@tlsld@h */
+#define R_PPC_GOT_TLSLD16_HA    86 /* half16    (sym+add)@got@tlsld@ha */
+#define R_PPC_GOT_TPREL16       87 /* half16*   (sym+add)@got@tprel */
+#define R_PPC_GOT_TPREL16_LO    88 /* half16    (sym+add)@got@tprel@l */
+#define R_PPC_GOT_TPREL16_HI    89 /* half16    (sym+add)@got@tprel@h */
+#define R_PPC_GOT_TPREL16_HA    90 /* half16    (sym+add)@got@tprel@ha */
+#define R_PPC_GOT_DTPREL16      91 /* half16*   (sym+add)@got@dtprel */
+#define R_PPC_GOT_DTPREL16_LO   92 /* half16*   (sym+add)@got@dtprel@l */
+#define R_PPC_GOT_DTPREL16_HI   93 /* half16*   (sym+add)@got@dtprel@h */
+#define R_PPC_GOT_DTPREL16_HA   94 /* half16*   (sym+add)@got@dtprel@ha */
+/* keep this the last entry. */
+#define R_PPC_NUM               95
+#define ELF_NGREG       48      /* includes nip, msr, lr, etc. */
+#define ELF_NFPREG      33      /* includes fpscr */
+typedef unsigned long elf_greg_t64;
+typedef elf_greg_t64 elf_gregset_t64[ELF_NGREG];
+typedef unsigned int elf_greg_t32;
+typedef elf_greg_t32 elf_gregset_t32[ELF_NGREG];
+typedef elf_gregset_t32 compat_elf_gregset_t;
+/*
+ * ELF_ARCH, CLASS, and DATA are used to set parameters in the core dumps.
+ */
+#ifdef __powerpc64__
+# define ELF_NVRREG32   33      /* includes vscr & vrsave stuffed together */
+# define ELF_NVRREG     34      /* includes vscr & vrsave in split vectors */
+# define ELF_NVSRHALFREG 32     /* Half the vsx registers */
+# define ELF_GREG_TYPE  elf_greg_t64
+#else
+# define ELF_NEVRREG    34      /* includes acc (as 2) */
+# define ELF_NVRREG     33      /* includes vscr */
+# define ELF_GREG_TYPE  elf_greg_t32
+# define ELF_ARCH       EM_PPC
+# define ELF_CLASS      ELFCLASS32
+# define ELF_DATA       ELFDATA2MSB
+#endif /* __powerpc64__ */
+#ifndef ELF_ARCH
+# define ELF_ARCH       EM_PPC64
+# define ELF_CLASS      ELFCLASS64
+# define ELF_DATA       ELFDATA2MSB
+  typedef elf_greg_t64 elf_greg_t;
+  typedef elf_gregset_t64 elf_gregset_t;
+#else
+  /* Assumption: ELF_ARCH == EM_PPC and ELF_CLASS == ELFCLASS32 */
+  typedef elf_greg_t32 elf_greg_t;
+  typedef elf_gregset_t32 elf_gregset_t;
+#endif /* ELF_ARCH */
+/* Floating point registers */
+typedef double elf_fpreg_t;
+typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
+/* Altivec registers */
+/*
+ * The entries with indexes 0-31 contain the corresponding vector registers. 
+ * The entry with index 32 contains the vscr as the last word (offset 12) 
+ * within the quadword.  This allows the vscr to be stored as either a 
+ * quadword (since it must be copied via a vector register to/from storage) 
+ * or as a word.  
+ *
+ * 64-bit kernel notes: The entry at index 33 contains the vrsave as the first  
+ * word (offset 0) within the quadword.
+ *
+ * This definition of the VMX state is compatible with the current PPC32 
+ * ptrace interface.  This allows signal handling and ptrace to use the same 
+ * structures.  This also simplifies the implementation of a bi-arch 
+ * (combined (32- and 64-bit) gdb.
+ *
+ * Note that it's _not_ compatible with 32 bits ucontext which stuffs the
+ * vrsave along with vscr and so only uses 33 vectors for the register set
+ */
+typedef __vector128 elf_vrreg_t;
+typedef elf_vrreg_t elf_vrregset_t[ELF_NVRREG];
+#ifdef __powerpc64__
+typedef elf_vrreg_t elf_vrregset_t32[ELF_NVRREG32];
+typedef elf_fpreg_t elf_vsrreghalf_t32[ELF_NVSRHALFREG];
+#endif
+/*
+ * The requirements here are:
+ * - keep the final alignment of sp (sp & 0xf)
+ * - make sure the 32-bit value at the first 16 byte aligned position of
+ *   AUXV is greater than 16 for glibc compatibility.
+ *   AT_IGNOREPPC is used for that.
+ * - for compatibility with glibc ARCH_DLINFO must always be defined on PPC,
+ *   even if DLINFO_ARCH_ITEMS goes to zero or is undefined.
+ * update AT_VECTOR_SIZE_ARCH if the number of NEW_AUX_ENT entries changes
+ */
+#define ARCH_DLINFO                                                     \
+do {                                                                    \
+        /* Handle glibc compatibility. */                               \
+        NEW_AUX_ENT(AT_IGNOREPPC, AT_IGNOREPPC);                        \
+        NEW_AUX_ENT(AT_IGNOREPPC, AT_IGNOREPPC);                        \
+        /* Cache size items */                                          \
+        NEW_AUX_ENT(AT_DCACHEBSIZE, dcache_bsize);                      \
+        NEW_AUX_ENT(AT_ICACHEBSIZE, icache_bsize);                      \
+        NEW_AUX_ENT(AT_UCACHEBSIZE, ucache_bsize);                      \
+        VDSO_AUX_ENT(AT_SYSINFO_EHDR, current->mm->context.vdso_base);  \
+} while (0)
+/* PowerPC64 relocations defined by the ABIs */
+#define R_PPC64_NONE    R_PPC_NONE
+#define R_PPC64_ADDR32  R_PPC_ADDR32  /* 32bit absolute address.  */
+#define R_PPC64_ADDR24  R_PPC_ADDR24  /* 26bit address, word aligned.  */
+#define R_PPC64_ADDR16  R_PPC_ADDR16  /* 16bit absolute address. */
+#define R_PPC64_ADDR16_LO R_PPC_ADDR16_LO /* lower 16bits of abs. address.  */
+#define R_PPC64_ADDR16_HI R_PPC_ADDR16_HI /* high 16bits of abs. address. */
+#define R_PPC64_ADDR16_HA R_PPC_ADDR16_HA /* adjusted high 16bits.  */
+#define R_PPC64_ADDR14 R_PPC_ADDR14   /* 16bit address, word aligned.  */
+#define R_PPC64_ADDR14_BRTAKEN  R_PPC_ADDR14_BRTAKEN
+#define R_PPC64_ADDR14_BRNTAKEN R_PPC_ADDR14_BRNTAKEN
+#define R_PPC64_REL24   R_PPC_REL24 /* PC relative 26 bit, word aligned.  */
+#define R_PPC64_REL14   R_PPC_REL14 /* PC relative 16 bit. */
+#define R_PPC64_REL14_BRTAKEN   R_PPC_REL14_BRTAKEN
+#define R_PPC64_REL14_BRNTAKEN  R_PPC_REL14_BRNTAKEN
+#define R_PPC64_GOT16     R_PPC_GOT16
+#define R_PPC64_GOT16_LO  R_PPC_GOT16_LO
+#define R_PPC64_GOT16_HI  R_PPC_GOT16_HI
+#define R_PPC64_GOT16_HA  R_PPC_GOT16_HA
+#define R_PPC64_COPY      R_PPC_COPY
+#define R_PPC64_GLOB_DAT  R_PPC_GLOB_DAT
+#define R_PPC64_JMP_SLOT  R_PPC_JMP_SLOT
+#define R_PPC64_RELATIVE  R_PPC_RELATIVE
+#define R_PPC64_UADDR32   R_PPC_UADDR32
+#define R_PPC64_UADDR16   R_PPC_UADDR16
+#define R_PPC64_REL32     R_PPC_REL32
+#define R_PPC64_PLT32     R_PPC_PLT32
+#define R_PPC64_PLTREL32  R_PPC_PLTREL32
+#define R_PPC64_PLT16_LO  R_PPC_PLT16_LO
+#define R_PPC64_PLT16_HI  R_PPC_PLT16_HI
+#define R_PPC64_PLT16_HA  R_PPC_PLT16_HA
+#define R_PPC64_SECTOFF     R_PPC_SECTOFF
+#define R_PPC64_SECTOFF_LO  R_PPC_SECTOFF_LO
+#define R_PPC64_SECTOFF_HI  R_PPC_SECTOFF_HI
+#define R_PPC64_SECTOFF_HA  R_PPC_SECTOFF_HA
+#define R_PPC64_ADDR30          37  /* word30 (S + A - P) >> 2.  */
+#define R_PPC64_ADDR64          38  /* doubleword64 S + A.  */
+#define R_PPC64_ADDR16_HIGHER   39  /* half16 #higher(S + A).  */
+#define R_PPC64_ADDR16_HIGHERA  40  /* half16 #highera(S + A).  */
+#define R_PPC64_ADDR16_HIGHEST  41  /* half16 #highest(S + A).  */
+#define R_PPC64_ADDR16_HIGHESTA 42  /* half16 #highesta(S + A). */
+#define R_PPC64_UADDR64     43  /* doubleword64 S + A.  */
+#define R_PPC64_REL64       44  /* doubleword64 S + A - P.  */
+#define R_PPC64_PLT64       45  /* doubleword64 L + A.  */
+#define R_PPC64_PLTREL64    46  /* doubleword64 L + A - P.  */
+#define R_PPC64_TOC16       47  /* half16* S + A - .TOC.  */
+#define R_PPC64_TOC16_LO    48  /* half16 #lo(S + A - .TOC.).  */
+#define R_PPC64_TOC16_HI    49  /* half16 #hi(S + A - .TOC.).  */
+#define R_PPC64_TOC16_HA    50  /* half16 #ha(S + A - .TOC.).  */
+#define R_PPC64_TOC         51  /* doubleword64 .TOC. */
+#define R_PPC64_PLTGOT16    52  /* half16* M + A.  */
+#define R_PPC64_PLTGOT16_LO 53  /* half16 #lo(M + A).  */
+#define R_PPC64_PLTGOT16_HI 54  /* half16 #hi(M + A).  */
+#define R_PPC64_PLTGOT16_HA 55  /* half16 #ha(M + A).  */
+#define R_PPC64_ADDR16_DS      56 /* half16ds* (S + A) >> 2.  */
+#define R_PPC64_ADDR16_LO_DS   57 /* half16ds  #lo(S + A) >> 2.  */
+#define R_PPC64_GOT16_DS       58 /* half16ds* (G + A) >> 2.  */
+#define R_PPC64_GOT16_LO_DS    59 /* half16ds  #lo(G + A) >> 2.  */
+#define R_PPC64_PLT16_LO_DS    60 /* half16ds  #lo(L + A) >> 2.  */
+#define R_PPC64_SECTOFF_DS     61 /* half16ds* (R + A) >> 2.  */
+#define R_PPC64_SECTOFF_LO_DS  62 /* half16ds  #lo(R + A) >> 2.  */
+#define R_PPC64_TOC16_DS       63 /* half16ds* (S + A - .TOC.) >> 2.  */
+#define R_PPC64_TOC16_LO_DS    64 /* half16ds  #lo(S + A - .TOC.) >> 2.  */
+#define R_PPC64_PLTGOT16_DS    65 /* half16ds* (M + A) >> 2.  */
+#define R_PPC64_PLTGOT16_LO_DS 66 /* half16ds  #lo(M + A) >> 2.  */
+/* PowerPC64 relocations defined for the TLS access ABI.  */
+#define R_PPC64_TLS             67 /* none      (sym+add)@tls */
+#define R_PPC64_DTPMOD64        68 /* doubleword64 (sym+add)@dtpmod */
+#define R_PPC64_TPREL16         69 /* half16*   (sym+add)@tprel */
+#define R_PPC64_TPREL16_LO      70 /* half16    (sym+add)@tprel@l */
+#define R_PPC64_TPREL16_HI      71 /* half16    (sym+add)@tprel@h */
+#define R_PPC64_TPREL16_HA      72 /* half16    (sym+add)@tprel@ha */
+#define R_PPC64_TPREL64         73 /* doubleword64 (sym+add)@tprel */
+#define R_PPC64_DTPREL16        74 /* half16*   (sym+add)@dtprel */
+#define R_PPC64_DTPREL16_LO     75 /* half16    (sym+add)@dtprel@l */
+#define R_PPC64_DTPREL16_HI     76 /* half16    (sym+add)@dtprel@h */
+#define R_PPC64_DTPREL16_HA     77 /* half16    (sym+add)@dtprel@ha */
+#define R_PPC64_DTPREL64        78 /* doubleword64 (sym+add)@dtprel */
+#define R_PPC64_GOT_TLSGD16     79 /* half16*   (sym+add)@got@tlsgd */
+#define R_PPC64_GOT_TLSGD16_LO  80 /* half16    (sym+add)@got@tlsgd@l */
+#define R_PPC64_GOT_TLSGD16_HI  81 /* half16    (sym+add)@got@tlsgd@h */
+#define R_PPC64_GOT_TLSGD16_HA  82 /* half16    (sym+add)@got@tlsgd@ha */
+#define R_PPC64_GOT_TLSLD16     83 /* half16*   (sym+add)@got@tlsld */
+#define R_PPC64_GOT_TLSLD16_LO  84 /* half16    (sym+add)@got@tlsld@l */
+#define R_PPC64_GOT_TLSLD16_HI  85 /* half16    (sym+add)@got@tlsld@h */
+#define R_PPC64_GOT_TLSLD16_HA  86 /* half16    (sym+add)@got@tlsld@ha */
+#define R_PPC64_GOT_TPREL16_DS  87 /* half16ds* (sym+add)@got@tprel */
+#define R_PPC64_GOT_TPREL16_LO_DS 88 /* half16ds (sym+add)@got@tprel@l */
+#define R_PPC64_GOT_TPREL16_HI  89 /* half16    (sym+add)@got@tprel@h */
+#define R_PPC64_GOT_TPREL16_HA  90 /* half16    (sym+add)@got@tprel@ha */
+#define R_PPC64_GOT_DTPREL16_DS 91 /* half16ds* (sym+add)@got@dtprel */
+#define R_PPC64_GOT_DTPREL16_LO_DS 92 /* half16ds (sym+add)@got@dtprel@l */
+#define R_PPC64_GOT_DTPREL16_HI 93 /* half16    (sym+add)@got@dtprel@h */
+#define R_PPC64_GOT_DTPREL16_HA 94 /* half16    (sym+add)@got@dtprel@ha */
+#define R_PPC64_TPREL16_DS      95 /* half16ds* (sym+add)@tprel */
+#define R_PPC64_TPREL16_LO_DS   96 /* half16ds  (sym+add)@tprel@l */
+#define R_PPC64_TPREL16_HIGHER  97 /* half16    (sym+add)@tprel@higher */
+#define R_PPC64_TPREL16_HIGHERA 98 /* half16    (sym+add)@tprel@highera */
+#define R_PPC64_TPREL16_HIGHEST 99 /* half16    (sym+add)@tprel@highest */
+#define R_PPC64_TPREL16_HIGHESTA 100 /* half16  (sym+add)@tprel@highesta */
+#define R_PPC64_DTPREL16_DS     101 /* half16ds* (sym+add)@dtprel */
+#define R_PPC64_DTPREL16_LO_DS  102 /* half16ds (sym+add)@dtprel@l */
+#define R_PPC64_DTPREL16_HIGHER 103 /* half16   (sym+add)@dtprel@higher */
+#define R_PPC64_DTPREL16_HIGHERA 104 /* half16  (sym+add)@dtprel@highera */
+#define R_PPC64_DTPREL16_HIGHEST 105 /* half16  (sym+add)@dtprel@highest */
+#define R_PPC64_DTPREL16_HIGHESTA 106 /* half16 (sym+add)@dtprel@highesta */
+/* Keep this the last entry.  */
+#define R_PPC64_NUM             107
+/* There's actually a third entry here, but it's unused */
+struct ppc64_opd_entry
+{
+        unsigned long funcaddr;
+        unsigned long r2;
+};
+#endif /* _UAPI_ASM_POWERPC_ELF_H */

diff --git a/arch/powerpc/include/uapi/asm/elf.h b/arch/powerpc/include/uapi/asm/elf.h new file mode 100644 index 000000000000..05b8d560cfba --- /dev/null +++ b/arch/powerpc/include/uapi/asm/elf.h
@@ -0,0 +1,307 @@
	1	/*
	2	* ELF register definitions..
	3	*
	4	* This program is free software; you can redistribute it and/or
	5	* modify it under the terms of the GNU General Public License
	6	* as published by the Free Software Foundation; either version
	7	* 2 of the License, or (at your option) any later version.
	8	*/
	9	#ifndef _UAPI_ASM_POWERPC_ELF_H
	10	#define _UAPI_ASM_POWERPC_ELF_H
	11
	12
	13	#include <linux/types.h>
	14
	15	#include <asm/ptrace.h>
	16	#include <asm/cputable.h>
	17	#include <asm/auxvec.h>
	18
	19	/* PowerPC relocations defined by the ABIs */
	20	#define R_PPC_NONE 0
	21	#define R_PPC_ADDR32 1 /* 32bit absolute address */
	22	#define R_PPC_ADDR24 2 /* 26bit address, 2 bits ignored. */
	23	#define R_PPC_ADDR16 3 /* 16bit absolute address */
	24	#define R_PPC_ADDR16_LO 4 /* lower 16bit of absolute address */
	25	#define R_PPC_ADDR16_HI 5 /* high 16bit of absolute address */
	26	#define R_PPC_ADDR16_HA 6 /* adjusted high 16bit */
	27	#define R_PPC_ADDR14 7 /* 16bit address, 2 bits ignored */
	28	#define R_PPC_ADDR14_BRTAKEN 8
	29	#define R_PPC_ADDR14_BRNTAKEN 9
	30	#define R_PPC_REL24 10 /* PC relative 26 bit */
	31	#define R_PPC_REL14 11 /* PC relative 16 bit */
	32	#define R_PPC_REL14_BRTAKEN 12
	33	#define R_PPC_REL14_BRNTAKEN 13
	34	#define R_PPC_GOT16 14
	35	#define R_PPC_GOT16_LO 15
	36	#define R_PPC_GOT16_HI 16
	37	#define R_PPC_GOT16_HA 17
	38	#define R_PPC_PLTREL24 18
	39	#define R_PPC_COPY 19
	40	#define R_PPC_GLOB_DAT 20
	41	#define R_PPC_JMP_SLOT 21
	42	#define R_PPC_RELATIVE 22
	43	#define R_PPC_LOCAL24PC 23
	44	#define R_PPC_UADDR32 24
	45	#define R_PPC_UADDR16 25
	46	#define R_PPC_REL32 26
	47	#define R_PPC_PLT32 27
	48	#define R_PPC_PLTREL32 28
	49	#define R_PPC_PLT16_LO 29
	50	#define R_PPC_PLT16_HI 30
	51	#define R_PPC_PLT16_HA 31
	52	#define R_PPC_SDAREL16 32
	53	#define R_PPC_SECTOFF 33
	54	#define R_PPC_SECTOFF_LO 34
	55	#define R_PPC_SECTOFF_HI 35
	56	#define R_PPC_SECTOFF_HA 36
	57
	58	/* PowerPC relocations defined for the TLS access ABI. */
	59	#define R_PPC_TLS 67 /* none (sym+add)@tls */
	60	#define R_PPC_DTPMOD32 68 /* word32 (sym+add)@dtpmod */
	61	#define R_PPC_TPREL16 69 /* half16* (sym+add)@tprel */
	62	#define R_PPC_TPREL16_LO 70 /* half16 (sym+add)@tprel@l */
	63	#define R_PPC_TPREL16_HI 71 /* half16 (sym+add)@tprel@h */
	64	#define R_PPC_TPREL16_HA 72 /* half16 (sym+add)@tprel@ha */
	65	#define R_PPC_TPREL32 73 /* word32 (sym+add)@tprel */
	66	#define R_PPC_DTPREL16 74 /* half16* (sym+add)@dtprel */
	67	#define R_PPC_DTPREL16_LO 75 /* half16 (sym+add)@dtprel@l */
	68	#define R_PPC_DTPREL16_HI 76 /* half16 (sym+add)@dtprel@h */
	69	#define R_PPC_DTPREL16_HA 77 /* half16 (sym+add)@dtprel@ha */
	70	#define R_PPC_DTPREL32 78 /* word32 (sym+add)@dtprel */
	71	#define R_PPC_GOT_TLSGD16 79 /* half16* (sym+add)@got@tlsgd */
	72	#define R_PPC_GOT_TLSGD16_LO 80 /* half16 (sym+add)@got@tlsgd@l */
	73	#define R_PPC_GOT_TLSGD16_HI 81 /* half16 (sym+add)@got@tlsgd@h */
	74	#define R_PPC_GOT_TLSGD16_HA 82 /* half16 (sym+add)@got@tlsgd@ha */
	75	#define R_PPC_GOT_TLSLD16 83 /* half16* (sym+add)@got@tlsld */
	76	#define R_PPC_GOT_TLSLD16_LO 84 /* half16 (sym+add)@got@tlsld@l */
	77	#define R_PPC_GOT_TLSLD16_HI 85 /* half16 (sym+add)@got@tlsld@h */
	78	#define R_PPC_GOT_TLSLD16_HA 86 /* half16 (sym+add)@got@tlsld@ha */
	79	#define R_PPC_GOT_TPREL16 87 /* half16* (sym+add)@got@tprel */
	80	#define R_PPC_GOT_TPREL16_LO 88 /* half16 (sym+add)@got@tprel@l */
	81	#define R_PPC_GOT_TPREL16_HI 89 /* half16 (sym+add)@got@tprel@h */
	82	#define R_PPC_GOT_TPREL16_HA 90 /* half16 (sym+add)@got@tprel@ha */
	83	#define R_PPC_GOT_DTPREL16 91 /* half16* (sym+add)@got@dtprel */
	84	#define R_PPC_GOT_DTPREL16_LO 92 /* half16* (sym+add)@got@dtprel@l */
	85	#define R_PPC_GOT_DTPREL16_HI 93 /* half16* (sym+add)@got@dtprel@h */
	86	#define R_PPC_GOT_DTPREL16_HA 94 /* half16* (sym+add)@got@dtprel@ha */
	87
	88	/* keep this the last entry. */
	89	#define R_PPC_NUM 95
	90
	91
	92	#define ELF_NGREG 48 /* includes nip, msr, lr, etc. */
	93	#define ELF_NFPREG 33 /* includes fpscr */
	94
	95	typedef unsigned long elf_greg_t64;
	96	typedef elf_greg_t64 elf_gregset_t64[ELF_NGREG];
	97
	98	typedef unsigned int elf_greg_t32;
	99	typedef elf_greg_t32 elf_gregset_t32[ELF_NGREG];
	100	typedef elf_gregset_t32 compat_elf_gregset_t;
	101
	102	/*
	103	* ELF_ARCH, CLASS, and DATA are used to set parameters in the core dumps.
	104	*/
	105	#ifdef __powerpc64__
	106	# define ELF_NVRREG32 33 /* includes vscr & vrsave stuffed together */
	107	# define ELF_NVRREG 34 /* includes vscr & vrsave in split vectors */
	108	# define ELF_NVSRHALFREG 32 /* Half the vsx registers */
	109	# define ELF_GREG_TYPE elf_greg_t64
	110	#else
	111	# define ELF_NEVRREG 34 /* includes acc (as 2) */
	112	# define ELF_NVRREG 33 /* includes vscr */
	113	# define ELF_GREG_TYPE elf_greg_t32
	114	# define ELF_ARCH EM_PPC
	115	# define ELF_CLASS ELFCLASS32
	116	# define ELF_DATA ELFDATA2MSB
	117	#endif /* __powerpc64__ */
	118
	119	#ifndef ELF_ARCH
	120	# define ELF_ARCH EM_PPC64
	121	# define ELF_CLASS ELFCLASS64
	122	# define ELF_DATA ELFDATA2MSB
	123	typedef elf_greg_t64 elf_greg_t;
	124	typedef elf_gregset_t64 elf_gregset_t;
	125	#else
	126	/* Assumption: ELF_ARCH == EM_PPC and ELF_CLASS == ELFCLASS32 */
	127	typedef elf_greg_t32 elf_greg_t;
	128	typedef elf_gregset_t32 elf_gregset_t;
	129	#endif /* ELF_ARCH */
	130
	131	/* Floating point registers */
	132	typedef double elf_fpreg_t;
	133	typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
	134
	135	/* Altivec registers */
	136	/*
	137	* The entries with indexes 0-31 contain the corresponding vector registers.
	138	* The entry with index 32 contains the vscr as the last word (offset 12)
	139	* within the quadword. This allows the vscr to be stored as either a
	140	* quadword (since it must be copied via a vector register to/from storage)
	141	* or as a word.
	142	*
	143	* 64-bit kernel notes: The entry at index 33 contains the vrsave as the first
	144	* word (offset 0) within the quadword.
	145	*
	146	* This definition of the VMX state is compatible with the current PPC32
	147	* ptrace interface. This allows signal handling and ptrace to use the same
	148	* structures. This also simplifies the implementation of a bi-arch
	149	* (combined (32- and 64-bit) gdb.
	150	*
	151	* Note that it's _not_ compatible with 32 bits ucontext which stuffs the
	152	* vrsave along with vscr and so only uses 33 vectors for the register set
	153	*/
	154	typedef __vector128 elf_vrreg_t;
	155	typedef elf_vrreg_t elf_vrregset_t[ELF_NVRREG];
	156	#ifdef __powerpc64__
	157	typedef elf_vrreg_t elf_vrregset_t32[ELF_NVRREG32];
	158	typedef elf_fpreg_t elf_vsrreghalf_t32[ELF_NVSRHALFREG];
	159	#endif
	160
	161
	162	/*
	163	* The requirements here are:
	164	* - keep the final alignment of sp (sp & 0xf)
	165	* - make sure the 32-bit value at the first 16 byte aligned position of
	166	* AUXV is greater than 16 for glibc compatibility.
	167	* AT_IGNOREPPC is used for that.
	168	* - for compatibility with glibc ARCH_DLINFO must always be defined on PPC,
	169	* even if DLINFO_ARCH_ITEMS goes to zero or is undefined.
	170	* update AT_VECTOR_SIZE_ARCH if the number of NEW_AUX_ENT entries changes
	171	*/
	172	#define ARCH_DLINFO \
	173	do { \
	174	/* Handle glibc compatibility. */ \
	175	NEW_AUX_ENT(AT_IGNOREPPC, AT_IGNOREPPC); \
	176	NEW_AUX_ENT(AT_IGNOREPPC, AT_IGNOREPPC); \
	177	/* Cache size items */ \
	178	NEW_AUX_ENT(AT_DCACHEBSIZE, dcache_bsize); \
	179	NEW_AUX_ENT(AT_ICACHEBSIZE, icache_bsize); \
	180	NEW_AUX_ENT(AT_UCACHEBSIZE, ucache_bsize); \
	181	VDSO_AUX_ENT(AT_SYSINFO_EHDR, current->mm->context.vdso_base); \
	182	} while (0)
	183
	184	/* PowerPC64 relocations defined by the ABIs */
	185	#define R_PPC64_NONE R_PPC_NONE
	186	#define R_PPC64_ADDR32 R_PPC_ADDR32 /* 32bit absolute address. */
	187	#define R_PPC64_ADDR24 R_PPC_ADDR24 /* 26bit address, word aligned. */
	188	#define R_PPC64_ADDR16 R_PPC_ADDR16 /* 16bit absolute address. */
	189	#define R_PPC64_ADDR16_LO R_PPC_ADDR16_LO /* lower 16bits of abs. address. */
	190	#define R_PPC64_ADDR16_HI R_PPC_ADDR16_HI /* high 16bits of abs. address. */
	191	#define R_PPC64_ADDR16_HA R_PPC_ADDR16_HA /* adjusted high 16bits. */
	192	#define R_PPC64_ADDR14 R_PPC_ADDR14 /* 16bit address, word aligned. */
	193	#define R_PPC64_ADDR14_BRTAKEN R_PPC_ADDR14_BRTAKEN
	194	#define R_PPC64_ADDR14_BRNTAKEN R_PPC_ADDR14_BRNTAKEN
	195	#define R_PPC64_REL24 R_PPC_REL24 /* PC relative 26 bit, word aligned. */
	196	#define R_PPC64_REL14 R_PPC_REL14 /* PC relative 16 bit. */
	197	#define R_PPC64_REL14_BRTAKEN R_PPC_REL14_BRTAKEN
	198	#define R_PPC64_REL14_BRNTAKEN R_PPC_REL14_BRNTAKEN
	199	#define R_PPC64_GOT16 R_PPC_GOT16
	200	#define R_PPC64_GOT16_LO R_PPC_GOT16_LO
	201	#define R_PPC64_GOT16_HI R_PPC_GOT16_HI
	202	#define R_PPC64_GOT16_HA R_PPC_GOT16_HA
	203
	204	#define R_PPC64_COPY R_PPC_COPY
	205	#define R_PPC64_GLOB_DAT R_PPC_GLOB_DAT
	206	#define R_PPC64_JMP_SLOT R_PPC_JMP_SLOT
	207	#define R_PPC64_RELATIVE R_PPC_RELATIVE
	208
	209	#define R_PPC64_UADDR32 R_PPC_UADDR32
	210	#define R_PPC64_UADDR16 R_PPC_UADDR16
	211	#define R_PPC64_REL32 R_PPC_REL32
	212	#define R_PPC64_PLT32 R_PPC_PLT32
	213	#define R_PPC64_PLTREL32 R_PPC_PLTREL32
	214	#define R_PPC64_PLT16_LO R_PPC_PLT16_LO
	215	#define R_PPC64_PLT16_HI R_PPC_PLT16_HI
	216	#define R_PPC64_PLT16_HA R_PPC_PLT16_HA
	217
	218	#define R_PPC64_SECTOFF R_PPC_SECTOFF
	219	#define R_PPC64_SECTOFF_LO R_PPC_SECTOFF_LO
	220	#define R_PPC64_SECTOFF_HI R_PPC_SECTOFF_HI
	221	#define R_PPC64_SECTOFF_HA R_PPC_SECTOFF_HA
	222	#define R_PPC64_ADDR30 37 /* word30 (S + A - P) >> 2. */
	223	#define R_PPC64_ADDR64 38 /* doubleword64 S + A. */
	224	#define R_PPC64_ADDR16_HIGHER 39 /* half16 #higher(S + A). */
	225	#define R_PPC64_ADDR16_HIGHERA 40 /* half16 #highera(S + A). */
	226	#define R_PPC64_ADDR16_HIGHEST 41 /* half16 #highest(S + A). */
	227	#define R_PPC64_ADDR16_HIGHESTA 42 /* half16 #highesta(S + A). */
	228	#define R_PPC64_UADDR64 43 /* doubleword64 S + A. */
	229	#define R_PPC64_REL64 44 /* doubleword64 S + A - P. */
	230	#define R_PPC64_PLT64 45 /* doubleword64 L + A. */
	231	#define R_PPC64_PLTREL64 46 /* doubleword64 L + A - P. */
	232	#define R_PPC64_TOC16 47 /* half16* S + A - .TOC. */
	233	#define R_PPC64_TOC16_LO 48 /* half16 #lo(S + A - .TOC.). */
	234	#define R_PPC64_TOC16_HI 49 /* half16 #hi(S + A - .TOC.). */
	235	#define R_PPC64_TOC16_HA 50 /* half16 #ha(S + A - .TOC.). */
	236	#define R_PPC64_TOC 51 /* doubleword64 .TOC. */
	237	#define R_PPC64_PLTGOT16 52 /* half16* M + A. */
	238	#define R_PPC64_PLTGOT16_LO 53 /* half16 #lo(M + A). */
	239	#define R_PPC64_PLTGOT16_HI 54 /* half16 #hi(M + A). */
	240	#define R_PPC64_PLTGOT16_HA 55 /* half16 #ha(M + A). */
	241
	242	#define R_PPC64_ADDR16_DS 56 /* half16ds* (S + A) >> 2. */
	243	#define R_PPC64_ADDR16_LO_DS 57 /* half16ds #lo(S + A) >> 2. */
	244	#define R_PPC64_GOT16_DS 58 /* half16ds* (G + A) >> 2. */
	245	#define R_PPC64_GOT16_LO_DS 59 /* half16ds #lo(G + A) >> 2. */
	246	#define R_PPC64_PLT16_LO_DS 60 /* half16ds #lo(L + A) >> 2. */
	247	#define R_PPC64_SECTOFF_DS 61 /* half16ds* (R + A) >> 2. */
	248	#define R_PPC64_SECTOFF_LO_DS 62 /* half16ds #lo(R + A) >> 2. */
	249	#define R_PPC64_TOC16_DS 63 /* half16ds* (S + A - .TOC.) >> 2. */
	250	#define R_PPC64_TOC16_LO_DS 64 /* half16ds #lo(S + A - .TOC.) >> 2. */
	251	#define R_PPC64_PLTGOT16_DS 65 /* half16ds* (M + A) >> 2. */
	252	#define R_PPC64_PLTGOT16_LO_DS 66 /* half16ds #lo(M + A) >> 2. */
	253
	254	/* PowerPC64 relocations defined for the TLS access ABI. */
	255	#define R_PPC64_TLS 67 /* none (sym+add)@tls */
	256	#define R_PPC64_DTPMOD64 68 /* doubleword64 (sym+add)@dtpmod */
	257	#define R_PPC64_TPREL16 69 /* half16* (sym+add)@tprel */
	258	#define R_PPC64_TPREL16_LO 70 /* half16 (sym+add)@tprel@l */
	259	#define R_PPC64_TPREL16_HI 71 /* half16 (sym+add)@tprel@h */
	260	#define R_PPC64_TPREL16_HA 72 /* half16 (sym+add)@tprel@ha */
	261	#define R_PPC64_TPREL64 73 /* doubleword64 (sym+add)@tprel */
	262	#define R_PPC64_DTPREL16 74 /* half16* (sym+add)@dtprel */
	263	#define R_PPC64_DTPREL16_LO 75 /* half16 (sym+add)@dtprel@l */
	264	#define R_PPC64_DTPREL16_HI 76 /* half16 (sym+add)@dtprel@h */
	265	#define R_PPC64_DTPREL16_HA 77 /* half16 (sym+add)@dtprel@ha */
	266	#define R_PPC64_DTPREL64 78 /* doubleword64 (sym+add)@dtprel */
	267	#define R_PPC64_GOT_TLSGD16 79 /* half16* (sym+add)@got@tlsgd */
	268	#define R_PPC64_GOT_TLSGD16_LO 80 /* half16 (sym+add)@got@tlsgd@l */
	269	#define R_PPC64_GOT_TLSGD16_HI 81 /* half16 (sym+add)@got@tlsgd@h */
	270	#define R_PPC64_GOT_TLSGD16_HA 82 /* half16 (sym+add)@got@tlsgd@ha */
	271	#define R_PPC64_GOT_TLSLD16 83 /* half16* (sym+add)@got@tlsld */
	272	#define R_PPC64_GOT_TLSLD16_LO 84 /* half16 (sym+add)@got@tlsld@l */
	273	#define R_PPC64_GOT_TLSLD16_HI 85 /* half16 (sym+add)@got@tlsld@h */
	274	#define R_PPC64_GOT_TLSLD16_HA 86 /* half16 (sym+add)@got@tlsld@ha */
	275	#define R_PPC64_GOT_TPREL16_DS 87 /* half16ds* (sym+add)@got@tprel */
	276	#define R_PPC64_GOT_TPREL16_LO_DS 88 /* half16ds (sym+add)@got@tprel@l */
	277	#define R_PPC64_GOT_TPREL16_HI 89 /* half16 (sym+add)@got@tprel@h */
	278	#define R_PPC64_GOT_TPREL16_HA 90 /* half16 (sym+add)@got@tprel@ha */
	279	#define R_PPC64_GOT_DTPREL16_DS 91 /* half16ds* (sym+add)@got@dtprel */
	280	#define R_PPC64_GOT_DTPREL16_LO_DS 92 /* half16ds (sym+add)@got@dtprel@l */
	281	#define R_PPC64_GOT_DTPREL16_HI 93 /* half16 (sym+add)@got@dtprel@h */
	282	#define R_PPC64_GOT_DTPREL16_HA 94 /* half16 (sym+add)@got@dtprel@ha */
	283	#define R_PPC64_TPREL16_DS 95 /* half16ds* (sym+add)@tprel */
	284	#define R_PPC64_TPREL16_LO_DS 96 /* half16ds (sym+add)@tprel@l */
	285	#define R_PPC64_TPREL16_HIGHER 97 /* half16 (sym+add)@tprel@higher */
	286	#define R_PPC64_TPREL16_HIGHERA 98 /* half16 (sym+add)@tprel@highera */
	287	#define R_PPC64_TPREL16_HIGHEST 99 /* half16 (sym+add)@tprel@highest */
	288	#define R_PPC64_TPREL16_HIGHESTA 100 /* half16 (sym+add)@tprel@highesta */
	289	#define R_PPC64_DTPREL16_DS 101 /* half16ds* (sym+add)@dtprel */
	290	#define R_PPC64_DTPREL16_LO_DS 102 /* half16ds (sym+add)@dtprel@l */
	291	#define R_PPC64_DTPREL16_HIGHER 103 /* half16 (sym+add)@dtprel@higher */
	292	#define R_PPC64_DTPREL16_HIGHERA 104 /* half16 (sym+add)@dtprel@highera */
	293	#define R_PPC64_DTPREL16_HIGHEST 105 /* half16 (sym+add)@dtprel@highest */
	294	#define R_PPC64_DTPREL16_HIGHESTA 106 /* half16 (sym+add)@dtprel@highesta */
	295
	296	/* Keep this the last entry. */
	297	#define R_PPC64_NUM 107
	298
	299	/* There's actually a third entry here, but it's unused */
	300	struct ppc64_opd_entry
	301	{
	302	unsigned long funcaddr;
	303	unsigned long r2;
	304	};
	305
	306
	307	#endif /* _UAPI_ASM_POWERPC_ELF_H */