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-rw-r--r--arch/powerpc/include/asm/cputable.h126
-rw-r--r--arch/powerpc/include/asm/dbell.h30
-rw-r--r--arch/powerpc/include/asm/debug.h15
-rw-r--r--arch/powerpc/include/asm/eeh.h3
-rw-r--r--arch/powerpc/include/asm/exception-64s.h138
-rw-r--r--arch/powerpc/include/asm/firmware.h3
-rw-r--r--arch/powerpc/include/asm/hvcall.h9
-rw-r--r--arch/powerpc/include/asm/hw_breakpoint.h35
-rw-r--r--arch/powerpc/include/asm/kvm_book3s_asm.h3
-rw-r--r--arch/powerpc/include/asm/kvm_host.h1
-rw-r--r--arch/powerpc/include/asm/machdep.h4
-rw-r--r--arch/powerpc/include/asm/mpc5121.h17
-rw-r--r--arch/powerpc/include/asm/paca.h10
-rw-r--r--arch/powerpc/include/asm/perf_event_server.h10
-rw-r--r--arch/powerpc/include/asm/ppc-opcode.h13
-rw-r--r--arch/powerpc/include/asm/ppc4xx_ocm.h45
-rw-r--r--arch/powerpc/include/asm/ppc_asm.h110
-rw-r--r--arch/powerpc/include/asm/processor.h48
-rw-r--r--arch/powerpc/include/asm/ps3.h2
-rw-r--r--arch/powerpc/include/asm/reg.h43
-rw-r--r--arch/powerpc/include/asm/sections.h3
-rw-r--r--arch/powerpc/include/asm/spinlock.h2
-rw-r--r--arch/powerpc/include/asm/tm.h20
23 files changed, 579 insertions, 111 deletions
diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h
index 76f81bd64f1d..fb3245e928ea 100644
--- a/arch/powerpc/include/asm/cputable.h
+++ b/arch/powerpc/include/asm/cputable.h
@@ -106,37 +106,37 @@ extern const char *powerpc_base_platform;
106/* CPU kernel features */ 106/* CPU kernel features */
107 107
108/* Retain the 32b definitions all use bottom half of word */ 108/* Retain the 32b definitions all use bottom half of word */
109#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0000000000000001) 109#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x00000001)
110#define CPU_FTR_L2CR ASM_CONST(0x0000000000000002) 110#define CPU_FTR_L2CR ASM_CONST(0x00000002)
111#define CPU_FTR_SPEC7450 ASM_CONST(0x0000000000000004) 111#define CPU_FTR_SPEC7450 ASM_CONST(0x00000004)
112#define CPU_FTR_ALTIVEC ASM_CONST(0x0000000000000008) 112#define CPU_FTR_ALTIVEC ASM_CONST(0x00000008)
113#define CPU_FTR_TAU ASM_CONST(0x0000000000000010) 113#define CPU_FTR_TAU ASM_CONST(0x00000010)
114#define CPU_FTR_CAN_DOZE ASM_CONST(0x0000000000000020) 114#define CPU_FTR_CAN_DOZE ASM_CONST(0x00000020)
115#define CPU_FTR_USE_TB ASM_CONST(0x0000000000000040) 115#define CPU_FTR_USE_TB ASM_CONST(0x00000040)
116#define CPU_FTR_L2CSR ASM_CONST(0x0000000000000080) 116#define CPU_FTR_L2CSR ASM_CONST(0x00000080)
117#define CPU_FTR_601 ASM_CONST(0x0000000000000100) 117#define CPU_FTR_601 ASM_CONST(0x00000100)
118#define CPU_FTR_DBELL ASM_CONST(0x0000000000000200) 118#define CPU_FTR_DBELL ASM_CONST(0x00000200)
119#define CPU_FTR_CAN_NAP ASM_CONST(0x0000000000000400) 119#define CPU_FTR_CAN_NAP ASM_CONST(0x00000400)
120#define CPU_FTR_L3CR ASM_CONST(0x0000000000000800) 120#define CPU_FTR_L3CR ASM_CONST(0x00000800)
121#define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x0000000000001000) 121#define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x00001000)
122#define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x0000000000002000) 122#define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x00002000)
123#define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x0000000000004000) 123#define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x00004000)
124#define CPU_FTR_NO_DPM ASM_CONST(0x0000000000008000) 124#define CPU_FTR_NO_DPM ASM_CONST(0x00008000)
125#define CPU_FTR_476_DD2 ASM_CONST(0x0000000000010000) 125#define CPU_FTR_476_DD2 ASM_CONST(0x00010000)
126#define CPU_FTR_NEED_COHERENT ASM_CONST(0x0000000000020000) 126#define CPU_FTR_NEED_COHERENT ASM_CONST(0x00020000)
127#define CPU_FTR_NO_BTIC ASM_CONST(0x0000000000040000) 127#define CPU_FTR_NO_BTIC ASM_CONST(0x00040000)
128#define CPU_FTR_DEBUG_LVL_EXC ASM_CONST(0x0000000000080000) 128#define CPU_FTR_DEBUG_LVL_EXC ASM_CONST(0x00080000)
129#define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000000000100000) 129#define CPU_FTR_NODSISRALIGN ASM_CONST(0x00100000)
130#define CPU_FTR_PPC_LE ASM_CONST(0x0000000000200000) 130#define CPU_FTR_PPC_LE ASM_CONST(0x00200000)
131#define CPU_FTR_REAL_LE ASM_CONST(0x0000000000400000) 131#define CPU_FTR_REAL_LE ASM_CONST(0x00400000)
132#define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x0000000000800000) 132#define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x00800000)
133#define CPU_FTR_UNIFIED_ID_CACHE ASM_CONST(0x0000000001000000) 133#define CPU_FTR_UNIFIED_ID_CACHE ASM_CONST(0x01000000)
134#define CPU_FTR_SPE ASM_CONST(0x0000000002000000) 134#define CPU_FTR_SPE ASM_CONST(0x02000000)
135#define CPU_FTR_NEED_PAIRED_STWCX ASM_CONST(0x0000000004000000) 135#define CPU_FTR_NEED_PAIRED_STWCX ASM_CONST(0x04000000)
136#define CPU_FTR_LWSYNC ASM_CONST(0x0000000008000000) 136#define CPU_FTR_LWSYNC ASM_CONST(0x08000000)
137#define CPU_FTR_NOEXECUTE ASM_CONST(0x0000000010000000) 137#define CPU_FTR_NOEXECUTE ASM_CONST(0x10000000)
138#define CPU_FTR_INDEXED_DCR ASM_CONST(0x0000000020000000) 138#define CPU_FTR_INDEXED_DCR ASM_CONST(0x20000000)
139#define CPU_FTR_EMB_HV ASM_CONST(0x0000000040000000) 139#define CPU_FTR_EMB_HV ASM_CONST(0x40000000)
140 140
141/* 141/*
142 * Add the 64-bit processor unique features in the top half of the word; 142 * Add the 64-bit processor unique features in the top half of the word;
@@ -148,29 +148,33 @@ extern const char *powerpc_base_platform;
148#define LONG_ASM_CONST(x) 0 148#define LONG_ASM_CONST(x) 0
149#endif 149#endif
150 150
151#define CPU_FTR_HVMODE LONG_ASM_CONST(0x0000000200000000) 151#define CPU_FTR_HVMODE LONG_ASM_CONST(0x0000000100000000)
152#define CPU_FTR_ARCH_201 LONG_ASM_CONST(0x0000000400000000) 152#define CPU_FTR_ARCH_201 LONG_ASM_CONST(0x0000000200000000)
153#define CPU_FTR_ARCH_206 LONG_ASM_CONST(0x0000000800000000) 153#define CPU_FTR_ARCH_206 LONG_ASM_CONST(0x0000000400000000)
154#define CPU_FTR_CFAR LONG_ASM_CONST(0x0000001000000000) 154#define CPU_FTR_CFAR LONG_ASM_CONST(0x0000000800000000)
155#define CPU_FTR_IABR LONG_ASM_CONST(0x0000002000000000) 155#define CPU_FTR_IABR LONG_ASM_CONST(0x0000001000000000)
156#define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000004000000000) 156#define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000002000000000)
157#define CPU_FTR_CTRL LONG_ASM_CONST(0x0000008000000000) 157#define CPU_FTR_CTRL LONG_ASM_CONST(0x0000004000000000)
158#define CPU_FTR_SMT LONG_ASM_CONST(0x0000010000000000) 158#define CPU_FTR_SMT LONG_ASM_CONST(0x0000008000000000)
159#define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000200000000000) 159#define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000010000000000)
160#define CPU_FTR_PURR LONG_ASM_CONST(0x0000400000000000) 160#define CPU_FTR_PURR LONG_ASM_CONST(0x0000020000000000)
161#define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000800000000000) 161#define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000040000000000)
162#define CPU_FTR_SPURR LONG_ASM_CONST(0x0001000000000000) 162#define CPU_FTR_SPURR LONG_ASM_CONST(0x0000080000000000)
163#define CPU_FTR_DSCR LONG_ASM_CONST(0x0002000000000000) 163#define CPU_FTR_DSCR LONG_ASM_CONST(0x0000100000000000)
164#define CPU_FTR_VSX LONG_ASM_CONST(0x0010000000000000) 164#define CPU_FTR_VSX LONG_ASM_CONST(0x0000200000000000)
165#define CPU_FTR_SAO LONG_ASM_CONST(0x0020000000000000) 165#define CPU_FTR_SAO LONG_ASM_CONST(0x0000400000000000)
166#define CPU_FTR_CP_USE_DCBTZ LONG_ASM_CONST(0x0040000000000000) 166#define CPU_FTR_CP_USE_DCBTZ LONG_ASM_CONST(0x0000800000000000)
167#define CPU_FTR_UNALIGNED_LD_STD LONG_ASM_CONST(0x0080000000000000) 167#define CPU_FTR_UNALIGNED_LD_STD LONG_ASM_CONST(0x0001000000000000)
168#define CPU_FTR_ASYM_SMT LONG_ASM_CONST(0x0100000000000000) 168#define CPU_FTR_ASYM_SMT LONG_ASM_CONST(0x0002000000000000)
169#define CPU_FTR_STCX_CHECKS_ADDRESS LONG_ASM_CONST(0x0200000000000000) 169#define CPU_FTR_STCX_CHECKS_ADDRESS LONG_ASM_CONST(0x0004000000000000)
170#define CPU_FTR_POPCNTB LONG_ASM_CONST(0x0400000000000000) 170#define CPU_FTR_POPCNTB LONG_ASM_CONST(0x0008000000000000)
171#define CPU_FTR_POPCNTD LONG_ASM_CONST(0x0800000000000000) 171#define CPU_FTR_POPCNTD LONG_ASM_CONST(0x0010000000000000)
172#define CPU_FTR_ICSWX LONG_ASM_CONST(0x1000000000000000) 172#define CPU_FTR_ICSWX LONG_ASM_CONST(0x0020000000000000)
173#define CPU_FTR_VMX_COPY LONG_ASM_CONST(0x2000000000000000) 173#define CPU_FTR_VMX_COPY LONG_ASM_CONST(0x0040000000000000)
174#define CPU_FTR_TM LONG_ASM_CONST(0x0080000000000000)
175#define CPU_FTR_BCTAR LONG_ASM_CONST(0x0100000000000000)
176#define CPU_FTR_HAS_PPR LONG_ASM_CONST(0x0200000000000000)
177#define CPU_FTR_DAWR LONG_ASM_CONST(0x0400000000000000)
174 178
175#ifndef __ASSEMBLY__ 179#ifndef __ASSEMBLY__
176 180
@@ -216,6 +220,13 @@ extern const char *powerpc_base_platform;
216#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP 0 220#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP 0
217#endif 221#endif
218 222
223/* We only set the TM feature if the kernel was compiled with TM supprt */
224#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
225#define CPU_FTR_TM_COMP CPU_FTR_TM
226#else
227#define CPU_FTR_TM_COMP 0
228#endif
229
219/* We need to mark all pages as being coherent if we're SMP or we have a 230/* We need to mark all pages as being coherent if we're SMP or we have a
220 * 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II 231 * 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II
221 * require it for PCI "streaming/prefetch" to work properly. 232 * require it for PCI "streaming/prefetch" to work properly.
@@ -400,7 +411,8 @@ extern const char *powerpc_base_platform;
400 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ 411 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
401 CPU_FTR_DSCR | CPU_FTR_SAO | CPU_FTR_ASYM_SMT | \ 412 CPU_FTR_DSCR | CPU_FTR_SAO | CPU_FTR_ASYM_SMT | \
402 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \ 413 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
403 CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY) 414 CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | \
415 CPU_FTR_VMX_COPY | CPU_FTR_HAS_PPR)
404#define CPU_FTRS_POWER8 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ 416#define CPU_FTRS_POWER8 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
405 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\ 417 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
406 CPU_FTR_MMCRA | CPU_FTR_SMT | \ 418 CPU_FTR_MMCRA | CPU_FTR_SMT | \
@@ -408,7 +420,9 @@ extern const char *powerpc_base_platform;
408 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ 420 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
409 CPU_FTR_DSCR | CPU_FTR_SAO | \ 421 CPU_FTR_DSCR | CPU_FTR_SAO | \
410 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \ 422 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
411 CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY) 423 CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
424 CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_DAWR | CPU_FTR_BCTAR | \
425 CPU_FTR_TM_COMP)
412#define CPU_FTRS_CELL (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ 426#define CPU_FTRS_CELL (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
413 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ 427 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
414 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \ 428 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
diff --git a/arch/powerpc/include/asm/dbell.h b/arch/powerpc/include/asm/dbell.h
index 607e4eeeb694..5fa6b20eba10 100644
--- a/arch/powerpc/include/asm/dbell.h
+++ b/arch/powerpc/include/asm/dbell.h
@@ -28,8 +28,36 @@ enum ppc_dbell {
28 PPC_G_DBELL = 2, /* guest doorbell */ 28 PPC_G_DBELL = 2, /* guest doorbell */
29 PPC_G_DBELL_CRIT = 3, /* guest critical doorbell */ 29 PPC_G_DBELL_CRIT = 3, /* guest critical doorbell */
30 PPC_G_DBELL_MC = 4, /* guest mcheck doorbell */ 30 PPC_G_DBELL_MC = 4, /* guest mcheck doorbell */
31 PPC_DBELL_SERVER = 5, /* doorbell on server */
31}; 32};
32 33
34#ifdef CONFIG_PPC_BOOK3S
35
36#define PPC_DBELL_MSGTYPE PPC_DBELL_SERVER
37#define SPRN_DOORBELL_CPUTAG SPRN_TIR
38#define PPC_DBELL_TAG_MASK 0x7f
39
40static inline void _ppc_msgsnd(u32 msg)
41{
42 if (cpu_has_feature(CPU_FTR_HVMODE))
43 __asm__ __volatile__ (PPC_MSGSND(%0) : : "r" (msg));
44 else
45 __asm__ __volatile__ (PPC_MSGSNDP(%0) : : "r" (msg));
46}
47
48#else /* CONFIG_PPC_BOOK3S */
49
50#define PPC_DBELL_MSGTYPE PPC_DBELL
51#define SPRN_DOORBELL_CPUTAG SPRN_PIR
52#define PPC_DBELL_TAG_MASK 0x3fff
53
54static inline void _ppc_msgsnd(u32 msg)
55{
56 __asm__ __volatile__ (PPC_MSGSND(%0) : : "r" (msg));
57}
58
59#endif /* CONFIG_PPC_BOOK3S */
60
33extern void doorbell_cause_ipi(int cpu, unsigned long data); 61extern void doorbell_cause_ipi(int cpu, unsigned long data);
34extern void doorbell_exception(struct pt_regs *regs); 62extern void doorbell_exception(struct pt_regs *regs);
35extern void doorbell_setup_this_cpu(void); 63extern void doorbell_setup_this_cpu(void);
@@ -39,7 +67,7 @@ static inline void ppc_msgsnd(enum ppc_dbell type, u32 flags, u32 tag)
39 u32 msg = PPC_DBELL_TYPE(type) | (flags & PPC_DBELL_MSG_BRDCAST) | 67 u32 msg = PPC_DBELL_TYPE(type) | (flags & PPC_DBELL_MSG_BRDCAST) |
40 (tag & 0x07ffffff); 68 (tag & 0x07ffffff);
41 69
42 __asm__ __volatile__ (PPC_MSGSND(%0) : : "r" (msg)); 70 _ppc_msgsnd(msg);
43} 71}
44 72
45#endif /* _ASM_POWERPC_DBELL_H */ 73#endif /* _ASM_POWERPC_DBELL_H */
diff --git a/arch/powerpc/include/asm/debug.h b/arch/powerpc/include/asm/debug.h
index 32de2577bb6d..d2516308ed1e 100644
--- a/arch/powerpc/include/asm/debug.h
+++ b/arch/powerpc/include/asm/debug.h
@@ -4,6 +4,8 @@
4#ifndef _ASM_POWERPC_DEBUG_H 4#ifndef _ASM_POWERPC_DEBUG_H
5#define _ASM_POWERPC_DEBUG_H 5#define _ASM_POWERPC_DEBUG_H
6 6
7#include <asm/hw_breakpoint.h>
8
7struct pt_regs; 9struct pt_regs;
8 10
9extern struct dentry *powerpc_debugfs_root; 11extern struct dentry *powerpc_debugfs_root;
@@ -15,7 +17,7 @@ extern int (*__debugger_ipi)(struct pt_regs *regs);
15extern int (*__debugger_bpt)(struct pt_regs *regs); 17extern int (*__debugger_bpt)(struct pt_regs *regs);
16extern int (*__debugger_sstep)(struct pt_regs *regs); 18extern int (*__debugger_sstep)(struct pt_regs *regs);
17extern int (*__debugger_iabr_match)(struct pt_regs *regs); 19extern int (*__debugger_iabr_match)(struct pt_regs *regs);
18extern int (*__debugger_dabr_match)(struct pt_regs *regs); 20extern int (*__debugger_break_match)(struct pt_regs *regs);
19extern int (*__debugger_fault_handler)(struct pt_regs *regs); 21extern int (*__debugger_fault_handler)(struct pt_regs *regs);
20 22
21#define DEBUGGER_BOILERPLATE(__NAME) \ 23#define DEBUGGER_BOILERPLATE(__NAME) \
@@ -31,7 +33,7 @@ DEBUGGER_BOILERPLATE(debugger_ipi)
31DEBUGGER_BOILERPLATE(debugger_bpt) 33DEBUGGER_BOILERPLATE(debugger_bpt)
32DEBUGGER_BOILERPLATE(debugger_sstep) 34DEBUGGER_BOILERPLATE(debugger_sstep)
33DEBUGGER_BOILERPLATE(debugger_iabr_match) 35DEBUGGER_BOILERPLATE(debugger_iabr_match)
34DEBUGGER_BOILERPLATE(debugger_dabr_match) 36DEBUGGER_BOILERPLATE(debugger_break_match)
35DEBUGGER_BOILERPLATE(debugger_fault_handler) 37DEBUGGER_BOILERPLATE(debugger_fault_handler)
36 38
37#else 39#else
@@ -40,17 +42,18 @@ static inline int debugger_ipi(struct pt_regs *regs) { return 0; }
40static inline int debugger_bpt(struct pt_regs *regs) { return 0; } 42static inline int debugger_bpt(struct pt_regs *regs) { return 0; }
41static inline int debugger_sstep(struct pt_regs *regs) { return 0; } 43static inline int debugger_sstep(struct pt_regs *regs) { return 0; }
42static inline int debugger_iabr_match(struct pt_regs *regs) { return 0; } 44static inline int debugger_iabr_match(struct pt_regs *regs) { return 0; }
43static inline int debugger_dabr_match(struct pt_regs *regs) { return 0; } 45static inline int debugger_break_match(struct pt_regs *regs) { return 0; }
44static inline int debugger_fault_handler(struct pt_regs *regs) { return 0; } 46static inline int debugger_fault_handler(struct pt_regs *regs) { return 0; }
45#endif 47#endif
46 48
47extern int set_dabr(unsigned long dabr, unsigned long dabrx); 49int set_breakpoint(struct arch_hw_breakpoint *brk);
48#ifdef CONFIG_PPC_ADV_DEBUG_REGS 50#ifdef CONFIG_PPC_ADV_DEBUG_REGS
49extern void do_send_trap(struct pt_regs *regs, unsigned long address, 51extern void do_send_trap(struct pt_regs *regs, unsigned long address,
50 unsigned long error_code, int signal_code, int brkpt); 52 unsigned long error_code, int signal_code, int brkpt);
51#else 53#else
52extern void do_dabr(struct pt_regs *regs, unsigned long address, 54
53 unsigned long error_code); 55extern void do_break(struct pt_regs *regs, unsigned long address,
56 unsigned long error_code);
54#endif 57#endif
55 58
56#endif /* _ASM_POWERPC_DEBUG_H */ 59#endif /* _ASM_POWERPC_DEBUG_H */
diff --git a/arch/powerpc/include/asm/eeh.h b/arch/powerpc/include/asm/eeh.h
index a8fb03e22770..a80e32b46c11 100644
--- a/arch/powerpc/include/asm/eeh.h
+++ b/arch/powerpc/include/asm/eeh.h
@@ -201,6 +201,7 @@ int eeh_dev_check_failure(struct eeh_dev *edev);
201void __init eeh_addr_cache_build(void); 201void __init eeh_addr_cache_build(void);
202void eeh_add_device_tree_early(struct device_node *); 202void eeh_add_device_tree_early(struct device_node *);
203void eeh_add_device_tree_late(struct pci_bus *); 203void eeh_add_device_tree_late(struct pci_bus *);
204void eeh_add_sysfs_files(struct pci_bus *);
204void eeh_remove_bus_device(struct pci_dev *, int); 205void eeh_remove_bus_device(struct pci_dev *, int);
205 206
206/** 207/**
@@ -240,6 +241,8 @@ static inline void eeh_add_device_tree_early(struct device_node *dn) { }
240 241
241static inline void eeh_add_device_tree_late(struct pci_bus *bus) { } 242static inline void eeh_add_device_tree_late(struct pci_bus *bus) { }
242 243
244static inline void eeh_add_sysfs_files(struct pci_bus *bus) { }
245
243static inline void eeh_remove_bus_device(struct pci_dev *dev, int purge_pe) { } 246static inline void eeh_remove_bus_device(struct pci_dev *dev, int purge_pe) { }
244 247
245static inline void eeh_lock(void) { } 248static inline void eeh_lock(void) { }
diff --git a/arch/powerpc/include/asm/exception-64s.h b/arch/powerpc/include/asm/exception-64s.h
index ad708dda3ba3..05e6d2ee1db9 100644
--- a/arch/powerpc/include/asm/exception-64s.h
+++ b/arch/powerpc/include/asm/exception-64s.h
@@ -47,9 +47,10 @@
47#define EX_R3 64 47#define EX_R3 64
48#define EX_LR 72 48#define EX_LR 72
49#define EX_CFAR 80 49#define EX_CFAR 80
50#define EX_PPR 88 /* SMT thread status register (priority) */
50 51
51#ifdef CONFIG_RELOCATABLE 52#ifdef CONFIG_RELOCATABLE
52#define EXCEPTION_RELON_PROLOG_PSERIES_1(label, h) \ 53#define __EXCEPTION_RELON_PROLOG_PSERIES_1(label, h) \
53 ld r12,PACAKBASE(r13); /* get high part of &label */ \ 54 ld r12,PACAKBASE(r13); /* get high part of &label */ \
54 mfspr r11,SPRN_##h##SRR0; /* save SRR0 */ \ 55 mfspr r11,SPRN_##h##SRR0; /* save SRR0 */ \
55 LOAD_HANDLER(r12,label); \ 56 LOAD_HANDLER(r12,label); \
@@ -60,13 +61,15 @@
60 blr; 61 blr;
61#else 62#else
62/* If not relocatable, we can jump directly -- and save messing with LR */ 63/* If not relocatable, we can jump directly -- and save messing with LR */
63#define EXCEPTION_RELON_PROLOG_PSERIES_1(label, h) \ 64#define __EXCEPTION_RELON_PROLOG_PSERIES_1(label, h) \
64 mfspr r11,SPRN_##h##SRR0; /* save SRR0 */ \ 65 mfspr r11,SPRN_##h##SRR0; /* save SRR0 */ \
65 mfspr r12,SPRN_##h##SRR1; /* and SRR1 */ \ 66 mfspr r12,SPRN_##h##SRR1; /* and SRR1 */ \
66 li r10,MSR_RI; \ 67 li r10,MSR_RI; \
67 mtmsrd r10,1; /* Set RI (EE=0) */ \ 68 mtmsrd r10,1; /* Set RI (EE=0) */ \
68 b label; 69 b label;
69#endif 70#endif
71#define EXCEPTION_RELON_PROLOG_PSERIES_1(label, h) \
72 __EXCEPTION_RELON_PROLOG_PSERIES_1(label, h) \
70 73
71/* 74/*
72 * As EXCEPTION_PROLOG_PSERIES(), except we've already got relocation on 75 * As EXCEPTION_PROLOG_PSERIES(), except we've already got relocation on
@@ -74,6 +77,7 @@
74 * case EXCEPTION_RELON_PROLOG_PSERIES_1 will be using lr. 77 * case EXCEPTION_RELON_PROLOG_PSERIES_1 will be using lr.
75 */ 78 */
76#define EXCEPTION_RELON_PROLOG_PSERIES(area, label, h, extra, vec) \ 79#define EXCEPTION_RELON_PROLOG_PSERIES(area, label, h, extra, vec) \
80 EXCEPTION_PROLOG_0(area); \
77 EXCEPTION_PROLOG_1(area, extra, vec); \ 81 EXCEPTION_PROLOG_1(area, extra, vec); \
78 EXCEPTION_RELON_PROLOG_PSERIES_1(label, h) 82 EXCEPTION_RELON_PROLOG_PSERIES_1(label, h)
79 83
@@ -107,14 +111,59 @@
107#define RESTORE_LR(reg, area) 111#define RESTORE_LR(reg, area)
108#endif 112#endif
109 113
110#define __EXCEPTION_PROLOG_1(area, extra, vec) \ 114/*
115 * PPR save/restore macros used in exceptions_64s.S
116 * Used for P7 or later processors
117 */
118#define SAVE_PPR(area, ra, rb) \
119BEGIN_FTR_SECTION_NESTED(940) \
120 ld ra,PACACURRENT(r13); \
121 ld rb,area+EX_PPR(r13); /* Read PPR from paca */ \
122 std rb,TASKTHREADPPR(ra); \
123END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,940)
124
125#define RESTORE_PPR_PACA(area, ra) \
126BEGIN_FTR_SECTION_NESTED(941) \
127 ld ra,area+EX_PPR(r13); \
128 mtspr SPRN_PPR,ra; \
129END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,941)
130
131/*
132 * Increase the priority on systems where PPR save/restore is not
133 * implemented/ supported.
134 */
135#define HMT_MEDIUM_PPR_DISCARD \
136BEGIN_FTR_SECTION_NESTED(942) \
137 HMT_MEDIUM; \
138END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,0,942) /*non P7*/
139
140/*
141 * Get an SPR into a register if the CPU has the given feature
142 */
143#define OPT_GET_SPR(ra, spr, ftr) \
144BEGIN_FTR_SECTION_NESTED(943) \
145 mfspr ra,spr; \
146END_FTR_SECTION_NESTED(ftr,ftr,943)
147
148/*
149 * Save a register to the PACA if the CPU has the given feature
150 */
151#define OPT_SAVE_REG_TO_PACA(offset, ra, ftr) \
152BEGIN_FTR_SECTION_NESTED(943) \
153 std ra,offset(r13); \
154END_FTR_SECTION_NESTED(ftr,ftr,943)
155
156#define EXCEPTION_PROLOG_0(area) \
111 GET_PACA(r13); \ 157 GET_PACA(r13); \
112 std r9,area+EX_R9(r13); /* save r9 - r12 */ \ 158 std r9,area+EX_R9(r13); /* save r9 */ \
113 std r10,area+EX_R10(r13); \ 159 OPT_GET_SPR(r9, SPRN_PPR, CPU_FTR_HAS_PPR); \
114 BEGIN_FTR_SECTION_NESTED(66); \ 160 HMT_MEDIUM; \
115 mfspr r10,SPRN_CFAR; \ 161 std r10,area+EX_R10(r13); /* save r10 - r12 */ \
116 std r10,area+EX_CFAR(r13); \ 162 OPT_GET_SPR(r10, SPRN_CFAR, CPU_FTR_CFAR)
117 END_FTR_SECTION_NESTED(CPU_FTR_CFAR, CPU_FTR_CFAR, 66); \ 163
164#define __EXCEPTION_PROLOG_1(area, extra, vec) \
165 OPT_SAVE_REG_TO_PACA(area+EX_PPR, r9, CPU_FTR_HAS_PPR); \
166 OPT_SAVE_REG_TO_PACA(area+EX_CFAR, r10, CPU_FTR_CFAR); \
118 SAVE_LR(r10, area); \ 167 SAVE_LR(r10, area); \
119 mfcr r9; \ 168 mfcr r9; \
120 extra(vec); \ 169 extra(vec); \
@@ -139,6 +188,7 @@
139 __EXCEPTION_PROLOG_PSERIES_1(label, h) 188 __EXCEPTION_PROLOG_PSERIES_1(label, h)
140 189
141#define EXCEPTION_PROLOG_PSERIES(area, label, h, extra, vec) \ 190#define EXCEPTION_PROLOG_PSERIES(area, label, h, extra, vec) \
191 EXCEPTION_PROLOG_0(area); \
142 EXCEPTION_PROLOG_1(area, extra, vec); \ 192 EXCEPTION_PROLOG_1(area, extra, vec); \
143 EXCEPTION_PROLOG_PSERIES_1(label, h); 193 EXCEPTION_PROLOG_PSERIES_1(label, h);
144 194
@@ -149,10 +199,14 @@
149 199
150#define __KVM_HANDLER(area, h, n) \ 200#define __KVM_HANDLER(area, h, n) \
151do_kvm_##n: \ 201do_kvm_##n: \
202 BEGIN_FTR_SECTION_NESTED(947) \
203 ld r10,area+EX_CFAR(r13); \
204 std r10,HSTATE_CFAR(r13); \
205 END_FTR_SECTION_NESTED(CPU_FTR_CFAR,CPU_FTR_CFAR,947); \
152 ld r10,area+EX_R10(r13); \ 206 ld r10,area+EX_R10(r13); \
153 stw r9,HSTATE_SCRATCH1(r13); \ 207 stw r9,HSTATE_SCRATCH1(r13); \
154 ld r9,area+EX_R9(r13); \ 208 ld r9,area+EX_R9(r13); \
155 std r12,HSTATE_SCRATCH0(r13); \ 209 std r12,HSTATE_SCRATCH0(r13); \
156 li r12,n; \ 210 li r12,n; \
157 b kvmppc_interrupt 211 b kvmppc_interrupt
158 212
@@ -224,8 +278,10 @@ do_kvm_##n: \
224 std r10,0(r1); /* make stack chain pointer */ \ 278 std r10,0(r1); /* make stack chain pointer */ \
225 std r0,GPR0(r1); /* save r0 in stackframe */ \ 279 std r0,GPR0(r1); /* save r0 in stackframe */ \
226 std r10,GPR1(r1); /* save r1 in stackframe */ \ 280 std r10,GPR1(r1); /* save r1 in stackframe */ \
281 beq 4f; /* if from kernel mode */ \
227 ACCOUNT_CPU_USER_ENTRY(r9, r10); \ 282 ACCOUNT_CPU_USER_ENTRY(r9, r10); \
228 std r2,GPR2(r1); /* save r2 in stackframe */ \ 283 SAVE_PPR(area, r9, r10); \
2844: std r2,GPR2(r1); /* save r2 in stackframe */ \
229 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \ 285 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \
230 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \ 286 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \
231 ld r9,area+EX_R9(r13); /* move r9, r10 to stackframe */ \ 287 ld r9,area+EX_R9(r13); /* move r9, r10 to stackframe */ \
@@ -266,45 +322,74 @@ do_kvm_##n: \
266 . = loc; \ 322 . = loc; \
267 .globl label##_pSeries; \ 323 .globl label##_pSeries; \
268label##_pSeries: \ 324label##_pSeries: \
269 HMT_MEDIUM; \ 325 HMT_MEDIUM_PPR_DISCARD; \
270 SET_SCRATCH0(r13); /* save r13 */ \ 326 SET_SCRATCH0(r13); /* save r13 */ \
271 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common, \ 327 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common, \
272 EXC_STD, KVMTEST_PR, vec) 328 EXC_STD, KVMTEST_PR, vec)
273 329
330/* Version of above for when we have to branch out-of-line */
331#define STD_EXCEPTION_PSERIES_OOL(vec, label) \
332 .globl label##_pSeries; \
333label##_pSeries: \
334 EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST_PR, vec); \
335 EXCEPTION_PROLOG_PSERIES_1(label##_common, EXC_STD)
336
274#define STD_EXCEPTION_HV(loc, vec, label) \ 337#define STD_EXCEPTION_HV(loc, vec, label) \
275 . = loc; \ 338 . = loc; \
276 .globl label##_hv; \ 339 .globl label##_hv; \
277label##_hv: \ 340label##_hv: \
278 HMT_MEDIUM; \ 341 HMT_MEDIUM_PPR_DISCARD; \
279 SET_SCRATCH0(r13); /* save r13 */ \ 342 SET_SCRATCH0(r13); /* save r13 */ \
280 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common, \ 343 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common, \
281 EXC_HV, KVMTEST, vec) 344 EXC_HV, KVMTEST, vec)
282 345
346/* Version of above for when we have to branch out-of-line */
347#define STD_EXCEPTION_HV_OOL(vec, label) \
348 .globl label##_hv; \
349label##_hv: \
350 EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST, vec); \
351 EXCEPTION_PROLOG_PSERIES_1(label##_common, EXC_HV)
352
283#define STD_RELON_EXCEPTION_PSERIES(loc, vec, label) \ 353#define STD_RELON_EXCEPTION_PSERIES(loc, vec, label) \
284 . = loc; \ 354 . = loc; \
285 .globl label##_relon_pSeries; \ 355 .globl label##_relon_pSeries; \
286label##_relon_pSeries: \ 356label##_relon_pSeries: \
287 HMT_MEDIUM; \ 357 HMT_MEDIUM_PPR_DISCARD; \
288 /* No guest interrupts come through here */ \ 358 /* No guest interrupts come through here */ \
289 SET_SCRATCH0(r13); /* save r13 */ \ 359 SET_SCRATCH0(r13); /* save r13 */ \
290 EXCEPTION_RELON_PROLOG_PSERIES(PACA_EXGEN, label##_common, \ 360 EXCEPTION_RELON_PROLOG_PSERIES(PACA_EXGEN, label##_common, \
291 EXC_STD, KVMTEST_PR, vec) 361 EXC_STD, KVMTEST_PR, vec)
292 362
363#define STD_RELON_EXCEPTION_PSERIES_OOL(vec, label) \
364 .globl label##_relon_pSeries; \
365label##_relon_pSeries: \
366 EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST_PR, vec); \
367 EXCEPTION_RELON_PROLOG_PSERIES_1(label##_common, EXC_STD)
368
293#define STD_RELON_EXCEPTION_HV(loc, vec, label) \ 369#define STD_RELON_EXCEPTION_HV(loc, vec, label) \
294 . = loc; \ 370 . = loc; \
295 .globl label##_relon_hv; \ 371 .globl label##_relon_hv; \
296label##_relon_hv: \ 372label##_relon_hv: \
297 HMT_MEDIUM; \ 373 HMT_MEDIUM_PPR_DISCARD; \
298 /* No guest interrupts come through here */ \ 374 /* No guest interrupts come through here */ \
299 SET_SCRATCH0(r13); /* save r13 */ \ 375 SET_SCRATCH0(r13); /* save r13 */ \
300 EXCEPTION_RELON_PROLOG_PSERIES(PACA_EXGEN, label##_common, \ 376 EXCEPTION_RELON_PROLOG_PSERIES(PACA_EXGEN, label##_common, \
301 EXC_HV, KVMTEST, vec) 377 EXC_HV, KVMTEST, vec)
302 378
379#define STD_RELON_EXCEPTION_HV_OOL(vec, label) \
380 .globl label##_relon_hv; \
381label##_relon_hv: \
382 EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST, vec); \
383 EXCEPTION_RELON_PROLOG_PSERIES_1(label##_common, EXC_HV)
384
303/* This associate vector numbers with bits in paca->irq_happened */ 385/* This associate vector numbers with bits in paca->irq_happened */
304#define SOFTEN_VALUE_0x500 PACA_IRQ_EE 386#define SOFTEN_VALUE_0x500 PACA_IRQ_EE
305#define SOFTEN_VALUE_0x502 PACA_IRQ_EE 387#define SOFTEN_VALUE_0x502 PACA_IRQ_EE
306#define SOFTEN_VALUE_0x900 PACA_IRQ_DEC 388#define SOFTEN_VALUE_0x900 PACA_IRQ_DEC
307#define SOFTEN_VALUE_0x982 PACA_IRQ_DEC 389#define SOFTEN_VALUE_0x982 PACA_IRQ_DEC
390#define SOFTEN_VALUE_0xa00 PACA_IRQ_DBELL
391#define SOFTEN_VALUE_0xe80 PACA_IRQ_DBELL
392#define SOFTEN_VALUE_0xe82 PACA_IRQ_DBELL
308 393
309#define __SOFTEN_TEST(h, vec) \ 394#define __SOFTEN_TEST(h, vec) \
310 lbz r10,PACASOFTIRQEN(r13); \ 395 lbz r10,PACASOFTIRQEN(r13); \
@@ -329,10 +414,12 @@ label##_relon_hv: \
329#define SOFTEN_NOTEST_HV(vec) _SOFTEN_TEST(EXC_HV, vec) 414#define SOFTEN_NOTEST_HV(vec) _SOFTEN_TEST(EXC_HV, vec)
330 415
331#define __MASKABLE_EXCEPTION_PSERIES(vec, label, h, extra) \ 416#define __MASKABLE_EXCEPTION_PSERIES(vec, label, h, extra) \
332 HMT_MEDIUM; \ 417 HMT_MEDIUM_PPR_DISCARD; \
333 SET_SCRATCH0(r13); /* save r13 */ \ 418 SET_SCRATCH0(r13); /* save r13 */ \
334 __EXCEPTION_PROLOG_1(PACA_EXGEN, extra, vec); \ 419 EXCEPTION_PROLOG_0(PACA_EXGEN); \
420 __EXCEPTION_PROLOG_1(PACA_EXGEN, extra, vec); \
335 EXCEPTION_PROLOG_PSERIES_1(label##_common, h); 421 EXCEPTION_PROLOG_PSERIES_1(label##_common, h);
422
336#define _MASKABLE_EXCEPTION_PSERIES(vec, label, h, extra) \ 423#define _MASKABLE_EXCEPTION_PSERIES(vec, label, h, extra) \
337 __MASKABLE_EXCEPTION_PSERIES(vec, label, h, extra) 424 __MASKABLE_EXCEPTION_PSERIES(vec, label, h, extra)
338 425
@@ -350,9 +437,16 @@ label##_hv: \
350 _MASKABLE_EXCEPTION_PSERIES(vec, label, \ 437 _MASKABLE_EXCEPTION_PSERIES(vec, label, \
351 EXC_HV, SOFTEN_TEST_HV) 438 EXC_HV, SOFTEN_TEST_HV)
352 439
440#define MASKABLE_EXCEPTION_HV_OOL(vec, label) \
441 .globl label##_hv; \
442label##_hv: \
443 EXCEPTION_PROLOG_1(PACA_EXGEN, SOFTEN_TEST_HV, vec); \
444 EXCEPTION_PROLOG_PSERIES_1(label##_common, EXC_HV);
445
353#define __MASKABLE_RELON_EXCEPTION_PSERIES(vec, label, h, extra) \ 446#define __MASKABLE_RELON_EXCEPTION_PSERIES(vec, label, h, extra) \
354 HMT_MEDIUM; \ 447 HMT_MEDIUM_PPR_DISCARD; \
355 SET_SCRATCH0(r13); /* save r13 */ \ 448 SET_SCRATCH0(r13); /* save r13 */ \
449 EXCEPTION_PROLOG_0(PACA_EXGEN); \
356 __EXCEPTION_PROLOG_1(PACA_EXGEN, extra, vec); \ 450 __EXCEPTION_PROLOG_1(PACA_EXGEN, extra, vec); \
357 EXCEPTION_RELON_PROLOG_PSERIES_1(label##_common, h); 451 EXCEPTION_RELON_PROLOG_PSERIES_1(label##_common, h);
358#define _MASKABLE_RELON_EXCEPTION_PSERIES(vec, label, h, extra) \ 452#define _MASKABLE_RELON_EXCEPTION_PSERIES(vec, label, h, extra) \
@@ -372,6 +466,12 @@ label##_relon_hv: \
372 _MASKABLE_RELON_EXCEPTION_PSERIES(vec, label, \ 466 _MASKABLE_RELON_EXCEPTION_PSERIES(vec, label, \
373 EXC_HV, SOFTEN_NOTEST_HV) 467 EXC_HV, SOFTEN_NOTEST_HV)
374 468
469#define MASKABLE_RELON_EXCEPTION_HV_OOL(vec, label) \
470 .globl label##_relon_hv; \
471label##_relon_hv: \
472 EXCEPTION_PROLOG_1(PACA_EXGEN, SOFTEN_NOTEST_HV, vec); \
473 EXCEPTION_PROLOG_PSERIES_1(label##_common, EXC_HV);
474
375/* 475/*
376 * Our exception common code can be passed various "additions" 476 * Our exception common code can be passed various "additions"
377 * to specify the behaviour of interrupts, whether to kick the 477 * to specify the behaviour of interrupts, whether to kick the
diff --git a/arch/powerpc/include/asm/firmware.h b/arch/powerpc/include/asm/firmware.h
index 973cc3be011b..097dee57a7a9 100644
--- a/arch/powerpc/include/asm/firmware.h
+++ b/arch/powerpc/include/asm/firmware.h
@@ -50,6 +50,7 @@
50#define FW_FEATURE_OPAL ASM_CONST(0x0000000010000000) 50#define FW_FEATURE_OPAL ASM_CONST(0x0000000010000000)
51#define FW_FEATURE_OPALv2 ASM_CONST(0x0000000020000000) 51#define FW_FEATURE_OPALv2 ASM_CONST(0x0000000020000000)
52#define FW_FEATURE_SET_MODE ASM_CONST(0x0000000040000000) 52#define FW_FEATURE_SET_MODE ASM_CONST(0x0000000040000000)
53#define FW_FEATURE_BEST_ENERGY ASM_CONST(0x0000000080000000)
53 54
54#ifndef __ASSEMBLY__ 55#ifndef __ASSEMBLY__
55 56
@@ -64,7 +65,7 @@ enum {
64 FW_FEATURE_BULK_REMOVE | FW_FEATURE_XDABR | 65 FW_FEATURE_BULK_REMOVE | FW_FEATURE_XDABR |
65 FW_FEATURE_MULTITCE | FW_FEATURE_SPLPAR | FW_FEATURE_LPAR | 66 FW_FEATURE_MULTITCE | FW_FEATURE_SPLPAR | FW_FEATURE_LPAR |
66 FW_FEATURE_CMO | FW_FEATURE_VPHN | FW_FEATURE_XCMO | 67 FW_FEATURE_CMO | FW_FEATURE_VPHN | FW_FEATURE_XCMO |
67 FW_FEATURE_SET_MODE, 68 FW_FEATURE_SET_MODE | FW_FEATURE_BEST_ENERGY,
68 FW_FEATURE_PSERIES_ALWAYS = 0, 69 FW_FEATURE_PSERIES_ALWAYS = 0,
69 FW_FEATURE_POWERNV_POSSIBLE = FW_FEATURE_OPAL | FW_FEATURE_OPALv2, 70 FW_FEATURE_POWERNV_POSSIBLE = FW_FEATURE_OPAL | FW_FEATURE_OPALv2,
70 FW_FEATURE_POWERNV_ALWAYS = 0, 71 FW_FEATURE_POWERNV_ALWAYS = 0,
diff --git a/arch/powerpc/include/asm/hvcall.h b/arch/powerpc/include/asm/hvcall.h
index 0975e5c0bb19..4bc2c3dad6ad 100644
--- a/arch/powerpc/include/asm/hvcall.h
+++ b/arch/powerpc/include/asm/hvcall.h
@@ -395,6 +395,15 @@ static inline unsigned long cmo_get_page_size(void)
395{ 395{
396 return CMO_PageSize; 396 return CMO_PageSize;
397} 397}
398
399extern long pSeries_enable_reloc_on_exc(void);
400extern long pSeries_disable_reloc_on_exc(void);
401
402#else
403
404#define pSeries_enable_reloc_on_exc() do {} while (0)
405#define pSeries_disable_reloc_on_exc() do {} while (0)
406
398#endif /* CONFIG_PPC_PSERIES */ 407#endif /* CONFIG_PPC_PSERIES */
399 408
400#endif /* __ASSEMBLY__ */ 409#endif /* __ASSEMBLY__ */
diff --git a/arch/powerpc/include/asm/hw_breakpoint.h b/arch/powerpc/include/asm/hw_breakpoint.h
index 423424599dad..eb0f4ac75c4c 100644
--- a/arch/powerpc/include/asm/hw_breakpoint.h
+++ b/arch/powerpc/include/asm/hw_breakpoint.h
@@ -24,16 +24,30 @@
24#define _PPC_BOOK3S_64_HW_BREAKPOINT_H 24#define _PPC_BOOK3S_64_HW_BREAKPOINT_H
25 25
26#ifdef __KERNEL__ 26#ifdef __KERNEL__
27#ifdef CONFIG_HAVE_HW_BREAKPOINT
28
29struct arch_hw_breakpoint { 27struct arch_hw_breakpoint {
30 unsigned long address; 28 unsigned long address;
31 unsigned long dabrx; 29 u16 type;
32 int type; 30 u16 len; /* length of the target data symbol */
33 u8 len; /* length of the target data symbol */
34 bool extraneous_interrupt;
35}; 31};
36 32
33/* Note: Don't change the the first 6 bits below as they are in the same order
34 * as the dabr and dabrx.
35 */
36#define HW_BRK_TYPE_READ 0x01
37#define HW_BRK_TYPE_WRITE 0x02
38#define HW_BRK_TYPE_TRANSLATE 0x04
39#define HW_BRK_TYPE_USER 0x08
40#define HW_BRK_TYPE_KERNEL 0x10
41#define HW_BRK_TYPE_HYP 0x20
42#define HW_BRK_TYPE_EXTRANEOUS_IRQ 0x80
43
44/* bits that overlap with the bottom 3 bits of the dabr */
45#define HW_BRK_TYPE_RDWR (HW_BRK_TYPE_READ | HW_BRK_TYPE_WRITE)
46#define HW_BRK_TYPE_DABR (HW_BRK_TYPE_RDWR | HW_BRK_TYPE_TRANSLATE)
47#define HW_BRK_TYPE_PRIV_ALL (HW_BRK_TYPE_USER | HW_BRK_TYPE_KERNEL | \
48 HW_BRK_TYPE_HYP)
49
50#ifdef CONFIG_HAVE_HW_BREAKPOINT
37#include <linux/kdebug.h> 51#include <linux/kdebug.h>
38#include <asm/reg.h> 52#include <asm/reg.h>
39#include <asm/debug.h> 53#include <asm/debug.h>
@@ -43,8 +57,6 @@ struct pmu;
43struct perf_sample_data; 57struct perf_sample_data;
44 58
45#define HW_BREAKPOINT_ALIGN 0x7 59#define HW_BREAKPOINT_ALIGN 0x7
46/* Maximum permissible length of any HW Breakpoint */
47#define HW_BREAKPOINT_LEN 0x8
48 60
49extern int hw_breakpoint_slots(int type); 61extern int hw_breakpoint_slots(int type);
50extern int arch_bp_generic_fields(int type, int *gen_bp_type); 62extern int arch_bp_generic_fields(int type, int *gen_bp_type);
@@ -62,7 +74,12 @@ extern void ptrace_triggered(struct perf_event *bp,
62 struct perf_sample_data *data, struct pt_regs *regs); 74 struct perf_sample_data *data, struct pt_regs *regs);
63static inline void hw_breakpoint_disable(void) 75static inline void hw_breakpoint_disable(void)
64{ 76{
65 set_dabr(0, 0); 77 struct arch_hw_breakpoint brk;
78
79 brk.address = 0;
80 brk.type = 0;
81 brk.len = 0;
82 set_breakpoint(&brk);
66} 83}
67extern void thread_change_pc(struct task_struct *tsk, struct pt_regs *regs); 84extern void thread_change_pc(struct task_struct *tsk, struct pt_regs *regs);
68 85
diff --git a/arch/powerpc/include/asm/kvm_book3s_asm.h b/arch/powerpc/include/asm/kvm_book3s_asm.h
index 88609b23b775..cdc3d2717cc6 100644
--- a/arch/powerpc/include/asm/kvm_book3s_asm.h
+++ b/arch/powerpc/include/asm/kvm_book3s_asm.h
@@ -93,6 +93,9 @@ struct kvmppc_host_state {
93 u64 host_dscr; 93 u64 host_dscr;
94 u64 dec_expires; 94 u64 dec_expires;
95#endif 95#endif
96#ifdef CONFIG_PPC_BOOK3S_64
97 u64 cfar;
98#endif
96}; 99};
97 100
98struct kvmppc_book3s_shadow_vcpu { 101struct kvmppc_book3s_shadow_vcpu {
diff --git a/arch/powerpc/include/asm/kvm_host.h b/arch/powerpc/include/asm/kvm_host.h
index ca9bf459db6a..03d7beae89a0 100644
--- a/arch/powerpc/include/asm/kvm_host.h
+++ b/arch/powerpc/include/asm/kvm_host.h
@@ -440,6 +440,7 @@ struct kvm_vcpu_arch {
440 ulong uamor; 440 ulong uamor;
441 u32 ctrl; 441 u32 ctrl;
442 ulong dabr; 442 ulong dabr;
443 ulong cfar;
443#endif 444#endif
444 u32 vrsave; /* also USPRG0 */ 445 u32 vrsave; /* also USPRG0 */
445 u32 mmucr; 446 u32 mmucr;
diff --git a/arch/powerpc/include/asm/machdep.h b/arch/powerpc/include/asm/machdep.h
index 19d9d96eb8d3..3d6b4100dac1 100644
--- a/arch/powerpc/include/asm/machdep.h
+++ b/arch/powerpc/include/asm/machdep.h
@@ -180,6 +180,10 @@ struct machdep_calls {
180 int (*set_dabr)(unsigned long dabr, 180 int (*set_dabr)(unsigned long dabr,
181 unsigned long dabrx); 181 unsigned long dabrx);
182 182
183 /* Set DAWR for this platform, leave empty for default implemenation */
184 int (*set_dawr)(unsigned long dawr,
185 unsigned long dawrx);
186
183#ifdef CONFIG_PPC32 /* XXX for now */ 187#ifdef CONFIG_PPC32 /* XXX for now */
184 /* A general init function, called by ppc_init in init/main.c. 188 /* A general init function, called by ppc_init in init/main.c.
185 May be NULL. */ 189 May be NULL. */
diff --git a/arch/powerpc/include/asm/mpc5121.h b/arch/powerpc/include/asm/mpc5121.h
index 8c0ab2ca689c..885c040d6194 100644
--- a/arch/powerpc/include/asm/mpc5121.h
+++ b/arch/powerpc/include/asm/mpc5121.h
@@ -53,4 +53,21 @@ struct mpc512x_ccm {
53 u32 m4ccr; /* MSCAN4 CCR */ 53 u32 m4ccr; /* MSCAN4 CCR */
54 u8 res[0x98]; /* Reserved */ 54 u8 res[0x98]; /* Reserved */
55}; 55};
56
57/*
58 * LPC Module
59 */
60struct mpc512x_lpc {
61 u32 cs_cfg[8]; /* CS config */
62 u32 cs_ctrl; /* CS Control Register */
63 u32 cs_status; /* CS Status Register */
64 u32 burst_ctrl; /* CS Burst Control Register */
65 u32 deadcycle_ctrl; /* CS Deadcycle Control Register */
66 u32 holdcycle_ctrl; /* CS Holdcycle Control Register */
67 u32 alt; /* Address Latch Timing Register */
68};
69
70int mpc512x_cs_config(unsigned int cs, u32 val);
71int __init mpc5121_clk_init(void);
72
56#endif /* __ASM_POWERPC_MPC5121_H__ */ 73#endif /* __ASM_POWERPC_MPC5121_H__ */
diff --git a/arch/powerpc/include/asm/paca.h b/arch/powerpc/include/asm/paca.h
index e9e7a6999bb8..77c91e74b612 100644
--- a/arch/powerpc/include/asm/paca.h
+++ b/arch/powerpc/include/asm/paca.h
@@ -93,9 +93,9 @@ struct paca_struct {
93 * Now, starting in cacheline 2, the exception save areas 93 * Now, starting in cacheline 2, the exception save areas
94 */ 94 */
95 /* used for most interrupts/exceptions */ 95 /* used for most interrupts/exceptions */
96 u64 exgen[11] __attribute__((aligned(0x80))); 96 u64 exgen[12] __attribute__((aligned(0x80)));
97 u64 exmc[11]; /* used for machine checks */ 97 u64 exmc[12]; /* used for machine checks */
98 u64 exslb[11]; /* used for SLB/segment table misses 98 u64 exslb[12]; /* used for SLB/segment table misses
99 * on the linear mapping */ 99 * on the linear mapping */
100 /* SLB related definitions */ 100 /* SLB related definitions */
101 u16 vmalloc_sllp; 101 u16 vmalloc_sllp;
@@ -137,6 +137,9 @@ struct paca_struct {
137 u8 irq_work_pending; /* IRQ_WORK interrupt while soft-disable */ 137 u8 irq_work_pending; /* IRQ_WORK interrupt while soft-disable */
138 u8 nap_state_lost; /* NV GPR values lost in power7_idle */ 138 u8 nap_state_lost; /* NV GPR values lost in power7_idle */
139 u64 sprg3; /* Saved user-visible sprg */ 139 u64 sprg3; /* Saved user-visible sprg */
140#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
141 u64 tm_scratch; /* TM scratch area for reclaim */
142#endif
140 143
141#ifdef CONFIG_PPC_POWERNV 144#ifdef CONFIG_PPC_POWERNV
142 /* Pointer to OPAL machine check event structure set by the 145 /* Pointer to OPAL machine check event structure set by the
@@ -167,7 +170,6 @@ struct paca_struct {
167}; 170};
168 171
169extern struct paca_struct *paca; 172extern struct paca_struct *paca;
170extern __initdata struct paca_struct boot_paca;
171extern void initialise_paca(struct paca_struct *new_paca, int cpu); 173extern void initialise_paca(struct paca_struct *new_paca, int cpu);
172extern void setup_paca(struct paca_struct *new_paca); 174extern void setup_paca(struct paca_struct *new_paca);
173extern void allocate_pacas(void); 175extern void allocate_pacas(void);
diff --git a/arch/powerpc/include/asm/perf_event_server.h b/arch/powerpc/include/asm/perf_event_server.h
index 136bba62efa4..d0aec72722e9 100644
--- a/arch/powerpc/include/asm/perf_event_server.h
+++ b/arch/powerpc/include/asm/perf_event_server.h
@@ -47,11 +47,11 @@ struct power_pmu {
47/* 47/*
48 * Values for power_pmu.flags 48 * Values for power_pmu.flags
49 */ 49 */
50#define PPMU_LIMITED_PMC5_6 1 /* PMC5/6 have limited function */ 50#define PPMU_LIMITED_PMC5_6 0x00000001 /* PMC5/6 have limited function */
51#define PPMU_ALT_SIPR 2 /* uses alternate posn for SIPR/HV */ 51#define PPMU_ALT_SIPR 0x00000002 /* uses alternate posn for SIPR/HV */
52#define PPMU_NO_SIPR 4 /* no SIPR/HV in MMCRA at all */ 52#define PPMU_NO_SIPR 0x00000004 /* no SIPR/HV in MMCRA at all */
53#define PPMU_NO_CONT_SAMPLING 8 /* no continuous sampling */ 53#define PPMU_NO_CONT_SAMPLING 0x00000008 /* no continuous sampling */
54#define PPMU_SIAR_VALID 16 /* Processor has SIAR Valid bit */ 54#define PPMU_SIAR_VALID 0x00000010 /* Processor has SIAR Valid bit */
55 55
56/* 56/*
57 * Values for flags to get_alternatives() 57 * Values for flags to get_alternatives()
diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h
index 51fb00a20d7e..8752bc8e34a3 100644
--- a/arch/powerpc/include/asm/ppc-opcode.h
+++ b/arch/powerpc/include/asm/ppc-opcode.h
@@ -100,6 +100,7 @@
100#define PPC_INST_MFSPR_PVR 0x7c1f42a6 100#define PPC_INST_MFSPR_PVR 0x7c1f42a6
101#define PPC_INST_MFSPR_PVR_MASK 0xfc1fffff 101#define PPC_INST_MFSPR_PVR_MASK 0xfc1fffff
102#define PPC_INST_MSGSND 0x7c00019c 102#define PPC_INST_MSGSND 0x7c00019c
103#define PPC_INST_MSGSNDP 0x7c00011c
103#define PPC_INST_NOP 0x60000000 104#define PPC_INST_NOP 0x60000000
104#define PPC_INST_POPCNTB 0x7c0000f4 105#define PPC_INST_POPCNTB 0x7c0000f4
105#define PPC_INST_POPCNTB_MASK 0xfc0007fe 106#define PPC_INST_POPCNTB_MASK 0xfc0007fe
@@ -128,6 +129,9 @@
128#define PPC_INST_TLBSRX_DOT 0x7c0006a5 129#define PPC_INST_TLBSRX_DOT 0x7c0006a5
129#define PPC_INST_XXLOR 0xf0000510 130#define PPC_INST_XXLOR 0xf0000510
130#define PPC_INST_XVCPSGNDP 0xf0000780 131#define PPC_INST_XVCPSGNDP 0xf0000780
132#define PPC_INST_TRECHKPT 0x7c0007dd
133#define PPC_INST_TRECLAIM 0x7c00075d
134#define PPC_INST_TABORT 0x7c00071d
131 135
132#define PPC_INST_NAP 0x4c000364 136#define PPC_INST_NAP 0x4c000364
133#define PPC_INST_SLEEP 0x4c0003a4 137#define PPC_INST_SLEEP 0x4c0003a4
@@ -227,6 +231,8 @@
227 ___PPC_RB(b) | __PPC_EH(eh)) 231 ___PPC_RB(b) | __PPC_EH(eh))
228#define PPC_MSGSND(b) stringify_in_c(.long PPC_INST_MSGSND | \ 232#define PPC_MSGSND(b) stringify_in_c(.long PPC_INST_MSGSND | \
229 ___PPC_RB(b)) 233 ___PPC_RB(b))
234#define PPC_MSGSNDP(b) stringify_in_c(.long PPC_INST_MSGSNDP | \
235 ___PPC_RB(b))
230#define PPC_POPCNTB(a, s) stringify_in_c(.long PPC_INST_POPCNTB | \ 236#define PPC_POPCNTB(a, s) stringify_in_c(.long PPC_INST_POPCNTB | \
231 __PPC_RA(a) | __PPC_RS(s)) 237 __PPC_RA(a) | __PPC_RS(s))
232#define PPC_POPCNTD(a, s) stringify_in_c(.long PPC_INST_POPCNTD | \ 238#define PPC_POPCNTD(a, s) stringify_in_c(.long PPC_INST_POPCNTD | \
@@ -291,4 +297,11 @@
291#define PPC_NAP stringify_in_c(.long PPC_INST_NAP) 297#define PPC_NAP stringify_in_c(.long PPC_INST_NAP)
292#define PPC_SLEEP stringify_in_c(.long PPC_INST_SLEEP) 298#define PPC_SLEEP stringify_in_c(.long PPC_INST_SLEEP)
293 299
300/* Transactional memory instructions */
301#define TRECHKPT stringify_in_c(.long PPC_INST_TRECHKPT)
302#define TRECLAIM(r) stringify_in_c(.long PPC_INST_TRECLAIM \
303 | __PPC_RA(r))
304#define TABORT(r) stringify_in_c(.long PPC_INST_TABORT \
305 | __PPC_RA(r))
306
294#endif /* _ASM_POWERPC_PPC_OPCODE_H */ 307#endif /* _ASM_POWERPC_PPC_OPCODE_H */
diff --git a/arch/powerpc/include/asm/ppc4xx_ocm.h b/arch/powerpc/include/asm/ppc4xx_ocm.h
new file mode 100644
index 000000000000..6ce904605538
--- /dev/null
+++ b/arch/powerpc/include/asm/ppc4xx_ocm.h
@@ -0,0 +1,45 @@
1/*
2 * PowerPC 4xx OCM memory allocation support
3 *
4 * (C) Copyright 2009, Applied Micro Circuits Corporation
5 * Victor Gallardo (vgallardo@amcc.com)
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#ifndef __ASM_POWERPC_PPC4XX_OCM_H__
27#define __ASM_POWERPC_PPC4XX_OCM_H__
28
29#define PPC4XX_OCM_NON_CACHED 0
30#define PPC4XX_OCM_CACHED 1
31
32#if defined(CONFIG_PPC4xx_OCM)
33
34void *ppc4xx_ocm_alloc(phys_addr_t *phys, int size, int align,
35 int flags, const char *owner);
36void ppc4xx_ocm_free(const void *virt);
37
38#else
39
40#define ppc4xx_ocm_alloc(phys, size, align, flags, owner) NULL
41#define ppc4xx_ocm_free(addr) ((void)0)
42
43#endif /* CONFIG_PPC4xx_OCM */
44
45#endif /* __ASM_POWERPC_PPC4XX_OCM_H__ */
diff --git a/arch/powerpc/include/asm/ppc_asm.h b/arch/powerpc/include/asm/ppc_asm.h
index 2d0e1f5d8339..cea8496091ff 100644
--- a/arch/powerpc/include/asm/ppc_asm.h
+++ b/arch/powerpc/include/asm/ppc_asm.h
@@ -30,7 +30,6 @@
30#define ACCOUNT_STOLEN_TIME 30#define ACCOUNT_STOLEN_TIME
31#else 31#else
32#define ACCOUNT_CPU_USER_ENTRY(ra, rb) \ 32#define ACCOUNT_CPU_USER_ENTRY(ra, rb) \
33 beq 2f; /* if from kernel mode */ \
34 MFTB(ra); /* get timebase */ \ 33 MFTB(ra); /* get timebase */ \
35 ld rb,PACA_STARTTIME_USER(r13); \ 34 ld rb,PACA_STARTTIME_USER(r13); \
36 std ra,PACA_STARTTIME(r13); \ 35 std ra,PACA_STARTTIME(r13); \
@@ -38,7 +37,6 @@
38 ld ra,PACA_USER_TIME(r13); \ 37 ld ra,PACA_USER_TIME(r13); \
39 add ra,ra,rb; /* add on to user time */ \ 38 add ra,ra,rb; /* add on to user time */ \
40 std ra,PACA_USER_TIME(r13); \ 39 std ra,PACA_USER_TIME(r13); \
412:
42 40
43#define ACCOUNT_CPU_USER_EXIT(ra, rb) \ 41#define ACCOUNT_CPU_USER_EXIT(ra, rb) \
44 MFTB(ra); /* get timebase */ \ 42 MFTB(ra); /* get timebase */ \
@@ -125,6 +123,89 @@ END_FW_FTR_SECTION_IFSET(FW_FEATURE_SPLPAR)
125#define REST_16VRS(n,b,base) REST_8VRS(n,b,base); REST_8VRS(n+8,b,base) 123#define REST_16VRS(n,b,base) REST_8VRS(n,b,base); REST_8VRS(n+8,b,base)
126#define REST_32VRS(n,b,base) REST_16VRS(n,b,base); REST_16VRS(n+16,b,base) 124#define REST_32VRS(n,b,base) REST_16VRS(n,b,base); REST_16VRS(n+16,b,base)
127 125
126/* Save/restore FPRs, VRs and VSRs from their checkpointed backups in
127 * thread_struct:
128 */
129#define SAVE_FPR_TRANSACT(n, base) stfd n,THREAD_TRANSACT_FPR0+ \
130 8*TS_FPRWIDTH*(n)(base)
131#define SAVE_2FPRS_TRANSACT(n, base) SAVE_FPR_TRANSACT(n, base); \
132 SAVE_FPR_TRANSACT(n+1, base)
133#define SAVE_4FPRS_TRANSACT(n, base) SAVE_2FPRS_TRANSACT(n, base); \
134 SAVE_2FPRS_TRANSACT(n+2, base)
135#define SAVE_8FPRS_TRANSACT(n, base) SAVE_4FPRS_TRANSACT(n, base); \
136 SAVE_4FPRS_TRANSACT(n+4, base)
137#define SAVE_16FPRS_TRANSACT(n, base) SAVE_8FPRS_TRANSACT(n, base); \
138 SAVE_8FPRS_TRANSACT(n+8, base)
139#define SAVE_32FPRS_TRANSACT(n, base) SAVE_16FPRS_TRANSACT(n, base); \
140 SAVE_16FPRS_TRANSACT(n+16, base)
141
142#define REST_FPR_TRANSACT(n, base) lfd n,THREAD_TRANSACT_FPR0+ \
143 8*TS_FPRWIDTH*(n)(base)
144#define REST_2FPRS_TRANSACT(n, base) REST_FPR_TRANSACT(n, base); \
145 REST_FPR_TRANSACT(n+1, base)
146#define REST_4FPRS_TRANSACT(n, base) REST_2FPRS_TRANSACT(n, base); \
147 REST_2FPRS_TRANSACT(n+2, base)
148#define REST_8FPRS_TRANSACT(n, base) REST_4FPRS_TRANSACT(n, base); \
149 REST_4FPRS_TRANSACT(n+4, base)
150#define REST_16FPRS_TRANSACT(n, base) REST_8FPRS_TRANSACT(n, base); \
151 REST_8FPRS_TRANSACT(n+8, base)
152#define REST_32FPRS_TRANSACT(n, base) REST_16FPRS_TRANSACT(n, base); \
153 REST_16FPRS_TRANSACT(n+16, base)
154
155
156#define SAVE_VR_TRANSACT(n,b,base) li b,THREAD_TRANSACT_VR0+(16*(n)); \
157 stvx n,b,base
158#define SAVE_2VRS_TRANSACT(n,b,base) SAVE_VR_TRANSACT(n,b,base); \
159 SAVE_VR_TRANSACT(n+1,b,base)
160#define SAVE_4VRS_TRANSACT(n,b,base) SAVE_2VRS_TRANSACT(n,b,base); \
161 SAVE_2VRS_TRANSACT(n+2,b,base)
162#define SAVE_8VRS_TRANSACT(n,b,base) SAVE_4VRS_TRANSACT(n,b,base); \
163 SAVE_4VRS_TRANSACT(n+4,b,base)
164#define SAVE_16VRS_TRANSACT(n,b,base) SAVE_8VRS_TRANSACT(n,b,base); \
165 SAVE_8VRS_TRANSACT(n+8,b,base)
166#define SAVE_32VRS_TRANSACT(n,b,base) SAVE_16VRS_TRANSACT(n,b,base); \
167 SAVE_16VRS_TRANSACT(n+16,b,base)
168
169#define REST_VR_TRANSACT(n,b,base) li b,THREAD_TRANSACT_VR0+(16*(n)); \
170 lvx n,b,base
171#define REST_2VRS_TRANSACT(n,b,base) REST_VR_TRANSACT(n,b,base); \
172 REST_VR_TRANSACT(n+1,b,base)
173#define REST_4VRS_TRANSACT(n,b,base) REST_2VRS_TRANSACT(n,b,base); \
174 REST_2VRS_TRANSACT(n+2,b,base)
175#define REST_8VRS_TRANSACT(n,b,base) REST_4VRS_TRANSACT(n,b,base); \
176 REST_4VRS_TRANSACT(n+4,b,base)
177#define REST_16VRS_TRANSACT(n,b,base) REST_8VRS_TRANSACT(n,b,base); \
178 REST_8VRS_TRANSACT(n+8,b,base)
179#define REST_32VRS_TRANSACT(n,b,base) REST_16VRS_TRANSACT(n,b,base); \
180 REST_16VRS_TRANSACT(n+16,b,base)
181
182
183#define SAVE_VSR_TRANSACT(n,b,base) li b,THREAD_TRANSACT_VSR0+(16*(n)); \
184 STXVD2X(n,R##base,R##b)
185#define SAVE_2VSRS_TRANSACT(n,b,base) SAVE_VSR_TRANSACT(n,b,base); \
186 SAVE_VSR_TRANSACT(n+1,b,base)
187#define SAVE_4VSRS_TRANSACT(n,b,base) SAVE_2VSRS_TRANSACT(n,b,base); \
188 SAVE_2VSRS_TRANSACT(n+2,b,base)
189#define SAVE_8VSRS_TRANSACT(n,b,base) SAVE_4VSRS_TRANSACT(n,b,base); \
190 SAVE_4VSRS_TRANSACT(n+4,b,base)
191#define SAVE_16VSRS_TRANSACT(n,b,base) SAVE_8VSRS_TRANSACT(n,b,base); \
192 SAVE_8VSRS_TRANSACT(n+8,b,base)
193#define SAVE_32VSRS_TRANSACT(n,b,base) SAVE_16VSRS_TRANSACT(n,b,base); \
194 SAVE_16VSRS_TRANSACT(n+16,b,base)
195
196#define REST_VSR_TRANSACT(n,b,base) li b,THREAD_TRANSACT_VSR0+(16*(n)); \
197 LXVD2X(n,R##base,R##b)
198#define REST_2VSRS_TRANSACT(n,b,base) REST_VSR_TRANSACT(n,b,base); \
199 REST_VSR_TRANSACT(n+1,b,base)
200#define REST_4VSRS_TRANSACT(n,b,base) REST_2VSRS_TRANSACT(n,b,base); \
201 REST_2VSRS_TRANSACT(n+2,b,base)
202#define REST_8VSRS_TRANSACT(n,b,base) REST_4VSRS_TRANSACT(n,b,base); \
203 REST_4VSRS_TRANSACT(n+4,b,base)
204#define REST_16VSRS_TRANSACT(n,b,base) REST_8VSRS_TRANSACT(n,b,base); \
205 REST_8VSRS_TRANSACT(n+8,b,base)
206#define REST_32VSRS_TRANSACT(n,b,base) REST_16VSRS_TRANSACT(n,b,base); \
207 REST_16VSRS_TRANSACT(n+16,b,base)
208
128/* Save the lower 32 VSRs in the thread VSR region */ 209/* Save the lower 32 VSRs in the thread VSR region */
129#define SAVE_VSR(n,b,base) li b,THREAD_VSR0+(16*(n)); STXVD2X(n,R##base,R##b) 210#define SAVE_VSR(n,b,base) li b,THREAD_VSR0+(16*(n)); STXVD2X(n,R##base,R##b)
130#define SAVE_2VSRS(n,b,base) SAVE_VSR(n,b,base); SAVE_VSR(n+1,b,base) 211#define SAVE_2VSRS(n,b,base) SAVE_VSR(n,b,base); SAVE_VSR(n+1,b,base)
@@ -391,6 +472,31 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601)
391 FTR_SECTION_ELSE_NESTED(848); \ 472 FTR_SECTION_ELSE_NESTED(848); \
392 mtocrf (FXM), RS; \ 473 mtocrf (FXM), RS; \
393 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_NOEXECUTE, 848) 474 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_NOEXECUTE, 848)
475
476/*
477 * PPR restore macros used in entry_64.S
478 * Used for P7 or later processors
479 */
480#define HMT_MEDIUM_LOW_HAS_PPR \
481BEGIN_FTR_SECTION_NESTED(944) \
482 HMT_MEDIUM_LOW; \
483END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,944)
484
485#define SET_DEFAULT_THREAD_PPR(ra, rb) \
486BEGIN_FTR_SECTION_NESTED(945) \
487 lis ra,INIT_PPR@highest; /* default ppr=3 */ \
488 ld rb,PACACURRENT(r13); \
489 sldi ra,ra,32; /* 11- 13 bits are used for ppr */ \
490 std ra,TASKTHREADPPR(rb); \
491END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,945)
492
493#define RESTORE_PPR(ra, rb) \
494BEGIN_FTR_SECTION_NESTED(946) \
495 ld ra,PACACURRENT(r13); \
496 ld rb,TASKTHREADPPR(ra); \
497 mtspr SPRN_PPR,rb; /* Restore PPR */ \
498END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,946)
499
394#endif 500#endif
395 501
396/* 502/*
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index 87502046c0dc..7ff9eaa3ea6c 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -18,11 +18,22 @@
18#define TS_FPRWIDTH 1 18#define TS_FPRWIDTH 1
19#endif 19#endif
20 20
21#ifdef CONFIG_PPC64
22/* Default SMT priority is set to 3. Use 11- 13bits to save priority. */
23#define PPR_PRIORITY 3
24#ifdef __ASSEMBLY__
25#define INIT_PPR (PPR_PRIORITY << 50)
26#else
27#define INIT_PPR ((u64)PPR_PRIORITY << 50)
28#endif /* __ASSEMBLY__ */
29#endif /* CONFIG_PPC64 */
30
21#ifndef __ASSEMBLY__ 31#ifndef __ASSEMBLY__
22#include <linux/compiler.h> 32#include <linux/compiler.h>
23#include <linux/cache.h> 33#include <linux/cache.h>
24#include <asm/ptrace.h> 34#include <asm/ptrace.h>
25#include <asm/types.h> 35#include <asm/types.h>
36#include <asm/hw_breakpoint.h>
26 37
27/* We do _not_ want to define new machine types at all, those must die 38/* We do _not_ want to define new machine types at all, those must die
28 * in favor of using the device-tree 39 * in favor of using the device-tree
@@ -141,6 +152,7 @@ typedef struct {
141#define TS_FPROFFSET 0 152#define TS_FPROFFSET 0
142#define TS_VSRLOWOFFSET 1 153#define TS_VSRLOWOFFSET 1
143#define TS_FPR(i) fpr[i][TS_FPROFFSET] 154#define TS_FPR(i) fpr[i][TS_FPROFFSET]
155#define TS_TRANS_FPR(i) transact_fpr[i][TS_FPROFFSET]
144 156
145struct thread_struct { 157struct thread_struct {
146 unsigned long ksp; /* Kernel stack pointer */ 158 unsigned long ksp; /* Kernel stack pointer */
@@ -215,8 +227,7 @@ struct thread_struct {
215 struct perf_event *last_hit_ubp; 227 struct perf_event *last_hit_ubp;
216#endif /* CONFIG_HAVE_HW_BREAKPOINT */ 228#endif /* CONFIG_HAVE_HW_BREAKPOINT */
217#endif 229#endif
218 unsigned long dabr; /* Data address breakpoint register */ 230 struct arch_hw_breakpoint hw_brk; /* info on the hardware breakpoint */
219 unsigned long dabrx; /* ... extension */
220 unsigned long trap_nr; /* last trap # on this thread */ 231 unsigned long trap_nr; /* last trap # on this thread */
221#ifdef CONFIG_ALTIVEC 232#ifdef CONFIG_ALTIVEC
222 /* Complete AltiVec register set */ 233 /* Complete AltiVec register set */
@@ -236,6 +247,34 @@ struct thread_struct {
236 unsigned long spefscr; /* SPE & eFP status */ 247 unsigned long spefscr; /* SPE & eFP status */
237 int used_spe; /* set if process has used spe */ 248 int used_spe; /* set if process has used spe */
238#endif /* CONFIG_SPE */ 249#endif /* CONFIG_SPE */
250#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
251 u64 tm_tfhar; /* Transaction fail handler addr */
252 u64 tm_texasr; /* Transaction exception & summary */
253 u64 tm_tfiar; /* Transaction fail instr address reg */
254 unsigned long tm_orig_msr; /* Thread's MSR on ctx switch */
255 struct pt_regs ckpt_regs; /* Checkpointed registers */
256
257 /*
258 * Transactional FP and VSX 0-31 register set.
259 * NOTE: the sense of these is the opposite of the integer ckpt_regs!
260 *
261 * When a transaction is active/signalled/scheduled etc., *regs is the
262 * most recent set of/speculated GPRs with ckpt_regs being the older
263 * checkpointed regs to which we roll back if transaction aborts.
264 *
265 * However, fpr[] is the checkpointed 'base state' of FP regs, and
266 * transact_fpr[] is the new set of transactional values.
267 * VRs work the same way.
268 */
269 double transact_fpr[32][TS_FPRWIDTH];
270 struct {
271 unsigned int pad;
272 unsigned int val; /* Floating point status */
273 } transact_fpscr;
274 vector128 transact_vr[32] __attribute__((aligned(16)));
275 vector128 transact_vscr __attribute__((aligned(16)));
276 unsigned long transact_vrsave;
277#endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
239#ifdef CONFIG_KVM_BOOK3S_32_HANDLER 278#ifdef CONFIG_KVM_BOOK3S_32_HANDLER
240 void* kvm_shadow_vcpu; /* KVM internal data */ 279 void* kvm_shadow_vcpu; /* KVM internal data */
241#endif /* CONFIG_KVM_BOOK3S_32_HANDLER */ 280#endif /* CONFIG_KVM_BOOK3S_32_HANDLER */
@@ -245,6 +284,10 @@ struct thread_struct {
245#ifdef CONFIG_PPC64 284#ifdef CONFIG_PPC64
246 unsigned long dscr; 285 unsigned long dscr;
247 int dscr_inherit; 286 int dscr_inherit;
287 unsigned long ppr; /* used to save/restore SMT priority */
288#endif
289#ifdef CONFIG_PPC_BOOK3S_64
290 unsigned long tar;
248#endif 291#endif
249}; 292};
250 293
@@ -278,6 +321,7 @@ struct thread_struct {
278 .fpr = {{0}}, \ 321 .fpr = {{0}}, \
279 .fpscr = { .val = 0, }, \ 322 .fpscr = { .val = 0, }, \
280 .fpexc_mode = 0, \ 323 .fpexc_mode = 0, \
324 .ppr = INIT_PPR, \
281} 325}
282#endif 326#endif
283 327
diff --git a/arch/powerpc/include/asm/ps3.h b/arch/powerpc/include/asm/ps3.h
index 0e15db4d703b..678a7c1d9cb8 100644
--- a/arch/powerpc/include/asm/ps3.h
+++ b/arch/powerpc/include/asm/ps3.h
@@ -245,7 +245,7 @@ enum lv1_result {
245 245
246static inline const char* ps3_result(int result) 246static inline const char* ps3_result(int result)
247{ 247{
248#if defined(DEBUG) 248#if defined(DEBUG) || defined(PS3_VERBOSE_RESULT)
249 switch (result) { 249 switch (result) {
250 case LV1_SUCCESS: 250 case LV1_SUCCESS:
251 return "LV1_SUCCESS (0)"; 251 return "LV1_SUCCESS (0)";
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index 3d5c9dc8917a..7035e608f3fa 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -29,6 +29,10 @@
29#define MSR_SF_LG 63 /* Enable 64 bit mode */ 29#define MSR_SF_LG 63 /* Enable 64 bit mode */
30#define MSR_ISF_LG 61 /* Interrupt 64b mode valid on 630 */ 30#define MSR_ISF_LG 61 /* Interrupt 64b mode valid on 630 */
31#define MSR_HV_LG 60 /* Hypervisor state */ 31#define MSR_HV_LG 60 /* Hypervisor state */
32#define MSR_TS_T_LG 34 /* Trans Mem state: Transactional */
33#define MSR_TS_S_LG 33 /* Trans Mem state: Suspended */
34#define MSR_TS_LG 33 /* Trans Mem state (2 bits) */
35#define MSR_TM_LG 32 /* Trans Mem Available */
32#define MSR_VEC_LG 25 /* Enable AltiVec */ 36#define MSR_VEC_LG 25 /* Enable AltiVec */
33#define MSR_VSX_LG 23 /* Enable VSX */ 37#define MSR_VSX_LG 23 /* Enable VSX */
34#define MSR_POW_LG 18 /* Enable Power Management */ 38#define MSR_POW_LG 18 /* Enable Power Management */
@@ -98,6 +102,26 @@
98#define MSR_RI __MASK(MSR_RI_LG) /* Recoverable Exception */ 102#define MSR_RI __MASK(MSR_RI_LG) /* Recoverable Exception */
99#define MSR_LE __MASK(MSR_LE_LG) /* Little Endian */ 103#define MSR_LE __MASK(MSR_LE_LG) /* Little Endian */
100 104
105#define MSR_TM __MASK(MSR_TM_LG) /* Transactional Mem Available */
106#define MSR_TS_N 0 /* Non-transactional */
107#define MSR_TS_S __MASK(MSR_TS_S_LG) /* Transaction Suspended */
108#define MSR_TS_T __MASK(MSR_TS_T_LG) /* Transaction Transactional */
109#define MSR_TS_MASK (MSR_TS_T | MSR_TS_S) /* Transaction State bits */
110#define MSR_TM_ACTIVE(x) (((x) & MSR_TS_MASK) != 0) /* Transaction active? */
111#define MSR_TM_TRANSACTIONAL(x) (((x) & MSR_TS_MASK) == MSR_TS_T)
112#define MSR_TM_SUSPENDED(x) (((x) & MSR_TS_MASK) == MSR_TS_S)
113
114/* Reason codes describing kernel causes for transaction aborts. By
115 convention, bit0 is copied to TEXASR[56] (IBM bit 7) which is set if
116 the failure is persistent.
117*/
118#define TM_CAUSE_RESCHED 0xfe
119#define TM_CAUSE_TLBI 0xfc
120#define TM_CAUSE_FAC_UNAV 0xfa
121#define TM_CAUSE_SYSCALL 0xf9 /* Persistent */
122#define TM_CAUSE_MISC 0xf6
123#define TM_CAUSE_SIGNAL 0xf4
124
101#if defined(CONFIG_PPC_BOOK3S_64) 125#if defined(CONFIG_PPC_BOOK3S_64)
102#define MSR_64BIT MSR_SF 126#define MSR_64BIT MSR_SF
103 127
@@ -193,6 +217,10 @@
193#define SPRN_UAMOR 0x9d /* User Authority Mask Override Register */ 217#define SPRN_UAMOR 0x9d /* User Authority Mask Override Register */
194#define SPRN_AMOR 0x15d /* Authority Mask Override Register */ 218#define SPRN_AMOR 0x15d /* Authority Mask Override Register */
195#define SPRN_ACOP 0x1F /* Available Coprocessor Register */ 219#define SPRN_ACOP 0x1F /* Available Coprocessor Register */
220#define SPRN_TFIAR 0x81 /* Transaction Failure Inst Addr */
221#define SPRN_TEXASR 0x82 /* Transaction EXception & Summary */
222#define SPRN_TEXASRU 0x83 /* '' '' '' Upper 32 */
223#define SPRN_TFHAR 0x80 /* Transaction Failure Handler Addr */
196#define SPRN_CTRLF 0x088 224#define SPRN_CTRLF 0x088
197#define SPRN_CTRLT 0x098 225#define SPRN_CTRLT 0x098
198#define CTRL_CT 0xc0000000 /* current thread */ 226#define CTRL_CT 0xc0000000 /* current thread */
@@ -200,10 +228,12 @@
200#define CTRL_CT1 0x40000000 /* thread 1 */ 228#define CTRL_CT1 0x40000000 /* thread 1 */
201#define CTRL_TE 0x00c00000 /* thread enable */ 229#define CTRL_TE 0x00c00000 /* thread enable */
202#define CTRL_RUNLATCH 0x1 230#define CTRL_RUNLATCH 0x1
231#define SPRN_DAWR 0xB4
232#define SPRN_DAWRX 0xBC
233#define DAWRX_USER (1UL << 0)
234#define DAWRX_KERNEL (1UL << 1)
235#define DAWRX_HYP (1UL << 2)
203#define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */ 236#define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */
204#define DABR_TRANSLATION (1UL << 2)
205#define DABR_DATA_WRITE (1UL << 1)
206#define DABR_DATA_READ (1UL << 0)
207#define SPRN_DABR2 0x13D /* e300 */ 237#define SPRN_DABR2 0x13D /* e300 */
208#define SPRN_DABRX 0x3F7 /* Data Address Breakpoint Register Extension */ 238#define SPRN_DABRX 0x3F7 /* Data Address Breakpoint Register Extension */
209#define DABRX_USER (1UL << 0) 239#define DABRX_USER (1UL << 0)
@@ -235,6 +265,9 @@
235#define SPRN_HRMOR 0x139 /* Real mode offset register */ 265#define SPRN_HRMOR 0x139 /* Real mode offset register */
236#define SPRN_HSRR0 0x13A /* Hypervisor Save/Restore 0 */ 266#define SPRN_HSRR0 0x13A /* Hypervisor Save/Restore 0 */
237#define SPRN_HSRR1 0x13B /* Hypervisor Save/Restore 1 */ 267#define SPRN_HSRR1 0x13B /* Hypervisor Save/Restore 1 */
268#define SPRN_FSCR 0x099 /* Facility Status & Control Register */
269#define FSCR_TAR (1<<8) /* Enable Target Adress Register */
270#define SPRN_TAR 0x32f /* Target Address Register */
238#define SPRN_LPCR 0x13E /* LPAR Control Register */ 271#define SPRN_LPCR 0x13E /* LPAR Control Register */
239#define LPCR_VPM0 (1ul << (63-0)) 272#define LPCR_VPM0 (1ul << (63-0))
240#define LPCR_VPM1 (1ul << (63-1)) 273#define LPCR_VPM1 (1ul << (63-1))
@@ -289,6 +322,7 @@
289#define SPRN_DBAT6U 0x23C /* Data BAT 6 Upper Register */ 322#define SPRN_DBAT6U 0x23C /* Data BAT 6 Upper Register */
290#define SPRN_DBAT7L 0x23F /* Data BAT 7 Lower Register */ 323#define SPRN_DBAT7L 0x23F /* Data BAT 7 Lower Register */
291#define SPRN_DBAT7U 0x23E /* Data BAT 7 Upper Register */ 324#define SPRN_DBAT7U 0x23E /* Data BAT 7 Upper Register */
325#define SPRN_PPR 0x380 /* SMT Thread status Register */
292 326
293#define SPRN_DEC 0x016 /* Decrement Register */ 327#define SPRN_DEC 0x016 /* Decrement Register */
294#define SPRN_DER 0x095 /* Debug Enable Regsiter */ 328#define SPRN_DER 0x095 /* Debug Enable Regsiter */
@@ -483,6 +517,7 @@
483#ifndef SPRN_PIR 517#ifndef SPRN_PIR
484#define SPRN_PIR 0x3FF /* Processor Identification Register */ 518#define SPRN_PIR 0x3FF /* Processor Identification Register */
485#endif 519#endif
520#define SPRN_TIR 0x1BE /* Thread Identification Register */
486#define SPRN_PTEHI 0x3D5 /* 981 7450 PTE HI word (S/W TLB load) */ 521#define SPRN_PTEHI 0x3D5 /* 981 7450 PTE HI word (S/W TLB load) */
487#define SPRN_PTELO 0x3D6 /* 982 7450 PTE LO word (S/W TLB load) */ 522#define SPRN_PTELO 0x3D6 /* 982 7450 PTE LO word (S/W TLB load) */
488#define SPRN_PURR 0x135 /* Processor Utilization of Resources Reg */ 523#define SPRN_PURR 0x135 /* Processor Utilization of Resources Reg */
@@ -763,7 +798,7 @@
763 * HV mode in which case it is HSPRG0 798 * HV mode in which case it is HSPRG0
764 * 799 *
765 * 64-bit server: 800 * 64-bit server:
766 * - SPRG0 unused (reserved for HV on Power4) 801 * - SPRG0 scratch for TM recheckpoint/reclaim (reserved for HV on Power4)
767 * - SPRG2 scratch for exception vectors 802 * - SPRG2 scratch for exception vectors
768 * - SPRG3 CPU and NUMA node for VDSO getcpu (user visible) 803 * - SPRG3 CPU and NUMA node for VDSO getcpu (user visible)
769 * - HSPRG0 stores PACA in HV mode 804 * - HSPRG0 stores PACA in HV mode
diff --git a/arch/powerpc/include/asm/sections.h b/arch/powerpc/include/asm/sections.h
index a0f358d4a00c..4ee06fe15de4 100644
--- a/arch/powerpc/include/asm/sections.h
+++ b/arch/powerpc/include/asm/sections.h
@@ -10,6 +10,9 @@
10 10
11extern char __end_interrupts[]; 11extern char __end_interrupts[];
12 12
13extern char __prom_init_toc_start[];
14extern char __prom_init_toc_end[];
15
13static inline int in_kernel_text(unsigned long addr) 16static inline int in_kernel_text(unsigned long addr)
14{ 17{
15 if (addr >= (unsigned long)_stext && addr < (unsigned long)__init_end) 18 if (addr >= (unsigned long)_stext && addr < (unsigned long)__init_end)
diff --git a/arch/powerpc/include/asm/spinlock.h b/arch/powerpc/include/asm/spinlock.h
index 7124fc06ad47..5b23f910ee57 100644
--- a/arch/powerpc/include/asm/spinlock.h
+++ b/arch/powerpc/include/asm/spinlock.h
@@ -96,7 +96,7 @@ static inline int arch_spin_trylock(arch_spinlock_t *lock)
96 96
97#if defined(CONFIG_PPC_SPLPAR) 97#if defined(CONFIG_PPC_SPLPAR)
98/* We only yield to the hypervisor if we are in shared processor mode */ 98/* We only yield to the hypervisor if we are in shared processor mode */
99#define SHARED_PROCESSOR (get_lppaca()->shared_proc) 99#define SHARED_PROCESSOR (local_paca->lppaca_ptr->shared_proc)
100extern void __spin_yield(arch_spinlock_t *lock); 100extern void __spin_yield(arch_spinlock_t *lock);
101extern void __rw_yield(arch_rwlock_t *lock); 101extern void __rw_yield(arch_rwlock_t *lock);
102#else /* SPLPAR */ 102#else /* SPLPAR */
diff --git a/arch/powerpc/include/asm/tm.h b/arch/powerpc/include/asm/tm.h
new file mode 100644
index 000000000000..4b4449abf3f8
--- /dev/null
+++ b/arch/powerpc/include/asm/tm.h
@@ -0,0 +1,20 @@
1/*
2 * Transactional memory support routines to reclaim and recheckpoint
3 * transactional process state.
4 *
5 * Copyright 2012 Matt Evans & Michael Neuling, IBM Corporation.
6 */
7
8#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
9extern void do_load_up_transact_fpu(struct thread_struct *thread);
10extern void do_load_up_transact_altivec(struct thread_struct *thread);
11#endif
12
13extern void tm_enable(void);
14extern void tm_reclaim(struct thread_struct *thread,
15 unsigned long orig_msr, uint8_t cause);
16extern void tm_recheckpoint(struct thread_struct *thread,
17 unsigned long orig_msr);
18extern void tm_abort(uint8_t cause);
19extern void tm_save_sprs(struct thread_struct *thread);
20extern void tm_restore_sprs(struct thread_struct *thread);
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-27 20:04:00 -0500