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-rw-r--r--arch/powerpc/include/asm/Kbuild3
-rw-r--r--arch/powerpc/include/asm/barrier.h21
-rw-r--r--arch/powerpc/include/asm/bitops.h5
-rw-r--r--arch/powerpc/include/asm/cache.h14
-rw-r--r--arch/powerpc/include/asm/clk_interface.h20
-rw-r--r--arch/powerpc/include/asm/cmpxchg.h1
-rw-r--r--arch/powerpc/include/asm/code-patching.h7
-rw-r--r--arch/powerpc/include/asm/compat.h5
-rw-r--r--arch/powerpc/include/asm/cputable.h12
-rw-r--r--arch/powerpc/include/asm/dma-mapping.h1
-rw-r--r--arch/powerpc/include/asm/eeh.h35
-rw-r--r--arch/powerpc/include/asm/epapr_hcalls.h111
-rw-r--r--arch/powerpc/include/asm/exception-64s.h21
-rw-r--r--arch/powerpc/include/asm/fixmap.h44
-rw-r--r--arch/powerpc/include/asm/fsl_lbc.h2
-rw-r--r--arch/powerpc/include/asm/hardirq.h3
-rw-r--r--arch/powerpc/include/asm/hugetlb.h2
-rw-r--r--arch/powerpc/include/asm/io.h16
-rw-r--r--arch/powerpc/include/asm/iommu.h55
-rw-r--r--arch/powerpc/include/asm/kvm_asm.h4
-rw-r--r--arch/powerpc/include/asm/kvm_book3s.h27
-rw-r--r--arch/powerpc/include/asm/kvm_book3s_asm.h1
-rw-r--r--arch/powerpc/include/asm/kvm_booke.h6
-rw-r--r--arch/powerpc/include/asm/kvm_host.h61
-rw-r--r--arch/powerpc/include/asm/kvm_para.h80
-rw-r--r--arch/powerpc/include/asm/kvm_ppc.h13
-rw-r--r--arch/powerpc/include/asm/lppaca.h2
-rw-r--r--arch/powerpc/include/asm/mce.h197
-rw-r--r--arch/powerpc/include/asm/mmu-book3e.h13
-rw-r--r--arch/powerpc/include/asm/mmu.h21
-rw-r--r--arch/powerpc/include/asm/mpc5121.h7
-rw-r--r--arch/powerpc/include/asm/opal.h112
-rw-r--r--arch/powerpc/include/asm/paca.h16
-rw-r--r--arch/powerpc/include/asm/pgtable-ppc64.h40
-rw-r--r--arch/powerpc/include/asm/pgtable.h109
-rw-r--r--arch/powerpc/include/asm/ppc_asm.h14
-rw-r--r--arch/powerpc/include/asm/processor.h15
-rw-r--r--arch/powerpc/include/asm/ps3.h1
-rw-r--r--arch/powerpc/include/asm/pte-hash64.h8
-rw-r--r--arch/powerpc/include/asm/ptrace.h16
-rw-r--r--arch/powerpc/include/asm/reg.h45
-rw-r--r--arch/powerpc/include/asm/reg_booke.h10
-rw-r--r--arch/powerpc/include/asm/sections.h12
-rw-r--r--arch/powerpc/include/asm/setup.h1
-rw-r--r--arch/powerpc/include/asm/spinlock.h12
-rw-r--r--arch/powerpc/include/asm/switch_to.h2
-rw-r--r--arch/powerpc/include/asm/systbl.h2
-rw-r--r--arch/powerpc/include/asm/thread_info.h9
-rw-r--r--arch/powerpc/include/asm/tm.h1
-rw-r--r--arch/powerpc/include/asm/topology.h10
-rw-r--r--arch/powerpc/include/asm/unistd.h2
-rw-r--r--arch/powerpc/include/asm/uprobes.h5
-rw-r--r--arch/powerpc/include/asm/vdso.h6
-rw-r--r--arch/powerpc/include/asm/vio.h1
54 files changed, 994 insertions, 265 deletions
diff --git a/arch/powerpc/include/asm/Kbuild b/arch/powerpc/include/asm/Kbuild
index d8f9d2f18a23..6c0a955a1b06 100644
--- a/arch/powerpc/include/asm/Kbuild
+++ b/arch/powerpc/include/asm/Kbuild
@@ -3,4 +3,5 @@ generic-y += clkdev.h
3generic-y += rwsem.h 3generic-y += rwsem.h
4generic-y += trace_clock.h 4generic-y += trace_clock.h
5generic-y += preempt.h 5generic-y += preempt.h
6generic-y += vtime.h \ No newline at end of file 6generic-y += vtime.h
7generic-y += hash.h
diff --git a/arch/powerpc/include/asm/barrier.h b/arch/powerpc/include/asm/barrier.h
index ae782254e731..f89da808ce31 100644
--- a/arch/powerpc/include/asm/barrier.h
+++ b/arch/powerpc/include/asm/barrier.h
@@ -45,11 +45,15 @@
45# define SMPWMB eieio 45# define SMPWMB eieio
46#endif 46#endif
47 47
48#define __lwsync() __asm__ __volatile__ (stringify_in_c(LWSYNC) : : :"memory")
49
48#define smp_mb() mb() 50#define smp_mb() mb()
49#define smp_rmb() __asm__ __volatile__ (stringify_in_c(LWSYNC) : : :"memory") 51#define smp_rmb() __lwsync()
50#define smp_wmb() __asm__ __volatile__ (stringify_in_c(SMPWMB) : : :"memory") 52#define smp_wmb() __asm__ __volatile__ (stringify_in_c(SMPWMB) : : :"memory")
51#define smp_read_barrier_depends() read_barrier_depends() 53#define smp_read_barrier_depends() read_barrier_depends()
52#else 54#else
55#define __lwsync() barrier()
56
53#define smp_mb() barrier() 57#define smp_mb() barrier()
54#define smp_rmb() barrier() 58#define smp_rmb() barrier()
55#define smp_wmb() barrier() 59#define smp_wmb() barrier()
@@ -65,4 +69,19 @@
65#define data_barrier(x) \ 69#define data_barrier(x) \
66 asm volatile("twi 0,%0,0; isync" : : "r" (x) : "memory"); 70 asm volatile("twi 0,%0,0; isync" : : "r" (x) : "memory");
67 71
72#define smp_store_release(p, v) \
73do { \
74 compiletime_assert_atomic_type(*p); \
75 __lwsync(); \
76 ACCESS_ONCE(*p) = (v); \
77} while (0)
78
79#define smp_load_acquire(p) \
80({ \
81 typeof(*p) ___p1 = ACCESS_ONCE(*p); \
82 compiletime_assert_atomic_type(*p); \
83 __lwsync(); \
84 ___p1; \
85})
86
68#endif /* _ASM_POWERPC_BARRIER_H */ 87#endif /* _ASM_POWERPC_BARRIER_H */
diff --git a/arch/powerpc/include/asm/bitops.h b/arch/powerpc/include/asm/bitops.h
index 910194e9a1e2..a5e9a7d494d8 100644
--- a/arch/powerpc/include/asm/bitops.h
+++ b/arch/powerpc/include/asm/bitops.h
@@ -46,6 +46,11 @@
46#include <asm/asm-compat.h> 46#include <asm/asm-compat.h>
47#include <asm/synch.h> 47#include <asm/synch.h>
48 48
49/* PPC bit number conversion */
50#define PPC_BITLSHIFT(be) (BITS_PER_LONG - 1 - (be))
51#define PPC_BIT(bit) (1UL << PPC_BITLSHIFT(bit))
52#define PPC_BITMASK(bs, be) ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
53
49/* 54/*
50 * clear_bit doesn't imply a memory barrier 55 * clear_bit doesn't imply a memory barrier
51 */ 56 */
diff --git a/arch/powerpc/include/asm/cache.h b/arch/powerpc/include/asm/cache.h
index 9e495c9a6a88..ed0afc1e44a4 100644
--- a/arch/powerpc/include/asm/cache.h
+++ b/arch/powerpc/include/asm/cache.h
@@ -41,8 +41,20 @@ struct ppc64_caches {
41extern struct ppc64_caches ppc64_caches; 41extern struct ppc64_caches ppc64_caches;
42#endif /* __powerpc64__ && ! __ASSEMBLY__ */ 42#endif /* __powerpc64__ && ! __ASSEMBLY__ */
43 43
44#if !defined(__ASSEMBLY__) 44#if defined(__ASSEMBLY__)
45/*
46 * For a snooping icache, we still need a dummy icbi to purge all the
47 * prefetched instructions from the ifetch buffers. We also need a sync
48 * before the icbi to order the the actual stores to memory that might
49 * have modified instructions with the icbi.
50 */
51#define PURGE_PREFETCHED_INS \
52 sync; \
53 icbi 0,r3; \
54 sync; \
55 isync
45 56
57#else
46#define __read_mostly __attribute__((__section__(".data..read_mostly"))) 58#define __read_mostly __attribute__((__section__(".data..read_mostly")))
47 59
48#ifdef CONFIG_6xx 60#ifdef CONFIG_6xx
diff --git a/arch/powerpc/include/asm/clk_interface.h b/arch/powerpc/include/asm/clk_interface.h
deleted file mode 100644
index ab1882c1e176..000000000000
--- a/arch/powerpc/include/asm/clk_interface.h
+++ /dev/null
@@ -1,20 +0,0 @@
1#ifndef __ASM_POWERPC_CLK_INTERFACE_H
2#define __ASM_POWERPC_CLK_INTERFACE_H
3
4#include <linux/clk.h>
5
6struct clk_interface {
7 struct clk* (*clk_get) (struct device *dev, const char *id);
8 int (*clk_enable) (struct clk *clk);
9 void (*clk_disable) (struct clk *clk);
10 unsigned long (*clk_get_rate) (struct clk *clk);
11 void (*clk_put) (struct clk *clk);
12 long (*clk_round_rate) (struct clk *clk, unsigned long rate);
13 int (*clk_set_rate) (struct clk *clk, unsigned long rate);
14 int (*clk_set_parent) (struct clk *clk, struct clk *parent);
15 struct clk* (*clk_get_parent) (struct clk *clk);
16};
17
18extern struct clk_interface clk_functions;
19
20#endif /* __ASM_POWERPC_CLK_INTERFACE_H */
diff --git a/arch/powerpc/include/asm/cmpxchg.h b/arch/powerpc/include/asm/cmpxchg.h
index e245aab7f191..d463c68fe7f0 100644
--- a/arch/powerpc/include/asm/cmpxchg.h
+++ b/arch/powerpc/include/asm/cmpxchg.h
@@ -300,6 +300,7 @@ __cmpxchg_local(volatile void *ptr, unsigned long old, unsigned long new,
300 BUILD_BUG_ON(sizeof(*(ptr)) != 8); \ 300 BUILD_BUG_ON(sizeof(*(ptr)) != 8); \
301 cmpxchg_local((ptr), (o), (n)); \ 301 cmpxchg_local((ptr), (o), (n)); \
302 }) 302 })
303#define cmpxchg64_relaxed cmpxchg64_local
303#else 304#else
304#include <asm-generic/cmpxchg-local.h> 305#include <asm-generic/cmpxchg-local.h>
305#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n)) 306#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
diff --git a/arch/powerpc/include/asm/code-patching.h b/arch/powerpc/include/asm/code-patching.h
index a6f8c7a5cbb7..97e02f985df8 100644
--- a/arch/powerpc/include/asm/code-patching.h
+++ b/arch/powerpc/include/asm/code-patching.h
@@ -34,6 +34,13 @@ int instr_is_branch_to_addr(const unsigned int *instr, unsigned long addr);
34unsigned long branch_target(const unsigned int *instr); 34unsigned long branch_target(const unsigned int *instr);
35unsigned int translate_branch(const unsigned int *dest, 35unsigned int translate_branch(const unsigned int *dest,
36 const unsigned int *src); 36 const unsigned int *src);
37#ifdef CONFIG_PPC_BOOK3E_64
38void __patch_exception(int exc, unsigned long addr);
39#define patch_exception(exc, name) do { \
40 extern unsigned int name; \
41 __patch_exception((exc), (unsigned long)&name); \
42} while (0)
43#endif
37 44
38static inline unsigned long ppc_function_entry(void *func) 45static inline unsigned long ppc_function_entry(void *func)
39{ 46{
diff --git a/arch/powerpc/include/asm/compat.h b/arch/powerpc/include/asm/compat.h
index 84fdf6857c31..a613d2c82fd9 100644
--- a/arch/powerpc/include/asm/compat.h
+++ b/arch/powerpc/include/asm/compat.h
@@ -200,10 +200,11 @@ static inline void __user *arch_compat_alloc_user_space(long len)
200 200
201 /* 201 /*
202 * We can't access below the stack pointer in the 32bit ABI and 202 * We can't access below the stack pointer in the 32bit ABI and
203 * can access 288 bytes in the 64bit ABI 203 * can access 288 bytes in the 64bit big-endian ABI,
204 * or 512 bytes with the new ELFv2 little-endian ABI.
204 */ 205 */
205 if (!is_32bit_task()) 206 if (!is_32bit_task())
206 usp -= 288; 207 usp -= USER_REDZONE_SIZE;
207 208
208 return (void __user *) (usp - len); 209 return (void __user *) (usp - len);
209} 210}
diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h
index 0d4939ba48e7..617cc767c076 100644
--- a/arch/powerpc/include/asm/cputable.h
+++ b/arch/powerpc/include/asm/cputable.h
@@ -90,6 +90,18 @@ struct cpu_spec {
90 * if the error is fatal, 1 if it was fully recovered and 0 to 90 * if the error is fatal, 1 if it was fully recovered and 0 to
91 * pass up (not CPU originated) */ 91 * pass up (not CPU originated) */
92 int (*machine_check)(struct pt_regs *regs); 92 int (*machine_check)(struct pt_regs *regs);
93
94 /*
95 * Processor specific early machine check handler which is
96 * called in real mode to handle SLB and TLB errors.
97 */
98 long (*machine_check_early)(struct pt_regs *regs);
99
100 /*
101 * Processor specific routine to flush tlbs.
102 */
103 void (*flush_tlb)(unsigned long inval_selector);
104
93}; 105};
94 106
95extern struct cpu_spec *cur_cpu_spec; 107extern struct cpu_spec *cur_cpu_spec;
diff --git a/arch/powerpc/include/asm/dma-mapping.h b/arch/powerpc/include/asm/dma-mapping.h
index e27e9ad6818e..150866b2a3fe 100644
--- a/arch/powerpc/include/asm/dma-mapping.h
+++ b/arch/powerpc/include/asm/dma-mapping.h
@@ -134,6 +134,7 @@ static inline int dma_supported(struct device *dev, u64 mask)
134} 134}
135 135
136extern int dma_set_mask(struct device *dev, u64 dma_mask); 136extern int dma_set_mask(struct device *dev, u64 dma_mask);
137extern int __dma_set_mask(struct device *dev, u64 dma_mask);
137 138
138#define dma_alloc_coherent(d,s,h,f) dma_alloc_attrs(d,s,h,f,NULL) 139#define dma_alloc_coherent(d,s,h,f) dma_alloc_attrs(d,s,h,f,NULL)
139 140
diff --git a/arch/powerpc/include/asm/eeh.h b/arch/powerpc/include/asm/eeh.h
index d3e5e9bc8f94..d4dd41fb951b 100644
--- a/arch/powerpc/include/asm/eeh.h
+++ b/arch/powerpc/include/asm/eeh.h
@@ -90,7 +90,8 @@ struct eeh_pe {
90#define EEH_DEV_IRQ_DISABLED (1 << 3) /* Interrupt disabled */ 90#define EEH_DEV_IRQ_DISABLED (1 << 3) /* Interrupt disabled */
91#define EEH_DEV_DISCONNECTED (1 << 4) /* Removing from PE */ 91#define EEH_DEV_DISCONNECTED (1 << 4) /* Removing from PE */
92 92
93#define EEH_DEV_SYSFS (1 << 8) /* Sysfs created */ 93#define EEH_DEV_NO_HANDLER (1 << 8) /* No error handler */
94#define EEH_DEV_SYSFS (1 << 9) /* Sysfs created */
94 95
95struct eeh_dev { 96struct eeh_dev {
96 int mode; /* EEH mode */ 97 int mode; /* EEH mode */
@@ -117,6 +118,16 @@ static inline struct pci_dev *eeh_dev_to_pci_dev(struct eeh_dev *edev)
117 return edev ? edev->pdev : NULL; 118 return edev ? edev->pdev : NULL;
118} 119}
119 120
121/* Return values from eeh_ops::next_error */
122enum {
123 EEH_NEXT_ERR_NONE = 0,
124 EEH_NEXT_ERR_INF,
125 EEH_NEXT_ERR_FROZEN_PE,
126 EEH_NEXT_ERR_FENCED_PHB,
127 EEH_NEXT_ERR_DEAD_PHB,
128 EEH_NEXT_ERR_DEAD_IOC
129};
130
120/* 131/*
121 * The struct is used to trace the registered EEH operation 132 * The struct is used to trace the registered EEH operation
122 * callback functions. Actually, those operation callback 133 * callback functions. Actually, those operation callback
@@ -157,13 +168,24 @@ struct eeh_ops {
157 int (*read_config)(struct device_node *dn, int where, int size, u32 *val); 168 int (*read_config)(struct device_node *dn, int where, int size, u32 *val);
158 int (*write_config)(struct device_node *dn, int where, int size, u32 val); 169 int (*write_config)(struct device_node *dn, int where, int size, u32 val);
159 int (*next_error)(struct eeh_pe **pe); 170 int (*next_error)(struct eeh_pe **pe);
171 int (*restore_config)(struct device_node *dn);
160}; 172};
161 173
162extern struct eeh_ops *eeh_ops; 174extern struct eeh_ops *eeh_ops;
163extern int eeh_subsystem_enabled; 175extern bool eeh_subsystem_enabled;
164extern raw_spinlock_t confirm_error_lock; 176extern raw_spinlock_t confirm_error_lock;
165extern int eeh_probe_mode; 177extern int eeh_probe_mode;
166 178
179static inline bool eeh_enabled(void)
180{
181 return eeh_subsystem_enabled;
182}
183
184static inline void eeh_set_enable(bool mode)
185{
186 eeh_subsystem_enabled = mode;
187}
188
167#define EEH_PROBE_MODE_DEV (1<<0) /* From PCI device */ 189#define EEH_PROBE_MODE_DEV (1<<0) /* From PCI device */
168#define EEH_PROBE_MODE_DEVTREE (1<<1) /* From device tree */ 190#define EEH_PROBE_MODE_DEVTREE (1<<1) /* From device tree */
169 191
@@ -234,7 +256,7 @@ void eeh_remove_device(struct pci_dev *);
234 * If this macro yields TRUE, the caller relays to eeh_check_failure() 256 * If this macro yields TRUE, the caller relays to eeh_check_failure()
235 * which does further tests out of line. 257 * which does further tests out of line.
236 */ 258 */
237#define EEH_POSSIBLE_ERROR(val, type) ((val) == (type)~0 && eeh_subsystem_enabled) 259#define EEH_POSSIBLE_ERROR(val, type) ((val) == (type)~0 && eeh_enabled())
238 260
239/* 261/*
240 * Reads from a device which has been isolated by EEH will return 262 * Reads from a device which has been isolated by EEH will return
@@ -245,6 +267,13 @@ void eeh_remove_device(struct pci_dev *);
245 267
246#else /* !CONFIG_EEH */ 268#else /* !CONFIG_EEH */
247 269
270static inline bool eeh_enabled(void)
271{
272 return false;
273}
274
275static inline void eeh_set_enable(bool mode) { }
276
248static inline int eeh_init(void) 277static inline int eeh_init(void)
249{ 278{
250 return 0; 279 return 0;
diff --git a/arch/powerpc/include/asm/epapr_hcalls.h b/arch/powerpc/include/asm/epapr_hcalls.h
index 86b0ac79990c..334459ad145b 100644
--- a/arch/powerpc/include/asm/epapr_hcalls.h
+++ b/arch/powerpc/include/asm/epapr_hcalls.h
@@ -460,5 +460,116 @@ static inline unsigned int ev_idle(void)
460 460
461 return r3; 461 return r3;
462} 462}
463
464#ifdef CONFIG_EPAPR_PARAVIRT
465static inline unsigned long epapr_hypercall(unsigned long *in,
466 unsigned long *out,
467 unsigned long nr)
468{
469 unsigned long register r0 asm("r0");
470 unsigned long register r3 asm("r3") = in[0];
471 unsigned long register r4 asm("r4") = in[1];
472 unsigned long register r5 asm("r5") = in[2];
473 unsigned long register r6 asm("r6") = in[3];
474 unsigned long register r7 asm("r7") = in[4];
475 unsigned long register r8 asm("r8") = in[5];
476 unsigned long register r9 asm("r9") = in[6];
477 unsigned long register r10 asm("r10") = in[7];
478 unsigned long register r11 asm("r11") = nr;
479 unsigned long register r12 asm("r12");
480
481 asm volatile("bl epapr_hypercall_start"
482 : "=r"(r0), "=r"(r3), "=r"(r4), "=r"(r5), "=r"(r6),
483 "=r"(r7), "=r"(r8), "=r"(r9), "=r"(r10), "=r"(r11),
484 "=r"(r12)
485 : "r"(r3), "r"(r4), "r"(r5), "r"(r6), "r"(r7), "r"(r8),
486 "r"(r9), "r"(r10), "r"(r11)
487 : "memory", "cc", "xer", "ctr", "lr");
488
489 out[0] = r4;
490 out[1] = r5;
491 out[2] = r6;
492 out[3] = r7;
493 out[4] = r8;
494 out[5] = r9;
495 out[6] = r10;
496 out[7] = r11;
497
498 return r3;
499}
500#else
501static unsigned long epapr_hypercall(unsigned long *in,
502 unsigned long *out,
503 unsigned long nr)
504{
505 return EV_UNIMPLEMENTED;
506}
507#endif
508
509static inline long epapr_hypercall0_1(unsigned int nr, unsigned long *r2)
510{
511 unsigned long in[8];
512 unsigned long out[8];
513 unsigned long r;
514
515 r = epapr_hypercall(in, out, nr);
516 *r2 = out[0];
517
518 return r;
519}
520
521static inline long epapr_hypercall0(unsigned int nr)
522{
523 unsigned long in[8];
524 unsigned long out[8];
525
526 return epapr_hypercall(in, out, nr);
527}
528
529static inline long epapr_hypercall1(unsigned int nr, unsigned long p1)
530{
531 unsigned long in[8];
532 unsigned long out[8];
533
534 in[0] = p1;
535 return epapr_hypercall(in, out, nr);
536}
537
538static inline long epapr_hypercall2(unsigned int nr, unsigned long p1,
539 unsigned long p2)
540{
541 unsigned long in[8];
542 unsigned long out[8];
543
544 in[0] = p1;
545 in[1] = p2;
546 return epapr_hypercall(in, out, nr);
547}
548
549static inline long epapr_hypercall3(unsigned int nr, unsigned long p1,
550 unsigned long p2, unsigned long p3)
551{
552 unsigned long in[8];
553 unsigned long out[8];
554
555 in[0] = p1;
556 in[1] = p2;
557 in[2] = p3;
558 return epapr_hypercall(in, out, nr);
559}
560
561static inline long epapr_hypercall4(unsigned int nr, unsigned long p1,
562 unsigned long p2, unsigned long p3,
563 unsigned long p4)
564{
565 unsigned long in[8];
566 unsigned long out[8];
567
568 in[0] = p1;
569 in[1] = p2;
570 in[2] = p3;
571 in[3] = p4;
572 return epapr_hypercall(in, out, nr);
573}
463#endif /* !__ASSEMBLY__ */ 574#endif /* !__ASSEMBLY__ */
464#endif /* _EPAPR_HCALLS_H */ 575#endif /* _EPAPR_HCALLS_H */
diff --git a/arch/powerpc/include/asm/exception-64s.h b/arch/powerpc/include/asm/exception-64s.h
index 243ce69ad685..66830618cc19 100644
--- a/arch/powerpc/include/asm/exception-64s.h
+++ b/arch/powerpc/include/asm/exception-64s.h
@@ -301,9 +301,12 @@ do_kvm_##n: \
301 beq 4f; /* if from kernel mode */ \ 301 beq 4f; /* if from kernel mode */ \
302 ACCOUNT_CPU_USER_ENTRY(r9, r10); \ 302 ACCOUNT_CPU_USER_ENTRY(r9, r10); \
303 SAVE_PPR(area, r9, r10); \ 303 SAVE_PPR(area, r9, r10); \
3044: std r2,GPR2(r1); /* save r2 in stackframe */ \ 3044: EXCEPTION_PROLOG_COMMON_2(area) \
305 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \ 305 EXCEPTION_PROLOG_COMMON_3(n) \
306 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \ 306 ACCOUNT_STOLEN_TIME
307
308/* Save original regs values from save area to stack frame. */
309#define EXCEPTION_PROLOG_COMMON_2(area) \
307 ld r9,area+EX_R9(r13); /* move r9, r10 to stackframe */ \ 310 ld r9,area+EX_R9(r13); /* move r9, r10 to stackframe */ \
308 ld r10,area+EX_R10(r13); \ 311 ld r10,area+EX_R10(r13); \
309 std r9,GPR9(r1); \ 312 std r9,GPR9(r1); \
@@ -318,11 +321,16 @@ do_kvm_##n: \
318 ld r10,area+EX_CFAR(r13); \ 321 ld r10,area+EX_CFAR(r13); \
319 std r10,ORIG_GPR3(r1); \ 322 std r10,ORIG_GPR3(r1); \
320 END_FTR_SECTION_NESTED(CPU_FTR_CFAR, CPU_FTR_CFAR, 66); \ 323 END_FTR_SECTION_NESTED(CPU_FTR_CFAR, CPU_FTR_CFAR, 66); \
324 GET_CTR(r10, area); \
325 std r10,_CTR(r1);
326
327#define EXCEPTION_PROLOG_COMMON_3(n) \
328 std r2,GPR2(r1); /* save r2 in stackframe */ \
329 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \
330 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \
321 mflr r9; /* Get LR, later save to stack */ \ 331 mflr r9; /* Get LR, later save to stack */ \
322 ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \ 332 ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \
323 std r9,_LINK(r1); \ 333 std r9,_LINK(r1); \
324 GET_CTR(r10, area); \
325 std r10,_CTR(r1); \
326 lbz r10,PACASOFTIRQEN(r13); \ 334 lbz r10,PACASOFTIRQEN(r13); \
327 mfspr r11,SPRN_XER; /* save XER in stackframe */ \ 335 mfspr r11,SPRN_XER; /* save XER in stackframe */ \
328 std r10,SOFTE(r1); \ 336 std r10,SOFTE(r1); \
@@ -332,8 +340,7 @@ do_kvm_##n: \
332 li r10,0; \ 340 li r10,0; \
333 ld r11,exception_marker@toc(r2); \ 341 ld r11,exception_marker@toc(r2); \
334 std r10,RESULT(r1); /* clear regs->result */ \ 342 std r10,RESULT(r1); /* clear regs->result */ \
335 std r11,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */ \ 343 std r11,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */
336 ACCOUNT_STOLEN_TIME
337 344
338/* 345/*
339 * Exception vectors. 346 * Exception vectors.
diff --git a/arch/powerpc/include/asm/fixmap.h b/arch/powerpc/include/asm/fixmap.h
index 5c2c0233175e..90f604bbcd19 100644
--- a/arch/powerpc/include/asm/fixmap.h
+++ b/arch/powerpc/include/asm/fixmap.h
@@ -58,52 +58,12 @@ enum fixed_addresses {
58extern void __set_fixmap (enum fixed_addresses idx, 58extern void __set_fixmap (enum fixed_addresses idx,
59 phys_addr_t phys, pgprot_t flags); 59 phys_addr_t phys, pgprot_t flags);
60 60
61#define set_fixmap(idx, phys) \
62 __set_fixmap(idx, phys, PAGE_KERNEL)
63/*
64 * Some hardware wants to get fixmapped without caching.
65 */
66#define set_fixmap_nocache(idx, phys) \
67 __set_fixmap(idx, phys, PAGE_KERNEL_NCG)
68
69#define clear_fixmap(idx) \
70 __set_fixmap(idx, 0, __pgprot(0))
71
72#define __FIXADDR_SIZE (__end_of_fixed_addresses << PAGE_SHIFT) 61#define __FIXADDR_SIZE (__end_of_fixed_addresses << PAGE_SHIFT)
73#define FIXADDR_START (FIXADDR_TOP - __FIXADDR_SIZE) 62#define FIXADDR_START (FIXADDR_TOP - __FIXADDR_SIZE)
74 63
75#define __fix_to_virt(x) (FIXADDR_TOP - ((x) << PAGE_SHIFT)) 64#define FIXMAP_PAGE_NOCACHE PAGE_KERNEL_NCG
76#define __virt_to_fix(x) ((FIXADDR_TOP - ((x)&PAGE_MASK)) >> PAGE_SHIFT)
77
78extern void __this_fixmap_does_not_exist(void);
79
80/*
81 * 'index to address' translation. If anyone tries to use the idx
82 * directly without tranlation, we catch the bug with a NULL-deference
83 * kernel oops. Illegal ranges of incoming indices are caught too.
84 */
85static __always_inline unsigned long fix_to_virt(const unsigned int idx)
86{
87 /*
88 * this branch gets completely eliminated after inlining,
89 * except when someone tries to use fixaddr indices in an
90 * illegal way. (such as mixing up address types or using
91 * out-of-range indices).
92 *
93 * If it doesn't get removed, the linker will complain
94 * loudly with a reasonably clear error message..
95 */
96 if (idx >= __end_of_fixed_addresses)
97 __this_fixmap_does_not_exist();
98
99 return __fix_to_virt(idx);
100}
101 65
102static inline unsigned long virt_to_fix(const unsigned long vaddr) 66#include <asm-generic/fixmap.h>
103{
104 BUG_ON(vaddr >= FIXADDR_TOP || vaddr < FIXADDR_START);
105 return __virt_to_fix(vaddr);
106}
107 67
108#endif /* !__ASSEMBLY__ */ 68#endif /* !__ASSEMBLY__ */
109#endif 69#endif
diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h
index 420b45368fcf..067fb0dca549 100644
--- a/arch/powerpc/include/asm/fsl_lbc.h
+++ b/arch/powerpc/include/asm/fsl_lbc.h
@@ -285,7 +285,7 @@ struct fsl_lbc_ctrl {
285 /* device info */ 285 /* device info */
286 struct device *dev; 286 struct device *dev;
287 struct fsl_lbc_regs __iomem *regs; 287 struct fsl_lbc_regs __iomem *regs;
288 int irq; 288 int irq[2];
289 wait_queue_head_t irq_wait; 289 wait_queue_head_t irq_wait;
290 spinlock_t lock; 290 spinlock_t lock;
291 void *nand; 291 void *nand;
diff --git a/arch/powerpc/include/asm/hardirq.h b/arch/powerpc/include/asm/hardirq.h
index 3bdcfce2c42a..418fb654370d 100644
--- a/arch/powerpc/include/asm/hardirq.h
+++ b/arch/powerpc/include/asm/hardirq.h
@@ -6,7 +6,8 @@
6 6
7typedef struct { 7typedef struct {
8 unsigned int __softirq_pending; 8 unsigned int __softirq_pending;
9 unsigned int timer_irqs; 9 unsigned int timer_irqs_event;
10 unsigned int timer_irqs_others;
10 unsigned int pmu_irqs; 11 unsigned int pmu_irqs;
11 unsigned int mce_exceptions; 12 unsigned int mce_exceptions;
12 unsigned int spurious_irqs; 13 unsigned int spurious_irqs;
diff --git a/arch/powerpc/include/asm/hugetlb.h b/arch/powerpc/include/asm/hugetlb.h
index d750336b171d..623f2971ce0e 100644
--- a/arch/powerpc/include/asm/hugetlb.h
+++ b/arch/powerpc/include/asm/hugetlb.h
@@ -127,7 +127,7 @@ static inline pte_t huge_ptep_get_and_clear(struct mm_struct *mm,
127 unsigned long addr, pte_t *ptep) 127 unsigned long addr, pte_t *ptep)
128{ 128{
129#ifdef CONFIG_PPC64 129#ifdef CONFIG_PPC64
130 return __pte(pte_update(mm, addr, ptep, ~0UL, 1)); 130 return __pte(pte_update(mm, addr, ptep, ~0UL, 0, 1));
131#else 131#else
132 return __pte(pte_update(ptep, ~0UL, 0)); 132 return __pte(pte_update(ptep, ~0UL, 0));
133#endif 133#endif
diff --git a/arch/powerpc/include/asm/io.h b/arch/powerpc/include/asm/io.h
index 575fbf81fad0..97d3869991ca 100644
--- a/arch/powerpc/include/asm/io.h
+++ b/arch/powerpc/include/asm/io.h
@@ -191,8 +191,24 @@ DEF_MMIO_OUT_D(out_le32, 32, stw);
191 191
192#endif /* __BIG_ENDIAN */ 192#endif /* __BIG_ENDIAN */
193 193
194/*
195 * Cache inhibitied accessors for use in real mode, you don't want to use these
196 * unless you know what you're doing.
197 *
198 * NB. These use the cpu byte ordering.
199 */
200DEF_MMIO_OUT_X(out_rm8, 8, stbcix);
201DEF_MMIO_OUT_X(out_rm16, 16, sthcix);
202DEF_MMIO_OUT_X(out_rm32, 32, stwcix);
203DEF_MMIO_IN_X(in_rm8, 8, lbzcix);
204DEF_MMIO_IN_X(in_rm16, 16, lhzcix);
205DEF_MMIO_IN_X(in_rm32, 32, lwzcix);
206
194#ifdef __powerpc64__ 207#ifdef __powerpc64__
195 208
209DEF_MMIO_OUT_X(out_rm64, 64, stdcix);
210DEF_MMIO_IN_X(in_rm64, 64, ldcix);
211
196#ifdef __BIG_ENDIAN__ 212#ifdef __BIG_ENDIAN__
197DEF_MMIO_OUT_D(out_be64, 64, std); 213DEF_MMIO_OUT_D(out_be64, 64, std);
198DEF_MMIO_IN_D(in_be64, 64, ld); 214DEF_MMIO_IN_D(in_be64, 64, ld);
diff --git a/arch/powerpc/include/asm/iommu.h b/arch/powerpc/include/asm/iommu.h
index c34656a8925e..42632c7a2a4e 100644
--- a/arch/powerpc/include/asm/iommu.h
+++ b/arch/powerpc/include/asm/iommu.h
@@ -30,22 +30,19 @@
30#include <asm/machdep.h> 30#include <asm/machdep.h>
31#include <asm/types.h> 31#include <asm/types.h>
32 32
33#define IOMMU_PAGE_SHIFT 12 33#define IOMMU_PAGE_SHIFT_4K 12
34#define IOMMU_PAGE_SIZE (ASM_CONST(1) << IOMMU_PAGE_SHIFT) 34#define IOMMU_PAGE_SIZE_4K (ASM_CONST(1) << IOMMU_PAGE_SHIFT_4K)
35#define IOMMU_PAGE_MASK (~((1 << IOMMU_PAGE_SHIFT) - 1)) 35#define IOMMU_PAGE_MASK_4K (~((1 << IOMMU_PAGE_SHIFT_4K) - 1))
36#define IOMMU_PAGE_ALIGN(addr) _ALIGN_UP(addr, IOMMU_PAGE_SIZE) 36#define IOMMU_PAGE_ALIGN_4K(addr) _ALIGN_UP(addr, IOMMU_PAGE_SIZE_4K)
37
38#define IOMMU_PAGE_SIZE(tblptr) (ASM_CONST(1) << (tblptr)->it_page_shift)
39#define IOMMU_PAGE_MASK(tblptr) (~((1 << (tblptr)->it_page_shift) - 1))
40#define IOMMU_PAGE_ALIGN(addr, tblptr) _ALIGN_UP(addr, IOMMU_PAGE_SIZE(tblptr))
37 41
38/* Boot time flags */ 42/* Boot time flags */
39extern int iommu_is_off; 43extern int iommu_is_off;
40extern int iommu_force_on; 44extern int iommu_force_on;
41 45
42/* Pure 2^n version of get_order */
43static __inline__ __attribute_const__ int get_iommu_order(unsigned long size)
44{
45 return __ilog2((size - 1) >> IOMMU_PAGE_SHIFT) + 1;
46}
47
48
49/* 46/*
50 * IOMAP_MAX_ORDER defines the largest contiguous block 47 * IOMAP_MAX_ORDER defines the largest contiguous block
51 * of dma space we can get. IOMAP_MAX_ORDER = 13 48 * of dma space we can get. IOMAP_MAX_ORDER = 13
@@ -76,11 +73,21 @@ struct iommu_table {
76 struct iommu_pool large_pool; 73 struct iommu_pool large_pool;
77 struct iommu_pool pools[IOMMU_NR_POOLS]; 74 struct iommu_pool pools[IOMMU_NR_POOLS];
78 unsigned long *it_map; /* A simple allocation bitmap for now */ 75 unsigned long *it_map; /* A simple allocation bitmap for now */
76 unsigned long it_page_shift;/* table iommu page size */
79#ifdef CONFIG_IOMMU_API 77#ifdef CONFIG_IOMMU_API
80 struct iommu_group *it_group; 78 struct iommu_group *it_group;
81#endif 79#endif
80 void (*set_bypass)(struct iommu_table *tbl, bool enable);
82}; 81};
83 82
83/* Pure 2^n version of get_order */
84static inline __attribute_const__
85int get_iommu_order(unsigned long size, struct iommu_table *tbl)
86{
87 return __ilog2((size - 1) >> tbl->it_page_shift) + 1;
88}
89
90
84struct scatterlist; 91struct scatterlist;
85 92
86static inline void set_iommu_table_base(struct device *dev, void *base) 93static inline void set_iommu_table_base(struct device *dev, void *base)
@@ -101,8 +108,34 @@ extern void iommu_free_table(struct iommu_table *tbl, const char *node_name);
101 */ 108 */
102extern struct iommu_table *iommu_init_table(struct iommu_table * tbl, 109extern struct iommu_table *iommu_init_table(struct iommu_table * tbl,
103 int nid); 110 int nid);
111#ifdef CONFIG_IOMMU_API
104extern void iommu_register_group(struct iommu_table *tbl, 112extern void iommu_register_group(struct iommu_table *tbl,
105 int pci_domain_number, unsigned long pe_num); 113 int pci_domain_number, unsigned long pe_num);
114extern int iommu_add_device(struct device *dev);
115extern void iommu_del_device(struct device *dev);
116#else
117static inline void iommu_register_group(struct iommu_table *tbl,
118 int pci_domain_number,
119 unsigned long pe_num)
120{
121}
122
123static inline int iommu_add_device(struct device *dev)
124{
125 return 0;
126}
127
128static inline void iommu_del_device(struct device *dev)
129{
130}
131#endif /* !CONFIG_IOMMU_API */
132
133static inline void set_iommu_table_base_and_group(struct device *dev,
134 void *base)
135{
136 set_iommu_table_base(dev, base);
137 iommu_add_device(dev);
138}
106 139
107extern int iommu_map_sg(struct device *dev, struct iommu_table *tbl, 140extern int iommu_map_sg(struct device *dev, struct iommu_table *tbl,
108 struct scatterlist *sglist, int nelems, 141 struct scatterlist *sglist, int nelems,
diff --git a/arch/powerpc/include/asm/kvm_asm.h b/arch/powerpc/include/asm/kvm_asm.h
index 1bd92fd43cfb..19eb74a95b59 100644
--- a/arch/powerpc/include/asm/kvm_asm.h
+++ b/arch/powerpc/include/asm/kvm_asm.h
@@ -74,6 +74,7 @@
74#define BOOKE_INTERRUPT_GUEST_DBELL_CRIT 39 74#define BOOKE_INTERRUPT_GUEST_DBELL_CRIT 39
75#define BOOKE_INTERRUPT_HV_SYSCALL 40 75#define BOOKE_INTERRUPT_HV_SYSCALL 40
76#define BOOKE_INTERRUPT_HV_PRIV 41 76#define BOOKE_INTERRUPT_HV_PRIV 41
77#define BOOKE_INTERRUPT_LRAT_ERROR 42
77 78
78/* book3s */ 79/* book3s */
79 80
@@ -91,14 +92,17 @@
91#define BOOK3S_INTERRUPT_FP_UNAVAIL 0x800 92#define BOOK3S_INTERRUPT_FP_UNAVAIL 0x800
92#define BOOK3S_INTERRUPT_DECREMENTER 0x900 93#define BOOK3S_INTERRUPT_DECREMENTER 0x900
93#define BOOK3S_INTERRUPT_HV_DECREMENTER 0x980 94#define BOOK3S_INTERRUPT_HV_DECREMENTER 0x980
95#define BOOK3S_INTERRUPT_DOORBELL 0xa00
94#define BOOK3S_INTERRUPT_SYSCALL 0xc00 96#define BOOK3S_INTERRUPT_SYSCALL 0xc00
95#define BOOK3S_INTERRUPT_TRACE 0xd00 97#define BOOK3S_INTERRUPT_TRACE 0xd00
96#define BOOK3S_INTERRUPT_H_DATA_STORAGE 0xe00 98#define BOOK3S_INTERRUPT_H_DATA_STORAGE 0xe00
97#define BOOK3S_INTERRUPT_H_INST_STORAGE 0xe20 99#define BOOK3S_INTERRUPT_H_INST_STORAGE 0xe20
98#define BOOK3S_INTERRUPT_H_EMUL_ASSIST 0xe40 100#define BOOK3S_INTERRUPT_H_EMUL_ASSIST 0xe40
101#define BOOK3S_INTERRUPT_H_DOORBELL 0xe80
99#define BOOK3S_INTERRUPT_PERFMON 0xf00 102#define BOOK3S_INTERRUPT_PERFMON 0xf00
100#define BOOK3S_INTERRUPT_ALTIVEC 0xf20 103#define BOOK3S_INTERRUPT_ALTIVEC 0xf20
101#define BOOK3S_INTERRUPT_VSX 0xf40 104#define BOOK3S_INTERRUPT_VSX 0xf40
105#define BOOK3S_INTERRUPT_H_FAC_UNAVAIL 0xf80
102 106
103#define BOOK3S_IRQPRIO_SYSTEM_RESET 0 107#define BOOK3S_IRQPRIO_SYSTEM_RESET 0
104#define BOOK3S_IRQPRIO_DATA_SEGMENT 1 108#define BOOK3S_IRQPRIO_DATA_SEGMENT 1
diff --git a/arch/powerpc/include/asm/kvm_book3s.h b/arch/powerpc/include/asm/kvm_book3s.h
index bc23b1ba7980..83851aabfdc8 100644
--- a/arch/powerpc/include/asm/kvm_book3s.h
+++ b/arch/powerpc/include/asm/kvm_book3s.h
@@ -186,9 +186,6 @@ extern void kvmppc_update_lpcr(struct kvm *kvm, unsigned long lpcr,
186 186
187extern void kvmppc_entry_trampoline(void); 187extern void kvmppc_entry_trampoline(void);
188extern void kvmppc_hv_entry_trampoline(void); 188extern void kvmppc_hv_entry_trampoline(void);
189extern void kvmppc_load_up_fpu(void);
190extern void kvmppc_load_up_altivec(void);
191extern void kvmppc_load_up_vsx(void);
192extern u32 kvmppc_alignment_dsisr(struct kvm_vcpu *vcpu, unsigned int inst); 189extern u32 kvmppc_alignment_dsisr(struct kvm_vcpu *vcpu, unsigned int inst);
193extern ulong kvmppc_alignment_dar(struct kvm_vcpu *vcpu, unsigned int inst); 190extern ulong kvmppc_alignment_dar(struct kvm_vcpu *vcpu, unsigned int inst);
194extern int kvmppc_h_pr(struct kvm_vcpu *vcpu, unsigned long cmd); 191extern int kvmppc_h_pr(struct kvm_vcpu *vcpu, unsigned long cmd);
@@ -271,16 +268,25 @@ static inline ulong kvmppc_get_pc(struct kvm_vcpu *vcpu)
271 return vcpu->arch.pc; 268 return vcpu->arch.pc;
272} 269}
273 270
274static inline u32 kvmppc_get_last_inst(struct kvm_vcpu *vcpu) 271static inline bool kvmppc_need_byteswap(struct kvm_vcpu *vcpu)
275{ 272{
276 ulong pc = kvmppc_get_pc(vcpu); 273 return (vcpu->arch.shared->msr & MSR_LE) != (MSR_KERNEL & MSR_LE);
274}
277 275
276static inline u32 kvmppc_get_last_inst_internal(struct kvm_vcpu *vcpu, ulong pc)
277{
278 /* Load the instruction manually if it failed to do so in the 278 /* Load the instruction manually if it failed to do so in the
279 * exit path */ 279 * exit path */
280 if (vcpu->arch.last_inst == KVM_INST_FETCH_FAILED) 280 if (vcpu->arch.last_inst == KVM_INST_FETCH_FAILED)
281 kvmppc_ld(vcpu, &pc, sizeof(u32), &vcpu->arch.last_inst, false); 281 kvmppc_ld(vcpu, &pc, sizeof(u32), &vcpu->arch.last_inst, false);
282 282
283 return vcpu->arch.last_inst; 283 return kvmppc_need_byteswap(vcpu) ? swab32(vcpu->arch.last_inst) :
284 vcpu->arch.last_inst;
285}
286
287static inline u32 kvmppc_get_last_inst(struct kvm_vcpu *vcpu)
288{
289 return kvmppc_get_last_inst_internal(vcpu, kvmppc_get_pc(vcpu));
284} 290}
285 291
286/* 292/*
@@ -290,14 +296,7 @@ static inline u32 kvmppc_get_last_inst(struct kvm_vcpu *vcpu)
290 */ 296 */
291static inline u32 kvmppc_get_last_sc(struct kvm_vcpu *vcpu) 297static inline u32 kvmppc_get_last_sc(struct kvm_vcpu *vcpu)
292{ 298{
293 ulong pc = kvmppc_get_pc(vcpu) - 4; 299 return kvmppc_get_last_inst_internal(vcpu, kvmppc_get_pc(vcpu) - 4);
294
295 /* Load the instruction manually if it failed to do so in the
296 * exit path */
297 if (vcpu->arch.last_inst == KVM_INST_FETCH_FAILED)
298 kvmppc_ld(vcpu, &pc, sizeof(u32), &vcpu->arch.last_inst, false);
299
300 return vcpu->arch.last_inst;
301} 300}
302 301
303static inline ulong kvmppc_get_fault_dar(struct kvm_vcpu *vcpu) 302static inline ulong kvmppc_get_fault_dar(struct kvm_vcpu *vcpu)
diff --git a/arch/powerpc/include/asm/kvm_book3s_asm.h b/arch/powerpc/include/asm/kvm_book3s_asm.h
index 192917d2239c..f3a91dc02c98 100644
--- a/arch/powerpc/include/asm/kvm_book3s_asm.h
+++ b/arch/powerpc/include/asm/kvm_book3s_asm.h
@@ -88,6 +88,7 @@ struct kvmppc_host_state {
88 u8 hwthread_req; 88 u8 hwthread_req;
89 u8 hwthread_state; 89 u8 hwthread_state;
90 u8 host_ipi; 90 u8 host_ipi;
91 u8 ptid;
91 struct kvm_vcpu *kvm_vcpu; 92 struct kvm_vcpu *kvm_vcpu;
92 struct kvmppc_vcore *kvm_vcore; 93 struct kvmppc_vcore *kvm_vcore;
93 unsigned long xics_phys; 94 unsigned long xics_phys;
diff --git a/arch/powerpc/include/asm/kvm_booke.h b/arch/powerpc/include/asm/kvm_booke.h
index dd8f61510dfd..80d46b5a7efb 100644
--- a/arch/powerpc/include/asm/kvm_booke.h
+++ b/arch/powerpc/include/asm/kvm_booke.h
@@ -63,6 +63,12 @@ static inline u32 kvmppc_get_xer(struct kvm_vcpu *vcpu)
63 return vcpu->arch.xer; 63 return vcpu->arch.xer;
64} 64}
65 65
66static inline bool kvmppc_need_byteswap(struct kvm_vcpu *vcpu)
67{
68 /* XXX Would need to check TLB entry */
69 return false;
70}
71
66static inline u32 kvmppc_get_last_inst(struct kvm_vcpu *vcpu) 72static inline u32 kvmppc_get_last_inst(struct kvm_vcpu *vcpu)
67{ 73{
68 return vcpu->arch.last_inst; 74 return vcpu->arch.last_inst;
diff --git a/arch/powerpc/include/asm/kvm_host.h b/arch/powerpc/include/asm/kvm_host.h
index 237d1d25b448..1eaea2dea174 100644
--- a/arch/powerpc/include/asm/kvm_host.h
+++ b/arch/powerpc/include/asm/kvm_host.h
@@ -288,6 +288,7 @@ struct kvmppc_vcore {
288 int n_woken; 288 int n_woken;
289 int nap_count; 289 int nap_count;
290 int napping_threads; 290 int napping_threads;
291 int first_vcpuid;
291 u16 pcpu; 292 u16 pcpu;
292 u16 last_cpu; 293 u16 last_cpu;
293 u8 vcore_state; 294 u8 vcore_state;
@@ -298,10 +299,12 @@ struct kvmppc_vcore {
298 u64 stolen_tb; 299 u64 stolen_tb;
299 u64 preempt_tb; 300 u64 preempt_tb;
300 struct kvm_vcpu *runner; 301 struct kvm_vcpu *runner;
302 struct kvm *kvm;
301 u64 tb_offset; /* guest timebase - host timebase */ 303 u64 tb_offset; /* guest timebase - host timebase */
302 ulong lpcr; 304 ulong lpcr;
303 u32 arch_compat; 305 u32 arch_compat;
304 ulong pcr; 306 ulong pcr;
307 ulong dpdes; /* doorbell state (POWER8) */
305}; 308};
306 309
307#define VCORE_ENTRY_COUNT(vc) ((vc)->entry_exit_count & 0xff) 310#define VCORE_ENTRY_COUNT(vc) ((vc)->entry_exit_count & 0xff)
@@ -410,8 +413,7 @@ struct kvm_vcpu_arch {
410 413
411 ulong gpr[32]; 414 ulong gpr[32];
412 415
413 u64 fpr[32]; 416 struct thread_fp_state fp;
414 u64 fpscr;
415 417
416#ifdef CONFIG_SPE 418#ifdef CONFIG_SPE
417 ulong evr[32]; 419 ulong evr[32];
@@ -420,12 +422,7 @@ struct kvm_vcpu_arch {
420 u64 acc; 422 u64 acc;
421#endif 423#endif
422#ifdef CONFIG_ALTIVEC 424#ifdef CONFIG_ALTIVEC
423 vector128 vr[32]; 425 struct thread_vr_state vr;
424 vector128 vscr;
425#endif
426
427#ifdef CONFIG_VSX
428 u64 vsr[64];
429#endif 426#endif
430 427
431#ifdef CONFIG_KVM_BOOKE_HV 428#ifdef CONFIG_KVM_BOOKE_HV
@@ -452,6 +449,7 @@ struct kvm_vcpu_arch {
452 ulong pc; 449 ulong pc;
453 ulong ctr; 450 ulong ctr;
454 ulong lr; 451 ulong lr;
452 ulong tar;
455 453
456 ulong xer; 454 ulong xer;
457 u32 cr; 455 u32 cr;
@@ -461,13 +459,30 @@ struct kvm_vcpu_arch {
461 ulong guest_owned_ext; 459 ulong guest_owned_ext;
462 ulong purr; 460 ulong purr;
463 ulong spurr; 461 ulong spurr;
462 ulong ic;
463 ulong vtb;
464 ulong dscr; 464 ulong dscr;
465 ulong amr; 465 ulong amr;
466 ulong uamor; 466 ulong uamor;
467 ulong iamr;
467 u32 ctrl; 468 u32 ctrl;
469 u32 dabrx;
468 ulong dabr; 470 ulong dabr;
471 ulong dawr;
472 ulong dawrx;
473 ulong ciabr;
469 ulong cfar; 474 ulong cfar;
470 ulong ppr; 475 ulong ppr;
476 ulong pspb;
477 ulong fscr;
478 ulong ebbhr;
479 ulong ebbrr;
480 ulong bescr;
481 ulong csigr;
482 ulong tacr;
483 ulong tcscr;
484 ulong acop;
485 ulong wort;
471 ulong shadow_srr1; 486 ulong shadow_srr1;
472#endif 487#endif
473 u32 vrsave; /* also USPRG0 */ 488 u32 vrsave; /* also USPRG0 */
@@ -502,10 +517,33 @@ struct kvm_vcpu_arch {
502 u32 ccr1; 517 u32 ccr1;
503 u32 dbsr; 518 u32 dbsr;
504 519
505 u64 mmcr[3]; 520 u64 mmcr[5];
506 u32 pmc[8]; 521 u32 pmc[8];
522 u32 spmc[2];
507 u64 siar; 523 u64 siar;
508 u64 sdar; 524 u64 sdar;
525 u64 sier;
526#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
527 u64 tfhar;
528 u64 texasr;
529 u64 tfiar;
530
531 u32 cr_tm;
532 u64 lr_tm;
533 u64 ctr_tm;
534 u64 amr_tm;
535 u64 ppr_tm;
536 u64 dscr_tm;
537 u64 tar_tm;
538
539 ulong gpr_tm[32];
540
541 struct thread_fp_state fp_tm;
542
543 struct thread_vr_state vr_tm;
544 u32 vrsave_tm; /* also USPRG0 */
545
546#endif
509 547
510#ifdef CONFIG_KVM_EXIT_TIMING 548#ifdef CONFIG_KVM_EXIT_TIMING
511 struct mutex exit_timing_lock; 549 struct mutex exit_timing_lock;
@@ -546,6 +584,7 @@ struct kvm_vcpu_arch {
546#endif 584#endif
547 gpa_t paddr_accessed; 585 gpa_t paddr_accessed;
548 gva_t vaddr_accessed; 586 gva_t vaddr_accessed;
587 pgd_t *pgdir;
549 588
550 u8 io_gpr; /* GPR used as IO source/target */ 589 u8 io_gpr; /* GPR used as IO source/target */
551 u8 mmio_is_bigendian; 590 u8 mmio_is_bigendian;
@@ -603,7 +642,6 @@ struct kvm_vcpu_arch {
603 struct list_head run_list; 642 struct list_head run_list;
604 struct task_struct *run_task; 643 struct task_struct *run_task;
605 struct kvm_run *kvm_run; 644 struct kvm_run *kvm_run;
606 pgd_t *pgdir;
607 645
608 spinlock_t vpa_update_lock; 646 spinlock_t vpa_update_lock;
609 struct kvmppc_vpa vpa; 647 struct kvmppc_vpa vpa;
@@ -616,9 +654,12 @@ struct kvm_vcpu_arch {
616 spinlock_t tbacct_lock; 654 spinlock_t tbacct_lock;
617 u64 busy_stolen; 655 u64 busy_stolen;
618 u64 busy_preempt; 656 u64 busy_preempt;
657 unsigned long intr_msr;
619#endif 658#endif
620}; 659};
621 660
661#define VCPU_FPR(vcpu, i) (vcpu)->arch.fp.fpr[i][TS_FPROFFSET]
662
622/* Values for vcpu->arch.state */ 663/* Values for vcpu->arch.state */
623#define KVMPPC_VCPU_NOTREADY 0 664#define KVMPPC_VCPU_NOTREADY 0
624#define KVMPPC_VCPU_RUNNABLE 1 665#define KVMPPC_VCPU_RUNNABLE 1
diff --git a/arch/powerpc/include/asm/kvm_para.h b/arch/powerpc/include/asm/kvm_para.h
index 2b119654b4c1..336a91acb8b1 100644
--- a/arch/powerpc/include/asm/kvm_para.h
+++ b/arch/powerpc/include/asm/kvm_para.h
@@ -39,10 +39,6 @@ static inline int kvm_para_available(void)
39 return 1; 39 return 1;
40} 40}
41 41
42extern unsigned long kvm_hypercall(unsigned long *in,
43 unsigned long *out,
44 unsigned long nr);
45
46#else 42#else
47 43
48static inline int kvm_para_available(void) 44static inline int kvm_para_available(void)
@@ -50,82 +46,8 @@ static inline int kvm_para_available(void)
50 return 0; 46 return 0;
51} 47}
52 48
53static unsigned long kvm_hypercall(unsigned long *in,
54 unsigned long *out,
55 unsigned long nr)
56{
57 return EV_UNIMPLEMENTED;
58}
59
60#endif 49#endif
61 50
62static inline long kvm_hypercall0_1(unsigned int nr, unsigned long *r2)
63{
64 unsigned long in[8];
65 unsigned long out[8];
66 unsigned long r;
67
68 r = kvm_hypercall(in, out, KVM_HCALL_TOKEN(nr));
69 *r2 = out[0];
70
71 return r;
72}
73
74static inline long kvm_hypercall0(unsigned int nr)
75{
76 unsigned long in[8];
77 unsigned long out[8];
78
79 return kvm_hypercall(in, out, KVM_HCALL_TOKEN(nr));
80}
81
82static inline long kvm_hypercall1(unsigned int nr, unsigned long p1)
83{
84 unsigned long in[8];
85 unsigned long out[8];
86
87 in[0] = p1;
88 return kvm_hypercall(in, out, KVM_HCALL_TOKEN(nr));
89}
90
91static inline long kvm_hypercall2(unsigned int nr, unsigned long p1,
92 unsigned long p2)
93{
94 unsigned long in[8];
95 unsigned long out[8];
96
97 in[0] = p1;
98 in[1] = p2;
99 return kvm_hypercall(in, out, KVM_HCALL_TOKEN(nr));
100}
101
102static inline long kvm_hypercall3(unsigned int nr, unsigned long p1,
103 unsigned long p2, unsigned long p3)
104{
105 unsigned long in[8];
106 unsigned long out[8];
107
108 in[0] = p1;
109 in[1] = p2;
110 in[2] = p3;
111 return kvm_hypercall(in, out, KVM_HCALL_TOKEN(nr));
112}
113
114static inline long kvm_hypercall4(unsigned int nr, unsigned long p1,
115 unsigned long p2, unsigned long p3,
116 unsigned long p4)
117{
118 unsigned long in[8];
119 unsigned long out[8];
120
121 in[0] = p1;
122 in[1] = p2;
123 in[2] = p3;
124 in[3] = p4;
125 return kvm_hypercall(in, out, KVM_HCALL_TOKEN(nr));
126}
127
128
129static inline unsigned int kvm_arch_para_features(void) 51static inline unsigned int kvm_arch_para_features(void)
130{ 52{
131 unsigned long r; 53 unsigned long r;
@@ -133,7 +55,7 @@ static inline unsigned int kvm_arch_para_features(void)
133 if (!kvm_para_available()) 55 if (!kvm_para_available())
134 return 0; 56 return 0;
135 57
136 if(kvm_hypercall0_1(KVM_HC_FEATURES, &r)) 58 if(epapr_hypercall0_1(KVM_HCALL_TOKEN(KVM_HC_FEATURES), &r))
137 return 0; 59 return 0;
138 60
139 return r; 61 return r;
diff --git a/arch/powerpc/include/asm/kvm_ppc.h b/arch/powerpc/include/asm/kvm_ppc.h
index c8317fbf92c4..fcd53f0d34ba 100644
--- a/arch/powerpc/include/asm/kvm_ppc.h
+++ b/arch/powerpc/include/asm/kvm_ppc.h
@@ -54,12 +54,13 @@ extern void kvmppc_handler_highmem(void);
54extern void kvmppc_dump_vcpu(struct kvm_vcpu *vcpu); 54extern void kvmppc_dump_vcpu(struct kvm_vcpu *vcpu);
55extern int kvmppc_handle_load(struct kvm_run *run, struct kvm_vcpu *vcpu, 55extern int kvmppc_handle_load(struct kvm_run *run, struct kvm_vcpu *vcpu,
56 unsigned int rt, unsigned int bytes, 56 unsigned int rt, unsigned int bytes,
57 int is_bigendian); 57 int is_default_endian);
58extern int kvmppc_handle_loads(struct kvm_run *run, struct kvm_vcpu *vcpu, 58extern int kvmppc_handle_loads(struct kvm_run *run, struct kvm_vcpu *vcpu,
59 unsigned int rt, unsigned int bytes, 59 unsigned int rt, unsigned int bytes,
60 int is_bigendian); 60 int is_default_endian);
61extern int kvmppc_handle_store(struct kvm_run *run, struct kvm_vcpu *vcpu, 61extern int kvmppc_handle_store(struct kvm_run *run, struct kvm_vcpu *vcpu,
62 u64 val, unsigned int bytes, int is_bigendian); 62 u64 val, unsigned int bytes,
63 int is_default_endian);
63 64
64extern int kvmppc_emulate_instruction(struct kvm_run *run, 65extern int kvmppc_emulate_instruction(struct kvm_run *run,
65 struct kvm_vcpu *vcpu); 66 struct kvm_vcpu *vcpu);
@@ -455,6 +456,12 @@ static inline void kvmppc_fix_ee_before_entry(void)
455 trace_hardirqs_on(); 456 trace_hardirqs_on();
456 457
457#ifdef CONFIG_PPC64 458#ifdef CONFIG_PPC64
459 /*
460 * To avoid races, the caller must have gone directly from having
461 * interrupts fully-enabled to hard-disabled.
462 */
463 WARN_ON(local_paca->irq_happened != PACA_IRQ_HARD_DIS);
464
458 /* Only need to enable IRQs by hard enabling them after this */ 465 /* Only need to enable IRQs by hard enabling them after this */
459 local_paca->irq_happened = 0; 466 local_paca->irq_happened = 0;
460 local_paca->soft_enabled = 1; 467 local_paca->soft_enabled = 1;
diff --git a/arch/powerpc/include/asm/lppaca.h b/arch/powerpc/include/asm/lppaca.h
index 844c28de7ec0..d0a2a2f99564 100644
--- a/arch/powerpc/include/asm/lppaca.h
+++ b/arch/powerpc/include/asm/lppaca.h
@@ -132,8 +132,6 @@ struct slb_shadow {
132 } save_area[SLB_NUM_BOLTED]; 132 } save_area[SLB_NUM_BOLTED];
133} ____cacheline_aligned; 133} ____cacheline_aligned;
134 134
135extern struct slb_shadow slb_shadow[];
136
137/* 135/*
138 * Layout of entries in the hypervisor's dispatch trace log buffer. 136 * Layout of entries in the hypervisor's dispatch trace log buffer.
139 */ 137 */
diff --git a/arch/powerpc/include/asm/mce.h b/arch/powerpc/include/asm/mce.h
new file mode 100644
index 000000000000..8e99edf6d966
--- /dev/null
+++ b/arch/powerpc/include/asm/mce.h
@@ -0,0 +1,197 @@
1/*
2 * Machine check exception header file.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 *
18 * Copyright 2013 IBM Corporation
19 * Author: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com>
20 */
21
22#ifndef __ASM_PPC64_MCE_H__
23#define __ASM_PPC64_MCE_H__
24
25#include <linux/bitops.h>
26
27/*
28 * Machine Check bits on power7 and power8
29 */
30#define P7_SRR1_MC_LOADSTORE(srr1) ((srr1) & PPC_BIT(42)) /* P8 too */
31
32/* SRR1 bits for machine check (On Power7 and Power8) */
33#define P7_SRR1_MC_IFETCH(srr1) ((srr1) & PPC_BITMASK(43, 45)) /* P8 too */
34
35#define P7_SRR1_MC_IFETCH_UE (0x1 << PPC_BITLSHIFT(45)) /* P8 too */
36#define P7_SRR1_MC_IFETCH_SLB_PARITY (0x2 << PPC_BITLSHIFT(45)) /* P8 too */
37#define P7_SRR1_MC_IFETCH_SLB_MULTIHIT (0x3 << PPC_BITLSHIFT(45)) /* P8 too */
38#define P7_SRR1_MC_IFETCH_SLB_BOTH (0x4 << PPC_BITLSHIFT(45))
39#define P7_SRR1_MC_IFETCH_TLB_MULTIHIT (0x5 << PPC_BITLSHIFT(45)) /* P8 too */
40#define P7_SRR1_MC_IFETCH_UE_TLB_RELOAD (0x6 << PPC_BITLSHIFT(45)) /* P8 too */
41#define P7_SRR1_MC_IFETCH_UE_IFU_INTERNAL (0x7 << PPC_BITLSHIFT(45))
42
43/* SRR1 bits for machine check (On Power8) */
44#define P8_SRR1_MC_IFETCH_ERAT_MULTIHIT (0x4 << PPC_BITLSHIFT(45))
45
46/* DSISR bits for machine check (On Power7 and Power8) */
47#define P7_DSISR_MC_UE (PPC_BIT(48)) /* P8 too */
48#define P7_DSISR_MC_UE_TABLEWALK (PPC_BIT(49)) /* P8 too */
49#define P7_DSISR_MC_ERAT_MULTIHIT (PPC_BIT(52)) /* P8 too */
50#define P7_DSISR_MC_TLB_MULTIHIT_MFTLB (PPC_BIT(53)) /* P8 too */
51#define P7_DSISR_MC_SLB_PARITY_MFSLB (PPC_BIT(55)) /* P8 too */
52#define P7_DSISR_MC_SLB_MULTIHIT (PPC_BIT(56)) /* P8 too */
53#define P7_DSISR_MC_SLB_MULTIHIT_PARITY (PPC_BIT(57)) /* P8 too */
54
55/*
56 * DSISR bits for machine check (Power8) in addition to above.
57 * Secondary DERAT Multihit
58 */
59#define P8_DSISR_MC_ERAT_MULTIHIT_SEC (PPC_BIT(54))
60
61/* SLB error bits */
62#define P7_DSISR_MC_SLB_ERRORS (P7_DSISR_MC_ERAT_MULTIHIT | \
63 P7_DSISR_MC_SLB_PARITY_MFSLB | \
64 P7_DSISR_MC_SLB_MULTIHIT | \
65 P7_DSISR_MC_SLB_MULTIHIT_PARITY)
66
67#define P8_DSISR_MC_SLB_ERRORS (P7_DSISR_MC_SLB_ERRORS | \
68 P8_DSISR_MC_ERAT_MULTIHIT_SEC)
69enum MCE_Version {
70 MCE_V1 = 1,
71};
72
73enum MCE_Severity {
74 MCE_SEV_NO_ERROR = 0,
75 MCE_SEV_WARNING = 1,
76 MCE_SEV_ERROR_SYNC = 2,
77 MCE_SEV_FATAL = 3,
78};
79
80enum MCE_Disposition {
81 MCE_DISPOSITION_RECOVERED = 0,
82 MCE_DISPOSITION_NOT_RECOVERED = 1,
83};
84
85enum MCE_Initiator {
86 MCE_INITIATOR_UNKNOWN = 0,
87 MCE_INITIATOR_CPU = 1,
88};
89
90enum MCE_ErrorType {
91 MCE_ERROR_TYPE_UNKNOWN = 0,
92 MCE_ERROR_TYPE_UE = 1,
93 MCE_ERROR_TYPE_SLB = 2,
94 MCE_ERROR_TYPE_ERAT = 3,
95 MCE_ERROR_TYPE_TLB = 4,
96};
97
98enum MCE_UeErrorType {
99 MCE_UE_ERROR_INDETERMINATE = 0,
100 MCE_UE_ERROR_IFETCH = 1,
101 MCE_UE_ERROR_PAGE_TABLE_WALK_IFETCH = 2,
102 MCE_UE_ERROR_LOAD_STORE = 3,
103 MCE_UE_ERROR_PAGE_TABLE_WALK_LOAD_STORE = 4,
104};
105
106enum MCE_SlbErrorType {
107 MCE_SLB_ERROR_INDETERMINATE = 0,
108 MCE_SLB_ERROR_PARITY = 1,
109 MCE_SLB_ERROR_MULTIHIT = 2,
110};
111
112enum MCE_EratErrorType {
113 MCE_ERAT_ERROR_INDETERMINATE = 0,
114 MCE_ERAT_ERROR_PARITY = 1,
115 MCE_ERAT_ERROR_MULTIHIT = 2,
116};
117
118enum MCE_TlbErrorType {
119 MCE_TLB_ERROR_INDETERMINATE = 0,
120 MCE_TLB_ERROR_PARITY = 1,
121 MCE_TLB_ERROR_MULTIHIT = 2,
122};
123
124struct machine_check_event {
125 enum MCE_Version version:8; /* 0x00 */
126 uint8_t in_use; /* 0x01 */
127 enum MCE_Severity severity:8; /* 0x02 */
128 enum MCE_Initiator initiator:8; /* 0x03 */
129 enum MCE_ErrorType error_type:8; /* 0x04 */
130 enum MCE_Disposition disposition:8; /* 0x05 */
131 uint8_t reserved_1[2]; /* 0x06 */
132 uint64_t gpr3; /* 0x08 */
133 uint64_t srr0; /* 0x10 */
134 uint64_t srr1; /* 0x18 */
135 union { /* 0x20 */
136 struct {
137 enum MCE_UeErrorType ue_error_type:8;
138 uint8_t effective_address_provided;
139 uint8_t physical_address_provided;
140 uint8_t reserved_1[5];
141 uint64_t effective_address;
142 uint64_t physical_address;
143 uint8_t reserved_2[8];
144 } ue_error;
145
146 struct {
147 enum MCE_SlbErrorType slb_error_type:8;
148 uint8_t effective_address_provided;
149 uint8_t reserved_1[6];
150 uint64_t effective_address;
151 uint8_t reserved_2[16];
152 } slb_error;
153
154 struct {
155 enum MCE_EratErrorType erat_error_type:8;
156 uint8_t effective_address_provided;
157 uint8_t reserved_1[6];
158 uint64_t effective_address;
159 uint8_t reserved_2[16];
160 } erat_error;
161
162 struct {
163 enum MCE_TlbErrorType tlb_error_type:8;
164 uint8_t effective_address_provided;
165 uint8_t reserved_1[6];
166 uint64_t effective_address;
167 uint8_t reserved_2[16];
168 } tlb_error;
169 } u;
170};
171
172struct mce_error_info {
173 enum MCE_ErrorType error_type:8;
174 union {
175 enum MCE_UeErrorType ue_error_type:8;
176 enum MCE_SlbErrorType slb_error_type:8;
177 enum MCE_EratErrorType erat_error_type:8;
178 enum MCE_TlbErrorType tlb_error_type:8;
179 } u;
180 uint8_t reserved[2];
181};
182
183#define MAX_MC_EVT 100
184
185/* Release flags for get_mce_event() */
186#define MCE_EVENT_RELEASE true
187#define MCE_EVENT_DONTRELEASE false
188
189extern void save_mce_event(struct pt_regs *regs, long handled,
190 struct mce_error_info *mce_err, uint64_t addr);
191extern int get_mce_event(struct machine_check_event *mce, bool release);
192extern void release_mce_event(void);
193extern void machine_check_queue_event(void);
194extern void machine_check_print_event_info(struct machine_check_event *evt);
195extern uint64_t get_mce_fault_addr(struct machine_check_event *evt);
196
197#endif /* __ASM_PPC64_MCE_H__ */
diff --git a/arch/powerpc/include/asm/mmu-book3e.h b/arch/powerpc/include/asm/mmu-book3e.h
index 936db360790a..89b785d16846 100644
--- a/arch/powerpc/include/asm/mmu-book3e.h
+++ b/arch/powerpc/include/asm/mmu-book3e.h
@@ -286,8 +286,21 @@ static inline unsigned int mmu_psize_to_shift(unsigned int mmu_psize)
286extern int mmu_linear_psize; 286extern int mmu_linear_psize;
287extern int mmu_vmemmap_psize; 287extern int mmu_vmemmap_psize;
288 288
289struct tlb_core_data {
290 /* For software way selection, as on Freescale TLB1 */
291 u8 esel_next, esel_max, esel_first;
292
293 /* Per-core spinlock for e6500 TLB handlers (no tlbsrx.) */
294 u8 lock;
295};
296
289#ifdef CONFIG_PPC64 297#ifdef CONFIG_PPC64
290extern unsigned long linear_map_top; 298extern unsigned long linear_map_top;
299extern int book3e_htw_mode;
300
301#define PPC_HTW_NONE 0
302#define PPC_HTW_IBM 1
303#define PPC_HTW_E6500 2
291 304
292/* 305/*
293 * 64-bit booke platforms don't load the tlb in the tlb miss handler code. 306 * 64-bit booke platforms don't load the tlb in the tlb miss handler code.
diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h
index 691fd8aca939..f8d1d6dcf7db 100644
--- a/arch/powerpc/include/asm/mmu.h
+++ b/arch/powerpc/include/asm/mmu.h
@@ -180,16 +180,17 @@ static inline void assert_pte_locked(struct mm_struct *mm, unsigned long addr)
180#define MMU_PAGE_64K_AP 3 /* "Admixed pages" (hash64 only) */ 180#define MMU_PAGE_64K_AP 3 /* "Admixed pages" (hash64 only) */
181#define MMU_PAGE_256K 4 181#define MMU_PAGE_256K 4
182#define MMU_PAGE_1M 5 182#define MMU_PAGE_1M 5
183#define MMU_PAGE_4M 6 183#define MMU_PAGE_2M 6
184#define MMU_PAGE_8M 7 184#define MMU_PAGE_4M 7
185#define MMU_PAGE_16M 8 185#define MMU_PAGE_8M 8
186#define MMU_PAGE_64M 9 186#define MMU_PAGE_16M 9
187#define MMU_PAGE_256M 10 187#define MMU_PAGE_64M 10
188#define MMU_PAGE_1G 11 188#define MMU_PAGE_256M 11
189#define MMU_PAGE_16G 12 189#define MMU_PAGE_1G 12
190#define MMU_PAGE_64G 13 190#define MMU_PAGE_16G 13
191 191#define MMU_PAGE_64G 14
192#define MMU_PAGE_COUNT 14 192
193#define MMU_PAGE_COUNT 15
193 194
194#if defined(CONFIG_PPC_STD_MMU_64) 195#if defined(CONFIG_PPC_STD_MMU_64)
195/* 64-bit classic hash table MMU */ 196/* 64-bit classic hash table MMU */
diff --git a/arch/powerpc/include/asm/mpc5121.h b/arch/powerpc/include/asm/mpc5121.h
index 887d3d6133e3..4a69cd1d5041 100644
--- a/arch/powerpc/include/asm/mpc5121.h
+++ b/arch/powerpc/include/asm/mpc5121.h
@@ -37,7 +37,12 @@ struct mpc512x_ccm {
37 u32 cccr; /* CFM Clock Control Register */ 37 u32 cccr; /* CFM Clock Control Register */
38 u32 dccr; /* DIU Clock Control Register */ 38 u32 dccr; /* DIU Clock Control Register */
39 u32 mscan_ccr[4]; /* MSCAN Clock Control Registers */ 39 u32 mscan_ccr[4]; /* MSCAN Clock Control Registers */
40 u8 res[0x98]; /* Reserved */ 40 u32 out_ccr[4]; /* OUT CLK Configure Registers */
41 u32 rsv0[2]; /* Reserved */
42 u32 scfr3; /* System Clock Frequency Register 3 */
43 u32 rsv1[3]; /* Reserved */
44 u32 spll_lock_cnt; /* System PLL Lock Counter */
45 u8 res[0x6c]; /* Reserved */
41}; 46};
42 47
43/* 48/*
diff --git a/arch/powerpc/include/asm/opal.h b/arch/powerpc/include/asm/opal.h
index 7bdcf340016c..ed82142a3251 100644
--- a/arch/powerpc/include/asm/opal.h
+++ b/arch/powerpc/include/asm/opal.h
@@ -33,6 +33,28 @@ struct opal_takeover_args {
33 u64 rd_loc; /* r11 */ 33 u64 rd_loc; /* r11 */
34}; 34};
35 35
36/*
37 * SG entry
38 *
39 * WARNING: The current implementation requires each entry
40 * to represent a block that is 4k aligned *and* each block
41 * size except the last one in the list to be as well.
42 */
43struct opal_sg_entry {
44 void *data;
45 long length;
46};
47
48/* sg list */
49struct opal_sg_list {
50 unsigned long num_entries;
51 struct opal_sg_list *next;
52 struct opal_sg_entry entry[];
53};
54
55/* We calculate number of sg entries based on PAGE_SIZE */
56#define SG_ENTRIES_PER_NODE ((PAGE_SIZE - 16) / sizeof(struct opal_sg_entry))
57
36extern long opal_query_takeover(u64 *hal_size, u64 *hal_align); 58extern long opal_query_takeover(u64 *hal_size, u64 *hal_align);
37 59
38extern long opal_do_takeover(struct opal_takeover_args *args); 60extern long opal_do_takeover(struct opal_takeover_args *args);
@@ -132,6 +154,9 @@ extern int opal_enter_rtas(struct rtas_args *args,
132#define OPAL_FLASH_VALIDATE 76 154#define OPAL_FLASH_VALIDATE 76
133#define OPAL_FLASH_MANAGE 77 155#define OPAL_FLASH_MANAGE 77
134#define OPAL_FLASH_UPDATE 78 156#define OPAL_FLASH_UPDATE 78
157#define OPAL_GET_MSG 85
158#define OPAL_CHECK_ASYNC_COMPLETION 86
159#define OPAL_SYNC_HOST_REBOOT 87
135 160
136#ifndef __ASSEMBLY__ 161#ifndef __ASSEMBLY__
137 162
@@ -211,7 +236,16 @@ enum OpalPendingState {
211 OPAL_EVENT_ERROR_LOG = 0x40, 236 OPAL_EVENT_ERROR_LOG = 0x40,
212 OPAL_EVENT_EPOW = 0x80, 237 OPAL_EVENT_EPOW = 0x80,
213 OPAL_EVENT_LED_STATUS = 0x100, 238 OPAL_EVENT_LED_STATUS = 0x100,
214 OPAL_EVENT_PCI_ERROR = 0x200 239 OPAL_EVENT_PCI_ERROR = 0x200,
240 OPAL_EVENT_MSG_PENDING = 0x800,
241};
242
243enum OpalMessageType {
244 OPAL_MSG_ASYNC_COMP = 0,
245 OPAL_MSG_MEM_ERR,
246 OPAL_MSG_EPOW,
247 OPAL_MSG_SHUTDOWN,
248 OPAL_MSG_TYPE_MAX,
215}; 249};
216 250
217/* Machine check related definitions */ 251/* Machine check related definitions */
@@ -311,12 +345,16 @@ enum OpalMveEnableAction {
311 OPAL_ENABLE_MVE = 1 345 OPAL_ENABLE_MVE = 1
312}; 346};
313 347
314enum OpalPciResetAndReinitScope { 348enum OpalPciResetScope {
315 OPAL_PHB_COMPLETE = 1, OPAL_PCI_LINK = 2, OPAL_PHB_ERROR = 3, 349 OPAL_PHB_COMPLETE = 1, OPAL_PCI_LINK = 2, OPAL_PHB_ERROR = 3,
316 OPAL_PCI_HOT_RESET = 4, OPAL_PCI_FUNDAMENTAL_RESET = 5, 350 OPAL_PCI_HOT_RESET = 4, OPAL_PCI_FUNDAMENTAL_RESET = 5,
317 OPAL_PCI_IODA_TABLE_RESET = 6, 351 OPAL_PCI_IODA_TABLE_RESET = 6,
318}; 352};
319 353
354enum OpalPciReinitScope {
355 OPAL_REINIT_PCI_DEV = 1000
356};
357
320enum OpalPciResetState { 358enum OpalPciResetState {
321 OPAL_DEASSERT_RESET = 0, 359 OPAL_DEASSERT_RESET = 0,
322 OPAL_ASSERT_RESET = 1 360 OPAL_ASSERT_RESET = 1
@@ -356,6 +394,12 @@ enum OpalLPCAddressType {
356 OPAL_LPC_FW = 2, 394 OPAL_LPC_FW = 2,
357}; 395};
358 396
397struct opal_msg {
398 uint32_t msg_type;
399 uint32_t reserved;
400 uint64_t params[8];
401};
402
359struct opal_machine_check_event { 403struct opal_machine_check_event {
360 enum OpalMCE_Version version:8; /* 0x00 */ 404 enum OpalMCE_Version version:8; /* 0x00 */
361 uint8_t in_use; /* 0x01 */ 405 uint8_t in_use; /* 0x01 */
@@ -404,6 +448,58 @@ struct opal_machine_check_event {
404 } u; 448 } u;
405}; 449};
406 450
451/* FSP memory errors handling */
452enum OpalMemErr_Version {
453 OpalMemErr_V1 = 1,
454};
455
456enum OpalMemErrType {
457 OPAL_MEM_ERR_TYPE_RESILIENCE = 0,
458 OPAL_MEM_ERR_TYPE_DYN_DALLOC,
459 OPAL_MEM_ERR_TYPE_SCRUB,
460};
461
462/* Memory Reilience error type */
463enum OpalMemErr_ResilErrType {
464 OPAL_MEM_RESILIENCE_CE = 0,
465 OPAL_MEM_RESILIENCE_UE,
466 OPAL_MEM_RESILIENCE_UE_SCRUB,
467};
468
469/* Dynamic Memory Deallocation type */
470enum OpalMemErr_DynErrType {
471 OPAL_MEM_DYNAMIC_DEALLOC = 0,
472};
473
474/* OpalMemoryErrorData->flags */
475#define OPAL_MEM_CORRECTED_ERROR 0x0001
476#define OPAL_MEM_THRESHOLD_EXCEEDED 0x0002
477#define OPAL_MEM_ACK_REQUIRED 0x8000
478
479struct OpalMemoryErrorData {
480 enum OpalMemErr_Version version:8; /* 0x00 */
481 enum OpalMemErrType type:8; /* 0x01 */
482 uint16_t flags; /* 0x02 */
483 uint8_t reserved_1[4]; /* 0x04 */
484
485 union {
486 /* Memory Resilience corrected/uncorrected error info */
487 struct {
488 enum OpalMemErr_ResilErrType resil_err_type:8;
489 uint8_t reserved_1[7];
490 uint64_t physical_address_start;
491 uint64_t physical_address_end;
492 } resilience;
493 /* Dynamic memory deallocation error info */
494 struct {
495 enum OpalMemErr_DynErrType dyn_err_type:8;
496 uint8_t reserved_1[7];
497 uint64_t physical_address_start;
498 uint64_t physical_address_end;
499 } dyn_dealloc;
500 } u;
501};
502
407enum { 503enum {
408 OPAL_P7IOC_DIAG_TYPE_NONE = 0, 504 OPAL_P7IOC_DIAG_TYPE_NONE = 0,
409 OPAL_P7IOC_DIAG_TYPE_RGC = 1, 505 OPAL_P7IOC_DIAG_TYPE_RGC = 1,
@@ -710,7 +806,7 @@ int64_t opal_pci_get_phb_diag_data(uint64_t phb_id, void *diag_buffer,
710int64_t opal_pci_get_phb_diag_data2(uint64_t phb_id, void *diag_buffer, 806int64_t opal_pci_get_phb_diag_data2(uint64_t phb_id, void *diag_buffer,
711 uint64_t diag_buffer_len); 807 uint64_t diag_buffer_len);
712int64_t opal_pci_fence_phb(uint64_t phb_id); 808int64_t opal_pci_fence_phb(uint64_t phb_id);
713int64_t opal_pci_reinit(uint64_t phb_id, uint8_t reinit_scope); 809int64_t opal_pci_reinit(uint64_t phb_id, uint64_t reinit_scope, uint64_t data);
714int64_t opal_pci_mask_pe_error(uint64_t phb_id, uint16_t pe_number, uint8_t error_type, uint8_t mask_action); 810int64_t opal_pci_mask_pe_error(uint64_t phb_id, uint16_t pe_number, uint8_t error_type, uint8_t mask_action);
715int64_t opal_set_slot_led_status(uint64_t phb_id, uint64_t slot_id, uint8_t led_type, uint8_t led_action); 811int64_t opal_set_slot_led_status(uint64_t phb_id, uint64_t slot_id, uint8_t led_type, uint8_t led_action);
716int64_t opal_get_epow_status(__be64 *status); 812int64_t opal_get_epow_status(__be64 *status);
@@ -720,8 +816,8 @@ int64_t opal_pci_next_error(uint64_t phb_id, uint64_t *first_frozen_pe,
720int64_t opal_pci_poll(uint64_t phb_id); 816int64_t opal_pci_poll(uint64_t phb_id);
721int64_t opal_return_cpu(void); 817int64_t opal_return_cpu(void);
722 818
723int64_t opal_xscom_read(uint32_t gcid, uint32_t pcb_addr, __be64 *val); 819int64_t opal_xscom_read(uint32_t gcid, uint64_t pcb_addr, __be64 *val);
724int64_t opal_xscom_write(uint32_t gcid, uint32_t pcb_addr, uint64_t val); 820int64_t opal_xscom_write(uint32_t gcid, uint64_t pcb_addr, uint64_t val);
725 821
726int64_t opal_lpc_write(uint32_t chip_id, enum OpalLPCAddressType addr_type, 822int64_t opal_lpc_write(uint32_t chip_id, enum OpalLPCAddressType addr_type,
727 uint32_t addr, uint32_t data, uint32_t sz); 823 uint32_t addr, uint32_t data, uint32_t sz);
@@ -731,6 +827,10 @@ int64_t opal_validate_flash(uint64_t buffer, uint32_t *size, uint32_t *result);
731int64_t opal_manage_flash(uint8_t op); 827int64_t opal_manage_flash(uint8_t op);
732int64_t opal_update_flash(uint64_t blk_list); 828int64_t opal_update_flash(uint64_t blk_list);
733 829
830int64_t opal_get_msg(uint64_t buffer, size_t size);
831int64_t opal_check_completion(uint64_t buffer, size_t size, uint64_t token);
832int64_t opal_sync_host_reboot(void);
833
734/* Internal functions */ 834/* Internal functions */
735extern int early_init_dt_scan_opal(unsigned long node, const char *uname, int depth, void *data); 835extern int early_init_dt_scan_opal(unsigned long node, const char *uname, int depth, void *data);
736 836
@@ -744,6 +844,8 @@ extern int early_init_dt_scan_opal(unsigned long node, const char *uname,
744 int depth, void *data); 844 int depth, void *data);
745 845
746extern int opal_notifier_register(struct notifier_block *nb); 846extern int opal_notifier_register(struct notifier_block *nb);
847extern int opal_message_notifier_register(enum OpalMessageType msg_type,
848 struct notifier_block *nb);
747extern void opal_notifier_enable(void); 849extern void opal_notifier_enable(void);
748extern void opal_notifier_disable(void); 850extern void opal_notifier_disable(void);
749extern void opal_notifier_update_evt(uint64_t evt_mask, uint64_t evt_val); 851extern void opal_notifier_update_evt(uint64_t evt_mask, uint64_t evt_val);
diff --git a/arch/powerpc/include/asm/paca.h b/arch/powerpc/include/asm/paca.h
index b6ea9e068c13..9c5dbc3833fb 100644
--- a/arch/powerpc/include/asm/paca.h
+++ b/arch/powerpc/include/asm/paca.h
@@ -16,7 +16,6 @@
16 16
17#ifdef CONFIG_PPC64 17#ifdef CONFIG_PPC64
18 18
19#include <linux/init.h>
20#include <asm/types.h> 19#include <asm/types.h>
21#include <asm/lppaca.h> 20#include <asm/lppaca.h>
22#include <asm/mmu.h> 21#include <asm/mmu.h>
@@ -113,6 +112,10 @@ struct paca_struct {
113 /* Keep pgd in the same cacheline as the start of extlb */ 112 /* Keep pgd in the same cacheline as the start of extlb */
114 pgd_t *pgd __attribute__((aligned(0x80))); /* Current PGD */ 113 pgd_t *pgd __attribute__((aligned(0x80))); /* Current PGD */
115 pgd_t *kernel_pgd; /* Kernel PGD */ 114 pgd_t *kernel_pgd; /* Kernel PGD */
115
116 /* Shared by all threads of a core -- points to tcd of first thread */
117 struct tlb_core_data *tcd_ptr;
118
116 /* We can have up to 3 levels of reentrancy in the TLB miss handler */ 119 /* We can have up to 3 levels of reentrancy in the TLB miss handler */
117 u64 extlb[3][EX_TLB_SIZE / sizeof(u64)]; 120 u64 extlb[3][EX_TLB_SIZE / sizeof(u64)];
118 u64 exmc[8]; /* used for machine checks */ 121 u64 exmc[8]; /* used for machine checks */
@@ -123,6 +126,8 @@ struct paca_struct {
123 void *mc_kstack; 126 void *mc_kstack;
124 void *crit_kstack; 127 void *crit_kstack;
125 void *dbg_kstack; 128 void *dbg_kstack;
129
130 struct tlb_core_data tcd;
126#endif /* CONFIG_PPC_BOOK3E */ 131#endif /* CONFIG_PPC_BOOK3E */
127 132
128 mm_context_t context; 133 mm_context_t context;
@@ -152,6 +157,15 @@ struct paca_struct {
152 */ 157 */
153 struct opal_machine_check_event *opal_mc_evt; 158 struct opal_machine_check_event *opal_mc_evt;
154#endif 159#endif
160#ifdef CONFIG_PPC_BOOK3S_64
161 /* Exclusive emergency stack pointer for machine check exception. */
162 void *mc_emergency_sp;
163 /*
164 * Flag to check whether we are in machine check early handler
165 * and already using emergency stack.
166 */
167 u16 in_mce;
168#endif
155 169
156 /* Stuff for accurate time accounting */ 170 /* Stuff for accurate time accounting */
157 u64 user_time; /* accumulated usermode TB ticks */ 171 u64 user_time; /* accumulated usermode TB ticks */
diff --git a/arch/powerpc/include/asm/pgtable-ppc64.h b/arch/powerpc/include/asm/pgtable-ppc64.h
index 4a191c472867..eb9261024f51 100644
--- a/arch/powerpc/include/asm/pgtable-ppc64.h
+++ b/arch/powerpc/include/asm/pgtable-ppc64.h
@@ -195,6 +195,7 @@ extern void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
195static inline unsigned long pte_update(struct mm_struct *mm, 195static inline unsigned long pte_update(struct mm_struct *mm,
196 unsigned long addr, 196 unsigned long addr,
197 pte_t *ptep, unsigned long clr, 197 pte_t *ptep, unsigned long clr,
198 unsigned long set,
198 int huge) 199 int huge)
199{ 200{
200#ifdef PTE_ATOMIC_UPDATES 201#ifdef PTE_ATOMIC_UPDATES
@@ -205,14 +206,15 @@ static inline unsigned long pte_update(struct mm_struct *mm,
205 andi. %1,%0,%6\n\ 206 andi. %1,%0,%6\n\
206 bne- 1b \n\ 207 bne- 1b \n\
207 andc %1,%0,%4 \n\ 208 andc %1,%0,%4 \n\
209 or %1,%1,%7\n\
208 stdcx. %1,0,%3 \n\ 210 stdcx. %1,0,%3 \n\
209 bne- 1b" 211 bne- 1b"
210 : "=&r" (old), "=&r" (tmp), "=m" (*ptep) 212 : "=&r" (old), "=&r" (tmp), "=m" (*ptep)
211 : "r" (ptep), "r" (clr), "m" (*ptep), "i" (_PAGE_BUSY) 213 : "r" (ptep), "r" (clr), "m" (*ptep), "i" (_PAGE_BUSY), "r" (set)
212 : "cc" ); 214 : "cc" );
213#else 215#else
214 unsigned long old = pte_val(*ptep); 216 unsigned long old = pte_val(*ptep);
215 *ptep = __pte(old & ~clr); 217 *ptep = __pte((old & ~clr) | set);
216#endif 218#endif
217 /* huge pages use the old page table lock */ 219 /* huge pages use the old page table lock */
218 if (!huge) 220 if (!huge)
@@ -231,9 +233,9 @@ static inline int __ptep_test_and_clear_young(struct mm_struct *mm,
231{ 233{
232 unsigned long old; 234 unsigned long old;
233 235
234 if ((pte_val(*ptep) & (_PAGE_ACCESSED | _PAGE_HASHPTE)) == 0) 236 if ((pte_val(*ptep) & (_PAGE_ACCESSED | _PAGE_HASHPTE)) == 0)
235 return 0; 237 return 0;
236 old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0); 238 old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0, 0);
237 return (old & _PAGE_ACCESSED) != 0; 239 return (old & _PAGE_ACCESSED) != 0;
238} 240}
239#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 241#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
@@ -252,7 +254,7 @@ static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
252 if ((pte_val(*ptep) & _PAGE_RW) == 0) 254 if ((pte_val(*ptep) & _PAGE_RW) == 0)
253 return; 255 return;
254 256
255 pte_update(mm, addr, ptep, _PAGE_RW, 0); 257 pte_update(mm, addr, ptep, _PAGE_RW, 0, 0);
256} 258}
257 259
258static inline void huge_ptep_set_wrprotect(struct mm_struct *mm, 260static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
@@ -261,7 +263,7 @@ static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
261 if ((pte_val(*ptep) & _PAGE_RW) == 0) 263 if ((pte_val(*ptep) & _PAGE_RW) == 0)
262 return; 264 return;
263 265
264 pte_update(mm, addr, ptep, _PAGE_RW, 1); 266 pte_update(mm, addr, ptep, _PAGE_RW, 0, 1);
265} 267}
266 268
267/* 269/*
@@ -284,14 +286,14 @@ static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
284static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 286static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
285 unsigned long addr, pte_t *ptep) 287 unsigned long addr, pte_t *ptep)
286{ 288{
287 unsigned long old = pte_update(mm, addr, ptep, ~0UL, 0); 289 unsigned long old = pte_update(mm, addr, ptep, ~0UL, 0, 0);
288 return __pte(old); 290 return __pte(old);
289} 291}
290 292
291static inline void pte_clear(struct mm_struct *mm, unsigned long addr, 293static inline void pte_clear(struct mm_struct *mm, unsigned long addr,
292 pte_t * ptep) 294 pte_t * ptep)
293{ 295{
294 pte_update(mm, addr, ptep, ~0UL, 0); 296 pte_update(mm, addr, ptep, ~0UL, 0, 0);
295} 297}
296 298
297 299
@@ -506,7 +508,9 @@ extern int pmdp_set_access_flags(struct vm_area_struct *vma,
506 508
507extern unsigned long pmd_hugepage_update(struct mm_struct *mm, 509extern unsigned long pmd_hugepage_update(struct mm_struct *mm,
508 unsigned long addr, 510 unsigned long addr,
509 pmd_t *pmdp, unsigned long clr); 511 pmd_t *pmdp,
512 unsigned long clr,
513 unsigned long set);
510 514
511static inline int __pmdp_test_and_clear_young(struct mm_struct *mm, 515static inline int __pmdp_test_and_clear_young(struct mm_struct *mm,
512 unsigned long addr, pmd_t *pmdp) 516 unsigned long addr, pmd_t *pmdp)
@@ -515,7 +519,7 @@ static inline int __pmdp_test_and_clear_young(struct mm_struct *mm,
515 519
516 if ((pmd_val(*pmdp) & (_PAGE_ACCESSED | _PAGE_HASHPTE)) == 0) 520 if ((pmd_val(*pmdp) & (_PAGE_ACCESSED | _PAGE_HASHPTE)) == 0)
517 return 0; 521 return 0;
518 old = pmd_hugepage_update(mm, addr, pmdp, _PAGE_ACCESSED); 522 old = pmd_hugepage_update(mm, addr, pmdp, _PAGE_ACCESSED, 0);
519 return ((old & _PAGE_ACCESSED) != 0); 523 return ((old & _PAGE_ACCESSED) != 0);
520} 524}
521 525
@@ -542,7 +546,7 @@ static inline void pmdp_set_wrprotect(struct mm_struct *mm, unsigned long addr,
542 if ((pmd_val(*pmdp) & _PAGE_RW) == 0) 546 if ((pmd_val(*pmdp) & _PAGE_RW) == 0)
543 return; 547 return;
544 548
545 pmd_hugepage_update(mm, addr, pmdp, _PAGE_RW); 549 pmd_hugepage_update(mm, addr, pmdp, _PAGE_RW, 0);
546} 550}
547 551
548#define __HAVE_ARCH_PMDP_SPLITTING_FLUSH 552#define __HAVE_ARCH_PMDP_SPLITTING_FLUSH
@@ -558,5 +562,19 @@ extern pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp);
558#define __HAVE_ARCH_PMDP_INVALIDATE 562#define __HAVE_ARCH_PMDP_INVALIDATE
559extern void pmdp_invalidate(struct vm_area_struct *vma, unsigned long address, 563extern void pmdp_invalidate(struct vm_area_struct *vma, unsigned long address,
560 pmd_t *pmdp); 564 pmd_t *pmdp);
565
566#define pmd_move_must_withdraw pmd_move_must_withdraw
567struct spinlock;
568static inline int pmd_move_must_withdraw(struct spinlock *new_pmd_ptl,
569 struct spinlock *old_pmd_ptl)
570{
571 /*
572 * Archs like ppc64 use pgtable to store per pmd
573 * specific information. So when we switch the pmd,
574 * we should also withdraw and deposit the pgtable
575 */
576 return true;
577}
578
561#endif /* __ASSEMBLY__ */ 579#endif /* __ASSEMBLY__ */
562#endif /* _ASM_POWERPC_PGTABLE_PPC64_H_ */ 580#endif /* _ASM_POWERPC_PGTABLE_PPC64_H_ */
diff --git a/arch/powerpc/include/asm/pgtable.h b/arch/powerpc/include/asm/pgtable.h
index 7d6eacf249cf..3ebb188c3ff5 100644
--- a/arch/powerpc/include/asm/pgtable.h
+++ b/arch/powerpc/include/asm/pgtable.h
@@ -3,6 +3,7 @@
3#ifdef __KERNEL__ 3#ifdef __KERNEL__
4 4
5#ifndef __ASSEMBLY__ 5#ifndef __ASSEMBLY__
6#include <linux/mmdebug.h>
6#include <asm/processor.h> /* For TASK_SIZE */ 7#include <asm/processor.h> /* For TASK_SIZE */
7#include <asm/mmu.h> 8#include <asm/mmu.h>
8#include <asm/page.h> 9#include <asm/page.h>
@@ -33,10 +34,95 @@ static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; }
33static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; } 34static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
34static inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE; } 35static inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE; }
35static inline int pte_special(pte_t pte) { return pte_val(pte) & _PAGE_SPECIAL; } 36static inline int pte_special(pte_t pte) { return pte_val(pte) & _PAGE_SPECIAL; }
36static inline int pte_present(pte_t pte) { return pte_val(pte) & _PAGE_PRESENT; }
37static inline int pte_none(pte_t pte) { return (pte_val(pte) & ~_PTE_NONE_MASK) == 0; } 37static inline int pte_none(pte_t pte) { return (pte_val(pte) & ~_PTE_NONE_MASK) == 0; }
38static inline pgprot_t pte_pgprot(pte_t pte) { return __pgprot(pte_val(pte) & PAGE_PROT_BITS); } 38static inline pgprot_t pte_pgprot(pte_t pte) { return __pgprot(pte_val(pte) & PAGE_PROT_BITS); }
39 39
40#ifdef CONFIG_NUMA_BALANCING
41
42static inline int pte_present(pte_t pte)
43{
44 return pte_val(pte) & (_PAGE_PRESENT | _PAGE_NUMA);
45}
46
47#define pte_numa pte_numa
48static inline int pte_numa(pte_t pte)
49{
50 return (pte_val(pte) &
51 (_PAGE_NUMA|_PAGE_PRESENT)) == _PAGE_NUMA;
52}
53
54#define pte_mknonnuma pte_mknonnuma
55static inline pte_t pte_mknonnuma(pte_t pte)
56{
57 pte_val(pte) &= ~_PAGE_NUMA;
58 pte_val(pte) |= _PAGE_PRESENT | _PAGE_ACCESSED;
59 return pte;
60}
61
62#define pte_mknuma pte_mknuma
63static inline pte_t pte_mknuma(pte_t pte)
64{
65 /*
66 * We should not set _PAGE_NUMA on non present ptes. Also clear the
67 * present bit so that hash_page will return 1 and we collect this
68 * as numa fault.
69 */
70 if (pte_present(pte)) {
71 pte_val(pte) |= _PAGE_NUMA;
72 pte_val(pte) &= ~_PAGE_PRESENT;
73 } else
74 VM_BUG_ON(1);
75 return pte;
76}
77
78#define ptep_set_numa ptep_set_numa
79static inline void ptep_set_numa(struct mm_struct *mm, unsigned long addr,
80 pte_t *ptep)
81{
82 if ((pte_val(*ptep) & _PAGE_PRESENT) == 0)
83 VM_BUG_ON(1);
84
85 pte_update(mm, addr, ptep, _PAGE_PRESENT, _PAGE_NUMA, 0);
86 return;
87}
88
89#define pmd_numa pmd_numa
90static inline int pmd_numa(pmd_t pmd)
91{
92 return pte_numa(pmd_pte(pmd));
93}
94
95#define pmdp_set_numa pmdp_set_numa
96static inline void pmdp_set_numa(struct mm_struct *mm, unsigned long addr,
97 pmd_t *pmdp)
98{
99 if ((pmd_val(*pmdp) & _PAGE_PRESENT) == 0)
100 VM_BUG_ON(1);
101
102 pmd_hugepage_update(mm, addr, pmdp, _PAGE_PRESENT, _PAGE_NUMA);
103 return;
104}
105
106#define pmd_mknonnuma pmd_mknonnuma
107static inline pmd_t pmd_mknonnuma(pmd_t pmd)
108{
109 return pte_pmd(pte_mknonnuma(pmd_pte(pmd)));
110}
111
112#define pmd_mknuma pmd_mknuma
113static inline pmd_t pmd_mknuma(pmd_t pmd)
114{
115 return pte_pmd(pte_mknuma(pmd_pte(pmd)));
116}
117
118# else
119
120static inline int pte_present(pte_t pte)
121{
122 return pte_val(pte) & _PAGE_PRESENT;
123}
124#endif /* CONFIG_NUMA_BALANCING */
125
40/* Conversion functions: convert a page and protection to a page entry, 126/* Conversion functions: convert a page and protection to a page entry,
41 * and a page entry and page directory to the page they refer to. 127 * and a page entry and page directory to the page they refer to.
42 * 128 *
@@ -223,6 +309,27 @@ extern int gup_hugepte(pte_t *ptep, unsigned long sz, unsigned long addr,
223#endif 309#endif
224pte_t *find_linux_pte_or_hugepte(pgd_t *pgdir, unsigned long ea, 310pte_t *find_linux_pte_or_hugepte(pgd_t *pgdir, unsigned long ea,
225 unsigned *shift); 311 unsigned *shift);
312
313static inline pte_t *lookup_linux_ptep(pgd_t *pgdir, unsigned long hva,
314 unsigned long *pte_sizep)
315{
316 pte_t *ptep;
317 unsigned long ps = *pte_sizep;
318 unsigned int shift;
319
320 ptep = find_linux_pte_or_hugepte(pgdir, hva, &shift);
321 if (!ptep)
322 return NULL;
323 if (shift)
324 *pte_sizep = 1ul << shift;
325 else
326 *pte_sizep = PAGE_SIZE;
327
328 if (ps > *pte_sizep)
329 return NULL;
330
331 return ptep;
332}
226#endif /* __ASSEMBLY__ */ 333#endif /* __ASSEMBLY__ */
227 334
228#endif /* __KERNEL__ */ 335#endif /* __KERNEL__ */
diff --git a/arch/powerpc/include/asm/ppc_asm.h b/arch/powerpc/include/asm/ppc_asm.h
index f595b98079ee..6586a40a46ce 100644
--- a/arch/powerpc/include/asm/ppc_asm.h
+++ b/arch/powerpc/include/asm/ppc_asm.h
@@ -4,7 +4,6 @@
4#ifndef _ASM_POWERPC_PPC_ASM_H 4#ifndef _ASM_POWERPC_PPC_ASM_H
5#define _ASM_POWERPC_PPC_ASM_H 5#define _ASM_POWERPC_PPC_ASM_H
6 6
7#include <linux/init.h>
8#include <linux/stringify.h> 7#include <linux/stringify.h>
9#include <asm/asm-compat.h> 8#include <asm/asm-compat.h>
10#include <asm/processor.h> 9#include <asm/processor.h>
@@ -295,6 +294,11 @@ n:
295 * you want to access various offsets within it). On ppc32 this is 294 * you want to access various offsets within it). On ppc32 this is
296 * identical to LOAD_REG_IMMEDIATE. 295 * identical to LOAD_REG_IMMEDIATE.
297 * 296 *
297 * LOAD_REG_ADDR_PIC(rn, name)
298 * Loads the address of label 'name' into register 'run'. Use this when
299 * the kernel doesn't run at the linked or relocated address. Please
300 * note that this macro will clobber the lr register.
301 *
298 * LOAD_REG_ADDRBASE(rn, name) 302 * LOAD_REG_ADDRBASE(rn, name)
299 * ADDROFF(name) 303 * ADDROFF(name)
300 * LOAD_REG_ADDRBASE loads part of the address of label 'name' into 304 * LOAD_REG_ADDRBASE loads part of the address of label 'name' into
@@ -305,6 +309,14 @@ n:
305 * LOAD_REG_ADDRBASE(rX, name) 309 * LOAD_REG_ADDRBASE(rX, name)
306 * ld rY,ADDROFF(name)(rX) 310 * ld rY,ADDROFF(name)(rX)
307 */ 311 */
312
313/* Be careful, this will clobber the lr register. */
314#define LOAD_REG_ADDR_PIC(reg, name) \
315 bl 0f; \
3160: mflr reg; \
317 addis reg,reg,(name - 0b)@ha; \
318 addi reg,reg,(name - 0b)@l;
319
308#ifdef __powerpc64__ 320#ifdef __powerpc64__
309#define LOAD_REG_IMMEDIATE(reg,expr) \ 321#define LOAD_REG_IMMEDIATE(reg,expr) \
310 lis reg,(expr)@highest; \ 322 lis reg,(expr)@highest; \
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index fc14a38c7ccf..b62de43ae5f3 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -256,6 +256,8 @@ struct thread_struct {
256 unsigned long evr[32]; /* upper 32-bits of SPE regs */ 256 unsigned long evr[32]; /* upper 32-bits of SPE regs */
257 u64 acc; /* Accumulator */ 257 u64 acc; /* Accumulator */
258 unsigned long spefscr; /* SPE & eFP status */ 258 unsigned long spefscr; /* SPE & eFP status */
259 unsigned long spefscr_last; /* SPEFSCR value on last prctl
260 call or trap return */
259 int used_spe; /* set if process has used spe */ 261 int used_spe; /* set if process has used spe */
260#endif /* CONFIG_SPE */ 262#endif /* CONFIG_SPE */
261#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 263#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
@@ -317,7 +319,9 @@ struct thread_struct {
317 (_ALIGN_UP(sizeof(init_thread_info), 16) + (unsigned long) &init_stack) 319 (_ALIGN_UP(sizeof(init_thread_info), 16) + (unsigned long) &init_stack)
318 320
319#ifdef CONFIG_SPE 321#ifdef CONFIG_SPE
320#define SPEFSCR_INIT .spefscr = SPEFSCR_FINVE | SPEFSCR_FDBZE | SPEFSCR_FUNFE | SPEFSCR_FOVFE, 322#define SPEFSCR_INIT \
323 .spefscr = SPEFSCR_FINVE | SPEFSCR_FDBZE | SPEFSCR_FUNFE | SPEFSCR_FOVFE, \
324 .spefscr_last = SPEFSCR_FINVE | SPEFSCR_FDBZE | SPEFSCR_FUNFE | SPEFSCR_FOVFE,
321#else 325#else
322#define SPEFSCR_INIT 326#define SPEFSCR_INIT
323#endif 327#endif
@@ -373,6 +377,8 @@ extern int set_endian(struct task_struct *tsk, unsigned int val);
373extern int get_unalign_ctl(struct task_struct *tsk, unsigned long adr); 377extern int get_unalign_ctl(struct task_struct *tsk, unsigned long adr);
374extern int set_unalign_ctl(struct task_struct *tsk, unsigned int val); 378extern int set_unalign_ctl(struct task_struct *tsk, unsigned int val);
375 379
380extern void fp_enable(void);
381extern void vec_enable(void);
376extern void load_fp_state(struct thread_fp_state *fp); 382extern void load_fp_state(struct thread_fp_state *fp);
377extern void store_fp_state(struct thread_fp_state *fp); 383extern void store_fp_state(struct thread_fp_state *fp);
378extern void load_vr_state(struct thread_vr_state *vr); 384extern void load_vr_state(struct thread_vr_state *vr);
@@ -444,13 +450,6 @@ enum idle_boot_override {IDLE_NO_OVERRIDE = 0, IDLE_POWERSAVE_OFF};
444 450
445extern int powersave_nap; /* set if nap mode can be used in idle loop */ 451extern int powersave_nap; /* set if nap mode can be used in idle loop */
446extern void power7_nap(void); 452extern void power7_nap(void);
447
448#ifdef CONFIG_PSERIES_IDLE
449extern void update_smt_snooze_delay(int cpu, int residency);
450#else
451static inline void update_smt_snooze_delay(int cpu, int residency) {}
452#endif
453
454extern void flush_instruction_cache(void); 453extern void flush_instruction_cache(void);
455extern void hard_reset_now(void); 454extern void hard_reset_now(void);
456extern void poweroff_now(void); 455extern void poweroff_now(void);
diff --git a/arch/powerpc/include/asm/ps3.h b/arch/powerpc/include/asm/ps3.h
index 678a7c1d9cb8..a1bc7e758422 100644
--- a/arch/powerpc/include/asm/ps3.h
+++ b/arch/powerpc/include/asm/ps3.h
@@ -21,7 +21,6 @@
21#if !defined(_ASM_POWERPC_PS3_H) 21#if !defined(_ASM_POWERPC_PS3_H)
22#define _ASM_POWERPC_PS3_H 22#define _ASM_POWERPC_PS3_H
23 23
24#include <linux/init.h>
25#include <linux/types.h> 24#include <linux/types.h>
26#include <linux/device.h> 25#include <linux/device.h>
27#include <asm/cell-pmu.h> 26#include <asm/cell-pmu.h>
diff --git a/arch/powerpc/include/asm/pte-hash64.h b/arch/powerpc/include/asm/pte-hash64.h
index 0419eeb53274..2505d8eab15c 100644
--- a/arch/powerpc/include/asm/pte-hash64.h
+++ b/arch/powerpc/include/asm/pte-hash64.h
@@ -19,7 +19,7 @@
19#define _PAGE_FILE 0x0002 /* (!present only) software: pte holds file offset */ 19#define _PAGE_FILE 0x0002 /* (!present only) software: pte holds file offset */
20#define _PAGE_EXEC 0x0004 /* No execute on POWER4 and newer (we invert) */ 20#define _PAGE_EXEC 0x0004 /* No execute on POWER4 and newer (we invert) */
21#define _PAGE_GUARDED 0x0008 21#define _PAGE_GUARDED 0x0008
22#define _PAGE_COHERENT 0x0010 /* M: enforce memory coherence (SMP systems) */ 22/* We can derive Memory coherence from _PAGE_NO_CACHE */
23#define _PAGE_NO_CACHE 0x0020 /* I: cache inhibit */ 23#define _PAGE_NO_CACHE 0x0020 /* I: cache inhibit */
24#define _PAGE_WRITETHRU 0x0040 /* W: cache write-through */ 24#define _PAGE_WRITETHRU 0x0040 /* W: cache write-through */
25#define _PAGE_DIRTY 0x0080 /* C: page changed */ 25#define _PAGE_DIRTY 0x0080 /* C: page changed */
@@ -27,6 +27,12 @@
27#define _PAGE_RW 0x0200 /* software: user write access allowed */ 27#define _PAGE_RW 0x0200 /* software: user write access allowed */
28#define _PAGE_BUSY 0x0800 /* software: PTE & hash are busy */ 28#define _PAGE_BUSY 0x0800 /* software: PTE & hash are busy */
29 29
30/*
31 * Used for tracking numa faults
32 */
33#define _PAGE_NUMA 0x00000010 /* Gather numa placement stats */
34
35
30/* No separate kernel read-only */ 36/* No separate kernel read-only */
31#define _PAGE_KERNEL_RW (_PAGE_RW | _PAGE_DIRTY) /* user access blocked by key */ 37#define _PAGE_KERNEL_RW (_PAGE_RW | _PAGE_DIRTY) /* user access blocked by key */
32#define _PAGE_KERNEL_RO _PAGE_KERNEL_RW 38#define _PAGE_KERNEL_RO _PAGE_KERNEL_RW
diff --git a/arch/powerpc/include/asm/ptrace.h b/arch/powerpc/include/asm/ptrace.h
index becc08e6a65c..279b80f3bb29 100644
--- a/arch/powerpc/include/asm/ptrace.h
+++ b/arch/powerpc/include/asm/ptrace.h
@@ -28,11 +28,23 @@
28 28
29#ifdef __powerpc64__ 29#ifdef __powerpc64__
30 30
31/*
32 * Size of redzone that userspace is allowed to use below the stack
33 * pointer. This is 288 in the 64-bit big-endian ELF ABI, and 512 in
34 * the new ELFv2 little-endian ABI, so we allow the larger amount.
35 *
36 * For kernel code we allow a 288-byte redzone, in order to conserve
37 * kernel stack space; gcc currently only uses 288 bytes, and will
38 * hopefully allow explicit control of the redzone size in future.
39 */
40#define USER_REDZONE_SIZE 512
41#define KERNEL_REDZONE_SIZE 288
42
31#define STACK_FRAME_OVERHEAD 112 /* size of minimum stack frame */ 43#define STACK_FRAME_OVERHEAD 112 /* size of minimum stack frame */
32#define STACK_FRAME_LR_SAVE 2 /* Location of LR in stack frame */ 44#define STACK_FRAME_LR_SAVE 2 /* Location of LR in stack frame */
33#define STACK_FRAME_REGS_MARKER ASM_CONST(0x7265677368657265) 45#define STACK_FRAME_REGS_MARKER ASM_CONST(0x7265677368657265)
34#define STACK_INT_FRAME_SIZE (sizeof(struct pt_regs) + \ 46#define STACK_INT_FRAME_SIZE (sizeof(struct pt_regs) + \
35 STACK_FRAME_OVERHEAD + 288) 47 STACK_FRAME_OVERHEAD + KERNEL_REDZONE_SIZE)
36#define STACK_FRAME_MARKER 12 48#define STACK_FRAME_MARKER 12
37 49
38/* Size of dummy stack frame allocated when calling signal handler. */ 50/* Size of dummy stack frame allocated when calling signal handler. */
@@ -41,6 +53,8 @@
41 53
42#else /* __powerpc64__ */ 54#else /* __powerpc64__ */
43 55
56#define USER_REDZONE_SIZE 0
57#define KERNEL_REDZONE_SIZE 0
44#define STACK_FRAME_OVERHEAD 16 /* size of minimum stack frame */ 58#define STACK_FRAME_OVERHEAD 16 /* size of minimum stack frame */
45#define STACK_FRAME_LR_SAVE 1 /* Location of LR in stack frame */ 59#define STACK_FRAME_LR_SAVE 1 /* Location of LR in stack frame */
46#define STACK_FRAME_REGS_MARKER ASM_CONST(0x72656773) 60#define STACK_FRAME_REGS_MARKER ASM_CONST(0x72656773)
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index fa8388ed94c5..90c06ec6eff5 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -223,17 +223,26 @@
223#define CTRL_TE 0x00c00000 /* thread enable */ 223#define CTRL_TE 0x00c00000 /* thread enable */
224#define CTRL_RUNLATCH 0x1 224#define CTRL_RUNLATCH 0x1
225#define SPRN_DAWR 0xB4 225#define SPRN_DAWR 0xB4
226#define SPRN_CIABR 0xBB
227#define CIABR_PRIV 0x3
228#define CIABR_PRIV_USER 1
229#define CIABR_PRIV_SUPER 2
230#define CIABR_PRIV_HYPER 3
226#define SPRN_DAWRX 0xBC 231#define SPRN_DAWRX 0xBC
227#define DAWRX_USER (1UL << 0) 232#define DAWRX_USER __MASK(0)
228#define DAWRX_KERNEL (1UL << 1) 233#define DAWRX_KERNEL __MASK(1)
229#define DAWRX_HYP (1UL << 2) 234#define DAWRX_HYP __MASK(2)
235#define DAWRX_WTI __MASK(3)
236#define DAWRX_WT __MASK(4)
237#define DAWRX_DR __MASK(5)
238#define DAWRX_DW __MASK(6)
230#define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */ 239#define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */
231#define SPRN_DABR2 0x13D /* e300 */ 240#define SPRN_DABR2 0x13D /* e300 */
232#define SPRN_DABRX 0x3F7 /* Data Address Breakpoint Register Extension */ 241#define SPRN_DABRX 0x3F7 /* Data Address Breakpoint Register Extension */
233#define DABRX_USER (1UL << 0) 242#define DABRX_USER __MASK(0)
234#define DABRX_KERNEL (1UL << 1) 243#define DABRX_KERNEL __MASK(1)
235#define DABRX_HYP (1UL << 2) 244#define DABRX_HYP __MASK(2)
236#define DABRX_BTI (1UL << 3) 245#define DABRX_BTI __MASK(3)
237#define DABRX_ALL (DABRX_BTI | DABRX_HYP | DABRX_KERNEL | DABRX_USER) 246#define DABRX_ALL (DABRX_BTI | DABRX_HYP | DABRX_KERNEL | DABRX_USER)
238#define SPRN_DAR 0x013 /* Data Address Register */ 247#define SPRN_DAR 0x013 /* Data Address Register */
239#define SPRN_DBCR 0x136 /* e300 Data Breakpoint Control Reg */ 248#define SPRN_DBCR 0x136 /* e300 Data Breakpoint Control Reg */
@@ -260,6 +269,8 @@
260#define SPRN_HRMOR 0x139 /* Real mode offset register */ 269#define SPRN_HRMOR 0x139 /* Real mode offset register */
261#define SPRN_HSRR0 0x13A /* Hypervisor Save/Restore 0 */ 270#define SPRN_HSRR0 0x13A /* Hypervisor Save/Restore 0 */
262#define SPRN_HSRR1 0x13B /* Hypervisor Save/Restore 1 */ 271#define SPRN_HSRR1 0x13B /* Hypervisor Save/Restore 1 */
272#define SPRN_IC 0x350 /* Virtual Instruction Count */
273#define SPRN_VTB 0x351 /* Virtual Time Base */
263/* HFSCR and FSCR bit numbers are the same */ 274/* HFSCR and FSCR bit numbers are the same */
264#define FSCR_TAR_LG 8 /* Enable Target Address Register */ 275#define FSCR_TAR_LG 8 /* Enable Target Address Register */
265#define FSCR_EBB_LG 7 /* Enable Event Based Branching */ 276#define FSCR_EBB_LG 7 /* Enable Event Based Branching */
@@ -298,9 +309,13 @@
298#define LPCR_RMLS 0x1C000000 /* impl dependent rmo limit sel */ 309#define LPCR_RMLS 0x1C000000 /* impl dependent rmo limit sel */
299#define LPCR_RMLS_SH (63-37) 310#define LPCR_RMLS_SH (63-37)
300#define LPCR_ILE 0x02000000 /* !HV irqs set MSR:LE */ 311#define LPCR_ILE 0x02000000 /* !HV irqs set MSR:LE */
312#define LPCR_AIL 0x01800000 /* Alternate interrupt location */
301#define LPCR_AIL_0 0x00000000 /* MMU off exception offset 0x0 */ 313#define LPCR_AIL_0 0x00000000 /* MMU off exception offset 0x0 */
302#define LPCR_AIL_3 0x01800000 /* MMU on exception offset 0xc00...4xxx */ 314#define LPCR_AIL_3 0x01800000 /* MMU on exception offset 0xc00...4xxx */
303#define LPCR_PECE 0x00007000 /* powersave exit cause enable */ 315#define LPCR_ONL 0x00040000 /* online - PURR/SPURR count */
316#define LPCR_PECE 0x0001f000 /* powersave exit cause enable */
317#define LPCR_PECEDP 0x00010000 /* directed priv dbells cause exit */
318#define LPCR_PECEDH 0x00008000 /* directed hyp dbells cause exit */
304#define LPCR_PECE0 0x00004000 /* ext. exceptions can cause exit */ 319#define LPCR_PECE0 0x00004000 /* ext. exceptions can cause exit */
305#define LPCR_PECE1 0x00002000 /* decrementer can cause exit */ 320#define LPCR_PECE1 0x00002000 /* decrementer can cause exit */
306#define LPCR_PECE2 0x00001000 /* machine check etc can cause exit */ 321#define LPCR_PECE2 0x00001000 /* machine check etc can cause exit */
@@ -322,6 +337,8 @@
322#define SPRN_PCR 0x152 /* Processor compatibility register */ 337#define SPRN_PCR 0x152 /* Processor compatibility register */
323#define PCR_VEC_DIS (1ul << (63-0)) /* Vec. disable (bit NA since POWER8) */ 338#define PCR_VEC_DIS (1ul << (63-0)) /* Vec. disable (bit NA since POWER8) */
324#define PCR_VSX_DIS (1ul << (63-1)) /* VSX disable (bit NA since POWER8) */ 339#define PCR_VSX_DIS (1ul << (63-1)) /* VSX disable (bit NA since POWER8) */
340#define PCR_TM_DIS (1ul << (63-2)) /* Trans. memory disable (POWER8) */
341#define PCR_ARCH_206 0x4 /* Architecture 2.06 */
325#define PCR_ARCH_205 0x2 /* Architecture 2.05 */ 342#define PCR_ARCH_205 0x2 /* Architecture 2.05 */
326#define SPRN_HEIR 0x153 /* Hypervisor Emulated Instruction Register */ 343#define SPRN_HEIR 0x153 /* Hypervisor Emulated Instruction Register */
327#define SPRN_TLBINDEXR 0x154 /* P7 TLB control register */ 344#define SPRN_TLBINDEXR 0x154 /* P7 TLB control register */
@@ -368,6 +385,8 @@
368#define DER_EBRKE 0x00000002 /* External Breakpoint Interrupt */ 385#define DER_EBRKE 0x00000002 /* External Breakpoint Interrupt */
369#define DER_DPIE 0x00000001 /* Dev. Port Nonmaskable Request */ 386#define DER_DPIE 0x00000001 /* Dev. Port Nonmaskable Request */
370#define SPRN_DMISS 0x3D0 /* Data TLB Miss Register */ 387#define SPRN_DMISS 0x3D0 /* Data TLB Miss Register */
388#define SPRN_DHDES 0x0B1 /* Directed Hyp. Doorbell Exc. State */
389#define SPRN_DPDES 0x0B0 /* Directed Priv. Doorbell Exc. State */
371#define SPRN_EAR 0x11A /* External Address Register */ 390#define SPRN_EAR 0x11A /* External Address Register */
372#define SPRN_HASH1 0x3D2 /* Primary Hash Address Register */ 391#define SPRN_HASH1 0x3D2 /* Primary Hash Address Register */
373#define SPRN_HASH2 0x3D3 /* Secondary Hash Address Resgister */ 392#define SPRN_HASH2 0x3D3 /* Secondary Hash Address Resgister */
@@ -427,6 +446,7 @@
427#define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */ 446#define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */
428#define SPRN_IABR2 0x3FA /* 83xx */ 447#define SPRN_IABR2 0x3FA /* 83xx */
429#define SPRN_IBCR 0x135 /* 83xx Insn Breakpoint Control Reg */ 448#define SPRN_IBCR 0x135 /* 83xx Insn Breakpoint Control Reg */
449#define SPRN_IAMR 0x03D /* Instr. Authority Mask Reg */
430#define SPRN_HID4 0x3F4 /* 970 HID4 */ 450#define SPRN_HID4 0x3F4 /* 970 HID4 */
431#define HID4_LPES0 (1ul << (63-0)) /* LPAR env. sel. bit 0 */ 451#define HID4_LPES0 (1ul << (63-0)) /* LPAR env. sel. bit 0 */
432#define HID4_RMLS2_SH (63 - 2) /* Real mode limit bottom 2 bits */ 452#define HID4_RMLS2_SH (63 - 2) /* Real mode limit bottom 2 bits */
@@ -541,6 +561,7 @@
541#define SPRN_PIR 0x3FF /* Processor Identification Register */ 561#define SPRN_PIR 0x3FF /* Processor Identification Register */
542#endif 562#endif
543#define SPRN_TIR 0x1BE /* Thread Identification Register */ 563#define SPRN_TIR 0x1BE /* Thread Identification Register */
564#define SPRN_PSPB 0x09F /* Problem State Priority Boost reg */
544#define SPRN_PTEHI 0x3D5 /* 981 7450 PTE HI word (S/W TLB load) */ 565#define SPRN_PTEHI 0x3D5 /* 981 7450 PTE HI word (S/W TLB load) */
545#define SPRN_PTELO 0x3D6 /* 982 7450 PTE LO word (S/W TLB load) */ 566#define SPRN_PTELO 0x3D6 /* 982 7450 PTE LO word (S/W TLB load) */
546#define SPRN_PURR 0x135 /* Processor Utilization of Resources Reg */ 567#define SPRN_PURR 0x135 /* Processor Utilization of Resources Reg */
@@ -682,6 +703,7 @@
682#define SPRN_EBBHR 804 /* Event based branch handler register */ 703#define SPRN_EBBHR 804 /* Event based branch handler register */
683#define SPRN_EBBRR 805 /* Event based branch return register */ 704#define SPRN_EBBRR 805 /* Event based branch return register */
684#define SPRN_BESCR 806 /* Branch event status and control register */ 705#define SPRN_BESCR 806 /* Branch event status and control register */
706#define SPRN_WORT 895 /* Workload optimization register - thread */
685 707
686#define SPRN_PMC1 787 708#define SPRN_PMC1 787
687#define SPRN_PMC2 788 709#define SPRN_PMC2 788
@@ -698,6 +720,11 @@
698#define SIER_SIHV 0x1000000 /* Sampled MSR_HV */ 720#define SIER_SIHV 0x1000000 /* Sampled MSR_HV */
699#define SIER_SIAR_VALID 0x0400000 /* SIAR contents valid */ 721#define SIER_SIAR_VALID 0x0400000 /* SIAR contents valid */
700#define SIER_SDAR_VALID 0x0200000 /* SDAR contents valid */ 722#define SIER_SDAR_VALID 0x0200000 /* SDAR contents valid */
723#define SPRN_TACR 888
724#define SPRN_TCSCR 889
725#define SPRN_CSIGR 890
726#define SPRN_SPMC1 892
727#define SPRN_SPMC2 893
701 728
702/* When EBB is enabled, some of MMCR0/MMCR2/SIER are user accessible */ 729/* When EBB is enabled, some of MMCR0/MMCR2/SIER are user accessible */
703#define MMCR0_USER_MASK (MMCR0_FC | MMCR0_PMXE | MMCR0_PMAO) 730#define MMCR0_USER_MASK (MMCR0_FC | MMCR0_PMXE | MMCR0_PMAO)
@@ -1075,6 +1102,8 @@
1075#define PVR_8560 0x80200000 1102#define PVR_8560 0x80200000
1076#define PVR_VER_E500V1 0x8020 1103#define PVR_VER_E500V1 0x8020
1077#define PVR_VER_E500V2 0x8021 1104#define PVR_VER_E500V2 0x8021
1105#define PVR_VER_E6500 0x8040
1106
1078/* 1107/*
1079 * For the 8xx processors, all of them report the same PVR family for 1108 * For the 8xx processors, all of them report the same PVR family for
1080 * the PowerPC core. The various versions of these processors must be 1109 * the PowerPC core. The various versions of these processors must be
diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h
index 2e31aacd8acc..163c3b05a76e 100644
--- a/arch/powerpc/include/asm/reg_booke.h
+++ b/arch/powerpc/include/asm/reg_booke.h
@@ -101,6 +101,7 @@
101#define SPRN_IVOR39 0x1B1 /* Interrupt Vector Offset Register 39 */ 101#define SPRN_IVOR39 0x1B1 /* Interrupt Vector Offset Register 39 */
102#define SPRN_IVOR40 0x1B2 /* Interrupt Vector Offset Register 40 */ 102#define SPRN_IVOR40 0x1B2 /* Interrupt Vector Offset Register 40 */
103#define SPRN_IVOR41 0x1B3 /* Interrupt Vector Offset Register 41 */ 103#define SPRN_IVOR41 0x1B3 /* Interrupt Vector Offset Register 41 */
104#define SPRN_IVOR42 0x1B4 /* Interrupt Vector Offset Register 42 */
104#define SPRN_GIVOR2 0x1B8 /* Guest IVOR2 */ 105#define SPRN_GIVOR2 0x1B8 /* Guest IVOR2 */
105#define SPRN_GIVOR3 0x1B9 /* Guest IVOR3 */ 106#define SPRN_GIVOR3 0x1B9 /* Guest IVOR3 */
106#define SPRN_GIVOR4 0x1BA /* Guest IVOR4 */ 107#define SPRN_GIVOR4 0x1BA /* Guest IVOR4 */
@@ -170,6 +171,7 @@
170#define SPRN_L2CSR1 0x3FA /* L2 Data Cache Control and Status Register 1 */ 171#define SPRN_L2CSR1 0x3FA /* L2 Data Cache Control and Status Register 1 */
171#define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */ 172#define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */
172#define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */ 173#define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */
174#define SPRN_PWRMGTCR0 0x3FB /* Power management control register 0 */
173#define SPRN_SVR 0x3FF /* System Version Register */ 175#define SPRN_SVR 0x3FF /* System Version Register */
174 176
175/* 177/*
@@ -216,6 +218,14 @@
216#define CCR1_DPC 0x00000100 /* Disable L1 I-Cache/D-Cache parity checking */ 218#define CCR1_DPC 0x00000100 /* Disable L1 I-Cache/D-Cache parity checking */
217#define CCR1_TCS 0x00000080 /* Timer Clock Select */ 219#define CCR1_TCS 0x00000080 /* Timer Clock Select */
218 220
221/* Bit definitions for PWRMGTCR0. */
222#define PWRMGTCR0_PW20_WAIT (1 << 14) /* PW20 state enable bit */
223#define PWRMGTCR0_PW20_ENT_SHIFT 8
224#define PWRMGTCR0_PW20_ENT 0x3F00
225#define PWRMGTCR0_AV_IDLE_PD_EN (1 << 22) /* Altivec idle enable */
226#define PWRMGTCR0_AV_IDLE_CNT_SHIFT 16
227#define PWRMGTCR0_AV_IDLE_CNT 0x3F0000
228
219/* Bit definitions for the MCSR. */ 229/* Bit definitions for the MCSR. */
220#define MCSR_MCS 0x80000000 /* Machine Check Summary */ 230#define MCSR_MCS 0x80000000 /* Machine Check Summary */
221#define MCSR_IB 0x40000000 /* Instruction PLB Error */ 231#define MCSR_IB 0x40000000 /* Instruction PLB Error */
diff --git a/arch/powerpc/include/asm/sections.h b/arch/powerpc/include/asm/sections.h
index 4ee06fe15de4..d0e784e0ff48 100644
--- a/arch/powerpc/include/asm/sections.h
+++ b/arch/powerpc/include/asm/sections.h
@@ -8,6 +8,7 @@
8 8
9#ifdef __powerpc64__ 9#ifdef __powerpc64__
10 10
11extern char __start_interrupts[];
11extern char __end_interrupts[]; 12extern char __end_interrupts[];
12 13
13extern char __prom_init_toc_start[]; 14extern char __prom_init_toc_start[];
@@ -21,6 +22,17 @@ static inline int in_kernel_text(unsigned long addr)
21 return 0; 22 return 0;
22} 23}
23 24
25static inline int overlaps_interrupt_vector_text(unsigned long start,
26 unsigned long end)
27{
28 unsigned long real_start, real_end;
29 real_start = __start_interrupts - _stext;
30 real_end = __end_interrupts - _stext;
31
32 return start < (unsigned long)__va(real_end) &&
33 (unsigned long)__va(real_start) < end;
34}
35
24static inline int overlaps_kernel_text(unsigned long start, unsigned long end) 36static inline int overlaps_kernel_text(unsigned long start, unsigned long end)
25{ 37{
26 return start < (unsigned long)__init_end && 38 return start < (unsigned long)__init_end &&
diff --git a/arch/powerpc/include/asm/setup.h b/arch/powerpc/include/asm/setup.h
index 703a8412dac2..11ba86e17631 100644
--- a/arch/powerpc/include/asm/setup.h
+++ b/arch/powerpc/include/asm/setup.h
@@ -26,6 +26,7 @@ extern void reloc_got2(unsigned long);
26void check_for_initrd(void); 26void check_for_initrd(void);
27void do_init_bootmem(void); 27void do_init_bootmem(void);
28void setup_panic(void); 28void setup_panic(void);
29#define ARCH_PANIC_TIMEOUT 180
29 30
30#endif /* !__ASSEMBLY__ */ 31#endif /* !__ASSEMBLY__ */
31 32
diff --git a/arch/powerpc/include/asm/spinlock.h b/arch/powerpc/include/asm/spinlock.h
index 5f54a744dcc5..35aa339410bd 100644
--- a/arch/powerpc/include/asm/spinlock.h
+++ b/arch/powerpc/include/asm/spinlock.h
@@ -28,7 +28,7 @@
28#include <asm/synch.h> 28#include <asm/synch.h>
29#include <asm/ppc-opcode.h> 29#include <asm/ppc-opcode.h>
30 30
31#define arch_spin_is_locked(x) ((x)->slock != 0) 31#define smp_mb__after_unlock_lock() smp_mb() /* Full ordering for lock. */
32 32
33#ifdef CONFIG_PPC64 33#ifdef CONFIG_PPC64
34/* use 0x800000yy when locked, where yy == CPU number */ 34/* use 0x800000yy when locked, where yy == CPU number */
@@ -54,6 +54,16 @@
54#define SYNC_IO 54#define SYNC_IO
55#endif 55#endif
56 56
57static __always_inline int arch_spin_value_unlocked(arch_spinlock_t lock)
58{
59 return lock.slock == 0;
60}
61
62static inline int arch_spin_is_locked(arch_spinlock_t *lock)
63{
64 return !arch_spin_value_unlocked(*lock);
65}
66
57/* 67/*
58 * This returns the old value in the lock, so we succeeded 68 * This returns the old value in the lock, so we succeeded
59 * in getting the lock if the return value is 0. 69 * in getting the lock if the return value is 0.
diff --git a/arch/powerpc/include/asm/switch_to.h b/arch/powerpc/include/asm/switch_to.h
index aace90547614..0e83e7d8c73f 100644
--- a/arch/powerpc/include/asm/switch_to.h
+++ b/arch/powerpc/include/asm/switch_to.h
@@ -25,10 +25,8 @@ static inline void save_tar(struct thread_struct *prev)
25static inline void save_tar(struct thread_struct *prev) {} 25static inline void save_tar(struct thread_struct *prev) {}
26#endif 26#endif
27 27
28extern void load_up_fpu(void);
29extern void enable_kernel_fp(void); 28extern void enable_kernel_fp(void);
30extern void enable_kernel_altivec(void); 29extern void enable_kernel_altivec(void);
31extern void load_up_altivec(struct task_struct *);
32extern int emulate_altivec(struct pt_regs *); 30extern int emulate_altivec(struct pt_regs *);
33extern void __giveup_vsx(struct task_struct *); 31extern void __giveup_vsx(struct task_struct *);
34extern void giveup_vsx(struct task_struct *); 32extern void giveup_vsx(struct task_struct *);
diff --git a/arch/powerpc/include/asm/systbl.h b/arch/powerpc/include/asm/systbl.h
index 43523fe0d8b4..3ddf70276706 100644
--- a/arch/powerpc/include/asm/systbl.h
+++ b/arch/powerpc/include/asm/systbl.h
@@ -359,3 +359,5 @@ COMPAT_SYS(process_vm_readv)
359COMPAT_SYS(process_vm_writev) 359COMPAT_SYS(process_vm_writev)
360SYSCALL(finit_module) 360SYSCALL(finit_module)
361SYSCALL(ni_syscall) /* sys_kcmp */ 361SYSCALL(ni_syscall) /* sys_kcmp */
362SYSCALL_SPU(sched_setattr)
363SYSCALL_SPU(sched_getattr)
diff --git a/arch/powerpc/include/asm/thread_info.h b/arch/powerpc/include/asm/thread_info.h
index 9854c564ac52..b034ecdb7c74 100644
--- a/arch/powerpc/include/asm/thread_info.h
+++ b/arch/powerpc/include/asm/thread_info.h
@@ -91,8 +91,7 @@ static inline struct thread_info *current_thread_info(void)
91#define TIF_POLLING_NRFLAG 3 /* true if poll_idle() is polling 91#define TIF_POLLING_NRFLAG 3 /* true if poll_idle() is polling
92 TIF_NEED_RESCHED */ 92 TIF_NEED_RESCHED */
93#define TIF_32BIT 4 /* 32 bit binary */ 93#define TIF_32BIT 4 /* 32 bit binary */
94#define TIF_PERFMON_WORK 5 /* work for pfm_handle_work() */ 94#define TIF_RESTORE_TM 5 /* need to restore TM FP/VEC/VSX */
95#define TIF_PERFMON_CTXSW 6 /* perfmon needs ctxsw calls */
96#define TIF_SYSCALL_AUDIT 7 /* syscall auditing active */ 95#define TIF_SYSCALL_AUDIT 7 /* syscall auditing active */
97#define TIF_SINGLESTEP 8 /* singlestepping active */ 96#define TIF_SINGLESTEP 8 /* singlestepping active */
98#define TIF_NOHZ 9 /* in adaptive nohz mode */ 97#define TIF_NOHZ 9 /* in adaptive nohz mode */
@@ -115,8 +114,7 @@ static inline struct thread_info *current_thread_info(void)
115#define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED) 114#define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED)
116#define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG) 115#define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG)
117#define _TIF_32BIT (1<<TIF_32BIT) 116#define _TIF_32BIT (1<<TIF_32BIT)
118#define _TIF_PERFMON_WORK (1<<TIF_PERFMON_WORK) 117#define _TIF_RESTORE_TM (1<<TIF_RESTORE_TM)
119#define _TIF_PERFMON_CTXSW (1<<TIF_PERFMON_CTXSW)
120#define _TIF_SYSCALL_AUDIT (1<<TIF_SYSCALL_AUDIT) 118#define _TIF_SYSCALL_AUDIT (1<<TIF_SYSCALL_AUDIT)
121#define _TIF_SINGLESTEP (1<<TIF_SINGLESTEP) 119#define _TIF_SINGLESTEP (1<<TIF_SINGLESTEP)
122#define _TIF_SECCOMP (1<<TIF_SECCOMP) 120#define _TIF_SECCOMP (1<<TIF_SECCOMP)
@@ -132,7 +130,8 @@ static inline struct thread_info *current_thread_info(void)
132 _TIF_NOHZ) 130 _TIF_NOHZ)
133 131
134#define _TIF_USER_WORK_MASK (_TIF_SIGPENDING | _TIF_NEED_RESCHED | \ 132#define _TIF_USER_WORK_MASK (_TIF_SIGPENDING | _TIF_NEED_RESCHED | \
135 _TIF_NOTIFY_RESUME | _TIF_UPROBE) 133 _TIF_NOTIFY_RESUME | _TIF_UPROBE | \
134 _TIF_RESTORE_TM)
136#define _TIF_PERSYSCALL_MASK (_TIF_RESTOREALL|_TIF_NOERROR) 135#define _TIF_PERSYSCALL_MASK (_TIF_RESTOREALL|_TIF_NOERROR)
137 136
138/* Bits in local_flags */ 137/* Bits in local_flags */
diff --git a/arch/powerpc/include/asm/tm.h b/arch/powerpc/include/asm/tm.h
index 9dfbc34bdbf5..0c9f8b74dd97 100644
--- a/arch/powerpc/include/asm/tm.h
+++ b/arch/powerpc/include/asm/tm.h
@@ -15,6 +15,7 @@ extern void do_load_up_transact_altivec(struct thread_struct *thread);
15extern void tm_enable(void); 15extern void tm_enable(void);
16extern void tm_reclaim(struct thread_struct *thread, 16extern void tm_reclaim(struct thread_struct *thread,
17 unsigned long orig_msr, uint8_t cause); 17 unsigned long orig_msr, uint8_t cause);
18extern void tm_reclaim_current(uint8_t cause);
18extern void tm_recheckpoint(struct thread_struct *thread, 19extern void tm_recheckpoint(struct thread_struct *thread,
19 unsigned long orig_msr); 20 unsigned long orig_msr);
20extern void tm_abort(uint8_t cause); 21extern void tm_abort(uint8_t cause);
diff --git a/arch/powerpc/include/asm/topology.h b/arch/powerpc/include/asm/topology.h
index 89e3ef2496ac..d0b5fca6b077 100644
--- a/arch/powerpc/include/asm/topology.h
+++ b/arch/powerpc/include/asm/topology.h
@@ -22,7 +22,15 @@ struct device_node;
22 22
23static inline int cpu_to_node(int cpu) 23static inline int cpu_to_node(int cpu)
24{ 24{
25 return numa_cpu_lookup_table[cpu]; 25 int nid;
26
27 nid = numa_cpu_lookup_table[cpu];
28
29 /*
30 * During early boot, the numa-cpu lookup table might not have been
31 * setup for all CPUs yet. In such cases, default to node 0.
32 */
33 return (nid < 0) ? 0 : nid;
26} 34}
27 35
28#define parent_node(node) (node) 36#define parent_node(node) (node)
diff --git a/arch/powerpc/include/asm/unistd.h b/arch/powerpc/include/asm/unistd.h
index 3ca819f541bf..4494f029b632 100644
--- a/arch/powerpc/include/asm/unistd.h
+++ b/arch/powerpc/include/asm/unistd.h
@@ -12,7 +12,7 @@
12#include <uapi/asm/unistd.h> 12#include <uapi/asm/unistd.h>
13 13
14 14
15#define __NR_syscalls 355 15#define __NR_syscalls 357
16 16
17#define __NR__exit __NR_exit 17#define __NR__exit __NR_exit
18#define NR_syscalls __NR_syscalls 18#define NR_syscalls __NR_syscalls
diff --git a/arch/powerpc/include/asm/uprobes.h b/arch/powerpc/include/asm/uprobes.h
index 75c6ecdb8f37..7422a999a39a 100644
--- a/arch/powerpc/include/asm/uprobes.h
+++ b/arch/powerpc/include/asm/uprobes.h
@@ -36,9 +36,8 @@ typedef ppc_opcode_t uprobe_opcode_t;
36 36
37struct arch_uprobe { 37struct arch_uprobe {
38 union { 38 union {
39 u8 insn[MAX_UINSN_BYTES]; 39 u32 insn;
40 u8 ixol[MAX_UINSN_BYTES]; 40 u32 ixol;
41 u32 ainsn;
42 }; 41 };
43}; 42};
44 43
diff --git a/arch/powerpc/include/asm/vdso.h b/arch/powerpc/include/asm/vdso.h
index 0d9cecddf8a4..c53f5f6d1761 100644
--- a/arch/powerpc/include/asm/vdso.h
+++ b/arch/powerpc/include/asm/vdso.h
@@ -4,11 +4,11 @@
4#ifdef __KERNEL__ 4#ifdef __KERNEL__
5 5
6/* Default link addresses for the vDSOs */ 6/* Default link addresses for the vDSOs */
7#define VDSO32_LBASE 0x100000 7#define VDSO32_LBASE 0x0
8#define VDSO64_LBASE 0x100000 8#define VDSO64_LBASE 0x0
9 9
10/* Default map addresses for 32bit vDSO */ 10/* Default map addresses for 32bit vDSO */
11#define VDSO32_MBASE VDSO32_LBASE 11#define VDSO32_MBASE 0x100000
12 12
13#define VDSO_VERSION_STRING LINUX_2.6.15 13#define VDSO_VERSION_STRING LINUX_2.6.15
14 14
diff --git a/arch/powerpc/include/asm/vio.h b/arch/powerpc/include/asm/vio.h
index 68d0cc998b1b..4f9b7ca0710f 100644
--- a/arch/powerpc/include/asm/vio.h
+++ b/arch/powerpc/include/asm/vio.h
@@ -15,7 +15,6 @@
15#define _ASM_POWERPC_VIO_H 15#define _ASM_POWERPC_VIO_H
16#ifdef __KERNEL__ 16#ifdef __KERNEL__
17 17
18#include <linux/init.h>
19#include <linux/errno.h> 18#include <linux/errno.h>
20#include <linux/device.h> 19#include <linux/device.h>
21#include <linux/dma-mapping.h> 20#include <linux/dma-mapping.h>
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-06 17:17:12 -0500