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-rw-r--r--arch/powerpc/include/asm/8xx_immap.h4
-rw-r--r--arch/powerpc/include/asm/cputable.h65
-rw-r--r--arch/powerpc/include/asm/cputhreads.h12
-rw-r--r--arch/powerpc/include/asm/dbell.h3
-rw-r--r--arch/powerpc/include/asm/emulated_ops.h4
-rw-r--r--arch/powerpc/include/asm/exception-64s.h113
-rw-r--r--arch/powerpc/include/asm/feature-fixups.h15
-rw-r--r--arch/powerpc/include/asm/firmware.h3
-rw-r--r--arch/powerpc/include/asm/hvcall.h12
-rw-r--r--arch/powerpc/include/asm/io-workarounds.h48
-rw-r--r--arch/powerpc/include/asm/io.h33
-rw-r--r--arch/powerpc/include/asm/io_event_irq.h54
-rw-r--r--arch/powerpc/include/asm/irq.h18
-rw-r--r--arch/powerpc/include/asm/kexec.h2
-rw-r--r--arch/powerpc/include/asm/kvm.h184
-rw-r--r--arch/powerpc/include/asm/kvm_44x.h1
-rw-r--r--arch/powerpc/include/asm/kvm_asm.h1
-rw-r--r--arch/powerpc/include/asm/kvm_book3s_asm.h1
-rw-r--r--arch/powerpc/include/asm/kvm_e500.h2
-rw-r--r--arch/powerpc/include/asm/kvm_host.h5
-rw-r--r--arch/powerpc/include/asm/kvm_ppc.h9
-rw-r--r--arch/powerpc/include/asm/lppaca.h2
-rw-r--r--arch/powerpc/include/asm/machdep.h22
-rw-r--r--arch/powerpc/include/asm/mmu-book3e.h20
-rw-r--r--arch/powerpc/include/asm/mmu-hash64.h6
-rw-r--r--arch/powerpc/include/asm/mmu.h52
-rw-r--r--arch/powerpc/include/asm/mmu_context.h12
-rw-r--r--arch/powerpc/include/asm/mpic.h8
-rw-r--r--arch/powerpc/include/asm/pSeries_reconfig.h5
-rw-r--r--arch/powerpc/include/asm/paca.h11
-rw-r--r--arch/powerpc/include/asm/page_64.h21
-rw-r--r--arch/powerpc/include/asm/pgtable-ppc64.h13
-rw-r--r--arch/powerpc/include/asm/ppc-opcode.h35
-rw-r--r--arch/powerpc/include/asm/ppc_asm.h1
-rw-r--r--arch/powerpc/include/asm/processor.h4
-rw-r--r--arch/powerpc/include/asm/pte-common.h2
-rw-r--r--arch/powerpc/include/asm/pte-hash64-64k.h2
-rw-r--r--arch/powerpc/include/asm/reg.h104
-rw-r--r--arch/powerpc/include/asm/reg_a2.h165
-rw-r--r--arch/powerpc/include/asm/reg_booke.h10
-rw-r--r--arch/powerpc/include/asm/rtas.h45
-rw-r--r--arch/powerpc/include/asm/scom.h156
-rw-r--r--arch/powerpc/include/asm/smp.h38
-rw-r--r--arch/powerpc/include/asm/systbl.h1
-rw-r--r--arch/powerpc/include/asm/system.h2
-rw-r--r--arch/powerpc/include/asm/tlbflush.h2
-rw-r--r--arch/powerpc/include/asm/udbg.h1
-rw-r--r--arch/powerpc/include/asm/uninorth.h2
-rw-r--r--arch/powerpc/include/asm/unistd.h3
-rw-r--r--arch/powerpc/include/asm/wsp.h14
-rw-r--r--arch/powerpc/include/asm/xics.h142
51 files changed, 1295 insertions, 195 deletions
diff --git a/arch/powerpc/include/asm/8xx_immap.h b/arch/powerpc/include/asm/8xx_immap.h
index 6b6dc20b0beb..bdf0563ba423 100644
--- a/arch/powerpc/include/asm/8xx_immap.h
+++ b/arch/powerpc/include/asm/8xx_immap.h
@@ -393,8 +393,8 @@ typedef struct fec {
393 uint fec_addr_low; /* lower 32 bits of station address */ 393 uint fec_addr_low; /* lower 32 bits of station address */
394 ushort fec_addr_high; /* upper 16 bits of station address */ 394 ushort fec_addr_high; /* upper 16 bits of station address */
395 ushort res1; /* reserved */ 395 ushort res1; /* reserved */
396 uint fec_hash_table_high; /* upper 32-bits of hash table */ 396 uint fec_grp_hash_table_high; /* upper 32-bits of hash table */
397 uint fec_hash_table_low; /* lower 32-bits of hash table */ 397 uint fec_grp_hash_table_low; /* lower 32-bits of hash table */
398 uint fec_r_des_start; /* beginning of Rx descriptor ring */ 398 uint fec_r_des_start; /* beginning of Rx descriptor ring */
399 uint fec_x_des_start; /* beginning of Tx descriptor ring */ 399 uint fec_x_des_start; /* beginning of Tx descriptor ring */
400 uint fec_r_buff_size; /* Rx buffer size */ 400 uint fec_r_buff_size; /* Rx buffer size */
diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h
index be3cdf9134ce..c0d842cfd012 100644
--- a/arch/powerpc/include/asm/cputable.h
+++ b/arch/powerpc/include/asm/cputable.h
@@ -157,6 +157,7 @@ extern const char *powerpc_base_platform;
157#define CPU_FTR_476_DD2 ASM_CONST(0x0000000000010000) 157#define CPU_FTR_476_DD2 ASM_CONST(0x0000000000010000)
158#define CPU_FTR_NEED_COHERENT ASM_CONST(0x0000000000020000) 158#define CPU_FTR_NEED_COHERENT ASM_CONST(0x0000000000020000)
159#define CPU_FTR_NO_BTIC ASM_CONST(0x0000000000040000) 159#define CPU_FTR_NO_BTIC ASM_CONST(0x0000000000040000)
160#define CPU_FTR_DEBUG_LVL_EXC ASM_CONST(0x0000000000080000)
160#define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000000000100000) 161#define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000000000100000)
161#define CPU_FTR_PPC_LE ASM_CONST(0x0000000000200000) 162#define CPU_FTR_PPC_LE ASM_CONST(0x0000000000200000)
162#define CPU_FTR_REAL_LE ASM_CONST(0x0000000000400000) 163#define CPU_FTR_REAL_LE ASM_CONST(0x0000000000400000)
@@ -178,22 +179,18 @@ extern const char *powerpc_base_platform;
178#define LONG_ASM_CONST(x) 0 179#define LONG_ASM_CONST(x) 0
179#endif 180#endif
180 181
181#define CPU_FTR_SLB LONG_ASM_CONST(0x0000000100000000) 182
182#define CPU_FTR_16M_PAGE LONG_ASM_CONST(0x0000000200000000) 183#define CPU_FTR_HVMODE_206 LONG_ASM_CONST(0x0000000800000000)
183#define CPU_FTR_TLBIEL LONG_ASM_CONST(0x0000000400000000) 184#define CPU_FTR_CFAR LONG_ASM_CONST(0x0000001000000000)
184#define CPU_FTR_IABR LONG_ASM_CONST(0x0000002000000000) 185#define CPU_FTR_IABR LONG_ASM_CONST(0x0000002000000000)
185#define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000004000000000) 186#define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000004000000000)
186#define CPU_FTR_CTRL LONG_ASM_CONST(0x0000008000000000) 187#define CPU_FTR_CTRL LONG_ASM_CONST(0x0000008000000000)
187#define CPU_FTR_SMT LONG_ASM_CONST(0x0000010000000000) 188#define CPU_FTR_SMT LONG_ASM_CONST(0x0000010000000000)
188#define CPU_FTR_LOCKLESS_TLBIE LONG_ASM_CONST(0x0000040000000000)
189#define CPU_FTR_CI_LARGE_PAGE LONG_ASM_CONST(0x0000100000000000)
190#define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000200000000000) 189#define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000200000000000)
191#define CPU_FTR_PURR LONG_ASM_CONST(0x0000400000000000) 190#define CPU_FTR_PURR LONG_ASM_CONST(0x0000400000000000)
192#define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000800000000000) 191#define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000800000000000)
193#define CPU_FTR_SPURR LONG_ASM_CONST(0x0001000000000000) 192#define CPU_FTR_SPURR LONG_ASM_CONST(0x0001000000000000)
194#define CPU_FTR_DSCR LONG_ASM_CONST(0x0002000000000000) 193#define CPU_FTR_DSCR LONG_ASM_CONST(0x0002000000000000)
195#define CPU_FTR_1T_SEGMENT LONG_ASM_CONST(0x0004000000000000)
196#define CPU_FTR_NO_SLBIE_B LONG_ASM_CONST(0x0008000000000000)
197#define CPU_FTR_VSX LONG_ASM_CONST(0x0010000000000000) 194#define CPU_FTR_VSX LONG_ASM_CONST(0x0010000000000000)
198#define CPU_FTR_SAO LONG_ASM_CONST(0x0020000000000000) 195#define CPU_FTR_SAO LONG_ASM_CONST(0x0020000000000000)
199#define CPU_FTR_CP_USE_DCBTZ LONG_ASM_CONST(0x0040000000000000) 196#define CPU_FTR_CP_USE_DCBTZ LONG_ASM_CONST(0x0040000000000000)
@@ -202,12 +199,14 @@ extern const char *powerpc_base_platform;
202#define CPU_FTR_STCX_CHECKS_ADDRESS LONG_ASM_CONST(0x0200000000000000) 199#define CPU_FTR_STCX_CHECKS_ADDRESS LONG_ASM_CONST(0x0200000000000000)
203#define CPU_FTR_POPCNTB LONG_ASM_CONST(0x0400000000000000) 200#define CPU_FTR_POPCNTB LONG_ASM_CONST(0x0400000000000000)
204#define CPU_FTR_POPCNTD LONG_ASM_CONST(0x0800000000000000) 201#define CPU_FTR_POPCNTD LONG_ASM_CONST(0x0800000000000000)
202#define CPU_FTR_ICSWX LONG_ASM_CONST(0x1000000000000000)
205 203
206#ifndef __ASSEMBLY__ 204#ifndef __ASSEMBLY__
207 205
208#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_SLB | \ 206#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN)
209 CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \ 207
210 CPU_FTR_NODSISRALIGN | CPU_FTR_16M_PAGE) 208#define MMU_FTR_PPCAS_ARCH_V2 (MMU_FTR_SLB | MMU_FTR_TLBIEL | \
209 MMU_FTR_16M_PAGE)
211 210
212/* We only set the altivec features if the kernel was compiled with altivec 211/* We only set the altivec features if the kernel was compiled with altivec
213 * support 212 * support
@@ -382,10 +381,13 @@ extern const char *powerpc_base_platform;
382#define CPU_FTRS_E500_2 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \ 381#define CPU_FTRS_E500_2 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
383 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | \ 382 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | \
384 CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE) 383 CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
385#define CPU_FTRS_E500MC (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \ 384#define CPU_FTRS_E500MC (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
386 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN | \
387 CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \ 385 CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
388 CPU_FTR_DBELL) 386 CPU_FTR_DBELL)
387#define CPU_FTRS_E5500 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
388 CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
389 CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
390 CPU_FTR_DEBUG_LVL_EXC)
389#define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN) 391#define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
390 392
391/* 64-bit CPUs */ 393/* 64-bit CPUs */
@@ -405,41 +407,46 @@ extern const char *powerpc_base_platform;
405#define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ 407#define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
406 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ 408 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
407 CPU_FTR_MMCRA | CPU_FTR_SMT | \ 409 CPU_FTR_MMCRA | CPU_FTR_SMT | \
408 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \ 410 CPU_FTR_COHERENT_ICACHE | CPU_FTR_PURR | \
409 CPU_FTR_PURR | CPU_FTR_STCX_CHECKS_ADDRESS | \ 411 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB)
410 CPU_FTR_POPCNTB)
411#define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ 412#define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
412 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ 413 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
413 CPU_FTR_MMCRA | CPU_FTR_SMT | \ 414 CPU_FTR_MMCRA | CPU_FTR_SMT | \
414 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \ 415 CPU_FTR_COHERENT_ICACHE | \
415 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ 416 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
416 CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \ 417 CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \
417 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB) 418 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_CFAR)
418#define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ 419#define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
419 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ 420 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_HVMODE_206 |\
420 CPU_FTR_MMCRA | CPU_FTR_SMT | \ 421 CPU_FTR_MMCRA | CPU_FTR_SMT | \
421 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \ 422 CPU_FTR_COHERENT_ICACHE | \
422 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ 423 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
423 CPU_FTR_DSCR | CPU_FTR_SAO | CPU_FTR_ASYM_SMT | \ 424 CPU_FTR_DSCR | CPU_FTR_SAO | CPU_FTR_ASYM_SMT | \
424 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD) 425 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
426 CPU_FTR_ICSWX | CPU_FTR_CFAR)
425#define CPU_FTRS_CELL (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ 427#define CPU_FTRS_CELL (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
426 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ 428 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
427 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \ 429 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
428 CPU_FTR_PAUSE_ZERO | CPU_FTR_CI_LARGE_PAGE | \ 430 CPU_FTR_PAUSE_ZERO | CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \
429 CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \
430 CPU_FTR_UNALIGNED_LD_STD) 431 CPU_FTR_UNALIGNED_LD_STD)
431#define CPU_FTRS_PA6T (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ 432#define CPU_FTRS_PA6T (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
432 CPU_FTR_PPCAS_ARCH_V2 | \ 433 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | \
433 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CI_LARGE_PAGE | \ 434 CPU_FTR_PURR | CPU_FTR_REAL_LE)
434 CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_NO_SLBIE_B)
435#define CPU_FTRS_COMPATIBLE (CPU_FTR_USE_TB | CPU_FTR_PPCAS_ARCH_V2) 435#define CPU_FTRS_COMPATIBLE (CPU_FTR_USE_TB | CPU_FTR_PPCAS_ARCH_V2)
436 436
437#define CPU_FTRS_A2 (CPU_FTR_USE_TB | CPU_FTR_SMT | CPU_FTR_DBELL | \
438 CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN)
439
437#ifdef __powerpc64__ 440#ifdef __powerpc64__
441#ifdef CONFIG_PPC_BOOK3E
442#define CPU_FTRS_POSSIBLE (CPU_FTRS_E5500 | CPU_FTRS_A2)
443#else
438#define CPU_FTRS_POSSIBLE \ 444#define CPU_FTRS_POSSIBLE \
439 (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 | \ 445 (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 | \
440 CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 | \ 446 CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 | \
441 CPU_FTRS_POWER7 | CPU_FTRS_CELL | CPU_FTRS_PA6T | \ 447 CPU_FTRS_POWER7 | CPU_FTRS_CELL | CPU_FTRS_PA6T | \
442 CPU_FTR_1T_SEGMENT | CPU_FTR_VSX) 448 CPU_FTR_VSX)
449#endif
443#else 450#else
444enum { 451enum {
445 CPU_FTRS_POSSIBLE = 452 CPU_FTRS_POSSIBLE =
@@ -473,16 +480,21 @@ enum {
473#endif 480#endif
474#ifdef CONFIG_E500 481#ifdef CONFIG_E500
475 CPU_FTRS_E500 | CPU_FTRS_E500_2 | CPU_FTRS_E500MC | 482 CPU_FTRS_E500 | CPU_FTRS_E500_2 | CPU_FTRS_E500MC |
483 CPU_FTRS_E5500 |
476#endif 484#endif
477 0, 485 0,
478}; 486};
479#endif /* __powerpc64__ */ 487#endif /* __powerpc64__ */
480 488
481#ifdef __powerpc64__ 489#ifdef __powerpc64__
490#ifdef CONFIG_PPC_BOOK3E
491#define CPU_FTRS_ALWAYS (CPU_FTRS_E5500 & CPU_FTRS_A2)
492#else
482#define CPU_FTRS_ALWAYS \ 493#define CPU_FTRS_ALWAYS \
483 (CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 & \ 494 (CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 & \
484 CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_POWER6 & \ 495 CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_POWER6 & \
485 CPU_FTRS_POWER7 & CPU_FTRS_CELL & CPU_FTRS_PA6T & CPU_FTRS_POSSIBLE) 496 CPU_FTRS_POWER7 & CPU_FTRS_CELL & CPU_FTRS_PA6T & CPU_FTRS_POSSIBLE)
497#endif
486#else 498#else
487enum { 499enum {
488 CPU_FTRS_ALWAYS = 500 CPU_FTRS_ALWAYS =
@@ -513,6 +525,7 @@ enum {
513#endif 525#endif
514#ifdef CONFIG_E500 526#ifdef CONFIG_E500
515 CPU_FTRS_E500 & CPU_FTRS_E500_2 & CPU_FTRS_E500MC & 527 CPU_FTRS_E500 & CPU_FTRS_E500_2 & CPU_FTRS_E500MC &
528 CPU_FTRS_E5500 &
516#endif 529#endif
517 CPU_FTRS_POSSIBLE, 530 CPU_FTRS_POSSIBLE,
518}; 531};
diff --git a/arch/powerpc/include/asm/cputhreads.h b/arch/powerpc/include/asm/cputhreads.h
index f71bb4c118b4..ce516e5eb0d3 100644
--- a/arch/powerpc/include/asm/cputhreads.h
+++ b/arch/powerpc/include/asm/cputhreads.h
@@ -37,16 +37,16 @@ extern cpumask_t threads_core_mask;
37 * This can typically be used for things like IPI for tlb invalidations 37 * This can typically be used for things like IPI for tlb invalidations
38 * since those need to be done only once per core/TLB 38 * since those need to be done only once per core/TLB
39 */ 39 */
40static inline cpumask_t cpu_thread_mask_to_cores(cpumask_t threads) 40static inline cpumask_t cpu_thread_mask_to_cores(const struct cpumask *threads)
41{ 41{
42 cpumask_t tmp, res; 42 cpumask_t tmp, res;
43 int i; 43 int i;
44 44
45 res = CPU_MASK_NONE; 45 cpumask_clear(&res);
46 for (i = 0; i < NR_CPUS; i += threads_per_core) { 46 for (i = 0; i < NR_CPUS; i += threads_per_core) {
47 cpus_shift_left(tmp, threads_core_mask, i); 47 cpumask_shift_left(&tmp, &threads_core_mask, i);
48 if (cpus_intersects(threads, tmp)) 48 if (cpumask_intersects(threads, &tmp))
49 cpu_set(i, res); 49 cpumask_set_cpu(i, &res);
50 } 50 }
51 return res; 51 return res;
52} 52}
@@ -58,7 +58,7 @@ static inline int cpu_nr_cores(void)
58 58
59static inline cpumask_t cpu_online_cores_map(void) 59static inline cpumask_t cpu_online_cores_map(void)
60{ 60{
61 return cpu_thread_mask_to_cores(cpu_online_map); 61 return cpu_thread_mask_to_cores(cpu_online_mask);
62} 62}
63 63
64#ifdef CONFIG_SMP 64#ifdef CONFIG_SMP
diff --git a/arch/powerpc/include/asm/dbell.h b/arch/powerpc/include/asm/dbell.h
index 0893ab9343a6..9c70d0ca96d4 100644
--- a/arch/powerpc/include/asm/dbell.h
+++ b/arch/powerpc/include/asm/dbell.h
@@ -27,9 +27,8 @@ enum ppc_dbell {
27 PPC_G_DBELL_MC = 4, /* guest mcheck doorbell */ 27 PPC_G_DBELL_MC = 4, /* guest mcheck doorbell */
28}; 28};
29 29
30extern void doorbell_message_pass(int target, int msg); 30extern void doorbell_cause_ipi(int cpu, unsigned long data);
31extern void doorbell_exception(struct pt_regs *regs); 31extern void doorbell_exception(struct pt_regs *regs);
32extern void doorbell_check_self(void);
33extern void doorbell_setup_this_cpu(void); 32extern void doorbell_setup_this_cpu(void);
34 33
35static inline void ppc_msgsnd(enum ppc_dbell type, u32 flags, u32 tag) 34static inline void ppc_msgsnd(enum ppc_dbell type, u32 flags, u32 tag)
diff --git a/arch/powerpc/include/asm/emulated_ops.h b/arch/powerpc/include/asm/emulated_ops.h
index f0fb4fc1f6e6..45921672b97a 100644
--- a/arch/powerpc/include/asm/emulated_ops.h
+++ b/arch/powerpc/include/asm/emulated_ops.h
@@ -52,6 +52,10 @@ extern struct ppc_emulated {
52#ifdef CONFIG_VSX 52#ifdef CONFIG_VSX
53 struct ppc_emulated_entry vsx; 53 struct ppc_emulated_entry vsx;
54#endif 54#endif
55#ifdef CONFIG_PPC64
56 struct ppc_emulated_entry mfdscr;
57 struct ppc_emulated_entry mtdscr;
58#endif
55} ppc_emulated; 59} ppc_emulated;
56 60
57extern u32 ppc_warn_emulated; 61extern u32 ppc_warn_emulated;
diff --git a/arch/powerpc/include/asm/exception-64s.h b/arch/powerpc/include/asm/exception-64s.h
index 7778d6f0c878..f5dfe3411f64 100644
--- a/arch/powerpc/include/asm/exception-64s.h
+++ b/arch/powerpc/include/asm/exception-64s.h
@@ -46,6 +46,7 @@
46#define EX_CCR 60 46#define EX_CCR 60
47#define EX_R3 64 47#define EX_R3 64
48#define EX_LR 72 48#define EX_LR 72
49#define EX_CFAR 80
49 50
50/* 51/*
51 * We're short on space and time in the exception prolog, so we can't 52 * We're short on space and time in the exception prolog, so we can't
@@ -56,30 +57,40 @@
56#define LOAD_HANDLER(reg, label) \ 57#define LOAD_HANDLER(reg, label) \
57 addi reg,reg,(label)-_stext; /* virt addr of handler ... */ 58 addi reg,reg,(label)-_stext; /* virt addr of handler ... */
58 59
59#define EXCEPTION_PROLOG_1(area) \ 60/* Exception register prefixes */
60 mfspr r13,SPRN_SPRG_PACA; /* get paca address into r13 */ \ 61#define EXC_HV H
62#define EXC_STD
63
64#define EXCEPTION_PROLOG_1(area) \
65 GET_PACA(r13); \
61 std r9,area+EX_R9(r13); /* save r9 - r12 */ \ 66 std r9,area+EX_R9(r13); /* save r9 - r12 */ \
62 std r10,area+EX_R10(r13); \ 67 std r10,area+EX_R10(r13); \
63 std r11,area+EX_R11(r13); \ 68 std r11,area+EX_R11(r13); \
64 std r12,area+EX_R12(r13); \ 69 std r12,area+EX_R12(r13); \
65 mfspr r9,SPRN_SPRG_SCRATCH0; \ 70 BEGIN_FTR_SECTION_NESTED(66); \
71 mfspr r10,SPRN_CFAR; \
72 std r10,area+EX_CFAR(r13); \
73 END_FTR_SECTION_NESTED(CPU_FTR_CFAR, CPU_FTR_CFAR, 66); \
74 GET_SCRATCH0(r9); \
66 std r9,area+EX_R13(r13); \ 75 std r9,area+EX_R13(r13); \
67 mfcr r9 76 mfcr r9
68 77
69#define EXCEPTION_PROLOG_PSERIES_1(label) \ 78#define __EXCEPTION_PROLOG_PSERIES_1(label, h) \
70 ld r12,PACAKBASE(r13); /* get high part of &label */ \ 79 ld r12,PACAKBASE(r13); /* get high part of &label */ \
71 ld r10,PACAKMSR(r13); /* get MSR value for kernel */ \ 80 ld r10,PACAKMSR(r13); /* get MSR value for kernel */ \
72 mfspr r11,SPRN_SRR0; /* save SRR0 */ \ 81 mfspr r11,SPRN_##h##SRR0; /* save SRR0 */ \
73 LOAD_HANDLER(r12,label) \ 82 LOAD_HANDLER(r12,label) \
74 mtspr SPRN_SRR0,r12; \ 83 mtspr SPRN_##h##SRR0,r12; \
75 mfspr r12,SPRN_SRR1; /* and SRR1 */ \ 84 mfspr r12,SPRN_##h##SRR1; /* and SRR1 */ \
76 mtspr SPRN_SRR1,r10; \ 85 mtspr SPRN_##h##SRR1,r10; \
77 rfid; \ 86 h##rfid; \
78 b . /* prevent speculative execution */ 87 b . /* prevent speculative execution */
88#define EXCEPTION_PROLOG_PSERIES_1(label, h) \
89 __EXCEPTION_PROLOG_PSERIES_1(label, h)
79 90
80#define EXCEPTION_PROLOG_PSERIES(area, label) \ 91#define EXCEPTION_PROLOG_PSERIES(area, label, h) \
81 EXCEPTION_PROLOG_1(area); \ 92 EXCEPTION_PROLOG_1(area); \
82 EXCEPTION_PROLOG_PSERIES_1(label); 93 EXCEPTION_PROLOG_PSERIES_1(label, h);
83 94
84/* 95/*
85 * The common exception prolog is used for all except a few exceptions 96 * The common exception prolog is used for all except a few exceptions
@@ -98,10 +109,11 @@
98 beq- 1f; \ 109 beq- 1f; \
99 ld r1,PACAKSAVE(r13); /* kernel stack to use */ \ 110 ld r1,PACAKSAVE(r13); /* kernel stack to use */ \
1001: cmpdi cr1,r1,0; /* check if r1 is in userspace */ \ 1111: cmpdi cr1,r1,0; /* check if r1 is in userspace */ \
101 bge- cr1,2f; /* abort if it is */ \ 112 blt+ cr1,3f; /* abort if it is */ \
102 b 3f; \ 113 li r1,(n); /* will be reloaded later */ \
1032: li r1,(n); /* will be reloaded later */ \
104 sth r1,PACA_TRAP_SAVE(r13); \ 114 sth r1,PACA_TRAP_SAVE(r13); \
115 std r3,area+EX_R3(r13); \
116 addi r3,r13,area; /* r3 -> where regs are saved*/ \
105 b bad_stack; \ 117 b bad_stack; \
1063: std r9,_CCR(r1); /* save CR in stackframe */ \ 1183: std r9,_CCR(r1); /* save CR in stackframe */ \
107 std r11,_NIP(r1); /* save SRR0 in stackframe */ \ 119 std r11,_NIP(r1); /* save SRR0 in stackframe */ \
@@ -123,6 +135,10 @@
123 std r9,GPR11(r1); \ 135 std r9,GPR11(r1); \
124 std r10,GPR12(r1); \ 136 std r10,GPR12(r1); \
125 std r11,GPR13(r1); \ 137 std r11,GPR13(r1); \
138 BEGIN_FTR_SECTION_NESTED(66); \
139 ld r10,area+EX_CFAR(r13); \
140 std r10,ORIG_GPR3(r1); \
141 END_FTR_SECTION_NESTED(CPU_FTR_CFAR, CPU_FTR_CFAR, 66); \
126 ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \ 142 ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \
127 mflr r9; /* save LR in stackframe */ \ 143 mflr r9; /* save LR in stackframe */ \
128 std r9,_LINK(r1); \ 144 std r9,_LINK(r1); \
@@ -143,57 +159,62 @@
143/* 159/*
144 * Exception vectors. 160 * Exception vectors.
145 */ 161 */
146#define STD_EXCEPTION_PSERIES(n, label) \ 162#define STD_EXCEPTION_PSERIES(loc, vec, label) \
147 . = n; \ 163 . = loc; \
148 .globl label##_pSeries; \ 164 .globl label##_pSeries; \
149label##_pSeries: \ 165label##_pSeries: \
150 HMT_MEDIUM; \ 166 HMT_MEDIUM; \
151 DO_KVM n; \ 167 DO_KVM vec; \
152 mtspr SPRN_SPRG_SCRATCH0,r13; /* save r13 */ \ 168 SET_SCRATCH0(r13); /* save r13 */ \
153 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common) 169 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common, EXC_STD)
154 170
155#define HSTD_EXCEPTION_PSERIES(n, label) \ 171#define STD_EXCEPTION_HV(loc, vec, label) \
156 . = n; \ 172 . = loc; \
157 .globl label##_pSeries; \ 173 .globl label##_hv; \
158label##_pSeries: \ 174label##_hv: \
159 HMT_MEDIUM; \ 175 HMT_MEDIUM; \
160 mtspr SPRN_SPRG_SCRATCH0,r20; /* save r20 */ \ 176 DO_KVM vec; \
161 mfspr r20,SPRN_HSRR0; /* copy HSRR0 to SRR0 */ \ 177 SET_SCRATCH0(r13); /* save r13 */ \
162 mtspr SPRN_SRR0,r20; \ 178 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common, EXC_HV)
163 mfspr r20,SPRN_HSRR1; /* copy HSRR0 to SRR0 */ \
164 mtspr SPRN_SRR1,r20; \
165 mfspr r20,SPRN_SPRG_SCRATCH0; /* restore r20 */ \
166 mtspr SPRN_SPRG_SCRATCH0,r13; /* save r13 */ \
167 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common)
168 179
169 180#define __MASKABLE_EXCEPTION_PSERIES(vec, label, h) \
170#define MASKABLE_EXCEPTION_PSERIES(n, label) \
171 . = n; \
172 .globl label##_pSeries; \
173label##_pSeries: \
174 HMT_MEDIUM; \ 181 HMT_MEDIUM; \
175 DO_KVM n; \ 182 DO_KVM vec; \
176 mtspr SPRN_SPRG_SCRATCH0,r13; /* save r13 */ \ 183 SET_SCRATCH0(r13); /* save r13 */ \
177 mfspr r13,SPRN_SPRG_PACA; /* get paca address into r13 */ \ 184 GET_PACA(r13); \
178 std r9,PACA_EXGEN+EX_R9(r13); /* save r9, r10 */ \ 185 std r9,PACA_EXGEN+EX_R9(r13); /* save r9, r10 */ \
179 std r10,PACA_EXGEN+EX_R10(r13); \ 186 std r10,PACA_EXGEN+EX_R10(r13); \
180 lbz r10,PACASOFTIRQEN(r13); \ 187 lbz r10,PACASOFTIRQEN(r13); \
181 mfcr r9; \ 188 mfcr r9; \
182 cmpwi r10,0; \ 189 cmpwi r10,0; \
183 beq masked_interrupt; \ 190 beq masked_##h##interrupt; \
184 mfspr r10,SPRN_SPRG_SCRATCH0; \ 191 GET_SCRATCH0(r10); \
185 std r10,PACA_EXGEN+EX_R13(r13); \ 192 std r10,PACA_EXGEN+EX_R13(r13); \
186 std r11,PACA_EXGEN+EX_R11(r13); \ 193 std r11,PACA_EXGEN+EX_R11(r13); \
187 std r12,PACA_EXGEN+EX_R12(r13); \ 194 std r12,PACA_EXGEN+EX_R12(r13); \
188 ld r12,PACAKBASE(r13); /* get high part of &label */ \ 195 ld r12,PACAKBASE(r13); /* get high part of &label */ \
189 ld r10,PACAKMSR(r13); /* get MSR value for kernel */ \ 196 ld r10,PACAKMSR(r13); /* get MSR value for kernel */ \
190 mfspr r11,SPRN_SRR0; /* save SRR0 */ \ 197 mfspr r11,SPRN_##h##SRR0; /* save SRR0 */ \
191 LOAD_HANDLER(r12,label##_common) \ 198 LOAD_HANDLER(r12,label##_common) \
192 mtspr SPRN_SRR0,r12; \ 199 mtspr SPRN_##h##SRR0,r12; \
193 mfspr r12,SPRN_SRR1; /* and SRR1 */ \ 200 mfspr r12,SPRN_##h##SRR1; /* and SRR1 */ \
194 mtspr SPRN_SRR1,r10; \ 201 mtspr SPRN_##h##SRR1,r10; \
195 rfid; \ 202 h##rfid; \
196 b . /* prevent speculative execution */ 203 b . /* prevent speculative execution */
204#define _MASKABLE_EXCEPTION_PSERIES(vec, label, h) \
205 __MASKABLE_EXCEPTION_PSERIES(vec, label, h)
206
207#define MASKABLE_EXCEPTION_PSERIES(loc, vec, label) \
208 . = loc; \
209 .globl label##_pSeries; \
210label##_pSeries: \
211 _MASKABLE_EXCEPTION_PSERIES(vec, label, EXC_STD)
212
213#define MASKABLE_EXCEPTION_HV(loc, vec, label) \
214 . = loc; \
215 .globl label##_hv; \
216label##_hv: \
217 _MASKABLE_EXCEPTION_PSERIES(vec, label, EXC_HV)
197 218
198#ifdef CONFIG_PPC_ISERIES 219#ifdef CONFIG_PPC_ISERIES
199#define DISABLE_INTS \ 220#define DISABLE_INTS \
diff --git a/arch/powerpc/include/asm/feature-fixups.h b/arch/powerpc/include/asm/feature-fixups.h
index 921a8470e18a..9a67a38bf7b9 100644
--- a/arch/powerpc/include/asm/feature-fixups.h
+++ b/arch/powerpc/include/asm/feature-fixups.h
@@ -49,7 +49,7 @@ label##5: \
49 FTR_ENTRY_OFFSET label##2b-label##5b; \ 49 FTR_ENTRY_OFFSET label##2b-label##5b; \
50 FTR_ENTRY_OFFSET label##3b-label##5b; \ 50 FTR_ENTRY_OFFSET label##3b-label##5b; \
51 FTR_ENTRY_OFFSET label##4b-label##5b; \ 51 FTR_ENTRY_OFFSET label##4b-label##5b; \
52 .ifgt (label##4b-label##3b)-(label##2b-label##1b); \ 52 .ifgt (label##4b- label##3b)-(label##2b- label##1b); \
53 .error "Feature section else case larger than body"; \ 53 .error "Feature section else case larger than body"; \
54 .endif; \ 54 .endif; \
55 .popsection; 55 .popsection;
@@ -146,6 +146,19 @@ label##5: \
146 146
147#ifndef __ASSEMBLY__ 147#ifndef __ASSEMBLY__
148 148
149#define ASM_FTR_IF(section_if, section_else, msk, val) \
150 stringify_in_c(BEGIN_FTR_SECTION) \
151 section_if "; " \
152 stringify_in_c(FTR_SECTION_ELSE) \
153 section_else "; " \
154 stringify_in_c(ALT_FTR_SECTION_END((msk), (val)))
155
156#define ASM_FTR_IFSET(section_if, section_else, msk) \
157 ASM_FTR_IF(section_if, section_else, (msk), (msk))
158
159#define ASM_FTR_IFCLR(section_if, section_else, msk) \
160 ASM_FTR_IF(section_if, section_else, (msk), 0)
161
149#define ASM_MMU_FTR_IF(section_if, section_else, msk, val) \ 162#define ASM_MMU_FTR_IF(section_if, section_else, msk, val) \
150 stringify_in_c(BEGIN_MMU_FTR_SECTION) \ 163 stringify_in_c(BEGIN_MMU_FTR_SECTION) \
151 section_if "; " \ 164 section_if "; " \
diff --git a/arch/powerpc/include/asm/firmware.h b/arch/powerpc/include/asm/firmware.h
index 4ef662e4a31d..3a6c586c4e40 100644
--- a/arch/powerpc/include/asm/firmware.h
+++ b/arch/powerpc/include/asm/firmware.h
@@ -47,6 +47,7 @@
47#define FW_FEATURE_BEAT ASM_CONST(0x0000000001000000) 47#define FW_FEATURE_BEAT ASM_CONST(0x0000000001000000)
48#define FW_FEATURE_CMO ASM_CONST(0x0000000002000000) 48#define FW_FEATURE_CMO ASM_CONST(0x0000000002000000)
49#define FW_FEATURE_VPHN ASM_CONST(0x0000000004000000) 49#define FW_FEATURE_VPHN ASM_CONST(0x0000000004000000)
50#define FW_FEATURE_XCMO ASM_CONST(0x0000000008000000)
50 51
51#ifndef __ASSEMBLY__ 52#ifndef __ASSEMBLY__
52 53
@@ -60,7 +61,7 @@ enum {
60 FW_FEATURE_VIO | FW_FEATURE_RDMA | FW_FEATURE_LLAN | 61 FW_FEATURE_VIO | FW_FEATURE_RDMA | FW_FEATURE_LLAN |
61 FW_FEATURE_BULK_REMOVE | FW_FEATURE_XDABR | 62 FW_FEATURE_BULK_REMOVE | FW_FEATURE_XDABR |
62 FW_FEATURE_MULTITCE | FW_FEATURE_SPLPAR | FW_FEATURE_LPAR | 63 FW_FEATURE_MULTITCE | FW_FEATURE_SPLPAR | FW_FEATURE_LPAR |
63 FW_FEATURE_CMO | FW_FEATURE_VPHN, 64 FW_FEATURE_CMO | FW_FEATURE_VPHN | FW_FEATURE_XCMO,
64 FW_FEATURE_PSERIES_ALWAYS = 0, 65 FW_FEATURE_PSERIES_ALWAYS = 0,
65 FW_FEATURE_ISERIES_POSSIBLE = FW_FEATURE_ISERIES | FW_FEATURE_LPAR, 66 FW_FEATURE_ISERIES_POSSIBLE = FW_FEATURE_ISERIES | FW_FEATURE_LPAR,
66 FW_FEATURE_ISERIES_ALWAYS = FW_FEATURE_ISERIES | FW_FEATURE_LPAR, 67 FW_FEATURE_ISERIES_ALWAYS = FW_FEATURE_ISERIES | FW_FEATURE_LPAR,
diff --git a/arch/powerpc/include/asm/hvcall.h b/arch/powerpc/include/asm/hvcall.h
index 8edec710cc6d..852b8c1c09db 100644
--- a/arch/powerpc/include/asm/hvcall.h
+++ b/arch/powerpc/include/asm/hvcall.h
@@ -102,6 +102,7 @@
102#define H_ANDCOND (1UL<<(63-33)) 102#define H_ANDCOND (1UL<<(63-33))
103#define H_ICACHE_INVALIDATE (1UL<<(63-40)) /* icbi, etc. (ignored for IO pages) */ 103#define H_ICACHE_INVALIDATE (1UL<<(63-40)) /* icbi, etc. (ignored for IO pages) */
104#define H_ICACHE_SYNCHRONIZE (1UL<<(63-41)) /* dcbst, icbi, etc (ignored for IO pages */ 104#define H_ICACHE_SYNCHRONIZE (1UL<<(63-41)) /* dcbst, icbi, etc (ignored for IO pages */
105#define H_COALESCE_CAND (1UL<<(63-42)) /* page is a good candidate for coalescing */
105#define H_ZERO_PAGE (1UL<<(63-48)) /* zero the page before mapping (ignored for IO pages) */ 106#define H_ZERO_PAGE (1UL<<(63-48)) /* zero the page before mapping (ignored for IO pages) */
106#define H_COPY_PAGE (1UL<<(63-49)) 107#define H_COPY_PAGE (1UL<<(63-49))
107#define H_N (1UL<<(63-61)) 108#define H_N (1UL<<(63-61))
@@ -234,6 +235,7 @@
234#define H_GET_MPP 0x2D4 235#define H_GET_MPP 0x2D4
235#define H_HOME_NODE_ASSOCIATIVITY 0x2EC 236#define H_HOME_NODE_ASSOCIATIVITY 0x2EC
236#define H_BEST_ENERGY 0x2F4 237#define H_BEST_ENERGY 0x2F4
238#define H_GET_MPP_X 0x314
237#define MAX_HCALL_OPCODE H_BEST_ENERGY 239#define MAX_HCALL_OPCODE H_BEST_ENERGY
238 240
239#ifndef __ASSEMBLY__ 241#ifndef __ASSEMBLY__
@@ -312,6 +314,16 @@ struct hvcall_mpp_data {
312 314
313int h_get_mpp(struct hvcall_mpp_data *); 315int h_get_mpp(struct hvcall_mpp_data *);
314 316
317struct hvcall_mpp_x_data {
318 unsigned long coalesced_bytes;
319 unsigned long pool_coalesced_bytes;
320 unsigned long pool_purr_cycles;
321 unsigned long pool_spurr_cycles;
322 unsigned long reserved[3];
323};
324
325int h_get_mpp_x(struct hvcall_mpp_x_data *mpp_x_data);
326
315#ifdef CONFIG_PPC_PSERIES 327#ifdef CONFIG_PPC_PSERIES
316extern int CMO_PrPSP; 328extern int CMO_PrPSP;
317extern int CMO_SecPSP; 329extern int CMO_SecPSP;
diff --git a/arch/powerpc/include/asm/io-workarounds.h b/arch/powerpc/include/asm/io-workarounds.h
new file mode 100644
index 000000000000..fbae49286926
--- /dev/null
+++ b/arch/powerpc/include/asm/io-workarounds.h
@@ -0,0 +1,48 @@
1/*
2 * Support PCI IO workaround
3 *
4 * (C) Copyright 2007-2008 TOSHIBA CORPORATION
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 */
20
21#ifndef _IO_WORKAROUNDS_H
22#define _IO_WORKAROUNDS_H
23
24#include <linux/io.h>
25#include <asm/pci-bridge.h>
26
27/* Bus info */
28struct iowa_bus {
29 struct pci_controller *phb;
30 struct ppc_pci_io *ops;
31 void *private;
32};
33
34void __devinit iowa_register_bus(struct pci_controller *, struct ppc_pci_io *,
35 int (*)(struct iowa_bus *, void *), void *);
36struct iowa_bus *iowa_mem_find_bus(const PCI_IO_ADDR);
37struct iowa_bus *iowa_pio_find_bus(unsigned long);
38
39extern struct ppc_pci_io spiderpci_ops;
40extern int spiderpci_iowa_init(struct iowa_bus *, void *);
41
42#define SPIDER_PCI_REG_BASE 0xd000
43#define SPIDER_PCI_REG_SIZE 0x1000
44#define SPIDER_PCI_VCI_CNTL_STAT 0x0110
45#define SPIDER_PCI_DUMMY_READ 0x0810
46#define SPIDER_PCI_DUMMY_READ_BASE 0x0814
47
48#endif /* _IO_WORKAROUNDS_H */
diff --git a/arch/powerpc/include/asm/io.h b/arch/powerpc/include/asm/io.h
index 001f2f11c19b..45698d55cd6a 100644
--- a/arch/powerpc/include/asm/io.h
+++ b/arch/powerpc/include/asm/io.h
@@ -2,6 +2,8 @@
2#define _ASM_POWERPC_IO_H 2#define _ASM_POWERPC_IO_H
3#ifdef __KERNEL__ 3#ifdef __KERNEL__
4 4
5#define ARCH_HAS_IOREMAP_WC
6
5/* 7/*
6 * This program is free software; you can redistribute it and/or 8 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License 9 * modify it under the terms of the GNU General Public License
@@ -481,10 +483,16 @@ __do_out_asm(_rec_outl, "stwbrx")
481 _memcpy_fromio(dst,PCI_FIX_ADDR(src),n) 483 _memcpy_fromio(dst,PCI_FIX_ADDR(src),n)
482#endif /* !CONFIG_EEH */ 484#endif /* !CONFIG_EEH */
483 485
484#ifdef CONFIG_PPC_INDIRECT_IO 486#ifdef CONFIG_PPC_INDIRECT_PIO
485#define DEF_PCI_HOOK(x) x 487#define DEF_PCI_HOOK_pio(x) x
488#else
489#define DEF_PCI_HOOK_pio(x) NULL
490#endif
491
492#ifdef CONFIG_PPC_INDIRECT_MMIO
493#define DEF_PCI_HOOK_mem(x) x
486#else 494#else
487#define DEF_PCI_HOOK(x) NULL 495#define DEF_PCI_HOOK_mem(x) NULL
488#endif 496#endif
489 497
490/* Structure containing all the hooks */ 498/* Structure containing all the hooks */
@@ -504,7 +512,7 @@ extern struct ppc_pci_io {
504#define DEF_PCI_AC_RET(name, ret, at, al, space, aa) \ 512#define DEF_PCI_AC_RET(name, ret, at, al, space, aa) \
505static inline ret name at \ 513static inline ret name at \
506{ \ 514{ \
507 if (DEF_PCI_HOOK(ppc_pci_io.name) != NULL) \ 515 if (DEF_PCI_HOOK_##space(ppc_pci_io.name) != NULL) \
508 return ppc_pci_io.name al; \ 516 return ppc_pci_io.name al; \
509 return __do_##name al; \ 517 return __do_##name al; \
510} 518}
@@ -512,7 +520,7 @@ static inline ret name at \
512#define DEF_PCI_AC_NORET(name, at, al, space, aa) \ 520#define DEF_PCI_AC_NORET(name, at, al, space, aa) \
513static inline void name at \ 521static inline void name at \
514{ \ 522{ \
515 if (DEF_PCI_HOOK(ppc_pci_io.name) != NULL) \ 523 if (DEF_PCI_HOOK_##space(ppc_pci_io.name) != NULL) \
516 ppc_pci_io.name al; \ 524 ppc_pci_io.name al; \
517 else \ 525 else \
518 __do_##name al; \ 526 __do_##name al; \
@@ -616,12 +624,13 @@ static inline void iosync(void)
616 * * ioremap is the standard one and provides non-cacheable guarded mappings 624 * * ioremap is the standard one and provides non-cacheable guarded mappings
617 * and can be hooked by the platform via ppc_md 625 * and can be hooked by the platform via ppc_md
618 * 626 *
619 * * ioremap_flags allows to specify the page flags as an argument and can 627 * * ioremap_prot allows to specify the page flags as an argument and can
620 * also be hooked by the platform via ppc_md. ioremap_prot is the exact 628 * also be hooked by the platform via ppc_md.
621 * same thing as ioremap_flags.
622 * 629 *
623 * * ioremap_nocache is identical to ioremap 630 * * ioremap_nocache is identical to ioremap
624 * 631 *
632 * * ioremap_wc enables write combining
633 *
625 * * iounmap undoes such a mapping and can be hooked 634 * * iounmap undoes such a mapping and can be hooked
626 * 635 *
627 * * __ioremap_at (and the pending __iounmap_at) are low level functions to 636 * * __ioremap_at (and the pending __iounmap_at) are low level functions to
@@ -629,7 +638,7 @@ static inline void iosync(void)
629 * currently be hooked. Must be page aligned. 638 * currently be hooked. Must be page aligned.
630 * 639 *
631 * * __ioremap is the low level implementation used by ioremap and 640 * * __ioremap is the low level implementation used by ioremap and
632 * ioremap_flags and cannot be hooked (but can be used by a hook on one 641 * ioremap_prot and cannot be hooked (but can be used by a hook on one
633 * of the previous ones) 642 * of the previous ones)
634 * 643 *
635 * * __ioremap_caller is the same as above but takes an explicit caller 644 * * __ioremap_caller is the same as above but takes an explicit caller
@@ -640,10 +649,10 @@ static inline void iosync(void)
640 * 649 *
641 */ 650 */
642extern void __iomem *ioremap(phys_addr_t address, unsigned long size); 651extern void __iomem *ioremap(phys_addr_t address, unsigned long size);
643extern void __iomem *ioremap_flags(phys_addr_t address, unsigned long size, 652extern void __iomem *ioremap_prot(phys_addr_t address, unsigned long size,
644 unsigned long flags); 653 unsigned long flags);
654extern void __iomem *ioremap_wc(phys_addr_t address, unsigned long size);
645#define ioremap_nocache(addr, size) ioremap((addr), (size)) 655#define ioremap_nocache(addr, size) ioremap((addr), (size))
646#define ioremap_prot(addr, size, prot) ioremap_flags((addr), (size), (prot))
647 656
648extern void iounmap(volatile void __iomem *addr); 657extern void iounmap(volatile void __iomem *addr);
649 658
diff --git a/arch/powerpc/include/asm/io_event_irq.h b/arch/powerpc/include/asm/io_event_irq.h
new file mode 100644
index 000000000000..b1a9a1be3c21
--- /dev/null
+++ b/arch/powerpc/include/asm/io_event_irq.h
@@ -0,0 +1,54 @@
1/*
2 * Copyright 2010, 2011 Mark Nelson and Tseng-Hui (Frank) Lin, IBM Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 */
9
10#ifndef _ASM_POWERPC_IO_EVENT_IRQ_H
11#define _ASM_POWERPC_IO_EVENT_IRQ_H
12
13#include <linux/types.h>
14#include <linux/notifier.h>
15
16#define PSERIES_IOEI_RPC_MAX_LEN 216
17
18#define PSERIES_IOEI_TYPE_ERR_DETECTED 0x01
19#define PSERIES_IOEI_TYPE_ERR_RECOVERED 0x02
20#define PSERIES_IOEI_TYPE_EVENT 0x03
21#define PSERIES_IOEI_TYPE_RPC_PASS_THRU 0x04
22
23#define PSERIES_IOEI_SUBTYPE_NOT_APP 0x00
24#define PSERIES_IOEI_SUBTYPE_REBALANCE_REQ 0x01
25#define PSERIES_IOEI_SUBTYPE_NODE_ONLINE 0x03
26#define PSERIES_IOEI_SUBTYPE_NODE_OFFLINE 0x04
27#define PSERIES_IOEI_SUBTYPE_DUMP_SIZE_CHANGE 0x05
28#define PSERIES_IOEI_SUBTYPE_TORRENT_IRV_UPDATE 0x06
29#define PSERIES_IOEI_SUBTYPE_TORRENT_HFI_CFGED 0x07
30
31#define PSERIES_IOEI_SCOPE_NOT_APP 0x00
32#define PSERIES_IOEI_SCOPE_RIO_HUB 0x36
33#define PSERIES_IOEI_SCOPE_RIO_BRIDGE 0x37
34#define PSERIES_IOEI_SCOPE_PHB 0x38
35#define PSERIES_IOEI_SCOPE_EADS_GLOBAL 0x39
36#define PSERIES_IOEI_SCOPE_EADS_SLOT 0x3A
37#define PSERIES_IOEI_SCOPE_TORRENT_HUB 0x3B
38#define PSERIES_IOEI_SCOPE_SERVICE_PROC 0x51
39
40/* Platform Event Log Format, Version 6, data portition of IO event section */
41struct pseries_io_event {
42 uint8_t event_type; /* 0x00 IO-Event Type */
43 uint8_t rpc_data_len; /* 0x01 RPC data length */
44 uint8_t scope; /* 0x02 Error/Event Scope */
45 uint8_t event_subtype; /* 0x03 I/O-Event Sub-Type */
46 uint32_t drc_index; /* 0x04 DRC Index */
47 uint8_t rpc_data[PSERIES_IOEI_RPC_MAX_LEN];
48 /* 0x08 RPC Data (0-216 bytes, */
49 /* padded to 4 bytes alignment) */
50};
51
52extern struct atomic_notifier_head pseries_ioei_notifier_list;
53
54#endif /* _ASM_POWERPC_IO_EVENT_IRQ_H */
diff --git a/arch/powerpc/include/asm/irq.h b/arch/powerpc/include/asm/irq.h
index 67ab5fb7d153..1bff591f7f72 100644
--- a/arch/powerpc/include/asm/irq.h
+++ b/arch/powerpc/include/asm/irq.h
@@ -88,9 +88,6 @@ struct irq_host_ops {
88 /* Dispose of such a mapping */ 88 /* Dispose of such a mapping */
89 void (*unmap)(struct irq_host *h, unsigned int virq); 89 void (*unmap)(struct irq_host *h, unsigned int virq);
90 90
91 /* Update of such a mapping */
92 void (*remap)(struct irq_host *h, unsigned int virq, irq_hw_number_t hw);
93
94 /* Translate device-tree interrupt specifier from raw format coming 91 /* Translate device-tree interrupt specifier from raw format coming
95 * from the firmware to a irq_hw_number_t (interrupt line number) and 92 * from the firmware to a irq_hw_number_t (interrupt line number) and
96 * type (sense) that can be passed to set_irq_type(). In the absence 93 * type (sense) that can be passed to set_irq_type(). In the absence
@@ -128,19 +125,10 @@ struct irq_host {
128 struct device_node *of_node; 125 struct device_node *of_node;
129}; 126};
130 127
131/* The main irq map itself is an array of NR_IRQ entries containing the 128struct irq_data;
132 * associate host and irq number. An entry with a host of NULL is free. 129extern irq_hw_number_t irqd_to_hwirq(struct irq_data *d);
133 * An entry can be allocated if it's free, the allocator always then sets
134 * hwirq first to the host's invalid irq number and then fills ops.
135 */
136struct irq_map_entry {
137 irq_hw_number_t hwirq;
138 struct irq_host *host;
139};
140
141extern struct irq_map_entry irq_map[NR_IRQS];
142
143extern irq_hw_number_t virq_to_hw(unsigned int virq); 130extern irq_hw_number_t virq_to_hw(unsigned int virq);
131extern bool virq_is_host(unsigned int virq, struct irq_host *host);
144 132
145/** 133/**
146 * irq_alloc_host - Allocate a new irq_host data structure 134 * irq_alloc_host - Allocate a new irq_host data structure
diff --git a/arch/powerpc/include/asm/kexec.h b/arch/powerpc/include/asm/kexec.h
index f54408d995b5..8a33698c61bd 100644
--- a/arch/powerpc/include/asm/kexec.h
+++ b/arch/powerpc/include/asm/kexec.h
@@ -76,7 +76,7 @@ extern void crash_send_ipi(void (*crash_ipi_callback)(struct pt_regs *));
76extern cpumask_t cpus_in_sr; 76extern cpumask_t cpus_in_sr;
77static inline int kexec_sr_activated(int cpu) 77static inline int kexec_sr_activated(int cpu)
78{ 78{
79 return cpu_isset(cpu,cpus_in_sr); 79 return cpumask_test_cpu(cpu, &cpus_in_sr);
80} 80}
81 81
82struct kimage; 82struct kimage;
diff --git a/arch/powerpc/include/asm/kvm.h b/arch/powerpc/include/asm/kvm.h
index 18ea6963ad77..d2ca5ed3877b 100644
--- a/arch/powerpc/include/asm/kvm.h
+++ b/arch/powerpc/include/asm/kvm.h
@@ -45,6 +45,114 @@ struct kvm_regs {
45 __u64 gpr[32]; 45 __u64 gpr[32];
46}; 46};
47 47
48#define KVM_SREGS_E_IMPL_NONE 0
49#define KVM_SREGS_E_IMPL_FSL 1
50
51#define KVM_SREGS_E_FSL_PIDn (1 << 0) /* PID1/PID2 */
52
53/*
54 * Feature bits indicate which sections of the sregs struct are valid,
55 * both in KVM_GET_SREGS and KVM_SET_SREGS. On KVM_SET_SREGS, registers
56 * corresponding to unset feature bits will not be modified. This allows
57 * restoring a checkpoint made without that feature, while keeping the
58 * default values of the new registers.
59 *
60 * KVM_SREGS_E_BASE contains:
61 * CSRR0/1 (refers to SRR2/3 on 40x)
62 * ESR
63 * DEAR
64 * MCSR
65 * TSR
66 * TCR
67 * DEC
68 * TB
69 * VRSAVE (USPRG0)
70 */
71#define KVM_SREGS_E_BASE (1 << 0)
72
73/*
74 * KVM_SREGS_E_ARCH206 contains:
75 *
76 * PIR
77 * MCSRR0/1
78 * DECAR
79 * IVPR
80 */
81#define KVM_SREGS_E_ARCH206 (1 << 1)
82
83/*
84 * Contains EPCR, plus the upper half of 64-bit registers
85 * that are 32-bit on 32-bit implementations.
86 */
87#define KVM_SREGS_E_64 (1 << 2)
88
89#define KVM_SREGS_E_SPRG8 (1 << 3)
90#define KVM_SREGS_E_MCIVPR (1 << 4)
91
92/*
93 * IVORs are used -- contains IVOR0-15, plus additional IVORs
94 * in combination with an appropriate feature bit.
95 */
96#define KVM_SREGS_E_IVOR (1 << 5)
97
98/*
99 * Contains MAS0-4, MAS6-7, TLBnCFG, MMUCFG.
100 * Also TLBnPS if MMUCFG[MAVN] = 1.
101 */
102#define KVM_SREGS_E_ARCH206_MMU (1 << 6)
103
104/* DBSR, DBCR, IAC, DAC, DVC */
105#define KVM_SREGS_E_DEBUG (1 << 7)
106
107/* Enhanced debug -- DSRR0/1, SPRG9 */
108#define KVM_SREGS_E_ED (1 << 8)
109
110/* Embedded Floating Point (SPE) -- IVOR32-34 if KVM_SREGS_E_IVOR */
111#define KVM_SREGS_E_SPE (1 << 9)
112
113/* External Proxy (EXP) -- EPR */
114#define KVM_SREGS_EXP (1 << 10)
115
116/* External PID (E.PD) -- EPSC/EPLC */
117#define KVM_SREGS_E_PD (1 << 11)
118
119/* Processor Control (E.PC) -- IVOR36-37 if KVM_SREGS_E_IVOR */
120#define KVM_SREGS_E_PC (1 << 12)
121
122/* Page table (E.PT) -- EPTCFG */
123#define KVM_SREGS_E_PT (1 << 13)
124
125/* Embedded Performance Monitor (E.PM) -- IVOR35 if KVM_SREGS_E_IVOR */
126#define KVM_SREGS_E_PM (1 << 14)
127
128/*
129 * Special updates:
130 *
131 * Some registers may change even while a vcpu is not running.
132 * To avoid losing these changes, by default these registers are
133 * not updated by KVM_SET_SREGS. To force an update, set the bit
134 * in u.e.update_special corresponding to the register to be updated.
135 *
136 * The update_special field is zero on return from KVM_GET_SREGS.
137 *
138 * When restoring a checkpoint, the caller can set update_special
139 * to 0xffffffff to ensure that everything is restored, even new features
140 * that the caller doesn't know about.
141 */
142#define KVM_SREGS_E_UPDATE_MCSR (1 << 0)
143#define KVM_SREGS_E_UPDATE_TSR (1 << 1)
144#define KVM_SREGS_E_UPDATE_DEC (1 << 2)
145#define KVM_SREGS_E_UPDATE_DBSR (1 << 3)
146
147/*
148 * In KVM_SET_SREGS, reserved/pad fields must be left untouched from a
149 * previous KVM_GET_REGS.
150 *
151 * Unless otherwise indicated, setting any register with KVM_SET_SREGS
152 * directly sets its value. It does not trigger any special semantics such
153 * as write-one-to-clear. Calling KVM_SET_SREGS on an unmodified struct
154 * just received from KVM_GET_SREGS is always a no-op.
155 */
48struct kvm_sregs { 156struct kvm_sregs {
49 __u32 pvr; 157 __u32 pvr;
50 union { 158 union {
@@ -62,6 +170,82 @@ struct kvm_sregs {
62 __u64 dbat[8]; 170 __u64 dbat[8];
63 } ppc32; 171 } ppc32;
64 } s; 172 } s;
173 struct {
174 union {
175 struct { /* KVM_SREGS_E_IMPL_FSL */
176 __u32 features; /* KVM_SREGS_E_FSL_ */
177 __u32 svr;
178 __u64 mcar;
179 __u32 hid0;
180
181 /* KVM_SREGS_E_FSL_PIDn */
182 __u32 pid1, pid2;
183 } fsl;
184 __u8 pad[256];
185 } impl;
186
187 __u32 features; /* KVM_SREGS_E_ */
188 __u32 impl_id; /* KVM_SREGS_E_IMPL_ */
189 __u32 update_special; /* KVM_SREGS_E_UPDATE_ */
190 __u32 pir; /* read-only */
191 __u64 sprg8;
192 __u64 sprg9; /* E.ED */
193 __u64 csrr0;
194 __u64 dsrr0; /* E.ED */
195 __u64 mcsrr0;
196 __u32 csrr1;
197 __u32 dsrr1; /* E.ED */
198 __u32 mcsrr1;
199 __u32 esr;
200 __u64 dear;
201 __u64 ivpr;
202 __u64 mcivpr;
203 __u64 mcsr; /* KVM_SREGS_E_UPDATE_MCSR */
204
205 __u32 tsr; /* KVM_SREGS_E_UPDATE_TSR */
206 __u32 tcr;
207 __u32 decar;
208 __u32 dec; /* KVM_SREGS_E_UPDATE_DEC */
209
210 /*
211 * Userspace can read TB directly, but the
212 * value reported here is consistent with "dec".
213 *
214 * Read-only.
215 */
216 __u64 tb;
217
218 __u32 dbsr; /* KVM_SREGS_E_UPDATE_DBSR */
219 __u32 dbcr[3];
220 __u32 iac[4];
221 __u32 dac[2];
222 __u32 dvc[2];
223 __u8 num_iac; /* read-only */
224 __u8 num_dac; /* read-only */
225 __u8 num_dvc; /* read-only */
226 __u8 pad;
227
228 __u32 epr; /* EXP */
229 __u32 vrsave; /* a.k.a. USPRG0 */
230 __u32 epcr; /* KVM_SREGS_E_64 */
231
232 __u32 mas0;
233 __u32 mas1;
234 __u64 mas2;
235 __u64 mas7_3;
236 __u32 mas4;
237 __u32 mas6;
238
239 __u32 ivor_low[16]; /* IVOR0-15 */
240 __u32 ivor_high[18]; /* IVOR32+, plus room to expand */
241
242 __u32 mmucfg; /* read-only */
243 __u32 eptcfg; /* E.PT, read-only */
244 __u32 tlbcfg[4];/* read-only */
245 __u32 tlbps[4]; /* read-only */
246
247 __u32 eplc, epsc; /* E.PD */
248 } e;
65 __u8 pad[1020]; 249 __u8 pad[1020];
66 } u; 250 } u;
67}; 251};
diff --git a/arch/powerpc/include/asm/kvm_44x.h b/arch/powerpc/include/asm/kvm_44x.h
index d22d39942a92..a0e57618ff33 100644
--- a/arch/powerpc/include/asm/kvm_44x.h
+++ b/arch/powerpc/include/asm/kvm_44x.h
@@ -61,7 +61,6 @@ static inline struct kvmppc_vcpu_44x *to_44x(struct kvm_vcpu *vcpu)
61 return container_of(vcpu, struct kvmppc_vcpu_44x, vcpu); 61 return container_of(vcpu, struct kvmppc_vcpu_44x, vcpu);
62} 62}
63 63
64void kvmppc_set_pid(struct kvm_vcpu *vcpu, u32 new_pid);
65void kvmppc_44x_tlb_put(struct kvm_vcpu *vcpu); 64void kvmppc_44x_tlb_put(struct kvm_vcpu *vcpu);
66void kvmppc_44x_tlb_load(struct kvm_vcpu *vcpu); 65void kvmppc_44x_tlb_load(struct kvm_vcpu *vcpu);
67 66
diff --git a/arch/powerpc/include/asm/kvm_asm.h b/arch/powerpc/include/asm/kvm_asm.h
index 5b7504674397..0951b17f4eb5 100644
--- a/arch/powerpc/include/asm/kvm_asm.h
+++ b/arch/powerpc/include/asm/kvm_asm.h
@@ -59,6 +59,7 @@
59#define BOOK3S_INTERRUPT_INST_SEGMENT 0x480 59#define BOOK3S_INTERRUPT_INST_SEGMENT 0x480
60#define BOOK3S_INTERRUPT_EXTERNAL 0x500 60#define BOOK3S_INTERRUPT_EXTERNAL 0x500
61#define BOOK3S_INTERRUPT_EXTERNAL_LEVEL 0x501 61#define BOOK3S_INTERRUPT_EXTERNAL_LEVEL 0x501
62#define BOOK3S_INTERRUPT_EXTERNAL_HV 0x502
62#define BOOK3S_INTERRUPT_ALIGNMENT 0x600 63#define BOOK3S_INTERRUPT_ALIGNMENT 0x600
63#define BOOK3S_INTERRUPT_PROGRAM 0x700 64#define BOOK3S_INTERRUPT_PROGRAM 0x700
64#define BOOK3S_INTERRUPT_FP_UNAVAIL 0x800 65#define BOOK3S_INTERRUPT_FP_UNAVAIL 0x800
diff --git a/arch/powerpc/include/asm/kvm_book3s_asm.h b/arch/powerpc/include/asm/kvm_book3s_asm.h
index 36fdb3aff30b..d5a8a3861635 100644
--- a/arch/powerpc/include/asm/kvm_book3s_asm.h
+++ b/arch/powerpc/include/asm/kvm_book3s_asm.h
@@ -34,6 +34,7 @@
34 (\intno == BOOK3S_INTERRUPT_DATA_SEGMENT) || \ 34 (\intno == BOOK3S_INTERRUPT_DATA_SEGMENT) || \
35 (\intno == BOOK3S_INTERRUPT_INST_SEGMENT) || \ 35 (\intno == BOOK3S_INTERRUPT_INST_SEGMENT) || \
36 (\intno == BOOK3S_INTERRUPT_EXTERNAL) || \ 36 (\intno == BOOK3S_INTERRUPT_EXTERNAL) || \
37 (\intno == BOOK3S_INTERRUPT_EXTERNAL_HV) || \
37 (\intno == BOOK3S_INTERRUPT_ALIGNMENT) || \ 38 (\intno == BOOK3S_INTERRUPT_ALIGNMENT) || \
38 (\intno == BOOK3S_INTERRUPT_PROGRAM) || \ 39 (\intno == BOOK3S_INTERRUPT_PROGRAM) || \
39 (\intno == BOOK3S_INTERRUPT_FP_UNAVAIL) || \ 40 (\intno == BOOK3S_INTERRUPT_FP_UNAVAIL) || \
diff --git a/arch/powerpc/include/asm/kvm_e500.h b/arch/powerpc/include/asm/kvm_e500.h
index 7fea26fffb25..7a2a565f88c4 100644
--- a/arch/powerpc/include/asm/kvm_e500.h
+++ b/arch/powerpc/include/asm/kvm_e500.h
@@ -43,6 +43,7 @@ struct kvmppc_vcpu_e500 {
43 43
44 u32 host_pid[E500_PID_NUM]; 44 u32 host_pid[E500_PID_NUM];
45 u32 pid[E500_PID_NUM]; 45 u32 pid[E500_PID_NUM];
46 u32 svr;
46 47
47 u32 mas0; 48 u32 mas0;
48 u32 mas1; 49 u32 mas1;
@@ -58,6 +59,7 @@ struct kvmppc_vcpu_e500 {
58 u32 hid1; 59 u32 hid1;
59 u32 tlb0cfg; 60 u32 tlb0cfg;
60 u32 tlb1cfg; 61 u32 tlb1cfg;
62 u64 mcar;
61 63
62 struct kvm_vcpu vcpu; 64 struct kvm_vcpu vcpu;
63}; 65};
diff --git a/arch/powerpc/include/asm/kvm_host.h b/arch/powerpc/include/asm/kvm_host.h
index bba3b9b72a39..186f150b9b89 100644
--- a/arch/powerpc/include/asm/kvm_host.h
+++ b/arch/powerpc/include/asm/kvm_host.h
@@ -223,6 +223,7 @@ struct kvm_vcpu_arch {
223 ulong hflags; 223 ulong hflags;
224 ulong guest_owned_ext; 224 ulong guest_owned_ext;
225#endif 225#endif
226 u32 vrsave; /* also USPRG0 */
226 u32 mmucr; 227 u32 mmucr;
227 ulong sprg4; 228 ulong sprg4;
228 ulong sprg5; 229 ulong sprg5;
@@ -232,6 +233,9 @@ struct kvm_vcpu_arch {
232 ulong csrr1; 233 ulong csrr1;
233 ulong dsrr0; 234 ulong dsrr0;
234 ulong dsrr1; 235 ulong dsrr1;
236 ulong mcsrr0;
237 ulong mcsrr1;
238 ulong mcsr;
235 ulong esr; 239 ulong esr;
236 u32 dec; 240 u32 dec;
237 u32 decar; 241 u32 decar;
@@ -255,6 +259,7 @@ struct kvm_vcpu_arch {
255 u32 dbsr; 259 u32 dbsr;
256 260
257#ifdef CONFIG_KVM_EXIT_TIMING 261#ifdef CONFIG_KVM_EXIT_TIMING
262 struct mutex exit_timing_lock;
258 struct kvmppc_exit_timing timing_exit; 263 struct kvmppc_exit_timing timing_exit;
259 struct kvmppc_exit_timing timing_last_enter; 264 struct kvmppc_exit_timing timing_last_enter;
260 u32 last_exit_type; 265 u32 last_exit_type;
diff --git a/arch/powerpc/include/asm/kvm_ppc.h b/arch/powerpc/include/asm/kvm_ppc.h
index ecb3bc74c344..9345238edecf 100644
--- a/arch/powerpc/include/asm/kvm_ppc.h
+++ b/arch/powerpc/include/asm/kvm_ppc.h
@@ -61,6 +61,7 @@ extern int kvmppc_emulate_instruction(struct kvm_run *run,
61 struct kvm_vcpu *vcpu); 61 struct kvm_vcpu *vcpu);
62extern int kvmppc_emulate_mmio(struct kvm_run *run, struct kvm_vcpu *vcpu); 62extern int kvmppc_emulate_mmio(struct kvm_run *run, struct kvm_vcpu *vcpu);
63extern void kvmppc_emulate_dec(struct kvm_vcpu *vcpu); 63extern void kvmppc_emulate_dec(struct kvm_vcpu *vcpu);
64extern u32 kvmppc_get_dec(struct kvm_vcpu *vcpu, u64 tb);
64 65
65/* Core-specific hooks */ 66/* Core-specific hooks */
66 67
@@ -142,4 +143,12 @@ static inline u32 kvmppc_set_field(u64 inst, int msb, int lsb, int value)
142 return r; 143 return r;
143} 144}
144 145
146void kvmppc_core_get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs);
147int kvmppc_core_set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs);
148
149void kvmppc_get_sregs_ivor(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs);
150int kvmppc_set_sregs_ivor(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs);
151
152void kvmppc_set_pid(struct kvm_vcpu *vcpu, u32 pid);
153
145#endif /* __POWERPC_KVM_PPC_H__ */ 154#endif /* __POWERPC_KVM_PPC_H__ */
diff --git a/arch/powerpc/include/asm/lppaca.h b/arch/powerpc/include/asm/lppaca.h
index a077adc0b35e..e0298d26ce5d 100644
--- a/arch/powerpc/include/asm/lppaca.h
+++ b/arch/powerpc/include/asm/lppaca.h
@@ -210,6 +210,8 @@ struct dtl_entry {
210#define DISPATCH_LOG_BYTES 4096 /* bytes per cpu */ 210#define DISPATCH_LOG_BYTES 4096 /* bytes per cpu */
211#define N_DISPATCH_LOG (DISPATCH_LOG_BYTES / sizeof(struct dtl_entry)) 211#define N_DISPATCH_LOG (DISPATCH_LOG_BYTES / sizeof(struct dtl_entry))
212 212
213extern struct kmem_cache *dtl_cache;
214
213/* 215/*
214 * When CONFIG_VIRT_CPU_ACCOUNTING = y, the cpu accounting code controls 216 * When CONFIG_VIRT_CPU_ACCOUNTING = y, the cpu accounting code controls
215 * reading from the dispatch trace log. If other code wants to consume 217 * reading from the dispatch trace log. If other code wants to consume
diff --git a/arch/powerpc/include/asm/machdep.h b/arch/powerpc/include/asm/machdep.h
index e4f01915fbb0..47cacddb14cf 100644
--- a/arch/powerpc/include/asm/machdep.h
+++ b/arch/powerpc/include/asm/machdep.h
@@ -29,21 +29,6 @@ struct file;
29struct pci_controller; 29struct pci_controller;
30struct kimage; 30struct kimage;
31 31
32#ifdef CONFIG_SMP
33struct smp_ops_t {
34 void (*message_pass)(int target, int msg);
35 int (*probe)(void);
36 void (*kick_cpu)(int nr);
37 void (*setup_cpu)(int nr);
38 void (*bringup_done)(void);
39 void (*take_timebase)(void);
40 void (*give_timebase)(void);
41 int (*cpu_disable)(void);
42 void (*cpu_die)(unsigned int nr);
43 int (*cpu_bootable)(unsigned int nr);
44};
45#endif
46
47struct machdep_calls { 32struct machdep_calls {
48 char *name; 33 char *name;
49#ifdef CONFIG_PPC64 34#ifdef CONFIG_PPC64
@@ -267,6 +252,7 @@ struct machdep_calls {
267 252
268extern void e500_idle(void); 253extern void e500_idle(void);
269extern void power4_idle(void); 254extern void power4_idle(void);
255extern void power7_idle(void);
270extern void ppc6xx_idle(void); 256extern void ppc6xx_idle(void);
271extern void book3e_idle(void); 257extern void book3e_idle(void);
272 258
@@ -311,12 +297,6 @@ extern sys_ctrler_t sys_ctrler;
311 297
312#endif /* CONFIG_PPC_PMAC */ 298#endif /* CONFIG_PPC_PMAC */
313 299
314#ifdef CONFIG_SMP
315/* Poor default implementations */
316extern void __devinit smp_generic_give_timebase(void);
317extern void __devinit smp_generic_take_timebase(void);
318#endif /* CONFIG_SMP */
319
320 300
321/* Functions to produce codes on the leds. 301/* Functions to produce codes on the leds.
322 * The SRC code should be unique for the message category and should 302 * The SRC code should be unique for the message category and should
diff --git a/arch/powerpc/include/asm/mmu-book3e.h b/arch/powerpc/include/asm/mmu-book3e.h
index 17194fcd4040..3ea0f9a259d8 100644
--- a/arch/powerpc/include/asm/mmu-book3e.h
+++ b/arch/powerpc/include/asm/mmu-book3e.h
@@ -43,6 +43,7 @@
43#define MAS0_TLBSEL(x) (((x) << 28) & 0x30000000) 43#define MAS0_TLBSEL(x) (((x) << 28) & 0x30000000)
44#define MAS0_ESEL(x) (((x) << 16) & 0x0FFF0000) 44#define MAS0_ESEL(x) (((x) << 16) & 0x0FFF0000)
45#define MAS0_NV(x) ((x) & 0x00000FFF) 45#define MAS0_NV(x) ((x) & 0x00000FFF)
46#define MAS0_ESEL_MASK 0x0FFF0000
46#define MAS0_HES 0x00004000 47#define MAS0_HES 0x00004000
47#define MAS0_WQ_ALLWAYS 0x00000000 48#define MAS0_WQ_ALLWAYS 0x00000000
48#define MAS0_WQ_COND 0x00001000 49#define MAS0_WQ_COND 0x00001000
@@ -137,6 +138,21 @@
137#define MMUCSR0_TLB2PS 0x00078000 /* TLB2 Page Size */ 138#define MMUCSR0_TLB2PS 0x00078000 /* TLB2 Page Size */
138#define MMUCSR0_TLB3PS 0x00780000 /* TLB3 Page Size */ 139#define MMUCSR0_TLB3PS 0x00780000 /* TLB3 Page Size */
139 140
141/* MMUCFG bits */
142#define MMUCFG_MAVN_NASK 0x00000003
143#define MMUCFG_MAVN_V1_0 0x00000000
144#define MMUCFG_MAVN_V2_0 0x00000001
145#define MMUCFG_NTLB_MASK 0x0000000c
146#define MMUCFG_NTLB_SHIFT 2
147#define MMUCFG_PIDSIZE_MASK 0x000007c0
148#define MMUCFG_PIDSIZE_SHIFT 6
149#define MMUCFG_TWC 0x00008000
150#define MMUCFG_LRAT 0x00010000
151#define MMUCFG_RASIZE_MASK 0x00fe0000
152#define MMUCFG_RASIZE_SHIFT 17
153#define MMUCFG_LPIDSIZE_MASK 0x0f000000
154#define MMUCFG_LPIDSIZE_SHIFT 24
155
140/* TLBnCFG encoding */ 156/* TLBnCFG encoding */
141#define TLBnCFG_N_ENTRY 0x00000fff /* number of entries */ 157#define TLBnCFG_N_ENTRY 0x00000fff /* number of entries */
142#define TLBnCFG_HES 0x00002000 /* HW select supported */ 158#define TLBnCFG_HES 0x00002000 /* HW select supported */
@@ -229,6 +245,10 @@ extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
229extern int mmu_linear_psize; 245extern int mmu_linear_psize;
230extern int mmu_vmemmap_psize; 246extern int mmu_vmemmap_psize;
231 247
248#ifdef CONFIG_PPC64
249extern unsigned long linear_map_top;
250#endif
251
232#endif /* !__ASSEMBLY__ */ 252#endif /* !__ASSEMBLY__ */
233 253
234#endif /* _ASM_POWERPC_MMU_BOOK3E_H_ */ 254#endif /* _ASM_POWERPC_MMU_BOOK3E_H_ */
diff --git a/arch/powerpc/include/asm/mmu-hash64.h b/arch/powerpc/include/asm/mmu-hash64.h
index ae7b3efec8e5..d865bd909c7d 100644
--- a/arch/powerpc/include/asm/mmu-hash64.h
+++ b/arch/powerpc/include/asm/mmu-hash64.h
@@ -408,6 +408,7 @@ static inline void subpage_prot_init_new_context(struct mm_struct *mm) { }
408#endif /* CONFIG_PPC_SUBPAGE_PROT */ 408#endif /* CONFIG_PPC_SUBPAGE_PROT */
409 409
410typedef unsigned long mm_context_id_t; 410typedef unsigned long mm_context_id_t;
411struct spinlock;
411 412
412typedef struct { 413typedef struct {
413 mm_context_id_t id; 414 mm_context_id_t id;
@@ -423,6 +424,11 @@ typedef struct {
423#ifdef CONFIG_PPC_SUBPAGE_PROT 424#ifdef CONFIG_PPC_SUBPAGE_PROT
424 struct subpage_prot_table spt; 425 struct subpage_prot_table spt;
425#endif /* CONFIG_PPC_SUBPAGE_PROT */ 426#endif /* CONFIG_PPC_SUBPAGE_PROT */
427#ifdef CONFIG_PPC_ICSWX
428 struct spinlock *cop_lockp; /* guard acop and cop_pid */
429 unsigned long acop; /* mask of enabled coprocessor types */
430 unsigned int cop_pid; /* pid value used with coprocessors */
431#endif /* CONFIG_PPC_ICSWX */
426} mm_context_t; 432} mm_context_t;
427 433
428 434
diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h
index bb40a06d3b77..4138b21ae80a 100644
--- a/arch/powerpc/include/asm/mmu.h
+++ b/arch/powerpc/include/asm/mmu.h
@@ -56,11 +56,6 @@
56 */ 56 */
57#define MMU_FTR_NEED_DTLB_SW_LRU ASM_CONST(0x00200000) 57#define MMU_FTR_NEED_DTLB_SW_LRU ASM_CONST(0x00200000)
58 58
59/* This indicates that the processor uses the ISA 2.06 server tlbie
60 * mnemonics
61 */
62#define MMU_FTR_TLBIE_206 ASM_CONST(0x00400000)
63
64/* Enable use of TLB reservation. Processor should support tlbsrx. 59/* Enable use of TLB reservation. Processor should support tlbsrx.
65 * instruction and MAS0[WQ]. 60 * instruction and MAS0[WQ].
66 */ 61 */
@@ -70,6 +65,53 @@
70 */ 65 */
71#define MMU_FTR_USE_PAIRED_MAS ASM_CONST(0x01000000) 66#define MMU_FTR_USE_PAIRED_MAS ASM_CONST(0x01000000)
72 67
68/* MMU is SLB-based
69 */
70#define MMU_FTR_SLB ASM_CONST(0x02000000)
71
72/* Support 16M large pages
73 */
74#define MMU_FTR_16M_PAGE ASM_CONST(0x04000000)
75
76/* Supports TLBIEL variant
77 */
78#define MMU_FTR_TLBIEL ASM_CONST(0x08000000)
79
80/* Supports tlbies w/o locking
81 */
82#define MMU_FTR_LOCKLESS_TLBIE ASM_CONST(0x10000000)
83
84/* Large pages can be marked CI
85 */
86#define MMU_FTR_CI_LARGE_PAGE ASM_CONST(0x20000000)
87
88/* 1T segments available
89 */
90#define MMU_FTR_1T_SEGMENT ASM_CONST(0x40000000)
91
92/* Doesn't support the B bit (1T segment) in SLBIE
93 */
94#define MMU_FTR_NO_SLBIE_B ASM_CONST(0x80000000)
95
96/* MMU feature bit sets for various CPUs */
97#define MMU_FTRS_DEFAULT_HPTE_ARCH_V2 \
98 MMU_FTR_HPTE_TABLE | MMU_FTR_PPCAS_ARCH_V2
99#define MMU_FTRS_POWER4 MMU_FTRS_DEFAULT_HPTE_ARCH_V2
100#define MMU_FTRS_PPC970 MMU_FTRS_POWER4
101#define MMU_FTRS_POWER5 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE
102#define MMU_FTRS_POWER6 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE
103#define MMU_FTRS_POWER7 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE
104#define MMU_FTRS_CELL MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \
105 MMU_FTR_CI_LARGE_PAGE
106#define MMU_FTRS_PA6T MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \
107 MMU_FTR_CI_LARGE_PAGE | MMU_FTR_NO_SLBIE_B
108#define MMU_FTRS_A2 MMU_FTR_TYPE_3E | MMU_FTR_USE_TLBILX | \
109 MMU_FTR_USE_TLBIVAX_BCAST | \
110 MMU_FTR_LOCK_BCAST_INVAL | \
111 MMU_FTR_USE_TLBRSRV | \
112 MMU_FTR_USE_PAIRED_MAS | \
113 MMU_FTR_TLBIEL | \
114 MMU_FTR_16M_PAGE
73#ifndef __ASSEMBLY__ 115#ifndef __ASSEMBLY__
74#include <asm/cputable.h> 116#include <asm/cputable.h>
75 117
diff --git a/arch/powerpc/include/asm/mmu_context.h b/arch/powerpc/include/asm/mmu_context.h
index 81fb41289d6c..a73668a5f30d 100644
--- a/arch/powerpc/include/asm/mmu_context.h
+++ b/arch/powerpc/include/asm/mmu_context.h
@@ -32,6 +32,10 @@ extern void __destroy_context(unsigned long context_id);
32extern void mmu_context_init(void); 32extern void mmu_context_init(void);
33#endif 33#endif
34 34
35extern void switch_cop(struct mm_struct *next);
36extern int use_cop(unsigned long acop, struct mm_struct *mm);
37extern void drop_cop(unsigned long acop, struct mm_struct *mm);
38
35/* 39/*
36 * switch_mm is the entry point called from the architecture independent 40 * switch_mm is the entry point called from the architecture independent
37 * code in kernel/sched.c 41 * code in kernel/sched.c
@@ -55,6 +59,12 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
55 if (prev == next) 59 if (prev == next)
56 return; 60 return;
57 61
62#ifdef CONFIG_PPC_ICSWX
63 /* Switch coprocessor context only if prev or next uses a coprocessor */
64 if (prev->context.acop || next->context.acop)
65 switch_cop(next);
66#endif /* CONFIG_PPC_ICSWX */
67
58 /* We must stop all altivec streams before changing the HW 68 /* We must stop all altivec streams before changing the HW
59 * context 69 * context
60 */ 70 */
@@ -67,7 +77,7 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
67 * sub architectures. 77 * sub architectures.
68 */ 78 */
69#ifdef CONFIG_PPC_STD_MMU_64 79#ifdef CONFIG_PPC_STD_MMU_64
70 if (cpu_has_feature(CPU_FTR_SLB)) 80 if (mmu_has_feature(MMU_FTR_SLB))
71 switch_slb(tsk, next); 81 switch_slb(tsk, next);
72 else 82 else
73 switch_stab(tsk, next); 83 switch_stab(tsk, next);
diff --git a/arch/powerpc/include/asm/mpic.h b/arch/powerpc/include/asm/mpic.h
index 7005ee0b074d..df18989e78d4 100644
--- a/arch/powerpc/include/asm/mpic.h
+++ b/arch/powerpc/include/asm/mpic.h
@@ -3,7 +3,6 @@
3#ifdef __KERNEL__ 3#ifdef __KERNEL__
4 4
5#include <linux/irq.h> 5#include <linux/irq.h>
6#include <linux/sysdev.h>
7#include <asm/dcr.h> 6#include <asm/dcr.h>
8#include <asm/msi_bitmap.h> 7#include <asm/msi_bitmap.h>
9 8
@@ -263,6 +262,7 @@ struct mpic
263#ifdef CONFIG_SMP 262#ifdef CONFIG_SMP
264 struct irq_chip hc_ipi; 263 struct irq_chip hc_ipi;
265#endif 264#endif
265 struct irq_chip hc_tm;
266 const char *name; 266 const char *name;
267 /* Flags */ 267 /* Flags */
268 unsigned int flags; 268 unsigned int flags;
@@ -281,7 +281,7 @@ struct mpic
281 281
282 /* vector numbers used for internal sources (ipi/timers) */ 282 /* vector numbers used for internal sources (ipi/timers) */
283 unsigned int ipi_vecs[4]; 283 unsigned int ipi_vecs[4];
284 unsigned int timer_vecs[4]; 284 unsigned int timer_vecs[8];
285 285
286 /* Spurious vector to program into unused sources */ 286 /* Spurious vector to program into unused sources */
287 unsigned int spurious_vec; 287 unsigned int spurious_vec;
@@ -320,8 +320,6 @@ struct mpic
320 /* link */ 320 /* link */
321 struct mpic *next; 321 struct mpic *next;
322 322
323 struct sys_device sysdev;
324
325#ifdef CONFIG_PM 323#ifdef CONFIG_PM
326 struct mpic_irq_save *save_data; 324 struct mpic_irq_save *save_data;
327#endif 325#endif
@@ -371,6 +369,8 @@ struct mpic
371 * NOTE: This flag trumps MPIC_WANTS_RESET. 369 * NOTE: This flag trumps MPIC_WANTS_RESET.
372 */ 370 */
373#define MPIC_NO_RESET 0x00004000 371#define MPIC_NO_RESET 0x00004000
372/* Freescale MPIC (compatible includes "fsl,mpic") */
373#define MPIC_FSL 0x00008000
374 374
375/* MPIC HW modification ID */ 375/* MPIC HW modification ID */
376#define MPIC_REGSET_MASK 0xf0000000 376#define MPIC_REGSET_MASK 0xf0000000
diff --git a/arch/powerpc/include/asm/pSeries_reconfig.h b/arch/powerpc/include/asm/pSeries_reconfig.h
index d4b4bfa26fb3..89d2f99c1bf4 100644
--- a/arch/powerpc/include/asm/pSeries_reconfig.h
+++ b/arch/powerpc/include/asm/pSeries_reconfig.h
@@ -18,13 +18,18 @@
18extern int pSeries_reconfig_notifier_register(struct notifier_block *); 18extern int pSeries_reconfig_notifier_register(struct notifier_block *);
19extern void pSeries_reconfig_notifier_unregister(struct notifier_block *); 19extern void pSeries_reconfig_notifier_unregister(struct notifier_block *);
20extern struct blocking_notifier_head pSeries_reconfig_chain; 20extern struct blocking_notifier_head pSeries_reconfig_chain;
21/* Not the best place to put this, will be fixed when we move some
22 * of the rtas suspend-me stuff to pseries */
23extern void pSeries_coalesce_init(void);
21#else /* !CONFIG_PPC_PSERIES */ 24#else /* !CONFIG_PPC_PSERIES */
22static inline int pSeries_reconfig_notifier_register(struct notifier_block *nb) 25static inline int pSeries_reconfig_notifier_register(struct notifier_block *nb)
23{ 26{
24 return 0; 27 return 0;
25} 28}
26static inline void pSeries_reconfig_notifier_unregister(struct notifier_block *nb) { } 29static inline void pSeries_reconfig_notifier_unregister(struct notifier_block *nb) { }
30static inline void pSeries_coalesce_init(void) { }
27#endif /* CONFIG_PPC_PSERIES */ 31#endif /* CONFIG_PPC_PSERIES */
28 32
33
29#endif /* __KERNEL__ */ 34#endif /* __KERNEL__ */
30#endif /* _PPC64_PSERIES_RECONFIG_H */ 35#endif /* _PPC64_PSERIES_RECONFIG_H */
diff --git a/arch/powerpc/include/asm/paca.h b/arch/powerpc/include/asm/paca.h
index ec57540cd7af..74126765106a 100644
--- a/arch/powerpc/include/asm/paca.h
+++ b/arch/powerpc/include/asm/paca.h
@@ -92,9 +92,9 @@ struct paca_struct {
92 * Now, starting in cacheline 2, the exception save areas 92 * Now, starting in cacheline 2, the exception save areas
93 */ 93 */
94 /* used for most interrupts/exceptions */ 94 /* used for most interrupts/exceptions */
95 u64 exgen[10] __attribute__((aligned(0x80))); 95 u64 exgen[11] __attribute__((aligned(0x80)));
96 u64 exmc[10]; /* used for machine checks */ 96 u64 exmc[11]; /* used for machine checks */
97 u64 exslb[10]; /* used for SLB/segment table misses 97 u64 exslb[11]; /* used for SLB/segment table misses
98 * on the linear mapping */ 98 * on the linear mapping */
99 /* SLB related definitions */ 99 /* SLB related definitions */
100 u16 vmalloc_sllp; 100 u16 vmalloc_sllp;
@@ -106,7 +106,8 @@ struct paca_struct {
106 pgd_t *pgd; /* Current PGD */ 106 pgd_t *pgd; /* Current PGD */
107 pgd_t *kernel_pgd; /* Kernel PGD */ 107 pgd_t *kernel_pgd; /* Kernel PGD */
108 u64 exgen[8] __attribute__((aligned(0x80))); 108 u64 exgen[8] __attribute__((aligned(0x80)));
109 u64 extlb[EX_TLB_SIZE*3] __attribute__((aligned(0x80))); 109 /* We can have up to 3 levels of reentrancy in the TLB miss handler */
110 u64 extlb[3][EX_TLB_SIZE / sizeof(u64)] __attribute__((aligned(0x80)));
110 u64 exmc[8]; /* used for machine checks */ 111 u64 exmc[8]; /* used for machine checks */
111 u64 excrit[8]; /* used for crit interrupts */ 112 u64 excrit[8]; /* used for crit interrupts */
112 u64 exdbg[8]; /* used for debug interrupts */ 113 u64 exdbg[8]; /* used for debug interrupts */
@@ -125,7 +126,7 @@ struct paca_struct {
125 struct task_struct *__current; /* Pointer to current */ 126 struct task_struct *__current; /* Pointer to current */
126 u64 kstack; /* Saved Kernel stack addr */ 127 u64 kstack; /* Saved Kernel stack addr */
127 u64 stab_rr; /* stab/slb round-robin counter */ 128 u64 stab_rr; /* stab/slb round-robin counter */
128 u64 saved_r1; /* r1 save for RTAS calls */ 129 u64 saved_r1; /* r1 save for RTAS calls or PM */
129 u64 saved_msr; /* MSR saved here by enter_rtas */ 130 u64 saved_msr; /* MSR saved here by enter_rtas */
130 u16 trap_save; /* Used when bad stack is encountered */ 131 u16 trap_save; /* Used when bad stack is encountered */
131 u8 soft_enabled; /* irq soft-enable flag */ 132 u8 soft_enabled; /* irq soft-enable flag */
diff --git a/arch/powerpc/include/asm/page_64.h b/arch/powerpc/include/asm/page_64.h
index 812b2cd80aed..9356262fd3cc 100644
--- a/arch/powerpc/include/asm/page_64.h
+++ b/arch/powerpc/include/asm/page_64.h
@@ -59,24 +59,7 @@ static __inline__ void clear_page(void *addr)
59 : "ctr", "memory"); 59 : "ctr", "memory");
60} 60}
61 61
62extern void copy_4K_page(void *to, void *from); 62extern void copy_page(void *to, void *from);
63
64#ifdef CONFIG_PPC_64K_PAGES
65static inline void copy_page(void *to, void *from)
66{
67 unsigned int i;
68 for (i=0; i < (1 << (PAGE_SHIFT - 12)); i++) {
69 copy_4K_page(to, from);
70 to += 4096;
71 from += 4096;
72 }
73}
74#else /* CONFIG_PPC_64K_PAGES */
75static inline void copy_page(void *to, void *from)
76{
77 copy_4K_page(to, from);
78}
79#endif /* CONFIG_PPC_64K_PAGES */
80 63
81/* Log 2 of page table size */ 64/* Log 2 of page table size */
82extern u64 ppc64_pft_size; 65extern u64 ppc64_pft_size;
@@ -130,7 +113,7 @@ extern void slice_set_user_psize(struct mm_struct *mm, unsigned int psize);
130extern void slice_set_range_psize(struct mm_struct *mm, unsigned long start, 113extern void slice_set_range_psize(struct mm_struct *mm, unsigned long start,
131 unsigned long len, unsigned int psize); 114 unsigned long len, unsigned int psize);
132 115
133#define slice_mm_new_context(mm) ((mm)->context.id == 0) 116#define slice_mm_new_context(mm) ((mm)->context.id == MMU_NO_CONTEXT)
134 117
135#endif /* __ASSEMBLY__ */ 118#endif /* __ASSEMBLY__ */
136#else 119#else
diff --git a/arch/powerpc/include/asm/pgtable-ppc64.h b/arch/powerpc/include/asm/pgtable-ppc64.h
index 2b09cd522d33..81576ee0cfb1 100644
--- a/arch/powerpc/include/asm/pgtable-ppc64.h
+++ b/arch/powerpc/include/asm/pgtable-ppc64.h
@@ -257,21 +257,20 @@ static inline int __ptep_test_and_clear_young(struct mm_struct *mm,
257static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, 257static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
258 pte_t *ptep) 258 pte_t *ptep)
259{ 259{
260 unsigned long old;
261 260
262 if ((pte_val(*ptep) & _PAGE_RW) == 0) 261 if ((pte_val(*ptep) & _PAGE_RW) == 0)
263 return; 262 return;
264 old = pte_update(mm, addr, ptep, _PAGE_RW, 0); 263
264 pte_update(mm, addr, ptep, _PAGE_RW, 0);
265} 265}
266 266
267static inline void huge_ptep_set_wrprotect(struct mm_struct *mm, 267static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
268 unsigned long addr, pte_t *ptep) 268 unsigned long addr, pte_t *ptep)
269{ 269{
270 unsigned long old;
271
272 if ((pte_val(*ptep) & _PAGE_RW) == 0) 270 if ((pte_val(*ptep) & _PAGE_RW) == 0)
273 return; 271 return;
274 old = pte_update(mm, addr, ptep, _PAGE_RW, 1); 272
273 pte_update(mm, addr, ptep, _PAGE_RW, 1);
275} 274}
276 275
277/* 276/*
diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h
index 1255569387b6..e472659d906c 100644
--- a/arch/powerpc/include/asm/ppc-opcode.h
+++ b/arch/powerpc/include/asm/ppc-opcode.h
@@ -41,6 +41,10 @@
41#define PPC_INST_RFCI 0x4c000066 41#define PPC_INST_RFCI 0x4c000066
42#define PPC_INST_RFDI 0x4c00004e 42#define PPC_INST_RFDI 0x4c00004e
43#define PPC_INST_RFMCI 0x4c00004c 43#define PPC_INST_RFMCI 0x4c00004c
44#define PPC_INST_MFSPR_DSCR 0x7c1102a6
45#define PPC_INST_MFSPR_DSCR_MASK 0xfc1fffff
46#define PPC_INST_MTSPR_DSCR 0x7c1103a6
47#define PPC_INST_MTSPR_DSCR_MASK 0xfc1fffff
44 48
45#define PPC_INST_STRING 0x7c00042a 49#define PPC_INST_STRING 0x7c00042a
46#define PPC_INST_STRING_MASK 0xfc0007fe 50#define PPC_INST_STRING_MASK 0xfc0007fe
@@ -56,6 +60,17 @@
56#define PPC_INST_TLBSRX_DOT 0x7c0006a5 60#define PPC_INST_TLBSRX_DOT 0x7c0006a5
57#define PPC_INST_XXLOR 0xf0000510 61#define PPC_INST_XXLOR 0xf0000510
58 62
63#define PPC_INST_NAP 0x4c000364
64#define PPC_INST_SLEEP 0x4c0003a4
65
66/* A2 specific instructions */
67#define PPC_INST_ERATWE 0x7c0001a6
68#define PPC_INST_ERATRE 0x7c000166
69#define PPC_INST_ERATILX 0x7c000066
70#define PPC_INST_ERATIVAX 0x7c000666
71#define PPC_INST_ERATSX 0x7c000126
72#define PPC_INST_ERATSX_DOT 0x7c000127
73
59/* macros to insert fields into opcodes */ 74/* macros to insert fields into opcodes */
60#define __PPC_RA(a) (((a) & 0x1f) << 16) 75#define __PPC_RA(a) (((a) & 0x1f) << 16)
61#define __PPC_RB(b) (((b) & 0x1f) << 11) 76#define __PPC_RB(b) (((b) & 0x1f) << 11)
@@ -67,6 +82,8 @@
67#define __PPC_XT(s) __PPC_XS(s) 82#define __PPC_XT(s) __PPC_XS(s)
68#define __PPC_T_TLB(t) (((t) & 0x3) << 21) 83#define __PPC_T_TLB(t) (((t) & 0x3) << 21)
69#define __PPC_WC(w) (((w) & 0x3) << 21) 84#define __PPC_WC(w) (((w) & 0x3) << 21)
85#define __PPC_WS(w) (((w) & 0x1f) << 11)
86
70/* 87/*
71 * Only use the larx hint bit on 64bit CPUs. e500v1/v2 based CPUs will treat a 88 * Only use the larx hint bit on 64bit CPUs. e500v1/v2 based CPUs will treat a
72 * larx with EH set as an illegal instruction. 89 * larx with EH set as an illegal instruction.
@@ -113,6 +130,21 @@
113#define PPC_TLBIVAX(a,b) stringify_in_c(.long PPC_INST_TLBIVAX | \ 130#define PPC_TLBIVAX(a,b) stringify_in_c(.long PPC_INST_TLBIVAX | \
114 __PPC_RA(a) | __PPC_RB(b)) 131 __PPC_RA(a) | __PPC_RB(b))
115 132
133#define PPC_ERATWE(s, a, w) stringify_in_c(.long PPC_INST_ERATWE | \
134 __PPC_RS(s) | __PPC_RA(a) | __PPC_WS(w))
135#define PPC_ERATRE(s, a, w) stringify_in_c(.long PPC_INST_ERATRE | \
136 __PPC_RS(s) | __PPC_RA(a) | __PPC_WS(w))
137#define PPC_ERATILX(t, a, b) stringify_in_c(.long PPC_INST_ERATILX | \
138 __PPC_T_TLB(t) | __PPC_RA(a) | \
139 __PPC_RB(b))
140#define PPC_ERATIVAX(s, a, b) stringify_in_c(.long PPC_INST_ERATIVAX | \
141 __PPC_RS(s) | __PPC_RA(a) | __PPC_RB(b))
142#define PPC_ERATSX(t, a, w) stringify_in_c(.long PPC_INST_ERATSX | \
143 __PPC_RS(t) | __PPC_RA(a) | __PPC_RB(b))
144#define PPC_ERATSX_DOT(t, a, w) stringify_in_c(.long PPC_INST_ERATSX_DOT | \
145 __PPC_RS(t) | __PPC_RA(a) | __PPC_RB(b))
146
147
116/* 148/*
117 * Define what the VSX XX1 form instructions will look like, then add 149 * Define what the VSX XX1 form instructions will look like, then add
118 * the 128 bit load store instructions based on that. 150 * the 128 bit load store instructions based on that.
@@ -126,4 +158,7 @@
126#define XXLOR(t, a, b) stringify_in_c(.long PPC_INST_XXLOR | \ 158#define XXLOR(t, a, b) stringify_in_c(.long PPC_INST_XXLOR | \
127 VSX_XX3((t), (a), (b))) 159 VSX_XX3((t), (a), (b)))
128 160
161#define PPC_NAP stringify_in_c(.long PPC_INST_NAP)
162#define PPC_SLEEP stringify_in_c(.long PPC_INST_SLEEP)
163
129#endif /* _ASM_POWERPC_PPC_OPCODE_H */ 164#endif /* _ASM_POWERPC_PPC_OPCODE_H */
diff --git a/arch/powerpc/include/asm/ppc_asm.h b/arch/powerpc/include/asm/ppc_asm.h
index 98210067c1cc..1b422381fc16 100644
--- a/arch/powerpc/include/asm/ppc_asm.h
+++ b/arch/powerpc/include/asm/ppc_asm.h
@@ -170,6 +170,7 @@ END_FW_FTR_SECTION_IFSET(FW_FEATURE_SPLPAR)
170#define HMT_MEDIUM or 2,2,2 170#define HMT_MEDIUM or 2,2,2
171#define HMT_MEDIUM_HIGH or 5,5,5 # medium high priority 171#define HMT_MEDIUM_HIGH or 5,5,5 # medium high priority
172#define HMT_HIGH or 3,3,3 172#define HMT_HIGH or 3,3,3
173#define HMT_EXTRA_HIGH or 7,7,7 # power7 only
173 174
174#ifdef __KERNEL__ 175#ifdef __KERNEL__
175#ifdef CONFIG_PPC64 176#ifdef CONFIG_PPC64
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index de1967a1ff57..d50c2b6d9bc3 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -238,6 +238,10 @@ struct thread_struct {
238#ifdef CONFIG_KVM_BOOK3S_32_HANDLER 238#ifdef CONFIG_KVM_BOOK3S_32_HANDLER
239 void* kvm_shadow_vcpu; /* KVM internal data */ 239 void* kvm_shadow_vcpu; /* KVM internal data */
240#endif /* CONFIG_KVM_BOOK3S_32_HANDLER */ 240#endif /* CONFIG_KVM_BOOK3S_32_HANDLER */
241#ifdef CONFIG_PPC64
242 unsigned long dscr;
243 int dscr_inherit;
244#endif
241}; 245};
242 246
243#define ARCH_MIN_TASKALIGN 16 247#define ARCH_MIN_TASKALIGN 16
diff --git a/arch/powerpc/include/asm/pte-common.h b/arch/powerpc/include/asm/pte-common.h
index 811f04ac3660..8d1569c29042 100644
--- a/arch/powerpc/include/asm/pte-common.h
+++ b/arch/powerpc/include/asm/pte-common.h
@@ -162,7 +162,7 @@ extern unsigned long bad_call_to_PMD_PAGE_SIZE(void);
162 * on platforms where such control is possible. 162 * on platforms where such control is possible.
163 */ 163 */
164#if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH) ||\ 164#if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH) ||\
165 defined(CONFIG_KPROBES) 165 defined(CONFIG_KPROBES) || defined(CONFIG_DYNAMIC_FTRACE)
166#define PAGE_KERNEL_TEXT PAGE_KERNEL_X 166#define PAGE_KERNEL_TEXT PAGE_KERNEL_X
167#else 167#else
168#define PAGE_KERNEL_TEXT PAGE_KERNEL_ROX 168#define PAGE_KERNEL_TEXT PAGE_KERNEL_ROX
diff --git a/arch/powerpc/include/asm/pte-hash64-64k.h b/arch/powerpc/include/asm/pte-hash64-64k.h
index c4490f9c67c4..59247e816ac5 100644
--- a/arch/powerpc/include/asm/pte-hash64-64k.h
+++ b/arch/powerpc/include/asm/pte-hash64-64k.h
@@ -22,7 +22,7 @@
22#define _PAGE_HASHPTE _PAGE_HPTE_SUB 22#define _PAGE_HASHPTE _PAGE_HPTE_SUB
23 23
24/* Note the full page bits must be in the same location as for normal 24/* Note the full page bits must be in the same location as for normal
25 * 4k pages as the same asssembly will be used to insert 64K pages 25 * 4k pages as the same assembly will be used to insert 64K pages
26 * wether the kernel has CONFIG_PPC_64K_PAGES or not 26 * wether the kernel has CONFIG_PPC_64K_PAGES or not
27 */ 27 */
28#define _PAGE_F_SECOND 0x00008000 /* full page: hidx bits */ 28#define _PAGE_F_SECOND 0x00008000 /* full page: hidx bits */
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index 7e4abebe76c0..c5cae0dd176c 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -99,17 +99,23 @@
99#define MSR_LE __MASK(MSR_LE_LG) /* Little Endian */ 99#define MSR_LE __MASK(MSR_LE_LG) /* Little Endian */
100 100
101#if defined(CONFIG_PPC_BOOK3S_64) 101#if defined(CONFIG_PPC_BOOK3S_64)
102#define MSR_64BIT MSR_SF
103
102/* Server variant */ 104/* Server variant */
103#define MSR_ MSR_ME | MSR_RI | MSR_IR | MSR_DR | MSR_ISF |MSR_HV 105#define MSR_ MSR_ME | MSR_RI | MSR_IR | MSR_DR | MSR_ISF |MSR_HV
104#define MSR_KERNEL MSR_ | MSR_SF 106#define MSR_KERNEL MSR_ | MSR_64BIT
105#define MSR_USER32 MSR_ | MSR_PR | MSR_EE 107#define MSR_USER32 MSR_ | MSR_PR | MSR_EE
106#define MSR_USER64 MSR_USER32 | MSR_SF 108#define MSR_USER64 MSR_USER32 | MSR_64BIT
107#elif defined(CONFIG_PPC_BOOK3S_32) || defined(CONFIG_8xx) 109#elif defined(CONFIG_PPC_BOOK3S_32) || defined(CONFIG_8xx)
108/* Default MSR for kernel mode. */ 110/* Default MSR for kernel mode. */
109#define MSR_KERNEL (MSR_ME|MSR_RI|MSR_IR|MSR_DR) 111#define MSR_KERNEL (MSR_ME|MSR_RI|MSR_IR|MSR_DR)
110#define MSR_USER (MSR_KERNEL|MSR_PR|MSR_EE) 112#define MSR_USER (MSR_KERNEL|MSR_PR|MSR_EE)
111#endif 113#endif
112 114
115#ifndef MSR_64BIT
116#define MSR_64BIT 0
117#endif
118
113/* Floating Point Status and Control Register (FPSCR) Fields */ 119/* Floating Point Status and Control Register (FPSCR) Fields */
114#define FPSCR_FX 0x80000000 /* FPU exception summary */ 120#define FPSCR_FX 0x80000000 /* FPU exception summary */
115#define FPSCR_FEX 0x40000000 /* FPU enabled exception summary */ 121#define FPSCR_FEX 0x40000000 /* FPU enabled exception summary */
@@ -182,6 +188,8 @@
182 188
183#define SPRN_CTR 0x009 /* Count Register */ 189#define SPRN_CTR 0x009 /* Count Register */
184#define SPRN_DSCR 0x11 190#define SPRN_DSCR 0x11
191#define SPRN_CFAR 0x1c /* Come From Address Register */
192#define SPRN_ACOP 0x1F /* Available Coprocessor Register */
185#define SPRN_CTRLF 0x088 193#define SPRN_CTRLF 0x088
186#define SPRN_CTRLT 0x098 194#define SPRN_CTRLT 0x098
187#define CTRL_CT 0xc0000000 /* current thread */ 195#define CTRL_CT 0xc0000000 /* current thread */
@@ -210,8 +218,43 @@
210#define SPRN_TBWL 0x11C /* Time Base Lower Register (super, R/W) */ 218#define SPRN_TBWL 0x11C /* Time Base Lower Register (super, R/W) */
211#define SPRN_TBWU 0x11D /* Time Base Upper Register (super, R/W) */ 219#define SPRN_TBWU 0x11D /* Time Base Upper Register (super, R/W) */
212#define SPRN_SPURR 0x134 /* Scaled PURR */ 220#define SPRN_SPURR 0x134 /* Scaled PURR */
221#define SPRN_HSPRG0 0x130 /* Hypervisor Scratch 0 */
222#define SPRN_HSPRG1 0x131 /* Hypervisor Scratch 1 */
223#define SPRN_HDSISR 0x132
224#define SPRN_HDAR 0x133
225#define SPRN_HDEC 0x136 /* Hypervisor Decrementer */
213#define SPRN_HIOR 0x137 /* 970 Hypervisor interrupt offset */ 226#define SPRN_HIOR 0x137 /* 970 Hypervisor interrupt offset */
227#define SPRN_RMOR 0x138 /* Real mode offset register */
228#define SPRN_HRMOR 0x139 /* Real mode offset register */
229#define SPRN_HSRR0 0x13A /* Hypervisor Save/Restore 0 */
230#define SPRN_HSRR1 0x13B /* Hypervisor Save/Restore 1 */
214#define SPRN_LPCR 0x13E /* LPAR Control Register */ 231#define SPRN_LPCR 0x13E /* LPAR Control Register */
232#define LPCR_VPM0 (1ul << (63-0))
233#define LPCR_VPM1 (1ul << (63-1))
234#define LPCR_ISL (1ul << (63-2))
235#define LPCR_DPFD_SH (63-11)
236#define LPCR_VRMA_L (1ul << (63-12))
237#define LPCR_VRMA_LP0 (1ul << (63-15))
238#define LPCR_VRMA_LP1 (1ul << (63-16))
239#define LPCR_RMLS 0x1C000000 /* impl dependent rmo limit sel */
240#define LPCR_ILE 0x02000000 /* !HV irqs set MSR:LE */
241#define LPCR_PECE 0x00007000 /* powersave exit cause enable */
242#define LPCR_PECE0 0x00004000 /* ext. exceptions can cause exit */
243#define LPCR_PECE1 0x00002000 /* decrementer can cause exit */
244#define LPCR_PECE2 0x00001000 /* machine check etc can cause exit */
245#define LPCR_MER 0x00000800 /* Mediated External Exception */
246#define LPCR_LPES0 0x00000008 /* LPAR Env selector 0 */
247#define LPCR_LPES1 0x00000004 /* LPAR Env selector 1 */
248#define LPCR_RMI 0x00000002 /* real mode is cache inhibit */
249#define LPCR_HDICE 0x00000001 /* Hyp Decr enable (HV,PR,EE) */
250#define SPRN_LPID 0x13F /* Logical Partition Identifier */
251#define SPRN_HMER 0x150 /* Hardware m? error recovery */
252#define SPRN_HMEER 0x151 /* Hardware m? enable error recovery */
253#define SPRN_HEIR 0x153 /* Hypervisor Emulated Instruction Register */
254#define SPRN_TLBINDEXR 0x154 /* P7 TLB control register */
255#define SPRN_TLBVPNR 0x155 /* P7 TLB control register */
256#define SPRN_TLBRPNR 0x156 /* P7 TLB control register */
257#define SPRN_TLBLPIDR 0x157 /* P7 TLB control register */
215#define SPRN_DBAT0L 0x219 /* Data BAT 0 Lower Register */ 258#define SPRN_DBAT0L 0x219 /* Data BAT 0 Lower Register */
216#define SPRN_DBAT0U 0x218 /* Data BAT 0 Upper Register */ 259#define SPRN_DBAT0U 0x218 /* Data BAT 0 Upper Register */
217#define SPRN_DBAT1L 0x21B /* Data BAT 1 Lower Register */ 260#define SPRN_DBAT1L 0x21B /* Data BAT 1 Lower Register */
@@ -434,16 +477,23 @@
434#define SPRN_SRR0 0x01A /* Save/Restore Register 0 */ 477#define SPRN_SRR0 0x01A /* Save/Restore Register 0 */
435#define SPRN_SRR1 0x01B /* Save/Restore Register 1 */ 478#define SPRN_SRR1 0x01B /* Save/Restore Register 1 */
436#define SRR1_WAKEMASK 0x00380000 /* reason for wakeup */ 479#define SRR1_WAKEMASK 0x00380000 /* reason for wakeup */
437#define SRR1_WAKERESET 0x00380000 /* System reset */
438#define SRR1_WAKESYSERR 0x00300000 /* System error */ 480#define SRR1_WAKESYSERR 0x00300000 /* System error */
439#define SRR1_WAKEEE 0x00200000 /* External interrupt */ 481#define SRR1_WAKEEE 0x00200000 /* External interrupt */
440#define SRR1_WAKEMT 0x00280000 /* mtctrl */ 482#define SRR1_WAKEMT 0x00280000 /* mtctrl */
483#define SRR1_WAKEHMI 0x00280000 /* Hypervisor maintenance */
441#define SRR1_WAKEDEC 0x00180000 /* Decrementer interrupt */ 484#define SRR1_WAKEDEC 0x00180000 /* Decrementer interrupt */
442#define SRR1_WAKETHERM 0x00100000 /* Thermal management interrupt */ 485#define SRR1_WAKETHERM 0x00100000 /* Thermal management interrupt */
486#define SRR1_WAKERESET 0x00100000 /* System reset */
487#define SRR1_WAKESTATE 0x00030000 /* Powersave exit mask [46:47] */
488#define SRR1_WS_DEEPEST 0x00030000 /* Some resources not maintained,
489 * may not be recoverable */
490#define SRR1_WS_DEEPER 0x00020000 /* Some resources not maintained */
491#define SRR1_WS_DEEP 0x00010000 /* All resources maintained */
443#define SRR1_PROGFPE 0x00100000 /* Floating Point Enabled */ 492#define SRR1_PROGFPE 0x00100000 /* Floating Point Enabled */
444#define SRR1_PROGPRIV 0x00040000 /* Privileged instruction */ 493#define SRR1_PROGPRIV 0x00040000 /* Privileged instruction */
445#define SRR1_PROGTRAP 0x00020000 /* Trap */ 494#define SRR1_PROGTRAP 0x00020000 /* Trap */
446#define SRR1_PROGADDR 0x00010000 /* SRR0 contains subsequent addr */ 495#define SRR1_PROGADDR 0x00010000 /* SRR0 contains subsequent addr */
496
447#define SPRN_HSRR0 0x13A /* Save/Restore Register 0 */ 497#define SPRN_HSRR0 0x13A /* Save/Restore Register 0 */
448#define SPRN_HSRR1 0x13B /* Save/Restore Register 1 */ 498#define SPRN_HSRR1 0x13B /* Save/Restore Register 1 */
449 499
@@ -673,12 +723,15 @@
673 * SPRG usage: 723 * SPRG usage:
674 * 724 *
675 * All 64-bit: 725 * All 64-bit:
676 * - SPRG1 stores PACA pointer 726 * - SPRG1 stores PACA pointer except 64-bit server in
727 * HV mode in which case it is HSPRG0
677 * 728 *
678 * 64-bit server: 729 * 64-bit server:
679 * - SPRG0 unused (reserved for HV on Power4) 730 * - SPRG0 unused (reserved for HV on Power4)
680 * - SPRG2 scratch for exception vectors 731 * - SPRG2 scratch for exception vectors
681 * - SPRG3 unused (user visible) 732 * - SPRG3 unused (user visible)
733 * - HSPRG0 stores PACA in HV mode
734 * - HSPRG1 scratch for "HV" exceptions
682 * 735 *
683 * 64-bit embedded 736 * 64-bit embedded
684 * - SPRG0 generic exception scratch 737 * - SPRG0 generic exception scratch
@@ -741,6 +794,41 @@
741 794
742#ifdef CONFIG_PPC_BOOK3S_64 795#ifdef CONFIG_PPC_BOOK3S_64
743#define SPRN_SPRG_SCRATCH0 SPRN_SPRG2 796#define SPRN_SPRG_SCRATCH0 SPRN_SPRG2
797#define SPRN_SPRG_HPACA SPRN_HSPRG0
798#define SPRN_SPRG_HSCRATCH0 SPRN_HSPRG1
799
800#define GET_PACA(rX) \
801 BEGIN_FTR_SECTION_NESTED(66); \
802 mfspr rX,SPRN_SPRG_PACA; \
803 FTR_SECTION_ELSE_NESTED(66); \
804 mfspr rX,SPRN_SPRG_HPACA; \
805 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE_206, 66)
806
807#define SET_PACA(rX) \
808 BEGIN_FTR_SECTION_NESTED(66); \
809 mtspr SPRN_SPRG_PACA,rX; \
810 FTR_SECTION_ELSE_NESTED(66); \
811 mtspr SPRN_SPRG_HPACA,rX; \
812 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE_206, 66)
813
814#define GET_SCRATCH0(rX) \
815 BEGIN_FTR_SECTION_NESTED(66); \
816 mfspr rX,SPRN_SPRG_SCRATCH0; \
817 FTR_SECTION_ELSE_NESTED(66); \
818 mfspr rX,SPRN_SPRG_HSCRATCH0; \
819 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE_206, 66)
820
821#define SET_SCRATCH0(rX) \
822 BEGIN_FTR_SECTION_NESTED(66); \
823 mtspr SPRN_SPRG_SCRATCH0,rX; \
824 FTR_SECTION_ELSE_NESTED(66); \
825 mtspr SPRN_SPRG_HSCRATCH0,rX; \
826 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE_206, 66)
827
828#else /* CONFIG_PPC_BOOK3S_64 */
829#define GET_SCRATCH0(rX) mfspr rX,SPRN_SPRG_SCRATCH0
830#define SET_SCRATCH0(rX) mtspr SPRN_SPRG_SCRATCH0,rX
831
744#endif 832#endif
745 833
746#ifdef CONFIG_PPC_BOOK3E_64 834#ifdef CONFIG_PPC_BOOK3E_64
@@ -750,6 +838,10 @@
750#define SPRN_SPRG_TLB_EXFRAME SPRN_SPRG2 838#define SPRN_SPRG_TLB_EXFRAME SPRN_SPRG2
751#define SPRN_SPRG_TLB_SCRATCH SPRN_SPRG6 839#define SPRN_SPRG_TLB_SCRATCH SPRN_SPRG6
752#define SPRN_SPRG_GEN_SCRATCH SPRN_SPRG0 840#define SPRN_SPRG_GEN_SCRATCH SPRN_SPRG0
841
842#define SET_PACA(rX) mtspr SPRN_SPRG_PACA,rX
843#define GET_PACA(rX) mfspr rX,SPRN_SPRG_PACA
844
753#endif 845#endif
754 846
755#ifdef CONFIG_PPC_BOOK3S_32 847#ifdef CONFIG_PPC_BOOK3S_32
@@ -800,6 +892,8 @@
800#define SPRN_SPRG_SCRATCH1 SPRN_SPRG1 892#define SPRN_SPRG_SCRATCH1 SPRN_SPRG1
801#endif 893#endif
802 894
895
896
803/* 897/*
804 * An mtfsf instruction with the L bit set. On CPUs that support this a 898 * An mtfsf instruction with the L bit set. On CPUs that support this a
805 * full 64bits of FPSCR is restored and on other CPUs the L bit is ignored. 899 * full 64bits of FPSCR is restored and on other CPUs the L bit is ignored.
@@ -894,6 +988,8 @@
894#define PV_POWER5p 0x003B 988#define PV_POWER5p 0x003B
895#define PV_POWER7 0x003F 989#define PV_POWER7 0x003F
896#define PV_970FX 0x003C 990#define PV_970FX 0x003C
991#define PV_POWER6 0x003E
992#define PV_POWER7 0x003F
897#define PV_630 0x0040 993#define PV_630 0x0040
898#define PV_630p 0x0041 994#define PV_630p 0x0041
899#define PV_970MP 0x0044 995#define PV_970MP 0x0044
diff --git a/arch/powerpc/include/asm/reg_a2.h b/arch/powerpc/include/asm/reg_a2.h
new file mode 100644
index 000000000000..3d52a1132f3d
--- /dev/null
+++ b/arch/powerpc/include/asm/reg_a2.h
@@ -0,0 +1,165 @@
1/*
2 * Register definitions specific to the A2 core
3 *
4 * Copyright (C) 2008 Ben. Herrenschmidt (benh@kernel.crashing.org), IBM Corp.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12#ifndef __ASM_POWERPC_REG_A2_H__
13#define __ASM_POWERPC_REG_A2_H__
14
15#define SPRN_TENSR 0x1b5
16#define SPRN_TENS 0x1b6 /* Thread ENable Set */
17#define SPRN_TENC 0x1b7 /* Thread ENable Clear */
18
19#define SPRN_A2_CCR0 0x3f0 /* Core Configuration Register 0 */
20#define SPRN_A2_CCR1 0x3f1 /* Core Configuration Register 1 */
21#define SPRN_A2_CCR2 0x3f2 /* Core Configuration Register 2 */
22#define SPRN_MMUCR0 0x3fc /* MMU Control Register 0 */
23#define SPRN_MMUCR1 0x3fd /* MMU Control Register 1 */
24#define SPRN_MMUCR2 0x3fe /* MMU Control Register 2 */
25#define SPRN_MMUCR3 0x3ff /* MMU Control Register 3 */
26
27#define SPRN_IAR 0x372
28
29#define SPRN_IUCR0 0x3f3
30#define IUCR0_ICBI_ACK 0x1000
31
32#define SPRN_XUCR0 0x3f6 /* Execution Unit Config Register 0 */
33
34#define A2_IERAT_SIZE 16
35#define A2_DERAT_SIZE 32
36
37/* A2 MMUCR0 bits */
38#define MMUCR0_ECL 0x80000000 /* Extended Class for TLB fills */
39#define MMUCR0_TID_NZ 0x40000000 /* TID is non-zero */
40#define MMUCR0_TS 0x10000000 /* Translation space for TLB fills */
41#define MMUCR0_TGS 0x20000000 /* Guest space for TLB fills */
42#define MMUCR0_TLBSEL 0x0c000000 /* TLB or ERAT target for TLB fills */
43#define MMUCR0_TLBSEL_U 0x00000000 /* TLBSEL = UTLB */
44#define MMUCR0_TLBSEL_I 0x08000000 /* TLBSEL = I-ERAT */
45#define MMUCR0_TLBSEL_D 0x0c000000 /* TLBSEL = D-ERAT */
46#define MMUCR0_LOCKSRSH 0x02000000 /* Use TLB lock on tlbsx. */
47#define MMUCR0_TID_MASK 0x000000ff /* TID field */
48
49/* A2 MMUCR1 bits */
50#define MMUCR1_IRRE 0x80000000 /* I-ERAT round robin enable */
51#define MMUCR1_DRRE 0x40000000 /* D-ERAT round robin enable */
52#define MMUCR1_REE 0x20000000 /* Reference Exception Enable*/
53#define MMUCR1_CEE 0x10000000 /* Change exception enable */
54#define MMUCR1_CSINV_ALL 0x00000000 /* Inval ERAT on all CS evts */
55#define MMUCR1_CSINV_NISYNC 0x04000000 /* Inval ERAT on all ex isync*/
56#define MMUCR1_CSINV_NEVER 0x0c000000 /* Don't inval ERAT on CS */
57#define MMUCR1_ICTID 0x00080000 /* IERAT class field as TID */
58#define MMUCR1_ITTID 0x00040000 /* IERAT thdid field as TID */
59#define MMUCR1_DCTID 0x00020000 /* DERAT class field as TID */
60#define MMUCR1_DTTID 0x00010000 /* DERAT thdid field as TID */
61#define MMUCR1_DCCD 0x00008000 /* DERAT class ignore */
62#define MMUCR1_TLBWE_BINV 0x00004000 /* back invalidate on tlbwe */
63
64/* A2 MMUCR2 bits */
65#define MMUCR2_PSSEL_SHIFT 4
66
67/* A2 MMUCR3 bits */
68#define MMUCR3_THID 0x0000000f /* Thread ID */
69
70/* *** ERAT TLB bits definitions */
71#define TLB0_EPN_MASK ASM_CONST(0xfffffffffffff000)
72#define TLB0_CLASS_MASK ASM_CONST(0x0000000000000c00)
73#define TLB0_CLASS_00 ASM_CONST(0x0000000000000000)
74#define TLB0_CLASS_01 ASM_CONST(0x0000000000000400)
75#define TLB0_CLASS_10 ASM_CONST(0x0000000000000800)
76#define TLB0_CLASS_11 ASM_CONST(0x0000000000000c00)
77#define TLB0_V ASM_CONST(0x0000000000000200)
78#define TLB0_X ASM_CONST(0x0000000000000100)
79#define TLB0_SIZE_MASK ASM_CONST(0x00000000000000f0)
80#define TLB0_SIZE_4K ASM_CONST(0x0000000000000010)
81#define TLB0_SIZE_64K ASM_CONST(0x0000000000000030)
82#define TLB0_SIZE_1M ASM_CONST(0x0000000000000050)
83#define TLB0_SIZE_16M ASM_CONST(0x0000000000000070)
84#define TLB0_SIZE_1G ASM_CONST(0x00000000000000a0)
85#define TLB0_THDID_MASK ASM_CONST(0x000000000000000f)
86#define TLB0_THDID_0 ASM_CONST(0x0000000000000001)
87#define TLB0_THDID_1 ASM_CONST(0x0000000000000002)
88#define TLB0_THDID_2 ASM_CONST(0x0000000000000004)
89#define TLB0_THDID_3 ASM_CONST(0x0000000000000008)
90#define TLB0_THDID_ALL ASM_CONST(0x000000000000000f)
91
92#define TLB1_RESVATTR ASM_CONST(0x00f0000000000000)
93#define TLB1_U0 ASM_CONST(0x0008000000000000)
94#define TLB1_U1 ASM_CONST(0x0004000000000000)
95#define TLB1_U2 ASM_CONST(0x0002000000000000)
96#define TLB1_U3 ASM_CONST(0x0001000000000000)
97#define TLB1_R ASM_CONST(0x0000800000000000)
98#define TLB1_C ASM_CONST(0x0000400000000000)
99#define TLB1_RPN_MASK ASM_CONST(0x000003fffffff000)
100#define TLB1_W ASM_CONST(0x0000000000000800)
101#define TLB1_I ASM_CONST(0x0000000000000400)
102#define TLB1_M ASM_CONST(0x0000000000000200)
103#define TLB1_G ASM_CONST(0x0000000000000100)
104#define TLB1_E ASM_CONST(0x0000000000000080)
105#define TLB1_VF ASM_CONST(0x0000000000000040)
106#define TLB1_UX ASM_CONST(0x0000000000000020)
107#define TLB1_SX ASM_CONST(0x0000000000000010)
108#define TLB1_UW ASM_CONST(0x0000000000000008)
109#define TLB1_SW ASM_CONST(0x0000000000000004)
110#define TLB1_UR ASM_CONST(0x0000000000000002)
111#define TLB1_SR ASM_CONST(0x0000000000000001)
112
113#ifdef CONFIG_PPC_EARLY_DEBUG_WSP
114#define WSP_UART_PHYS 0xffc000c000
115/* This needs to be careful chosen to hit a !0 congruence class
116 * in the TLB since we bolt it in way 3, which is already occupied
117 * by our linear mapping primary bolted entry in CC 0.
118 */
119#define WSP_UART_VIRT 0xf000000000001000
120#endif
121
122/* A2 erativax attributes definitions */
123#define ERATIVAX_RS_IS_ALL 0x000
124#define ERATIVAX_RS_IS_TID 0x040
125#define ERATIVAX_RS_IS_CLASS 0x080
126#define ERATIVAX_RS_IS_FULLMATCH 0x0c0
127#define ERATIVAX_CLASS_00 0x000
128#define ERATIVAX_CLASS_01 0x010
129#define ERATIVAX_CLASS_10 0x020
130#define ERATIVAX_CLASS_11 0x030
131#define ERATIVAX_PSIZE_4K (TLB_PSIZE_4K >> 1)
132#define ERATIVAX_PSIZE_64K (TLB_PSIZE_64K >> 1)
133#define ERATIVAX_PSIZE_1M (TLB_PSIZE_1M >> 1)
134#define ERATIVAX_PSIZE_16M (TLB_PSIZE_16M >> 1)
135#define ERATIVAX_PSIZE_1G (TLB_PSIZE_1G >> 1)
136
137/* A2 eratilx attributes definitions */
138#define ERATILX_T_ALL 0
139#define ERATILX_T_TID 1
140#define ERATILX_T_TGS 2
141#define ERATILX_T_FULLMATCH 3
142#define ERATILX_T_CLASS0 4
143#define ERATILX_T_CLASS1 5
144#define ERATILX_T_CLASS2 6
145#define ERATILX_T_CLASS3 7
146
147/* XUCR0 bits */
148#define XUCR0_TRACE_UM_T0 0x40000000 /* Thread 0 */
149#define XUCR0_TRACE_UM_T1 0x20000000 /* Thread 1 */
150#define XUCR0_TRACE_UM_T2 0x10000000 /* Thread 2 */
151#define XUCR0_TRACE_UM_T3 0x08000000 /* Thread 3 */
152
153/* A2 CCR0 register */
154#define A2_CCR0_PME_DISABLED 0x00000000
155#define A2_CCR0_PME_SLEEP 0x40000000
156#define A2_CCR0_PME_RVW 0x80000000
157#define A2_CCR0_PME_DISABLED2 0xc0000000
158
159/* A2 CCR2 register */
160#define A2_CCR2_ERAT_ONLY_MODE 0x00000001
161#define A2_CCR2_ENABLE_ICSWX 0x00000002
162#define A2_CCR2_ENABLE_PC 0x20000000
163#define A2_CCR2_ENABLE_TRACE 0x40000000
164
165#endif /* __ASM_POWERPC_REG_A2_H__ */
diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h
index b316794aa2b5..0f0ad9fa01c1 100644
--- a/arch/powerpc/include/asm/reg_booke.h
+++ b/arch/powerpc/include/asm/reg_booke.h
@@ -27,10 +27,12 @@
27#define MSR_CM (1<<31) /* Computation Mode (0=32-bit, 1=64-bit) */ 27#define MSR_CM (1<<31) /* Computation Mode (0=32-bit, 1=64-bit) */
28 28
29#if defined(CONFIG_PPC_BOOK3E_64) 29#if defined(CONFIG_PPC_BOOK3E_64)
30#define MSR_64BIT MSR_CM
31
30#define MSR_ MSR_ME | MSR_CE 32#define MSR_ MSR_ME | MSR_CE
31#define MSR_KERNEL MSR_ | MSR_CM 33#define MSR_KERNEL MSR_ | MSR_64BIT
32#define MSR_USER32 MSR_ | MSR_PR | MSR_EE | MSR_DE 34#define MSR_USER32 MSR_ | MSR_PR | MSR_EE | MSR_DE
33#define MSR_USER64 MSR_USER32 | MSR_CM | MSR_DE 35#define MSR_USER64 MSR_USER32 | MSR_64BIT
34#elif defined (CONFIG_40x) 36#elif defined (CONFIG_40x)
35#define MSR_KERNEL (MSR_ME|MSR_RI|MSR_IR|MSR_DR|MSR_CE) 37#define MSR_KERNEL (MSR_ME|MSR_RI|MSR_IR|MSR_DR|MSR_CE)
36#define MSR_USER (MSR_KERNEL|MSR_PR|MSR_EE) 38#define MSR_USER (MSR_KERNEL|MSR_PR|MSR_EE)
@@ -81,6 +83,10 @@
81#define SPRN_IVOR13 0x19D /* Interrupt Vector Offset Register 13 */ 83#define SPRN_IVOR13 0x19D /* Interrupt Vector Offset Register 13 */
82#define SPRN_IVOR14 0x19E /* Interrupt Vector Offset Register 14 */ 84#define SPRN_IVOR14 0x19E /* Interrupt Vector Offset Register 14 */
83#define SPRN_IVOR15 0x19F /* Interrupt Vector Offset Register 15 */ 85#define SPRN_IVOR15 0x19F /* Interrupt Vector Offset Register 15 */
86#define SPRN_IVOR38 0x1B0 /* Interrupt Vector Offset Register 38 */
87#define SPRN_IVOR39 0x1B1 /* Interrupt Vector Offset Register 39 */
88#define SPRN_IVOR40 0x1B2 /* Interrupt Vector Offset Register 40 */
89#define SPRN_IVOR41 0x1B3 /* Interrupt Vector Offset Register 41 */
84#define SPRN_SPEFSCR 0x200 /* SPE & Embedded FP Status & Control */ 90#define SPRN_SPEFSCR 0x200 /* SPE & Embedded FP Status & Control */
85#define SPRN_BBEAR 0x201 /* Branch Buffer Entry Address Register */ 91#define SPRN_BBEAR 0x201 /* Branch Buffer Entry Address Register */
86#define SPRN_BBTAR 0x202 /* Branch Buffer Target Address Register */ 92#define SPRN_BBTAR 0x202 /* Branch Buffer Target Address Register */
diff --git a/arch/powerpc/include/asm/rtas.h b/arch/powerpc/include/asm/rtas.h
index 9a1193e30f26..58625d1e7802 100644
--- a/arch/powerpc/include/asm/rtas.h
+++ b/arch/powerpc/include/asm/rtas.h
@@ -158,7 +158,50 @@ struct rtas_error_log {
158 unsigned long target:4; /* Target of failed operation */ 158 unsigned long target:4; /* Target of failed operation */
159 unsigned long type:8; /* General event or error*/ 159 unsigned long type:8; /* General event or error*/
160 unsigned long extended_log_length:32; /* length in bytes */ 160 unsigned long extended_log_length:32; /* length in bytes */
161 unsigned char buffer[1]; 161 unsigned char buffer[1]; /* Start of extended log */
162 /* Variable length. */
163};
164
165#define RTAS_V6EXT_LOG_FORMAT_EVENT_LOG 14
166
167#define RTAS_V6EXT_COMPANY_ID_IBM (('I' << 24) | ('B' << 16) | ('M' << 8))
168
169/* RTAS general extended event log, Version 6. The extended log starts
170 * from "buffer" field of struct rtas_error_log defined above.
171 */
172struct rtas_ext_event_log_v6 {
173 /* Byte 0 */
174 uint32_t log_valid:1; /* 1:Log valid */
175 uint32_t unrecoverable_error:1; /* 1:Unrecoverable error */
176 uint32_t recoverable_error:1; /* 1:recoverable (correctable */
177 /* or successfully retried) */
178 uint32_t degraded_operation:1; /* 1:Unrecoverable err, bypassed*/
179 /* - degraded operation (e.g. */
180 /* CPU or mem taken off-line) */
181 uint32_t predictive_error:1;
182 uint32_t new_log:1; /* 1:"New" log (Always 1 for */
183 /* data returned from RTAS */
184 uint32_t big_endian:1; /* 1: Big endian */
185 uint32_t :1; /* reserved */
186 /* Byte 1 */
187 uint32_t :8; /* reserved */
188 /* Byte 2 */
189 uint32_t powerpc_format:1; /* Set to 1 (indicating log is */
190 /* in PowerPC format */
191 uint32_t :3; /* reserved */
192 uint32_t log_format:4; /* Log format indicator. Define */
193 /* format used for byte 12-2047 */
194 /* Byte 3 */
195 uint32_t :8; /* reserved */
196 /* Byte 4-11 */
197 uint8_t reserved[8]; /* reserved */
198 /* Byte 12-15 */
199 uint32_t company_id; /* Company ID of the company */
200 /* that defines the format for */
201 /* the vendor specific log type */
202 /* Byte 16-end of log */
203 uint8_t vendor_log[1]; /* Start of vendor specific log */
204 /* Variable length. */
162}; 205};
163 206
164/* 207/*
diff --git a/arch/powerpc/include/asm/scom.h b/arch/powerpc/include/asm/scom.h
new file mode 100644
index 000000000000..0cabfd7bc2d1
--- /dev/null
+++ b/arch/powerpc/include/asm/scom.h
@@ -0,0 +1,156 @@
1/*
2 * Copyright 2010 Benjamin Herrenschmidt, IBM Corp
3 * <benh@kernel.crashing.org>
4 * and David Gibson, IBM Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
14 * the GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#ifndef _ASM_POWERPC_SCOM_H
22#define _ASM_POWERPC_SCOM_H
23
24#ifdef __KERNEL__
25#ifndef __ASSEMBLY__
26#ifdef CONFIG_PPC_SCOM
27
28/*
29 * The SCOM bus is a sideband bus used for accessing various internal
30 * registers of the processor or the chipset. The implementation details
31 * differ between processors and platforms, and the access method as
32 * well.
33 *
34 * This API allows to "map" ranges of SCOM register numbers associated
35 * with a given SCOM controller. The later must be represented by a
36 * device node, though some implementations might support NULL if there
37 * is no possible ambiguity
38 *
39 * Then, scom_read/scom_write can be used to accesses registers inside
40 * that range. The argument passed is a register number relative to
41 * the beginning of the range mapped.
42 */
43
44typedef void *scom_map_t;
45
46/* Value for an invalid SCOM map */
47#define SCOM_MAP_INVALID (NULL)
48
49/* The scom_controller data structure is what the platform passes
50 * to the core code in scom_init, it provides the actual implementation
51 * of all the SCOM functions
52 */
53struct scom_controller {
54 scom_map_t (*map)(struct device_node *ctrl_dev, u64 reg, u64 count);
55 void (*unmap)(scom_map_t map);
56
57 u64 (*read)(scom_map_t map, u32 reg);
58 void (*write)(scom_map_t map, u32 reg, u64 value);
59};
60
61extern const struct scom_controller *scom_controller;
62
63/**
64 * scom_init - Initialize the SCOM backend, called by the platform
65 * @controller: The platform SCOM controller
66 */
67static inline void scom_init(const struct scom_controller *controller)
68{
69 scom_controller = controller;
70}
71
72/**
73 * scom_map_ok - Test is a SCOM mapping is successful
74 * @map: The result of scom_map to test
75 */
76static inline int scom_map_ok(scom_map_t map)
77{
78 return map != SCOM_MAP_INVALID;
79}
80
81/**
82 * scom_map - Map a block of SCOM registers
83 * @ctrl_dev: Device node of the SCOM controller
84 * some implementations allow NULL here
85 * @reg: first SCOM register to map
86 * @count: Number of SCOM registers to map
87 */
88
89static inline scom_map_t scom_map(struct device_node *ctrl_dev,
90 u64 reg, u64 count)
91{
92 return scom_controller->map(ctrl_dev, reg, count);
93}
94
95/**
96 * scom_find_parent - Find the SCOM controller for a device
97 * @dev: OF node of the device
98 *
99 * This is not meant for general usage, but in combination with
100 * scom_map() allows to map registers not represented by the
101 * device own scom-reg property. Useful for applying HW workarounds
102 * on things not properly represented in the device-tree for example.
103 */
104struct device_node *scom_find_parent(struct device_node *dev);
105
106
107/**
108 * scom_map_device - Map a device's block of SCOM registers
109 * @dev: OF node of the device
110 * @index: Register bank index (index in "scom-reg" property)
111 *
112 * This function will use the device-tree binding for SCOM which
113 * is to follow "scom-parent" properties until it finds a node with
114 * a "scom-controller" property to find the controller. It will then
115 * use the "scom-reg" property which is made of reg/count pairs,
116 * each of them having a size defined by the controller's #scom-cells
117 * property
118 */
119extern scom_map_t scom_map_device(struct device_node *dev, int index);
120
121
122/**
123 * scom_unmap - Unmap a block of SCOM registers
124 * @map: Result of scom_map is to be unmapped
125 */
126static inline void scom_unmap(scom_map_t map)
127{
128 if (scom_map_ok(map))
129 scom_controller->unmap(map);
130}
131
132/**
133 * scom_read - Read a SCOM register
134 * @map: Result of scom_map
135 * @reg: Register index within that map
136 */
137static inline u64 scom_read(scom_map_t map, u32 reg)
138{
139 return scom_controller->read(map, reg);
140}
141
142/**
143 * scom_write - Write to a SCOM register
144 * @map: Result of scom_map
145 * @reg: Register index within that map
146 * @value: Value to write
147 */
148static inline void scom_write(scom_map_t map, u32 reg, u64 value)
149{
150 scom_controller->write(map, reg, value);
151}
152
153#endif /* CONFIG_PPC_SCOM */
154#endif /* __ASSEMBLY__ */
155#endif /* __KERNEL__ */
156#endif /* _ASM_POWERPC_SCOM_H */
diff --git a/arch/powerpc/include/asm/smp.h b/arch/powerpc/include/asm/smp.h
index a902a0d3ae0d..880b8c1e6e53 100644
--- a/arch/powerpc/include/asm/smp.h
+++ b/arch/powerpc/include/asm/smp.h
@@ -20,6 +20,7 @@
20#include <linux/threads.h> 20#include <linux/threads.h>
21#include <linux/cpumask.h> 21#include <linux/cpumask.h>
22#include <linux/kernel.h> 22#include <linux/kernel.h>
23#include <linux/irqreturn.h>
23 24
24#ifndef __ASSEMBLY__ 25#ifndef __ASSEMBLY__
25 26
@@ -29,14 +30,32 @@
29#include <asm/percpu.h> 30#include <asm/percpu.h>
30 31
31extern int boot_cpuid; 32extern int boot_cpuid;
33extern int boot_cpu_count;
32 34
33extern void cpu_die(void); 35extern void cpu_die(void);
34 36
35#ifdef CONFIG_SMP 37#ifdef CONFIG_SMP
36 38
37extern void smp_send_debugger_break(int cpu); 39struct smp_ops_t {
38extern void smp_message_recv(int); 40 void (*message_pass)(int cpu, int msg);
41#ifdef CONFIG_PPC_SMP_MUXED_IPI
42 void (*cause_ipi)(int cpu, unsigned long data);
43#endif
44 int (*probe)(void);
45 int (*kick_cpu)(int nr);
46 void (*setup_cpu)(int nr);
47 void (*bringup_done)(void);
48 void (*take_timebase)(void);
49 void (*give_timebase)(void);
50 int (*cpu_disable)(void);
51 void (*cpu_die)(unsigned int nr);
52 int (*cpu_bootable)(unsigned int nr);
53};
54
55extern void smp_send_debugger_break(void);
39extern void start_secondary_resume(void); 56extern void start_secondary_resume(void);
57extern void __devinit smp_generic_give_timebase(void);
58extern void __devinit smp_generic_take_timebase(void);
40 59
41DECLARE_PER_CPU(unsigned int, cpu_pvr); 60DECLARE_PER_CPU(unsigned int, cpu_pvr);
42 61
@@ -93,13 +112,16 @@ extern int cpu_to_core_id(int cpu);
93#define PPC_MSG_CALL_FUNC_SINGLE 2 112#define PPC_MSG_CALL_FUNC_SINGLE 2
94#define PPC_MSG_DEBUGGER_BREAK 3 113#define PPC_MSG_DEBUGGER_BREAK 3
95 114
96/* 115/* for irq controllers that have dedicated ipis per message (4) */
97 * irq controllers that have dedicated ipis per message and don't
98 * need additional code in the action handler may use this
99 */
100extern int smp_request_message_ipi(int virq, int message); 116extern int smp_request_message_ipi(int virq, int message);
101extern const char *smp_ipi_name[]; 117extern const char *smp_ipi_name[];
102 118
119/* for irq controllers with only a single ipi */
120extern void smp_muxed_ipi_set_data(int cpu, unsigned long data);
121extern void smp_muxed_ipi_message_pass(int cpu, int msg);
122extern void smp_muxed_ipi_resend(void);
123extern irqreturn_t smp_ipi_demux(void);
124
103void smp_init_iSeries(void); 125void smp_init_iSeries(void);
104void smp_init_pSeries(void); 126void smp_init_pSeries(void);
105void smp_init_cell(void); 127void smp_init_cell(void);
@@ -149,7 +171,7 @@ extern int smt_enabled_at_boot;
149 171
150extern int smp_mpic_probe(void); 172extern int smp_mpic_probe(void);
151extern void smp_mpic_setup_cpu(int cpu); 173extern void smp_mpic_setup_cpu(int cpu);
152extern void smp_generic_kick_cpu(int nr); 174extern int smp_generic_kick_cpu(int nr);
153 175
154extern void smp_generic_give_timebase(void); 176extern void smp_generic_give_timebase(void);
155extern void smp_generic_take_timebase(void); 177extern void smp_generic_take_timebase(void);
@@ -169,6 +191,8 @@ extern unsigned long __secondary_hold_spinloop;
169extern unsigned long __secondary_hold_acknowledge; 191extern unsigned long __secondary_hold_acknowledge;
170extern char __secondary_hold; 192extern char __secondary_hold;
171 193
194extern irqreturn_t debug_ipi_action(int irq, void *data);
195
172#endif /* __ASSEMBLY__ */ 196#endif /* __ASSEMBLY__ */
173 197
174#endif /* __KERNEL__ */ 198#endif /* __KERNEL__ */
diff --git a/arch/powerpc/include/asm/systbl.h b/arch/powerpc/include/asm/systbl.h
index 60f64b132bd4..8489d372077f 100644
--- a/arch/powerpc/include/asm/systbl.h
+++ b/arch/powerpc/include/asm/systbl.h
@@ -352,3 +352,4 @@ SYSCALL_SPU(name_to_handle_at)
352COMPAT_SYS_SPU(open_by_handle_at) 352COMPAT_SYS_SPU(open_by_handle_at)
353COMPAT_SYS_SPU(clock_adjtime) 353COMPAT_SYS_SPU(clock_adjtime)
354SYSCALL_SPU(syncfs) 354SYSCALL_SPU(syncfs)
355COMPAT_SYS_SPU(sendmmsg)
diff --git a/arch/powerpc/include/asm/system.h b/arch/powerpc/include/asm/system.h
index 5e474ddd2273..2dc595dda03b 100644
--- a/arch/powerpc/include/asm/system.h
+++ b/arch/powerpc/include/asm/system.h
@@ -219,8 +219,6 @@ extern int mem_init_done; /* set on boot once kmalloc can be called */
219extern int init_bootmem_done; /* set once bootmem is available */ 219extern int init_bootmem_done; /* set once bootmem is available */
220extern phys_addr_t memory_limit; 220extern phys_addr_t memory_limit;
221extern unsigned long klimit; 221extern unsigned long klimit;
222
223extern void *alloc_maybe_bootmem(size_t size, gfp_t mask);
224extern void *zalloc_maybe_bootmem(size_t size, gfp_t mask); 222extern void *zalloc_maybe_bootmem(size_t size, gfp_t mask);
225 223
226extern int powersave_nap; /* set if nap mode can be used in idle loop */ 224extern int powersave_nap; /* set if nap mode can be used in idle loop */
diff --git a/arch/powerpc/include/asm/tlbflush.h b/arch/powerpc/include/asm/tlbflush.h
index d50a380b2b6f..81143fcbd113 100644
--- a/arch/powerpc/include/asm/tlbflush.h
+++ b/arch/powerpc/include/asm/tlbflush.h
@@ -79,6 +79,8 @@ static inline void local_flush_tlb_mm(struct mm_struct *mm)
79 79
80#elif defined(CONFIG_PPC_STD_MMU_64) 80#elif defined(CONFIG_PPC_STD_MMU_64)
81 81
82#define MMU_NO_CONTEXT 0
83
82/* 84/*
83 * TLB flushing for 64-bit hash-MMU CPUs 85 * TLB flushing for 64-bit hash-MMU CPUs
84 */ 86 */
diff --git a/arch/powerpc/include/asm/udbg.h b/arch/powerpc/include/asm/udbg.h
index 11ae699135ba..58580e94a2bb 100644
--- a/arch/powerpc/include/asm/udbg.h
+++ b/arch/powerpc/include/asm/udbg.h
@@ -52,6 +52,7 @@ extern void __init udbg_init_44x_as1(void);
52extern void __init udbg_init_40x_realmode(void); 52extern void __init udbg_init_40x_realmode(void);
53extern void __init udbg_init_cpm(void); 53extern void __init udbg_init_cpm(void);
54extern void __init udbg_init_usbgecko(void); 54extern void __init udbg_init_usbgecko(void);
55extern void __init udbg_init_wsp(void);
55 56
56#endif /* __KERNEL__ */ 57#endif /* __KERNEL__ */
57#endif /* _ASM_POWERPC_UDBG_H */ 58#endif /* _ASM_POWERPC_UDBG_H */
diff --git a/arch/powerpc/include/asm/uninorth.h b/arch/powerpc/include/asm/uninorth.h
index ae9c899c8a6d..d12b11d7641e 100644
--- a/arch/powerpc/include/asm/uninorth.h
+++ b/arch/powerpc/include/asm/uninorth.h
@@ -60,7 +60,7 @@
60 * 60 *
61 * Obviously, the GART is not cache coherent and so any change to it 61 * Obviously, the GART is not cache coherent and so any change to it
62 * must be flushed to memory (or maybe just make the GART space non 62 * must be flushed to memory (or maybe just make the GART space non
63 * cachable). AGP memory itself does't seem to be cache coherent neither. 63 * cachable). AGP memory itself doesn't seem to be cache coherent neither.
64 * 64 *
65 * In order to invalidate the GART (which is probably necessary to inval 65 * In order to invalidate the GART (which is probably necessary to inval
66 * the bridge internal TLBs), the following sequence has to be written, 66 * the bridge internal TLBs), the following sequence has to be written,
diff --git a/arch/powerpc/include/asm/unistd.h b/arch/powerpc/include/asm/unistd.h
index 3c215648ce6d..6d23c8193caa 100644
--- a/arch/powerpc/include/asm/unistd.h
+++ b/arch/powerpc/include/asm/unistd.h
@@ -371,10 +371,11 @@
371#define __NR_open_by_handle_at 346 371#define __NR_open_by_handle_at 346
372#define __NR_clock_adjtime 347 372#define __NR_clock_adjtime 347
373#define __NR_syncfs 348 373#define __NR_syncfs 348
374#define __NR_sendmmsg 349
374 375
375#ifdef __KERNEL__ 376#ifdef __KERNEL__
376 377
377#define __NR_syscalls 349 378#define __NR_syscalls 350
378 379
379#define __NR__exit __NR_exit 380#define __NR__exit __NR_exit
380#define NR_syscalls __NR_syscalls 381#define NR_syscalls __NR_syscalls
diff --git a/arch/powerpc/include/asm/wsp.h b/arch/powerpc/include/asm/wsp.h
new file mode 100644
index 000000000000..c7dc83088a33
--- /dev/null
+++ b/arch/powerpc/include/asm/wsp.h
@@ -0,0 +1,14 @@
1/*
2 * Copyright 2011 Michael Ellerman, IBM Corp.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 */
9#ifndef __ASM_POWERPC_WSP_H
10#define __ASM_POWERPC_WSP_H
11
12extern int wsp_get_chip_id(struct device_node *dn);
13
14#endif /* __ASM_POWERPC_WSP_H */
diff --git a/arch/powerpc/include/asm/xics.h b/arch/powerpc/include/asm/xics.h
new file mode 100644
index 000000000000..b183a4062011
--- /dev/null
+++ b/arch/powerpc/include/asm/xics.h
@@ -0,0 +1,142 @@
1/*
2 * Common definitions accross all variants of ICP and ICS interrupt
3 * controllers.
4 */
5
6#ifndef _XICS_H
7#define _XICS_H
8
9#include <linux/interrupt.h>
10
11#define XICS_IPI 2
12#define XICS_IRQ_SPURIOUS 0
13
14/* Want a priority other than 0. Various HW issues require this. */
15#define DEFAULT_PRIORITY 5
16
17/*
18 * Mark IPIs as higher priority so we can take them inside interrupts that
19 * arent marked IRQF_DISABLED
20 */
21#define IPI_PRIORITY 4
22
23/* The least favored priority */
24#define LOWEST_PRIORITY 0xFF
25
26/* The number of priorities defined above */
27#define MAX_NUM_PRIORITIES 3
28
29/* Native ICP */
30extern int icp_native_init(void);
31
32/* PAPR ICP */
33extern int icp_hv_init(void);
34
35/* ICP ops */
36struct icp_ops {
37 unsigned int (*get_irq)(void);
38 void (*eoi)(struct irq_data *d);
39 void (*set_priority)(unsigned char prio);
40 void (*teardown_cpu)(void);
41 void (*flush_ipi)(void);
42#ifdef CONFIG_SMP
43 void (*cause_ipi)(int cpu, unsigned long data);
44 irq_handler_t ipi_action;
45#endif
46};
47
48extern const struct icp_ops *icp_ops;
49
50/* Native ICS */
51extern int ics_native_init(void);
52
53/* RTAS ICS */
54extern int ics_rtas_init(void);
55
56/* ICS instance, hooked up to chip_data of an irq */
57struct ics {
58 struct list_head link;
59 int (*map)(struct ics *ics, unsigned int virq);
60 void (*mask_unknown)(struct ics *ics, unsigned long vec);
61 long (*get_server)(struct ics *ics, unsigned long vec);
62 int (*host_match)(struct ics *ics, struct device_node *node);
63 char data[];
64};
65
66/* Commons */
67extern unsigned int xics_default_server;
68extern unsigned int xics_default_distrib_server;
69extern unsigned int xics_interrupt_server_size;
70extern struct irq_host *xics_host;
71
72struct xics_cppr {
73 unsigned char stack[MAX_NUM_PRIORITIES];
74 int index;
75};
76
77DECLARE_PER_CPU(struct xics_cppr, xics_cppr);
78
79static inline void xics_push_cppr(unsigned int vec)
80{
81 struct xics_cppr *os_cppr = &__get_cpu_var(xics_cppr);
82
83 if (WARN_ON(os_cppr->index >= MAX_NUM_PRIORITIES - 1))
84 return;
85
86 if (vec == XICS_IPI)
87 os_cppr->stack[++os_cppr->index] = IPI_PRIORITY;
88 else
89 os_cppr->stack[++os_cppr->index] = DEFAULT_PRIORITY;
90}
91
92static inline unsigned char xics_pop_cppr(void)
93{
94 struct xics_cppr *os_cppr = &__get_cpu_var(xics_cppr);
95
96 if (WARN_ON(os_cppr->index < 1))
97 return LOWEST_PRIORITY;
98
99 return os_cppr->stack[--os_cppr->index];
100}
101
102static inline void xics_set_base_cppr(unsigned char cppr)
103{
104 struct xics_cppr *os_cppr = &__get_cpu_var(xics_cppr);
105
106 /* we only really want to set the priority when there's
107 * just one cppr value on the stack
108 */
109 WARN_ON(os_cppr->index != 0);
110
111 os_cppr->stack[0] = cppr;
112}
113
114static inline unsigned char xics_cppr_top(void)
115{
116 struct xics_cppr *os_cppr = &__get_cpu_var(xics_cppr);
117
118 return os_cppr->stack[os_cppr->index];
119}
120
121DECLARE_PER_CPU_SHARED_ALIGNED(unsigned long, xics_ipi_message);
122
123extern void xics_init(void);
124extern void xics_setup_cpu(void);
125extern void xics_update_irq_servers(void);
126extern void xics_set_cpu_giq(unsigned int gserver, unsigned int join);
127extern void xics_mask_unknown_vec(unsigned int vec);
128extern irqreturn_t xics_ipi_dispatch(int cpu);
129extern int xics_smp_probe(void);
130extern void xics_register_ics(struct ics *ics);
131extern void xics_teardown_cpu(void);
132extern void xics_kexec_teardown_cpu(int secondary);
133extern void xics_migrate_irqs_away(void);
134#ifdef CONFIG_SMP
135extern int xics_get_irq_server(unsigned int virq, const struct cpumask *cpumask,
136 unsigned int strict_check);
137#else
138#define xics_get_irq_server(virq, cpumask, strict_check) (xics_default_server)
139#endif
140
141
142#endif /* _XICS_H */
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