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-rw-r--r--arch/powerpc/include/asm/asm-compat.h2
-rw-r--r--arch/powerpc/include/asm/code-patching.h4
-rw-r--r--arch/powerpc/include/asm/device.h3
-rw-r--r--arch/powerpc/include/asm/epapr_hcalls.h2
-rw-r--r--arch/powerpc/include/asm/exception-64s.h4
-rw-r--r--arch/powerpc/include/asm/hw_irq.h8
-rw-r--r--arch/powerpc/include/asm/immap_qe.h4
-rw-r--r--arch/powerpc/include/asm/io.h8
-rw-r--r--arch/powerpc/include/asm/iommu.h18
-rw-r--r--arch/powerpc/include/asm/kvm_book3s_64.h7
-rw-r--r--arch/powerpc/include/asm/kvm_book3s_asm.h1
-rw-r--r--arch/powerpc/include/asm/kvm_host.h6
-rw-r--r--arch/powerpc/include/asm/kvm_ppc.h3
-rw-r--r--arch/powerpc/include/asm/mmu.h7
-rw-r--r--arch/powerpc/include/asm/pci-bridge.h1
-rw-r--r--arch/powerpc/include/asm/perf_event.h5
-rw-r--r--arch/powerpc/include/asm/ppc-opcode.h118
-rw-r--r--arch/powerpc/include/asm/ppc_asm.h121
-rw-r--r--arch/powerpc/include/asm/processor.h2
-rw-r--r--arch/powerpc/include/asm/qe.h1
-rw-r--r--arch/powerpc/include/asm/reg.h8
-rw-r--r--arch/powerpc/include/asm/thread_info.h6
-rw-r--r--arch/powerpc/include/asm/trace.h45
-rw-r--r--arch/powerpc/include/asm/vdso.h2
-rw-r--r--arch/powerpc/include/asm/vio.h2
25 files changed, 256 insertions, 132 deletions
diff --git a/arch/powerpc/include/asm/asm-compat.h b/arch/powerpc/include/asm/asm-compat.h
index 5d7fbe1950f9..6e82f5f9a6fd 100644
--- a/arch/powerpc/include/asm/asm-compat.h
+++ b/arch/powerpc/include/asm/asm-compat.h
@@ -29,7 +29,7 @@
29#define PPC_LLARX(t, a, b, eh) PPC_LDARX(t, a, b, eh) 29#define PPC_LLARX(t, a, b, eh) PPC_LDARX(t, a, b, eh)
30#define PPC_STLCX stringify_in_c(stdcx.) 30#define PPC_STLCX stringify_in_c(stdcx.)
31#define PPC_CNTLZL stringify_in_c(cntlzd) 31#define PPC_CNTLZL stringify_in_c(cntlzd)
32#define PPC_MTOCRF(FXM, RS) MTOCRF((FXM), (RS)) 32#define PPC_MTOCRF(FXM, RS) MTOCRF((FXM), RS)
33#define PPC_LR_STKOFF 16 33#define PPC_LR_STKOFF 16
34#define PPC_MIN_STKFRM 112 34#define PPC_MIN_STKFRM 112
35#else /* 32-bit */ 35#else /* 32-bit */
diff --git a/arch/powerpc/include/asm/code-patching.h b/arch/powerpc/include/asm/code-patching.h
index 37c32aba79b7..a6f8c7a5cbb7 100644
--- a/arch/powerpc/include/asm/code-patching.h
+++ b/arch/powerpc/include/asm/code-patching.h
@@ -26,8 +26,8 @@ unsigned int create_branch(const unsigned int *addr,
26 unsigned long target, int flags); 26 unsigned long target, int flags);
27unsigned int create_cond_branch(const unsigned int *addr, 27unsigned int create_cond_branch(const unsigned int *addr,
28 unsigned long target, int flags); 28 unsigned long target, int flags);
29void patch_branch(unsigned int *addr, unsigned long target, int flags); 29int patch_branch(unsigned int *addr, unsigned long target, int flags);
30void patch_instruction(unsigned int *addr, unsigned int instr); 30int patch_instruction(unsigned int *addr, unsigned int instr);
31 31
32int instr_is_relative_branch(unsigned int instr); 32int instr_is_relative_branch(unsigned int instr);
33int instr_is_branch_to_addr(const unsigned int *instr, unsigned long addr); 33int instr_is_branch_to_addr(const unsigned int *instr, unsigned long addr);
diff --git a/arch/powerpc/include/asm/device.h b/arch/powerpc/include/asm/device.h
index 63d5ca49cece..77e97dd0c15d 100644
--- a/arch/powerpc/include/asm/device.h
+++ b/arch/powerpc/include/asm/device.h
@@ -34,6 +34,9 @@ struct dev_archdata {
34#ifdef CONFIG_EEH 34#ifdef CONFIG_EEH
35 struct eeh_dev *edev; 35 struct eeh_dev *edev;
36#endif 36#endif
37#ifdef CONFIG_FAIL_IOMMU
38 int fail_iommu;
39#endif
37}; 40};
38 41
39struct pdev_archdata { 42struct pdev_archdata {
diff --git a/arch/powerpc/include/asm/epapr_hcalls.h b/arch/powerpc/include/asm/epapr_hcalls.h
index 976835d8f22e..bf2c06c33871 100644
--- a/arch/powerpc/include/asm/epapr_hcalls.h
+++ b/arch/powerpc/include/asm/epapr_hcalls.h
@@ -153,6 +153,8 @@
153#define EV_HCALL_CLOBBERS2 EV_HCALL_CLOBBERS3, "r5" 153#define EV_HCALL_CLOBBERS2 EV_HCALL_CLOBBERS3, "r5"
154#define EV_HCALL_CLOBBERS1 EV_HCALL_CLOBBERS2, "r4" 154#define EV_HCALL_CLOBBERS1 EV_HCALL_CLOBBERS2, "r4"
155 155
156extern bool epapr_paravirt_enabled;
157extern u32 epapr_hypercall_start[];
156 158
157/* 159/*
158 * We use "uintptr_t" to define a register because it's guaranteed to be a 160 * We use "uintptr_t" to define a register because it's guaranteed to be a
diff --git a/arch/powerpc/include/asm/exception-64s.h b/arch/powerpc/include/asm/exception-64s.h
index d58fc4e4149c..a43c1473915f 100644
--- a/arch/powerpc/include/asm/exception-64s.h
+++ b/arch/powerpc/include/asm/exception-64s.h
@@ -293,7 +293,7 @@ label##_hv: \
293 293
294#define RUNLATCH_ON \ 294#define RUNLATCH_ON \
295BEGIN_FTR_SECTION \ 295BEGIN_FTR_SECTION \
296 clrrdi r3,r1,THREAD_SHIFT; \ 296 CURRENT_THREAD_INFO(r3, r1); \
297 ld r4,TI_LOCAL_FLAGS(r3); \ 297 ld r4,TI_LOCAL_FLAGS(r3); \
298 andi. r0,r4,_TLF_RUNLATCH; \ 298 andi. r0,r4,_TLF_RUNLATCH; \
299 beql ppc64_runlatch_on_trampoline; \ 299 beql ppc64_runlatch_on_trampoline; \
@@ -332,7 +332,7 @@ label##_common: \
332#ifdef CONFIG_PPC_970_NAP 332#ifdef CONFIG_PPC_970_NAP
333#define FINISH_NAP \ 333#define FINISH_NAP \
334BEGIN_FTR_SECTION \ 334BEGIN_FTR_SECTION \
335 clrrdi r11,r1,THREAD_SHIFT; \ 335 CURRENT_THREAD_INFO(r11, r1); \
336 ld r9,TI_LOCAL_FLAGS(r11); \ 336 ld r9,TI_LOCAL_FLAGS(r11); \
337 andi. r10,r9,_TLF_NAPPING; \ 337 andi. r10,r9,_TLF_NAPPING; \
338 bnel power4_fixup_nap; \ 338 bnel power4_fixup_nap; \
diff --git a/arch/powerpc/include/asm/hw_irq.h b/arch/powerpc/include/asm/hw_irq.h
index 6eb75b80488c..e45c4947a772 100644
--- a/arch/powerpc/include/asm/hw_irq.h
+++ b/arch/powerpc/include/asm/hw_irq.h
@@ -34,6 +34,8 @@ extern void __replay_interrupt(unsigned int vector);
34 34
35extern void timer_interrupt(struct pt_regs *); 35extern void timer_interrupt(struct pt_regs *);
36extern void performance_monitor_exception(struct pt_regs *regs); 36extern void performance_monitor_exception(struct pt_regs *regs);
37extern void WatchdogException(struct pt_regs *regs);
38extern void unknown_exception(struct pt_regs *regs);
37 39
38#ifdef CONFIG_PPC64 40#ifdef CONFIG_PPC64
39#include <asm/paca.h> 41#include <asm/paca.h>
@@ -86,8 +88,8 @@ static inline bool arch_irqs_disabled(void)
86} 88}
87 89
88#ifdef CONFIG_PPC_BOOK3E 90#ifdef CONFIG_PPC_BOOK3E
89#define __hard_irq_enable() asm volatile("wrteei 1" : : : "memory"); 91#define __hard_irq_enable() asm volatile("wrteei 1" : : : "memory")
90#define __hard_irq_disable() asm volatile("wrteei 0" : : : "memory"); 92#define __hard_irq_disable() asm volatile("wrteei 0" : : : "memory")
91#else 93#else
92#define __hard_irq_enable() __mtmsrd(local_paca->kernel_msr | MSR_EE, 1) 94#define __hard_irq_enable() __mtmsrd(local_paca->kernel_msr | MSR_EE, 1)
93#define __hard_irq_disable() __mtmsrd(local_paca->kernel_msr, 1) 95#define __hard_irq_disable() __mtmsrd(local_paca->kernel_msr, 1)
@@ -125,6 +127,8 @@ static inline bool arch_irq_disabled_regs(struct pt_regs *regs)
125 return !regs->softe; 127 return !regs->softe;
126} 128}
127 129
130extern bool prep_irq_for_idle(void);
131
128#else /* CONFIG_PPC64 */ 132#else /* CONFIG_PPC64 */
129 133
130#define SET_MSR_EE(x) mtmsr(x) 134#define SET_MSR_EE(x) mtmsr(x)
diff --git a/arch/powerpc/include/asm/immap_qe.h b/arch/powerpc/include/asm/immap_qe.h
index 0edb6842b13d..61e8490786b8 100644
--- a/arch/powerpc/include/asm/immap_qe.h
+++ b/arch/powerpc/include/asm/immap_qe.h
@@ -26,7 +26,9 @@
26struct qe_iram { 26struct qe_iram {
27 __be32 iadd; /* I-RAM Address Register */ 27 __be32 iadd; /* I-RAM Address Register */
28 __be32 idata; /* I-RAM Data Register */ 28 __be32 idata; /* I-RAM Data Register */
29 u8 res0[0x78]; 29 u8 res0[0x04];
30 __be32 iready; /* I-RAM Ready Register */
31 u8 res1[0x70];
30} __attribute__ ((packed)); 32} __attribute__ ((packed));
31 33
32/* QE Interrupt Controller */ 34/* QE Interrupt Controller */
diff --git a/arch/powerpc/include/asm/io.h b/arch/powerpc/include/asm/io.h
index a3855b81eada..f94ef4213e9d 100644
--- a/arch/powerpc/include/asm/io.h
+++ b/arch/powerpc/include/asm/io.h
@@ -20,6 +20,14 @@ extern int check_legacy_ioport(unsigned long base_port);
20#define _PNPWRP 0xa79 20#define _PNPWRP 0xa79
21#define PNPBIOS_BASE 0xf000 21#define PNPBIOS_BASE 0xf000
22 22
23#if defined(CONFIG_PPC64) && defined(CONFIG_PCI)
24extern struct pci_dev *isa_bridge_pcidev;
25/*
26 * has legacy ISA devices ?
27 */
28#define arch_has_dev_port() (isa_bridge_pcidev != NULL)
29#endif
30
23#include <linux/device.h> 31#include <linux/device.h>
24#include <linux/io.h> 32#include <linux/io.h>
25 33
diff --git a/arch/powerpc/include/asm/iommu.h b/arch/powerpc/include/asm/iommu.h
index 957a83f43646..cbfe678e3dbe 100644
--- a/arch/powerpc/include/asm/iommu.h
+++ b/arch/powerpc/include/asm/iommu.h
@@ -53,6 +53,16 @@ static __inline__ __attribute_const__ int get_iommu_order(unsigned long size)
53 */ 53 */
54#define IOMAP_MAX_ORDER 13 54#define IOMAP_MAX_ORDER 13
55 55
56#define IOMMU_POOL_HASHBITS 2
57#define IOMMU_NR_POOLS (1 << IOMMU_POOL_HASHBITS)
58
59struct iommu_pool {
60 unsigned long start;
61 unsigned long end;
62 unsigned long hint;
63 spinlock_t lock;
64} ____cacheline_aligned_in_smp;
65
56struct iommu_table { 66struct iommu_table {
57 unsigned long it_busno; /* Bus number this table belongs to */ 67 unsigned long it_busno; /* Bus number this table belongs to */
58 unsigned long it_size; /* Size of iommu table in entries */ 68 unsigned long it_size; /* Size of iommu table in entries */
@@ -61,10 +71,10 @@ struct iommu_table {
61 unsigned long it_index; /* which iommu table this is */ 71 unsigned long it_index; /* which iommu table this is */
62 unsigned long it_type; /* type: PCI or Virtual Bus */ 72 unsigned long it_type; /* type: PCI or Virtual Bus */
63 unsigned long it_blocksize; /* Entries in each block (cacheline) */ 73 unsigned long it_blocksize; /* Entries in each block (cacheline) */
64 unsigned long it_hint; /* Hint for next alloc */ 74 unsigned long poolsize;
65 unsigned long it_largehint; /* Hint for large allocs */ 75 unsigned long nr_pools;
66 unsigned long it_halfpoint; /* Breaking point for small/large allocs */ 76 struct iommu_pool large_pool;
67 spinlock_t it_lock; /* Protects it_map */ 77 struct iommu_pool pools[IOMMU_NR_POOLS];
68 unsigned long *it_map; /* A simple allocation bitmap for now */ 78 unsigned long *it_map; /* A simple allocation bitmap for now */
69}; 79};
70 80
diff --git a/arch/powerpc/include/asm/kvm_book3s_64.h b/arch/powerpc/include/asm/kvm_book3s_64.h
index b0c08b142770..0dd1d86d3e31 100644
--- a/arch/powerpc/include/asm/kvm_book3s_64.h
+++ b/arch/powerpc/include/asm/kvm_book3s_64.h
@@ -36,11 +36,8 @@ static inline void svcpu_put(struct kvmppc_book3s_shadow_vcpu *svcpu)
36#define SPAPR_TCE_SHIFT 12 36#define SPAPR_TCE_SHIFT 12
37 37
38#ifdef CONFIG_KVM_BOOK3S_64_HV 38#ifdef CONFIG_KVM_BOOK3S_64_HV
39/* For now use fixed-size 16MB page table */ 39#define KVM_DEFAULT_HPT_ORDER 24 /* 16MB HPT by default */
40#define HPT_ORDER 24 40extern int kvm_hpt_order; /* order of preallocated HPTs */
41#define HPT_NPTEG (1ul << (HPT_ORDER - 7)) /* 128B per pteg */
42#define HPT_NPTE (HPT_NPTEG << 3) /* 8 PTEs per PTEG */
43#define HPT_HASH_MASK (HPT_NPTEG - 1)
44#endif 41#endif
45 42
46#define VRMA_VSID 0x1ffffffUL /* 1TB VSID reserved for VRMA */ 43#define VRMA_VSID 0x1ffffffUL /* 1TB VSID reserved for VRMA */
diff --git a/arch/powerpc/include/asm/kvm_book3s_asm.h b/arch/powerpc/include/asm/kvm_book3s_asm.h
index 88609b23b775..bfcd00c1485d 100644
--- a/arch/powerpc/include/asm/kvm_book3s_asm.h
+++ b/arch/powerpc/include/asm/kvm_book3s_asm.h
@@ -74,6 +74,7 @@ struct kvmppc_host_state {
74 ulong vmhandler; 74 ulong vmhandler;
75 ulong scratch0; 75 ulong scratch0;
76 ulong scratch1; 76 ulong scratch1;
77 ulong sprg3;
77 u8 in_guest; 78 u8 in_guest;
78 u8 restore_hid5; 79 u8 restore_hid5;
79 u8 napping; 80 u8 napping;
diff --git a/arch/powerpc/include/asm/kvm_host.h b/arch/powerpc/include/asm/kvm_host.h
index d848cdc49715..50ea12fd7bf5 100644
--- a/arch/powerpc/include/asm/kvm_host.h
+++ b/arch/powerpc/include/asm/kvm_host.h
@@ -237,6 +237,10 @@ struct kvm_arch {
237 unsigned long vrma_slb_v; 237 unsigned long vrma_slb_v;
238 int rma_setup_done; 238 int rma_setup_done;
239 int using_mmu_notifiers; 239 int using_mmu_notifiers;
240 u32 hpt_order;
241 atomic_t vcpus_running;
242 unsigned long hpt_npte;
243 unsigned long hpt_mask;
240 spinlock_t slot_phys_lock; 244 spinlock_t slot_phys_lock;
241 unsigned long *slot_phys[KVM_MEM_SLOTS_NUM]; 245 unsigned long *slot_phys[KVM_MEM_SLOTS_NUM];
242 int slot_npages[KVM_MEM_SLOTS_NUM]; 246 int slot_npages[KVM_MEM_SLOTS_NUM];
@@ -414,7 +418,9 @@ struct kvm_vcpu_arch {
414 ulong mcsrr1; 418 ulong mcsrr1;
415 ulong mcsr; 419 ulong mcsr;
416 u32 dec; 420 u32 dec;
421#ifdef CONFIG_BOOKE
417 u32 decar; 422 u32 decar;
423#endif
418 u32 tbl; 424 u32 tbl;
419 u32 tbu; 425 u32 tbu;
420 u32 tcr; 426 u32 tcr;
diff --git a/arch/powerpc/include/asm/kvm_ppc.h b/arch/powerpc/include/asm/kvm_ppc.h
index f68c22fa2fce..0124937a23b9 100644
--- a/arch/powerpc/include/asm/kvm_ppc.h
+++ b/arch/powerpc/include/asm/kvm_ppc.h
@@ -119,7 +119,8 @@ extern void kvmppc_core_destroy_mmu(struct kvm_vcpu *vcpu);
119extern int kvmppc_kvm_pv(struct kvm_vcpu *vcpu); 119extern int kvmppc_kvm_pv(struct kvm_vcpu *vcpu);
120extern void kvmppc_map_magic(struct kvm_vcpu *vcpu); 120extern void kvmppc_map_magic(struct kvm_vcpu *vcpu);
121 121
122extern long kvmppc_alloc_hpt(struct kvm *kvm); 122extern long kvmppc_alloc_hpt(struct kvm *kvm, u32 *htab_orderp);
123extern long kvmppc_alloc_reset_hpt(struct kvm *kvm, u32 *htab_orderp);
123extern void kvmppc_free_hpt(struct kvm *kvm); 124extern void kvmppc_free_hpt(struct kvm *kvm);
124extern long kvmppc_prepare_vrma(struct kvm *kvm, 125extern long kvmppc_prepare_vrma(struct kvm *kvm,
125 struct kvm_userspace_memory_region *mem); 126 struct kvm_userspace_memory_region *mem);
diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h
index f0145522cfba..e8a26db2e8f3 100644
--- a/arch/powerpc/include/asm/mmu.h
+++ b/arch/powerpc/include/asm/mmu.h
@@ -163,12 +163,7 @@ extern u64 ppc64_rma_size;
163 * to think about, feedback welcome. --BenH. 163 * to think about, feedback welcome. --BenH.
164 */ 164 */
165 165
166/* There are #define as they have to be used in assembly 166/* These are #defines as they have to be used in assembly */
167 *
168 * WARNING: If you change this list, make sure to update the array of
169 * names currently in arch/powerpc/mm/hugetlbpage.c or bad things will
170 * happen
171 */
172#define MMU_PAGE_4K 0 167#define MMU_PAGE_4K 0
173#define MMU_PAGE_16K 1 168#define MMU_PAGE_16K 1
174#define MMU_PAGE_64K 2 169#define MMU_PAGE_64K 2
diff --git a/arch/powerpc/include/asm/pci-bridge.h b/arch/powerpc/include/asm/pci-bridge.h
index ac39e6a3b25a..8cccbee61519 100644
--- a/arch/powerpc/include/asm/pci-bridge.h
+++ b/arch/powerpc/include/asm/pci-bridge.h
@@ -30,6 +30,7 @@ struct pci_controller {
30 int first_busno; 30 int first_busno;
31 int last_busno; 31 int last_busno;
32 int self_busno; 32 int self_busno;
33 struct resource busn;
33 34
34 void __iomem *io_base_virt; 35 void __iomem *io_base_virt;
35#ifdef CONFIG_PPC64 36#ifdef CONFIG_PPC64
diff --git a/arch/powerpc/include/asm/perf_event.h b/arch/powerpc/include/asm/perf_event.h
index 5c16b891d501..0bb23725b1e7 100644
--- a/arch/powerpc/include/asm/perf_event.h
+++ b/arch/powerpc/include/asm/perf_event.h
@@ -26,8 +26,13 @@
26#include <asm/ptrace.h> 26#include <asm/ptrace.h>
27#include <asm/reg.h> 27#include <asm/reg.h>
28 28
29/*
30 * Overload regs->result to specify whether we should use the MSR (result
31 * is zero) or the SIAR (result is non zero).
32 */
29#define perf_arch_fetch_caller_regs(regs, __ip) \ 33#define perf_arch_fetch_caller_regs(regs, __ip) \
30 do { \ 34 do { \
35 (regs)->result = 0; \
31 (regs)->nip = __ip; \ 36 (regs)->nip = __ip; \
32 (regs)->gpr[1] = *(unsigned long *)__get_SP(); \ 37 (regs)->gpr[1] = *(unsigned long *)__get_SP(); \
33 asm volatile("mfmsr %0" : "=r" ((regs)->msr)); \ 38 asm volatile("mfmsr %0" : "=r" ((regs)->msr)); \
diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h
index d81f99430fe7..4c25319f2fbc 100644
--- a/arch/powerpc/include/asm/ppc-opcode.h
+++ b/arch/powerpc/include/asm/ppc-opcode.h
@@ -15,6 +15,72 @@
15#include <linux/stringify.h> 15#include <linux/stringify.h>
16#include <asm/asm-compat.h> 16#include <asm/asm-compat.h>
17 17
18#define __REG_R0 0
19#define __REG_R1 1
20#define __REG_R2 2
21#define __REG_R3 3
22#define __REG_R4 4
23#define __REG_R5 5
24#define __REG_R6 6
25#define __REG_R7 7
26#define __REG_R8 8
27#define __REG_R9 9
28#define __REG_R10 10
29#define __REG_R11 11
30#define __REG_R12 12
31#define __REG_R13 13
32#define __REG_R14 14
33#define __REG_R15 15
34#define __REG_R16 16
35#define __REG_R17 17
36#define __REG_R18 18
37#define __REG_R19 19
38#define __REG_R20 20
39#define __REG_R21 21
40#define __REG_R22 22
41#define __REG_R23 23
42#define __REG_R24 24
43#define __REG_R25 25
44#define __REG_R26 26
45#define __REG_R27 27
46#define __REG_R28 28
47#define __REG_R29 29
48#define __REG_R30 30
49#define __REG_R31 31
50
51#define __REGA0_0 0
52#define __REGA0_R1 1
53#define __REGA0_R2 2
54#define __REGA0_R3 3
55#define __REGA0_R4 4
56#define __REGA0_R5 5
57#define __REGA0_R6 6
58#define __REGA0_R7 7
59#define __REGA0_R8 8
60#define __REGA0_R9 9
61#define __REGA0_R10 10
62#define __REGA0_R11 11
63#define __REGA0_R12 12
64#define __REGA0_R13 13
65#define __REGA0_R14 14
66#define __REGA0_R15 15
67#define __REGA0_R16 16
68#define __REGA0_R17 17
69#define __REGA0_R18 18
70#define __REGA0_R19 19
71#define __REGA0_R20 20
72#define __REGA0_R21 21
73#define __REGA0_R22 22
74#define __REGA0_R23 23
75#define __REGA0_R24 24
76#define __REGA0_R25 25
77#define __REGA0_R26 26
78#define __REGA0_R27 27
79#define __REGA0_R28 28
80#define __REGA0_R29 29
81#define __REGA0_R30 30
82#define __REGA0_R31 31
83
18/* sorted alphabetically */ 84/* sorted alphabetically */
19#define PPC_INST_DCBA 0x7c0005ec 85#define PPC_INST_DCBA 0x7c0005ec
20#define PPC_INST_DCBA_MASK 0xfc0007fe 86#define PPC_INST_DCBA_MASK 0xfc0007fe
@@ -107,12 +173,19 @@
107#define PPC_INST_NEG 0x7c0000d0 173#define PPC_INST_NEG 0x7c0000d0
108#define PPC_INST_BRANCH 0x48000000 174#define PPC_INST_BRANCH 0x48000000
109#define PPC_INST_BRANCH_COND 0x40800000 175#define PPC_INST_BRANCH_COND 0x40800000
176#define PPC_INST_LBZCIX 0x7c0006aa
177#define PPC_INST_STBCIX 0x7c0007aa
110 178
111/* macros to insert fields into opcodes */ 179/* macros to insert fields into opcodes */
112#define __PPC_RA(a) (((a) & 0x1f) << 16) 180#define ___PPC_RA(a) (((a) & 0x1f) << 16)
113#define __PPC_RB(b) (((b) & 0x1f) << 11) 181#define ___PPC_RB(b) (((b) & 0x1f) << 11)
114#define __PPC_RS(s) (((s) & 0x1f) << 21) 182#define ___PPC_RS(s) (((s) & 0x1f) << 21)
115#define __PPC_RT(s) __PPC_RS(s) 183#define ___PPC_RT(t) ___PPC_RS(t)
184#define __PPC_RA(a) ___PPC_RA(__REG_##a)
185#define __PPC_RA0(a) ___PPC_RA(__REGA0_##a)
186#define __PPC_RB(b) ___PPC_RB(__REG_##b)
187#define __PPC_RS(s) ___PPC_RS(__REG_##s)
188#define __PPC_RT(t) ___PPC_RT(__REG_##t)
116#define __PPC_XA(a) ((((a) & 0x1f) << 16) | (((a) & 0x20) >> 3)) 189#define __PPC_XA(a) ((((a) & 0x1f) << 16) | (((a) & 0x20) >> 3))
117#define __PPC_XB(b) ((((b) & 0x1f) << 11) | (((b) & 0x20) >> 4)) 190#define __PPC_XB(b) ((((b) & 0x1f) << 11) | (((b) & 0x20) >> 4))
118#define __PPC_XS(s) ((((s) & 0x1f) << 21) | (((s) & 0x20) >> 5)) 191#define __PPC_XS(s) ((((s) & 0x1f) << 21) | (((s) & 0x20) >> 5))
@@ -141,13 +214,13 @@
141#define PPC_DCBZL(a, b) stringify_in_c(.long PPC_INST_DCBZL | \ 214#define PPC_DCBZL(a, b) stringify_in_c(.long PPC_INST_DCBZL | \
142 __PPC_RA(a) | __PPC_RB(b)) 215 __PPC_RA(a) | __PPC_RB(b))
143#define PPC_LDARX(t, a, b, eh) stringify_in_c(.long PPC_INST_LDARX | \ 216#define PPC_LDARX(t, a, b, eh) stringify_in_c(.long PPC_INST_LDARX | \
144 __PPC_RT(t) | __PPC_RA(a) | \ 217 ___PPC_RT(t) | ___PPC_RA(a) | \
145 __PPC_RB(b) | __PPC_EH(eh)) 218 ___PPC_RB(b) | __PPC_EH(eh))
146#define PPC_LWARX(t, a, b, eh) stringify_in_c(.long PPC_INST_LWARX | \ 219#define PPC_LWARX(t, a, b, eh) stringify_in_c(.long PPC_INST_LWARX | \
147 __PPC_RT(t) | __PPC_RA(a) | \ 220 ___PPC_RT(t) | ___PPC_RA(a) | \
148 __PPC_RB(b) | __PPC_EH(eh)) 221 ___PPC_RB(b) | __PPC_EH(eh))
149#define PPC_MSGSND(b) stringify_in_c(.long PPC_INST_MSGSND | \ 222#define PPC_MSGSND(b) stringify_in_c(.long PPC_INST_MSGSND | \
150 __PPC_RB(b)) 223 ___PPC_RB(b))
151#define PPC_POPCNTB(a, s) stringify_in_c(.long PPC_INST_POPCNTB | \ 224#define PPC_POPCNTB(a, s) stringify_in_c(.long PPC_INST_POPCNTB | \
152 __PPC_RA(a) | __PPC_RS(s)) 225 __PPC_RA(a) | __PPC_RS(s))
153#define PPC_POPCNTD(a, s) stringify_in_c(.long PPC_INST_POPCNTD | \ 226#define PPC_POPCNTD(a, s) stringify_in_c(.long PPC_INST_POPCNTD | \
@@ -158,34 +231,39 @@
158#define PPC_RFDI stringify_in_c(.long PPC_INST_RFDI) 231#define PPC_RFDI stringify_in_c(.long PPC_INST_RFDI)
159#define PPC_RFMCI stringify_in_c(.long PPC_INST_RFMCI) 232#define PPC_RFMCI stringify_in_c(.long PPC_INST_RFMCI)
160#define PPC_TLBILX(t, a, b) stringify_in_c(.long PPC_INST_TLBILX | \ 233#define PPC_TLBILX(t, a, b) stringify_in_c(.long PPC_INST_TLBILX | \
161 __PPC_T_TLB(t) | __PPC_RA(a) | __PPC_RB(b)) 234 __PPC_T_TLB(t) | __PPC_RA0(a) | __PPC_RB(b))
162#define PPC_TLBILX_ALL(a, b) PPC_TLBILX(0, a, b) 235#define PPC_TLBILX_ALL(a, b) PPC_TLBILX(0, a, b)
163#define PPC_TLBILX_PID(a, b) PPC_TLBILX(1, a, b) 236#define PPC_TLBILX_PID(a, b) PPC_TLBILX(1, a, b)
164#define PPC_TLBILX_VA(a, b) PPC_TLBILX(3, a, b) 237#define PPC_TLBILX_VA(a, b) PPC_TLBILX(3, a, b)
165#define PPC_WAIT(w) stringify_in_c(.long PPC_INST_WAIT | \ 238#define PPC_WAIT(w) stringify_in_c(.long PPC_INST_WAIT | \
166 __PPC_WC(w)) 239 __PPC_WC(w))
167#define PPC_TLBIE(lp,a) stringify_in_c(.long PPC_INST_TLBIE | \ 240#define PPC_TLBIE(lp,a) stringify_in_c(.long PPC_INST_TLBIE | \
168 __PPC_RB(a) | __PPC_RS(lp)) 241 ___PPC_RB(a) | ___PPC_RS(lp))
169#define PPC_TLBSRX_DOT(a,b) stringify_in_c(.long PPC_INST_TLBSRX_DOT | \ 242#define PPC_TLBSRX_DOT(a,b) stringify_in_c(.long PPC_INST_TLBSRX_DOT | \
170 __PPC_RA(a) | __PPC_RB(b)) 243 __PPC_RA0(a) | __PPC_RB(b))
171#define PPC_TLBIVAX(a,b) stringify_in_c(.long PPC_INST_TLBIVAX | \ 244#define PPC_TLBIVAX(a,b) stringify_in_c(.long PPC_INST_TLBIVAX | \
172 __PPC_RA(a) | __PPC_RB(b)) 245 __PPC_RA0(a) | __PPC_RB(b))
173 246
174#define PPC_ERATWE(s, a, w) stringify_in_c(.long PPC_INST_ERATWE | \ 247#define PPC_ERATWE(s, a, w) stringify_in_c(.long PPC_INST_ERATWE | \
175 __PPC_RS(s) | __PPC_RA(a) | __PPC_WS(w)) 248 __PPC_RS(s) | __PPC_RA(a) | __PPC_WS(w))
176#define PPC_ERATRE(s, a, w) stringify_in_c(.long PPC_INST_ERATRE | \ 249#define PPC_ERATRE(s, a, w) stringify_in_c(.long PPC_INST_ERATRE | \
177 __PPC_RS(s) | __PPC_RA(a) | __PPC_WS(w)) 250 __PPC_RS(s) | __PPC_RA(a) | __PPC_WS(w))
178#define PPC_ERATILX(t, a, b) stringify_in_c(.long PPC_INST_ERATILX | \ 251#define PPC_ERATILX(t, a, b) stringify_in_c(.long PPC_INST_ERATILX | \
179 __PPC_T_TLB(t) | __PPC_RA(a) | \ 252 __PPC_T_TLB(t) | __PPC_RA0(a) | \
180 __PPC_RB(b)) 253 __PPC_RB(b))
181#define PPC_ERATIVAX(s, a, b) stringify_in_c(.long PPC_INST_ERATIVAX | \ 254#define PPC_ERATIVAX(s, a, b) stringify_in_c(.long PPC_INST_ERATIVAX | \
182 __PPC_RS(s) | __PPC_RA(a) | __PPC_RB(b)) 255 __PPC_RS(s) | __PPC_RA0(a) | __PPC_RB(b))
183#define PPC_ERATSX(t, a, w) stringify_in_c(.long PPC_INST_ERATSX | \ 256#define PPC_ERATSX(t, a, w) stringify_in_c(.long PPC_INST_ERATSX | \
184 __PPC_RS(t) | __PPC_RA(a) | __PPC_RB(b)) 257 __PPC_RS(t) | __PPC_RA0(a) | __PPC_RB(b))
185#define PPC_ERATSX_DOT(t, a, w) stringify_in_c(.long PPC_INST_ERATSX_DOT | \ 258#define PPC_ERATSX_DOT(t, a, w) stringify_in_c(.long PPC_INST_ERATSX_DOT | \
186 __PPC_RS(t) | __PPC_RA(a) | __PPC_RB(b)) 259 __PPC_RS(t) | __PPC_RA0(a) | __PPC_RB(b))
187#define PPC_SLBFEE_DOT(t, b) stringify_in_c(.long PPC_INST_SLBFEE | \ 260#define PPC_SLBFEE_DOT(t, b) stringify_in_c(.long PPC_INST_SLBFEE | \
188 __PPC_RT(t) | __PPC_RB(b)) 261 __PPC_RT(t) | __PPC_RB(b))
262/* PASemi instructions */
263#define LBZCIX(t,a,b) stringify_in_c(.long PPC_INST_LBZCIX | \
264 __PPC_RT(t) | __PPC_RA(a) | __PPC_RB(b))
265#define STBCIX(s,a,b) stringify_in_c(.long PPC_INST_STBCIX | \
266 __PPC_RS(s) | __PPC_RA(a) | __PPC_RB(b))
189 267
190/* 268/*
191 * Define what the VSX XX1 form instructions will look like, then add 269 * Define what the VSX XX1 form instructions will look like, then add
@@ -194,11 +272,11 @@
194#define VSX_XX1(s, a, b) (__PPC_XS(s) | __PPC_RA(a) | __PPC_RB(b)) 272#define VSX_XX1(s, a, b) (__PPC_XS(s) | __PPC_RA(a) | __PPC_RB(b))
195#define VSX_XX3(t, a, b) (__PPC_XT(t) | __PPC_XA(a) | __PPC_XB(b)) 273#define VSX_XX3(t, a, b) (__PPC_XT(t) | __PPC_XA(a) | __PPC_XB(b))
196#define STXVD2X(s, a, b) stringify_in_c(.long PPC_INST_STXVD2X | \ 274#define STXVD2X(s, a, b) stringify_in_c(.long PPC_INST_STXVD2X | \
197 VSX_XX1((s), (a), (b))) 275 VSX_XX1((s), a, b))
198#define LXVD2X(s, a, b) stringify_in_c(.long PPC_INST_LXVD2X | \ 276#define LXVD2X(s, a, b) stringify_in_c(.long PPC_INST_LXVD2X | \
199 VSX_XX1((s), (a), (b))) 277 VSX_XX1((s), a, b))
200#define XXLOR(t, a, b) stringify_in_c(.long PPC_INST_XXLOR | \ 278#define XXLOR(t, a, b) stringify_in_c(.long PPC_INST_XXLOR | \
201 VSX_XX3((t), (a), (b))) 279 VSX_XX3((t), a, b))
202 280
203#define PPC_NAP stringify_in_c(.long PPC_INST_NAP) 281#define PPC_NAP stringify_in_c(.long PPC_INST_NAP)
204#define PPC_SLEEP stringify_in_c(.long PPC_INST_SLEEP) 282#define PPC_SLEEP stringify_in_c(.long PPC_INST_SLEEP)
diff --git a/arch/powerpc/include/asm/ppc_asm.h b/arch/powerpc/include/asm/ppc_asm.h
index 15444204a3a1..ea2a86e8ff95 100644
--- a/arch/powerpc/include/asm/ppc_asm.h
+++ b/arch/powerpc/include/asm/ppc_asm.h
@@ -126,26 +126,26 @@ END_FW_FTR_SECTION_IFSET(FW_FEATURE_SPLPAR)
126#define REST_32VRS(n,b,base) REST_16VRS(n,b,base); REST_16VRS(n+16,b,base) 126#define REST_32VRS(n,b,base) REST_16VRS(n,b,base); REST_16VRS(n+16,b,base)
127 127
128/* Save the lower 32 VSRs in the thread VSR region */ 128/* Save the lower 32 VSRs in the thread VSR region */
129#define SAVE_VSR(n,b,base) li b,THREAD_VSR0+(16*(n)); STXVD2X(n,base,b) 129#define SAVE_VSR(n,b,base) li b,THREAD_VSR0+(16*(n)); STXVD2X(n,R##base,R##b)
130#define SAVE_2VSRS(n,b,base) SAVE_VSR(n,b,base); SAVE_VSR(n+1,b,base) 130#define SAVE_2VSRS(n,b,base) SAVE_VSR(n,b,base); SAVE_VSR(n+1,b,base)
131#define SAVE_4VSRS(n,b,base) SAVE_2VSRS(n,b,base); SAVE_2VSRS(n+2,b,base) 131#define SAVE_4VSRS(n,b,base) SAVE_2VSRS(n,b,base); SAVE_2VSRS(n+2,b,base)
132#define SAVE_8VSRS(n,b,base) SAVE_4VSRS(n,b,base); SAVE_4VSRS(n+4,b,base) 132#define SAVE_8VSRS(n,b,base) SAVE_4VSRS(n,b,base); SAVE_4VSRS(n+4,b,base)
133#define SAVE_16VSRS(n,b,base) SAVE_8VSRS(n,b,base); SAVE_8VSRS(n+8,b,base) 133#define SAVE_16VSRS(n,b,base) SAVE_8VSRS(n,b,base); SAVE_8VSRS(n+8,b,base)
134#define SAVE_32VSRS(n,b,base) SAVE_16VSRS(n,b,base); SAVE_16VSRS(n+16,b,base) 134#define SAVE_32VSRS(n,b,base) SAVE_16VSRS(n,b,base); SAVE_16VSRS(n+16,b,base)
135#define REST_VSR(n,b,base) li b,THREAD_VSR0+(16*(n)); LXVD2X(n,base,b) 135#define REST_VSR(n,b,base) li b,THREAD_VSR0+(16*(n)); LXVD2X(n,R##base,R##b)
136#define REST_2VSRS(n,b,base) REST_VSR(n,b,base); REST_VSR(n+1,b,base) 136#define REST_2VSRS(n,b,base) REST_VSR(n,b,base); REST_VSR(n+1,b,base)
137#define REST_4VSRS(n,b,base) REST_2VSRS(n,b,base); REST_2VSRS(n+2,b,base) 137#define REST_4VSRS(n,b,base) REST_2VSRS(n,b,base); REST_2VSRS(n+2,b,base)
138#define REST_8VSRS(n,b,base) REST_4VSRS(n,b,base); REST_4VSRS(n+4,b,base) 138#define REST_8VSRS(n,b,base) REST_4VSRS(n,b,base); REST_4VSRS(n+4,b,base)
139#define REST_16VSRS(n,b,base) REST_8VSRS(n,b,base); REST_8VSRS(n+8,b,base) 139#define REST_16VSRS(n,b,base) REST_8VSRS(n,b,base); REST_8VSRS(n+8,b,base)
140#define REST_32VSRS(n,b,base) REST_16VSRS(n,b,base); REST_16VSRS(n+16,b,base) 140#define REST_32VSRS(n,b,base) REST_16VSRS(n,b,base); REST_16VSRS(n+16,b,base)
141/* Save the upper 32 VSRs (32-63) in the thread VSX region (0-31) */ 141/* Save the upper 32 VSRs (32-63) in the thread VSX region (0-31) */
142#define SAVE_VSRU(n,b,base) li b,THREAD_VR0+(16*(n)); STXVD2X(n+32,base,b) 142#define SAVE_VSRU(n,b,base) li b,THREAD_VR0+(16*(n)); STXVD2X(n+32,R##base,R##b)
143#define SAVE_2VSRSU(n,b,base) SAVE_VSRU(n,b,base); SAVE_VSRU(n+1,b,base) 143#define SAVE_2VSRSU(n,b,base) SAVE_VSRU(n,b,base); SAVE_VSRU(n+1,b,base)
144#define SAVE_4VSRSU(n,b,base) SAVE_2VSRSU(n,b,base); SAVE_2VSRSU(n+2,b,base) 144#define SAVE_4VSRSU(n,b,base) SAVE_2VSRSU(n,b,base); SAVE_2VSRSU(n+2,b,base)
145#define SAVE_8VSRSU(n,b,base) SAVE_4VSRSU(n,b,base); SAVE_4VSRSU(n+4,b,base) 145#define SAVE_8VSRSU(n,b,base) SAVE_4VSRSU(n,b,base); SAVE_4VSRSU(n+4,b,base)
146#define SAVE_16VSRSU(n,b,base) SAVE_8VSRSU(n,b,base); SAVE_8VSRSU(n+8,b,base) 146#define SAVE_16VSRSU(n,b,base) SAVE_8VSRSU(n,b,base); SAVE_8VSRSU(n+8,b,base)
147#define SAVE_32VSRSU(n,b,base) SAVE_16VSRSU(n,b,base); SAVE_16VSRSU(n+16,b,base) 147#define SAVE_32VSRSU(n,b,base) SAVE_16VSRSU(n,b,base); SAVE_16VSRSU(n+16,b,base)
148#define REST_VSRU(n,b,base) li b,THREAD_VR0+(16*(n)); LXVD2X(n+32,base,b) 148#define REST_VSRU(n,b,base) li b,THREAD_VR0+(16*(n)); LXVD2X(n+32,R##base,R##b)
149#define REST_2VSRSU(n,b,base) REST_VSRU(n,b,base); REST_VSRU(n+1,b,base) 149#define REST_2VSRSU(n,b,base) REST_VSRU(n,b,base); REST_VSRU(n+1,b,base)
150#define REST_4VSRSU(n,b,base) REST_2VSRSU(n,b,base); REST_2VSRSU(n+2,b,base) 150#define REST_4VSRSU(n,b,base) REST_2VSRSU(n,b,base); REST_2VSRSU(n+2,b,base)
151#define REST_8VSRSU(n,b,base) REST_4VSRSU(n,b,base); REST_4VSRSU(n+4,b,base) 151#define REST_8VSRSU(n,b,base) REST_4VSRSU(n,b,base); REST_4VSRSU(n+4,b,base)
@@ -178,9 +178,24 @@ END_FW_FTR_SECTION_IFSET(FW_FEATURE_SPLPAR)
178#define HMT_HIGH or 3,3,3 178#define HMT_HIGH or 3,3,3
179#define HMT_EXTRA_HIGH or 7,7,7 # power7 only 179#define HMT_EXTRA_HIGH or 7,7,7 # power7 only
180 180
181#ifdef CONFIG_PPC64
182#define ULONG_SIZE 8
183#else
184#define ULONG_SIZE 4
185#endif
186#define __VCPU_GPR(n) (VCPU_GPRS + (n * ULONG_SIZE))
187#define VCPU_GPR(n) __VCPU_GPR(__REG_##n)
188
181#ifdef __KERNEL__ 189#ifdef __KERNEL__
182#ifdef CONFIG_PPC64 190#ifdef CONFIG_PPC64
183 191
192#define STACKFRAMESIZE 256
193#define __STK_REG(i) (112 + ((i)-14)*8)
194#define STK_REG(i) __STK_REG(__REG_##i)
195
196#define __STK_PARAM(i) (48 + ((i)-3)*8)
197#define STK_PARAM(i) __STK_PARAM(__REG_##i)
198
184#define XGLUE(a,b) a##b 199#define XGLUE(a,b) a##b
185#define GLUE(a,b) XGLUE(a,b) 200#define GLUE(a,b) XGLUE(a,b)
186 201
@@ -295,14 +310,14 @@ n:
295 */ 310 */
296#ifdef __powerpc64__ 311#ifdef __powerpc64__
297#define LOAD_REG_IMMEDIATE(reg,expr) \ 312#define LOAD_REG_IMMEDIATE(reg,expr) \
298 lis (reg),(expr)@highest; \ 313 lis reg,(expr)@highest; \
299 ori (reg),(reg),(expr)@higher; \ 314 ori reg,reg,(expr)@higher; \
300 rldicr (reg),(reg),32,31; \ 315 rldicr reg,reg,32,31; \
301 oris (reg),(reg),(expr)@h; \ 316 oris reg,reg,(expr)@h; \
302 ori (reg),(reg),(expr)@l; 317 ori reg,reg,(expr)@l;
303 318
304#define LOAD_REG_ADDR(reg,name) \ 319#define LOAD_REG_ADDR(reg,name) \
305 ld (reg),name@got(r2) 320 ld reg,name@got(r2)
306 321
307#define LOAD_REG_ADDRBASE(reg,name) LOAD_REG_ADDR(reg,name) 322#define LOAD_REG_ADDRBASE(reg,name) LOAD_REG_ADDR(reg,name)
308#define ADDROFF(name) 0 323#define ADDROFF(name) 0
@@ -313,12 +328,12 @@ n:
313#else /* 32-bit */ 328#else /* 32-bit */
314 329
315#define LOAD_REG_IMMEDIATE(reg,expr) \ 330#define LOAD_REG_IMMEDIATE(reg,expr) \
316 lis (reg),(expr)@ha; \ 331 lis reg,(expr)@ha; \
317 addi (reg),(reg),(expr)@l; 332 addi reg,reg,(expr)@l;
318 333
319#define LOAD_REG_ADDR(reg,name) LOAD_REG_IMMEDIATE(reg, name) 334#define LOAD_REG_ADDR(reg,name) LOAD_REG_IMMEDIATE(reg, name)
320 335
321#define LOAD_REG_ADDRBASE(reg, name) lis (reg),name@ha 336#define LOAD_REG_ADDRBASE(reg, name) lis reg,name@ha
322#define ADDROFF(name) name@l 337#define ADDROFF(name) name@l
323 338
324/* offsets for stack frame layout */ 339/* offsets for stack frame layout */
@@ -372,9 +387,9 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601)
372#ifdef CONFIG_PPC64 387#ifdef CONFIG_PPC64
373#define MTOCRF(FXM, RS) \ 388#define MTOCRF(FXM, RS) \
374 BEGIN_FTR_SECTION_NESTED(848); \ 389 BEGIN_FTR_SECTION_NESTED(848); \
375 mtcrf (FXM), (RS); \ 390 mtcrf (FXM), RS; \
376 FTR_SECTION_ELSE_NESTED(848); \ 391 FTR_SECTION_ELSE_NESTED(848); \
377 mtocrf (FXM), (RS); \ 392 mtocrf (FXM), RS; \
378 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_NOEXECUTE, 848) 393 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_NOEXECUTE, 848)
379#endif 394#endif
380 395
@@ -463,6 +478,7 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601)
463#ifdef CONFIG_PPC_BOOK3S_64 478#ifdef CONFIG_PPC_BOOK3S_64
464#define RFI rfid 479#define RFI rfid
465#define MTMSRD(r) mtmsrd r 480#define MTMSRD(r) mtmsrd r
481#define MTMSR_EERI(reg) mtmsrd reg,1
466#else 482#else
467#define FIX_SRR1(ra, rb) 483#define FIX_SRR1(ra, rb)
468#ifndef CONFIG_40x 484#ifndef CONFIG_40x
@@ -471,6 +487,7 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601)
471#define RFI rfi; b . /* Prevent prefetch past rfi */ 487#define RFI rfi; b . /* Prevent prefetch past rfi */
472#endif 488#endif
473#define MTMSRD(r) mtmsr r 489#define MTMSRD(r) mtmsr r
490#define MTMSR_EERI(reg) mtmsr reg
474#define CLR_TOP32(r) 491#define CLR_TOP32(r)
475#endif 492#endif
476 493
@@ -490,40 +507,46 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601)
490#define cr7 7 507#define cr7 7
491 508
492 509
493/* General Purpose Registers (GPRs) */ 510/*
494 511 * General Purpose Registers (GPRs)
495#define r0 0 512 *
496#define r1 1 513 * The lower case r0-r31 should be used in preference to the upper
497#define r2 2 514 * case R0-R31 as they provide more error checking in the assembler.
498#define r3 3 515 * Use R0-31 only when really nessesary.
499#define r4 4 516 */
500#define r5 5 517
501#define r6 6 518#define r0 %r0
502#define r7 7 519#define r1 %r1
503#define r8 8 520#define r2 %r2
504#define r9 9 521#define r3 %r3
505#define r10 10 522#define r4 %r4
506#define r11 11 523#define r5 %r5
507#define r12 12 524#define r6 %r6
508#define r13 13 525#define r7 %r7
509#define r14 14 526#define r8 %r8
510#define r15 15 527#define r9 %r9
511#define r16 16 528#define r10 %r10
512#define r17 17 529#define r11 %r11
513#define r18 18 530#define r12 %r12
514#define r19 19 531#define r13 %r13
515#define r20 20 532#define r14 %r14
516#define r21 21 533#define r15 %r15
517#define r22 22 534#define r16 %r16
518#define r23 23 535#define r17 %r17
519#define r24 24 536#define r18 %r18
520#define r25 25 537#define r19 %r19
521#define r26 26 538#define r20 %r20
522#define r27 27 539#define r21 %r21
523#define r28 28 540#define r22 %r22
524#define r29 29 541#define r23 %r23
525#define r30 30 542#define r24 %r24
526#define r31 31 543#define r25 %r25
544#define r26 %r26
545#define r27 %r27
546#define r28 %r28
547#define r29 %r29
548#define r30 %r30
549#define r31 %r31
527 550
528 551
529/* Floating Point Registers (FPRs) */ 552/* Floating Point Registers (FPRs) */
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index 413a5eaef56c..53b6dfa83344 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -389,10 +389,8 @@ extern int powersave_nap; /* set if nap mode can be used in idle loop */
389 389
390#ifdef CONFIG_PSERIES_IDLE 390#ifdef CONFIG_PSERIES_IDLE
391extern void update_smt_snooze_delay(int snooze); 391extern void update_smt_snooze_delay(int snooze);
392extern int pseries_notify_cpuidle_add_cpu(int cpu);
393#else 392#else
394static inline void update_smt_snooze_delay(int snooze) {} 393static inline void update_smt_snooze_delay(int snooze) {}
395static inline int pseries_notify_cpuidle_add_cpu(int cpu) { return 0; }
396#endif 394#endif
397 395
398extern void flush_instruction_cache(void); 396extern void flush_instruction_cache(void);
diff --git a/arch/powerpc/include/asm/qe.h b/arch/powerpc/include/asm/qe.h
index 5e0b6d511e14..229571a49391 100644
--- a/arch/powerpc/include/asm/qe.h
+++ b/arch/powerpc/include/asm/qe.h
@@ -499,6 +499,7 @@ enum comm_dir {
499/* I-RAM */ 499/* I-RAM */
500#define QE_IRAM_IADD_AIE 0x80000000 /* Auto Increment Enable */ 500#define QE_IRAM_IADD_AIE 0x80000000 /* Auto Increment Enable */
501#define QE_IRAM_IADD_BADDR 0x00080000 /* Base Address */ 501#define QE_IRAM_IADD_BADDR 0x00080000 /* Base Address */
502#define QE_IRAM_READY 0x80000000 /* Ready */
502 503
503/* UPC */ 504/* UPC */
504#define UPGCR_PROTOCOL 0x80000000 /* protocol ul2 or pl2 */ 505#define UPGCR_PROTOCOL 0x80000000 /* protocol ul2 or pl2 */
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index f0cb7f461b9d..638608677e2a 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -491,6 +491,7 @@
491#define SPRN_SPRG1 0x111 /* Special Purpose Register General 1 */ 491#define SPRN_SPRG1 0x111 /* Special Purpose Register General 1 */
492#define SPRN_SPRG2 0x112 /* Special Purpose Register General 2 */ 492#define SPRN_SPRG2 0x112 /* Special Purpose Register General 2 */
493#define SPRN_SPRG3 0x113 /* Special Purpose Register General 3 */ 493#define SPRN_SPRG3 0x113 /* Special Purpose Register General 3 */
494#define SPRN_USPRG3 0x103 /* SPRG3 userspace read */
494#define SPRN_SPRG4 0x114 /* Special Purpose Register General 4 */ 495#define SPRN_SPRG4 0x114 /* Special Purpose Register General 4 */
495#define SPRN_SPRG5 0x115 /* Special Purpose Register General 5 */ 496#define SPRN_SPRG5 0x115 /* Special Purpose Register General 5 */
496#define SPRN_SPRG6 0x116 /* Special Purpose Register General 6 */ 497#define SPRN_SPRG6 0x116 /* Special Purpose Register General 6 */
@@ -753,14 +754,14 @@
753 * 64-bit server: 754 * 64-bit server:
754 * - SPRG0 unused (reserved for HV on Power4) 755 * - SPRG0 unused (reserved for HV on Power4)
755 * - SPRG2 scratch for exception vectors 756 * - SPRG2 scratch for exception vectors
756 * - SPRG3 unused (user visible) 757 * - SPRG3 CPU and NUMA node for VDSO getcpu (user visible)
757 * - HSPRG0 stores PACA in HV mode 758 * - HSPRG0 stores PACA in HV mode
758 * - HSPRG1 scratch for "HV" exceptions 759 * - HSPRG1 scratch for "HV" exceptions
759 * 760 *
760 * 64-bit embedded 761 * 64-bit embedded
761 * - SPRG0 generic exception scratch 762 * - SPRG0 generic exception scratch
762 * - SPRG2 TLB exception stack 763 * - SPRG2 TLB exception stack
763 * - SPRG3 unused (user visible) 764 * - SPRG3 CPU and NUMA node for VDSO getcpu (user visible)
764 * - SPRG4 unused (user visible) 765 * - SPRG4 unused (user visible)
765 * - SPRG6 TLB miss scratch (user visible, sorry !) 766 * - SPRG6 TLB miss scratch (user visible, sorry !)
766 * - SPRG7 critical exception scratch 767 * - SPRG7 critical exception scratch
@@ -1024,7 +1025,8 @@
1024/* Macros for setting and retrieving special purpose registers */ 1025/* Macros for setting and retrieving special purpose registers */
1025#ifndef __ASSEMBLY__ 1026#ifndef __ASSEMBLY__
1026#define mfmsr() ({unsigned long rval; \ 1027#define mfmsr() ({unsigned long rval; \
1027 asm volatile("mfmsr %0" : "=r" (rval)); rval;}) 1028 asm volatile("mfmsr %0" : "=r" (rval) : \
1029 : "memory"); rval;})
1028#ifdef CONFIG_PPC_BOOK3S_64 1030#ifdef CONFIG_PPC_BOOK3S_64
1029#define __mtmsrd(v, l) asm volatile("mtmsrd %0," __stringify(l) \ 1031#define __mtmsrd(v, l) asm volatile("mtmsrd %0," __stringify(l) \
1030 : : "r" (v) : "memory") 1032 : : "r" (v) : "memory")
diff --git a/arch/powerpc/include/asm/thread_info.h b/arch/powerpc/include/asm/thread_info.h
index 68831e9cf82f..faf93529cbf0 100644
--- a/arch/powerpc/include/asm/thread_info.h
+++ b/arch/powerpc/include/asm/thread_info.h
@@ -22,6 +22,12 @@
22 22
23#define THREAD_SIZE (1 << THREAD_SHIFT) 23#define THREAD_SIZE (1 << THREAD_SHIFT)
24 24
25#ifdef CONFIG_PPC64
26#define CURRENT_THREAD_INFO(dest, sp) clrrdi dest, sp, THREAD_SHIFT
27#else
28#define CURRENT_THREAD_INFO(dest, sp) rlwinm dest, sp, 0, 0, 31-THREAD_SHIFT
29#endif
30
25#ifndef __ASSEMBLY__ 31#ifndef __ASSEMBLY__
26#include <linux/cache.h> 32#include <linux/cache.h>
27#include <asm/processor.h> 33#include <asm/processor.h>
diff --git a/arch/powerpc/include/asm/trace.h b/arch/powerpc/include/asm/trace.h
index cbe2297d68b6..5712f06905a9 100644
--- a/arch/powerpc/include/asm/trace.h
+++ b/arch/powerpc/include/asm/trace.h
@@ -8,7 +8,7 @@
8 8
9struct pt_regs; 9struct pt_regs;
10 10
11TRACE_EVENT(irq_entry, 11DECLARE_EVENT_CLASS(ppc64_interrupt_class,
12 12
13 TP_PROTO(struct pt_regs *regs), 13 TP_PROTO(struct pt_regs *regs),
14 14
@@ -25,55 +25,32 @@ TRACE_EVENT(irq_entry,
25 TP_printk("pt_regs=%p", __entry->regs) 25 TP_printk("pt_regs=%p", __entry->regs)
26); 26);
27 27
28TRACE_EVENT(irq_exit, 28DEFINE_EVENT(ppc64_interrupt_class, irq_entry,
29 29
30 TP_PROTO(struct pt_regs *regs), 30 TP_PROTO(struct pt_regs *regs),
31 31
32 TP_ARGS(regs), 32 TP_ARGS(regs)
33
34 TP_STRUCT__entry(
35 __field(struct pt_regs *, regs)
36 ),
37
38 TP_fast_assign(
39 __entry->regs = regs;
40 ),
41
42 TP_printk("pt_regs=%p", __entry->regs)
43); 33);
44 34
45TRACE_EVENT(timer_interrupt_entry, 35DEFINE_EVENT(ppc64_interrupt_class, irq_exit,
46 36
47 TP_PROTO(struct pt_regs *regs), 37 TP_PROTO(struct pt_regs *regs),
48 38
49 TP_ARGS(regs), 39 TP_ARGS(regs)
50
51 TP_STRUCT__entry(
52 __field(struct pt_regs *, regs)
53 ),
54
55 TP_fast_assign(
56 __entry->regs = regs;
57 ),
58
59 TP_printk("pt_regs=%p", __entry->regs)
60); 40);
61 41
62TRACE_EVENT(timer_interrupt_exit, 42DEFINE_EVENT(ppc64_interrupt_class, timer_interrupt_entry,
63 43
64 TP_PROTO(struct pt_regs *regs), 44 TP_PROTO(struct pt_regs *regs),
65 45
66 TP_ARGS(regs), 46 TP_ARGS(regs)
47);
67 48
68 TP_STRUCT__entry( 49DEFINE_EVENT(ppc64_interrupt_class, timer_interrupt_exit,
69 __field(struct pt_regs *, regs)
70 ),
71 50
72 TP_fast_assign( 51 TP_PROTO(struct pt_regs *regs),
73 __entry->regs = regs;
74 ),
75 52
76 TP_printk("pt_regs=%p", __entry->regs) 53 TP_ARGS(regs)
77); 54);
78 55
79#ifdef CONFIG_PPC_PSERIES 56#ifdef CONFIG_PPC_PSERIES
diff --git a/arch/powerpc/include/asm/vdso.h b/arch/powerpc/include/asm/vdso.h
index dc0419b66f17..50f261bc3e95 100644
--- a/arch/powerpc/include/asm/vdso.h
+++ b/arch/powerpc/include/asm/vdso.h
@@ -22,6 +22,8 @@ extern unsigned long vdso64_rt_sigtramp;
22extern unsigned long vdso32_sigtramp; 22extern unsigned long vdso32_sigtramp;
23extern unsigned long vdso32_rt_sigtramp; 23extern unsigned long vdso32_rt_sigtramp;
24 24
25int __cpuinit vdso_getcpu_init(void);
26
25#else /* __ASSEMBLY__ */ 27#else /* __ASSEMBLY__ */
26 28
27#ifdef __VDSO64__ 29#ifdef __VDSO64__
diff --git a/arch/powerpc/include/asm/vio.h b/arch/powerpc/include/asm/vio.h
index b19adf751dd9..df81cb72d1e0 100644
--- a/arch/powerpc/include/asm/vio.h
+++ b/arch/powerpc/include/asm/vio.h
@@ -44,6 +44,8 @@
44 */ 44 */
45#define VIO_CMO_MIN_ENT 1562624 45#define VIO_CMO_MIN_ENT 1562624
46 46
47extern struct bus_type vio_bus_type;
48
47struct iommu_table; 49struct iommu_table;
48 50
49/* 51/*
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-15 18:35:28 -0500