1 files changed, 1 insertions, 1 deletions
diff --git a/arch/powerpc/include/asm/uninorth.h b/arch/powerpc/include/asm/uninorth.h
index f737732c3861..ae9c899c8a6d 100644
--- a/arch/powerpc/include/asm/uninorth.h
+++ b/arch/powerpc/include/asm/uninorth.h
@@ -60,7 +60,7 @@
 *
 * Obviously, the GART is not cache coherent and so any change to it
 * must be flushed to memory (or maybe just make the GART space non
- * cachable). AGP memory itself doens't seem to be cache coherent neither.
+ * cachable). AGP memory itself does't seem to be cache coherent neither.
 *
 * In order to invalidate the GART (which is probably necessary to inval
 * the bridge internal TLBs), the following sequence has to be written,

diff --git a/arch/powerpc/include/asm/uninorth.h b/arch/powerpc/include/asm/uninorth.h index f737732c3861..ae9c899c8a6d 100644 --- a/arch/powerpc/include/asm/uninorth.h +++ b/arch/powerpc/include/asm/uninorth.h
@@ -60,7 +60,7 @@
60	*	60	*
61	* Obviously, the GART is not cache coherent and so any change to it	61	* Obviously, the GART is not cache coherent and so any change to it
62	* must be flushed to memory (or maybe just make the GART space non	62	* must be flushed to memory (or maybe just make the GART space non
63	* cachable). AGP memory itself doens't seem to be cache coherent neither.	63	* cachable). AGP memory itself does't seem to be cache coherent neither.
64	*	64	*
65	* In order to invalidate the GART (which is probably necessary to inval	65	* In order to invalidate the GART (which is probably necessary to inval
66	* the bridge internal TLBs), the following sequence has to be written,	66	* the bridge internal TLBs), the following sequence has to be written,