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Diffstat (limited to 'arch/powerpc/include/asm/system.h')
-rw-r--r--arch/powerpc/include/asm/system.h21
1 files changed, 13 insertions, 8 deletions
diff --git a/arch/powerpc/include/asm/system.h b/arch/powerpc/include/asm/system.h
index bb8e006a47c6..a6297c67c3d6 100644
--- a/arch/powerpc/include/asm/system.h
+++ b/arch/powerpc/include/asm/system.h
@@ -112,8 +112,13 @@ static inline int debugger_fault_handler(struct pt_regs *regs) { return 0; }
112#endif 112#endif
113 113
114extern int set_dabr(unsigned long dabr); 114extern int set_dabr(unsigned long dabr);
115#ifdef CONFIG_PPC_ADV_DEBUG_REGS
116extern void do_send_trap(struct pt_regs *regs, unsigned long address,
117 unsigned long error_code, int signal_code, int brkpt);
118#else
115extern void do_dabr(struct pt_regs *regs, unsigned long address, 119extern void do_dabr(struct pt_regs *regs, unsigned long address,
116 unsigned long error_code); 120 unsigned long error_code);
121#endif
117extern void print_backtrace(unsigned long *); 122extern void print_backtrace(unsigned long *);
118extern void show_regs(struct pt_regs * regs); 123extern void show_regs(struct pt_regs * regs);
119extern void flush_instruction_cache(void); 124extern void flush_instruction_cache(void);
@@ -232,12 +237,12 @@ __xchg_u32(volatile void *p, unsigned long val)
232 unsigned long prev; 237 unsigned long prev;
233 238
234 __asm__ __volatile__( 239 __asm__ __volatile__(
235 LWSYNC_ON_SMP 240 PPC_RELEASE_BARRIER
236"1: lwarx %0,0,%2 \n" 241"1: lwarx %0,0,%2 \n"
237 PPC405_ERR77(0,%2) 242 PPC405_ERR77(0,%2)
238" stwcx. %3,0,%2 \n\ 243" stwcx. %3,0,%2 \n\
239 bne- 1b" 244 bne- 1b"
240 ISYNC_ON_SMP 245 PPC_ACQUIRE_BARRIER
241 : "=&r" (prev), "+m" (*(volatile unsigned int *)p) 246 : "=&r" (prev), "+m" (*(volatile unsigned int *)p)
242 : "r" (p), "r" (val) 247 : "r" (p), "r" (val)
243 : "cc", "memory"); 248 : "cc", "memory");
@@ -275,12 +280,12 @@ __xchg_u64(volatile void *p, unsigned long val)
275 unsigned long prev; 280 unsigned long prev;
276 281
277 __asm__ __volatile__( 282 __asm__ __volatile__(
278 LWSYNC_ON_SMP 283 PPC_RELEASE_BARRIER
279"1: ldarx %0,0,%2 \n" 284"1: ldarx %0,0,%2 \n"
280 PPC405_ERR77(0,%2) 285 PPC405_ERR77(0,%2)
281" stdcx. %3,0,%2 \n\ 286" stdcx. %3,0,%2 \n\
282 bne- 1b" 287 bne- 1b"
283 ISYNC_ON_SMP 288 PPC_ACQUIRE_BARRIER
284 : "=&r" (prev), "+m" (*(volatile unsigned long *)p) 289 : "=&r" (prev), "+m" (*(volatile unsigned long *)p)
285 : "r" (p), "r" (val) 290 : "r" (p), "r" (val)
286 : "cc", "memory"); 291 : "cc", "memory");
@@ -366,14 +371,14 @@ __cmpxchg_u32(volatile unsigned int *p, unsigned long old, unsigned long new)
366 unsigned int prev; 371 unsigned int prev;
367 372
368 __asm__ __volatile__ ( 373 __asm__ __volatile__ (
369 LWSYNC_ON_SMP 374 PPC_RELEASE_BARRIER
370"1: lwarx %0,0,%2 # __cmpxchg_u32\n\ 375"1: lwarx %0,0,%2 # __cmpxchg_u32\n\
371 cmpw 0,%0,%3\n\ 376 cmpw 0,%0,%3\n\
372 bne- 2f\n" 377 bne- 2f\n"
373 PPC405_ERR77(0,%2) 378 PPC405_ERR77(0,%2)
374" stwcx. %4,0,%2\n\ 379" stwcx. %4,0,%2\n\
375 bne- 1b" 380 bne- 1b"
376 ISYNC_ON_SMP 381 PPC_ACQUIRE_BARRIER
377 "\n\ 382 "\n\
3782:" 3832:"
379 : "=&r" (prev), "+m" (*p) 384 : "=&r" (prev), "+m" (*p)
@@ -412,13 +417,13 @@ __cmpxchg_u64(volatile unsigned long *p, unsigned long old, unsigned long new)
412 unsigned long prev; 417 unsigned long prev;
413 418
414 __asm__ __volatile__ ( 419 __asm__ __volatile__ (
415 LWSYNC_ON_SMP 420 PPC_RELEASE_BARRIER
416"1: ldarx %0,0,%2 # __cmpxchg_u64\n\ 421"1: ldarx %0,0,%2 # __cmpxchg_u64\n\
417 cmpd 0,%0,%3\n\ 422 cmpd 0,%0,%3\n\
418 bne- 2f\n\ 423 bne- 2f\n\
419 stdcx. %4,0,%2\n\ 424 stdcx. %4,0,%2\n\
420 bne- 1b" 425 bne- 1b"
421 ISYNC_ON_SMP 426 PPC_ACQUIRE_BARRIER
422 "\n\ 427 "\n\
4232:" 4282:"
424 : "=&r" (prev), "+m" (*p) 429 : "=&r" (prev), "+m" (*p)