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-rw-r--r--arch/powerpc/include/asm/pci-bridge.h302
1 files changed, 302 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/pci-bridge.h b/arch/powerpc/include/asm/pci-bridge.h
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1#ifndef _ASM_POWERPC_PCI_BRIDGE_H
2#define _ASM_POWERPC_PCI_BRIDGE_H
3#ifdef __KERNEL__
4/*
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
9 */
10#include <linux/pci.h>
11#include <linux/list.h>
12#include <linux/ioport.h>
13
14struct device_node;
15
16extern unsigned int ppc_pci_flags;
17enum {
18 /* Force re-assigning all resources (ignore firmware
19 * setup completely)
20 */
21 PPC_PCI_REASSIGN_ALL_RSRC = 0x00000001,
22
23 /* Re-assign all bus numbers */
24 PPC_PCI_REASSIGN_ALL_BUS = 0x00000002,
25
26 /* Do not try to assign, just use existing setup */
27 PPC_PCI_PROBE_ONLY = 0x00000004,
28
29 /* Don't bother with ISA alignment unless the bridge has
30 * ISA forwarding enabled
31 */
32 PPC_PCI_CAN_SKIP_ISA_ALIGN = 0x00000008,
33
34 /* Enable domain numbers in /proc */
35 PPC_PCI_ENABLE_PROC_DOMAINS = 0x00000010,
36 /* ... except for domain 0 */
37 PPC_PCI_COMPAT_DOMAIN_0 = 0x00000020,
38};
39
40
41/*
42 * Structure of a PCI controller (host bridge)
43 */
44struct pci_controller {
45 struct pci_bus *bus;
46 char is_dynamic;
47#ifdef CONFIG_PPC64
48 int node;
49#endif
50 struct device_node *dn;
51 struct list_head list_node;
52 struct device *parent;
53
54 int first_busno;
55 int last_busno;
56#ifndef CONFIG_PPC64
57 int self_busno;
58#endif
59
60 void __iomem *io_base_virt;
61#ifdef CONFIG_PPC64
62 void *io_base_alloc;
63#endif
64 resource_size_t io_base_phys;
65#ifndef CONFIG_PPC64
66 resource_size_t pci_io_size;
67#endif
68
69 /* Some machines (PReP) have a non 1:1 mapping of
70 * the PCI memory space in the CPU bus space
71 */
72 resource_size_t pci_mem_offset;
73#ifdef CONFIG_PPC64
74 unsigned long pci_io_size;
75#endif
76
77 struct pci_ops *ops;
78 unsigned int __iomem *cfg_addr;
79 void __iomem *cfg_data;
80
81#ifndef CONFIG_PPC64
82 /*
83 * Used for variants of PCI indirect handling and possible quirks:
84 * SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1
85 * EXT_REG - provides access to PCI-e extended registers
86 * SURPRESS_PRIMARY_BUS - we surpress the setting of PCI_PRIMARY_BUS
87 * on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS
88 * to determine which bus number to match on when generating type0
89 * config cycles
90 * NO_PCIE_LINK - the Freescale PCI-e controllers have issues with
91 * hanging if we don't have link and try to do config cycles to
92 * anything but the PHB. Only allow talking to the PHB if this is
93 * set.
94 * BIG_ENDIAN - cfg_addr is a big endian register
95 * BROKEN_MRM - the 440EPx/GRx chips have an errata that causes hangs on
96 * the PLB4. Effectively disable MRM commands by setting this.
97 */
98#define PPC_INDIRECT_TYPE_SET_CFG_TYPE 0x00000001
99#define PPC_INDIRECT_TYPE_EXT_REG 0x00000002
100#define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS 0x00000004
101#define PPC_INDIRECT_TYPE_NO_PCIE_LINK 0x00000008
102#define PPC_INDIRECT_TYPE_BIG_ENDIAN 0x00000010
103#define PPC_INDIRECT_TYPE_BROKEN_MRM 0x00000020
104 u32 indirect_type;
105#endif /* !CONFIG_PPC64 */
106 /* Currently, we limit ourselves to 1 IO range and 3 mem
107 * ranges since the common pci_bus structure can't handle more
108 */
109 struct resource io_resource;
110 struct resource mem_resources[3];
111 int global_number; /* PCI domain number */
112#ifdef CONFIG_PPC64
113 unsigned long buid;
114 unsigned long dma_window_base_cur;
115 unsigned long dma_window_size;
116
117 void *private_data;
118#endif /* CONFIG_PPC64 */
119};
120
121#ifndef CONFIG_PPC64
122
123static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus)
124{
125 return bus->sysdata;
126}
127
128static inline int isa_vaddr_is_ioport(void __iomem *address)
129{
130 /* No specific ISA handling on ppc32 at this stage, it
131 * all goes through PCI
132 */
133 return 0;
134}
135
136/* These are used for config access before all the PCI probing
137 has been done. */
138extern int early_read_config_byte(struct pci_controller *hose, int bus,
139 int dev_fn, int where, u8 *val);
140extern int early_read_config_word(struct pci_controller *hose, int bus,
141 int dev_fn, int where, u16 *val);
142extern int early_read_config_dword(struct pci_controller *hose, int bus,
143 int dev_fn, int where, u32 *val);
144extern int early_write_config_byte(struct pci_controller *hose, int bus,
145 int dev_fn, int where, u8 val);
146extern int early_write_config_word(struct pci_controller *hose, int bus,
147 int dev_fn, int where, u16 val);
148extern int early_write_config_dword(struct pci_controller *hose, int bus,
149 int dev_fn, int where, u32 val);
150
151extern int early_find_capability(struct pci_controller *hose, int bus,
152 int dev_fn, int cap);
153
154extern void setup_indirect_pci(struct pci_controller* hose,
155 resource_size_t cfg_addr,
156 resource_size_t cfg_data, u32 flags);
157extern void setup_grackle(struct pci_controller *hose);
158#else /* CONFIG_PPC64 */
159
160/*
161 * PCI stuff, for nodes representing PCI devices, pointed to
162 * by device_node->data.
163 */
164struct iommu_table;
165
166struct pci_dn {
167 int busno; /* pci bus number */
168 int devfn; /* pci device and function number */
169
170 struct pci_controller *phb; /* for pci devices */
171 struct iommu_table *iommu_table; /* for phb's or bridges */
172 struct device_node *node; /* back-pointer to the device_node */
173
174 int pci_ext_config_space; /* for pci devices */
175
176#ifdef CONFIG_EEH
177 struct pci_dev *pcidev; /* back-pointer to the pci device */
178 int class_code; /* pci device class */
179 int eeh_mode; /* See eeh.h for possible EEH_MODEs */
180 int eeh_config_addr;
181 int eeh_pe_config_addr; /* new-style partition endpoint address */
182 int eeh_check_count; /* # times driver ignored error */
183 int eeh_freeze_count; /* # times this device froze up. */
184 int eeh_false_positives; /* # times this device reported #ff's */
185 u32 config_space[16]; /* saved PCI config space */
186#endif
187};
188
189/* Get the pointer to a device_node's pci_dn */
190#define PCI_DN(dn) ((struct pci_dn *) (dn)->data)
191
192extern struct device_node *fetch_dev_dn(struct pci_dev *dev);
193
194/* Get a device_node from a pci_dev. This code must be fast except
195 * in the case where the sysdata is incorrect and needs to be fixed
196 * up (this will only happen once).
197 * In this case the sysdata will have been inherited from a PCI host
198 * bridge or a PCI-PCI bridge further up the tree, so it will point
199 * to a valid struct pci_dn, just not the one we want.
200 */
201static inline struct device_node *pci_device_to_OF_node(struct pci_dev *dev)
202{
203 struct device_node *dn = dev->sysdata;
204 struct pci_dn *pdn = dn->data;
205
206 if (pdn && pdn->devfn == dev->devfn && pdn->busno == dev->bus->number)
207 return dn; /* fast path. sysdata is good */
208 return fetch_dev_dn(dev);
209}
210
211static inline int pci_device_from_OF_node(struct device_node *np,
212 u8 *bus, u8 *devfn)
213{
214 if (!PCI_DN(np))
215 return -ENODEV;
216 *bus = PCI_DN(np)->busno;
217 *devfn = PCI_DN(np)->devfn;
218 return 0;
219}
220
221static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
222{
223 if (bus->self)
224 return pci_device_to_OF_node(bus->self);
225 else
226 return bus->sysdata; /* Must be root bus (PHB) */
227}
228
229/** Find the bus corresponding to the indicated device node */
230extern struct pci_bus *pcibios_find_pci_bus(struct device_node *dn);
231
232/** Remove all of the PCI devices under this bus */
233extern void pcibios_remove_pci_devices(struct pci_bus *bus);
234
235/** Discover new pci devices under this bus, and add them */
236extern void pcibios_add_pci_devices(struct pci_bus *bus);
237extern void pcibios_fixup_new_pci_devices(struct pci_bus *bus);
238
239extern int pcibios_remove_root_bus(struct pci_controller *phb);
240
241static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus)
242{
243 struct device_node *busdn = bus->sysdata;
244
245 BUG_ON(busdn == NULL);
246 return PCI_DN(busdn)->phb;
247}
248
249
250extern void isa_bridge_find_early(struct pci_controller *hose);
251
252static inline int isa_vaddr_is_ioport(void __iomem *address)
253{
254 /* Check if address hits the reserved legacy IO range */
255 unsigned long ea = (unsigned long)address;
256 return ea >= ISA_IO_BASE && ea < ISA_IO_END;
257}
258
259extern int pcibios_unmap_io_space(struct pci_bus *bus);
260extern int pcibios_map_io_space(struct pci_bus *bus);
261
262/* Return values for ppc_md.pci_probe_mode function */
263#define PCI_PROBE_NONE -1 /* Don't look at this bus at all */
264#define PCI_PROBE_NORMAL 0 /* Do normal PCI probing */
265#define PCI_PROBE_DEVTREE 1 /* Instantiate from device tree */
266
267#ifdef CONFIG_NUMA
268#define PHB_SET_NODE(PHB, NODE) ((PHB)->node = (NODE))
269#else
270#define PHB_SET_NODE(PHB, NODE) ((PHB)->node = -1)
271#endif
272
273#endif /* CONFIG_PPC64 */
274
275/* Get the PCI host controller for an OF device */
276extern struct pci_controller *pci_find_hose_for_OF_device(
277 struct device_node* node);
278
279/* Fill up host controller resources from the OF node */
280extern void pci_process_bridge_OF_ranges(struct pci_controller *hose,
281 struct device_node *dev, int primary);
282
283/* Allocate & free a PCI host bridge structure */
284extern struct pci_controller *pcibios_alloc_controller(struct device_node *dev);
285extern void pcibios_free_controller(struct pci_controller *phb);
286
287#ifdef CONFIG_PCI
288extern unsigned long pci_address_to_pio(phys_addr_t address);
289extern int pcibios_vaddr_is_ioport(void __iomem *address);
290#else
291static inline unsigned long pci_address_to_pio(phys_addr_t address)
292{
293 return (unsigned long)-1;
294}
295static inline int pcibios_vaddr_is_ioport(void __iomem *address)
296{
297 return 0;
298}
299#endif /* CONFIG_PCI */
300
301#endif /* __KERNEL__ */
302#endif /* _ASM_POWERPC_PCI_BRIDGE_H */
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