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1/*
2 * Copyright 2011-2012, Meador Inge, Mentor Graphics Corporation.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; version 2 of the
7 * License.
8 *
9 */
10
11#ifndef _ASM_MPIC_MSGR_H
12#define _ASM_MPIC_MSGR_H
13
14#include <linux/types.h>
15#include <linux/spinlock.h>
16
17struct mpic_msgr {
18 u32 __iomem *base;
19 u32 __iomem *mer;
20 int irq;
21 unsigned char in_use;
22 raw_spinlock_t lock;
23 int num;
24};
25
26/* Get a message register
27 *
28 * @reg_num: the MPIC message register to get
29 *
30 * A pointer to the message register is returned. If
31 * the message register asked for is already in use, then
32 * EBUSY is returned. If the number given is not associated
33 * with an actual message register, then ENODEV is returned.
34 * Successfully getting the register marks it as in use.
35 */
36extern struct mpic_msgr *mpic_msgr_get(unsigned int reg_num);
37
38/* Relinquish a message register
39 *
40 * @msgr: the message register to return
41 *
42 * Disables the given message register and marks it as free.
43 * After this call has completed successully the message
44 * register is available to be acquired by a call to
45 * mpic_msgr_get.
46 */
47extern void mpic_msgr_put(struct mpic_msgr *msgr);
48
49/* Enable a message register
50 *
51 * @msgr: the message register to enable
52 *
53 * The given message register is enabled for sending
54 * messages.
55 */
56extern void mpic_msgr_enable(struct mpic_msgr *msgr);
57
58/* Disable a message register
59 *
60 * @msgr: the message register to disable
61 *
62 * The given message register is disabled for sending
63 * messages.
64 */
65extern void mpic_msgr_disable(struct mpic_msgr *msgr);
66
67/* Write a message to a message register
68 *
69 * @msgr: the message register to write to
70 * @message: the message to write
71 *
72 * The given 32-bit message is written to the given message
73 * register. Writing to an enabled message registers fires
74 * an interrupt.
75 */
76static inline void mpic_msgr_write(struct mpic_msgr *msgr, u32 message)
77{
78 out_be32(msgr->base, message);
79}
80
81/* Read a message from a message register
82 *
83 * @msgr: the message register to read from
84 *
85 * Returns the 32-bit value currently in the given message register.
86 * Upon reading the register any interrupts for that register are
87 * cleared.
88 */
89static inline u32 mpic_msgr_read(struct mpic_msgr *msgr)
90{
91 return in_be32(msgr->base);
92}
93
94/* Clear a message register
95 *
96 * @msgr: the message register to clear
97 *
98 * Clears any interrupts associated with the given message register.
99 */
100static inline void mpic_msgr_clear(struct mpic_msgr *msgr)
101{
102 (void) mpic_msgr_read(msgr);
103}
104
105/* Set the destination CPU for the message register
106 *
107 * @msgr: the message register whose destination is to be set
108 * @cpu_num: the Linux CPU number to bind the message register to
109 *
110 * Note that the CPU number given is the CPU number used by the kernel
111 * and *not* the actual hardware CPU number.
112 */
113static inline void mpic_msgr_set_destination(struct mpic_msgr *msgr,
114 u32 cpu_num)
115{
116 out_be32(msgr->base, 1 << get_hard_smp_processor_id(cpu_num));
117}
118
119/* Get the IRQ number for the message register
120 * @msgr: the message register whose IRQ is to be returned
121 *
122 * Returns the IRQ number associated with the given message register.
123 * NO_IRQ is returned if this message register is not capable of
124 * receiving interrupts. What message register can and cannot receive
125 * interrupts is specified in the device tree for the system.
126 */
127static inline int mpic_msgr_get_irq(struct mpic_msgr *msgr)
128{
129 return msgr->irq;
130}
131
132#endif