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Diffstat (limited to 'arch/powerpc/include/asm/fsl_lbc.h')
-rw-r--r--arch/powerpc/include/asm/fsl_lbc.h48
1 files changed, 4 insertions, 44 deletions
diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h
index 303f5484c050..63a4f779f531 100644
--- a/arch/powerpc/include/asm/fsl_lbc.h
+++ b/arch/powerpc/include/asm/fsl_lbc.h
@@ -23,9 +23,9 @@
23#ifndef __ASM_FSL_LBC_H 23#ifndef __ASM_FSL_LBC_H
24#define __ASM_FSL_LBC_H 24#define __ASM_FSL_LBC_H
25 25
26#include <linux/compiler.h>
26#include <linux/types.h> 27#include <linux/types.h>
27#include <linux/spinlock.h> 28#include <linux/io.h>
28#include <asm/io.h>
29 29
30struct fsl_lbc_bank { 30struct fsl_lbc_bank {
31 __be32 br; /**< Base Register */ 31 __be32 br; /**< Base Register */
@@ -227,9 +227,6 @@ struct fsl_lbc_regs {
227 u8 res8[0xF00]; 227 u8 res8[0xF00];
228}; 228};
229 229
230extern struct fsl_lbc_regs __iomem *fsl_lbc_regs;
231extern spinlock_t fsl_lbc_lock;
232
233/* 230/*
234 * FSL UPM routines 231 * FSL UPM routines
235 */ 232 */
@@ -268,44 +265,7 @@ static inline void fsl_upm_end_pattern(struct fsl_upm *upm)
268 cpu_relax(); 265 cpu_relax();
269} 266}
270 267
271/** 268extern int fsl_upm_run_pattern(struct fsl_upm *upm, void __iomem *io_base,
272 * fsl_upm_run_pattern - actually run an UPM pattern 269 u32 mar);
273 * @upm: pointer to the fsl_upm structure obtained via fsl_upm_find
274 * @io_base: remapped pointer to where memory access should happen
275 * @mar: MAR register content during pattern execution
276 *
277 * This function triggers dummy write to the memory specified by the io_base,
278 * thus UPM pattern actually executed. Note that mar usage depends on the
279 * pre-programmed AMX bits in the UPM RAM.
280 */
281static inline int fsl_upm_run_pattern(struct fsl_upm *upm,
282 void __iomem *io_base, u32 mar)
283{
284 int ret = 0;
285 unsigned long flags;
286
287 spin_lock_irqsave(&fsl_lbc_lock, flags);
288
289 out_be32(&fsl_lbc_regs->mar, mar << (32 - upm->width));
290
291 switch (upm->width) {
292 case 8:
293 out_8(io_base, 0x0);
294 break;
295 case 16:
296 out_be16(io_base, 0x0);
297 break;
298 case 32:
299 out_be32(io_base, 0x0);
300 break;
301 default:
302 ret = -EINVAL;
303 break;
304 }
305
306 spin_unlock_irqrestore(&fsl_lbc_lock, flags);
307
308 return ret;
309}
310 270
311#endif /* __ASM_FSL_LBC_H */ 271#endif /* __ASM_FSL_LBC_H */