diff options
Diffstat (limited to 'arch/powerpc/include/asm/exception.h')
-rw-r--r-- | arch/powerpc/include/asm/exception.h | 42 |
1 files changed, 5 insertions, 37 deletions
diff --git a/arch/powerpc/include/asm/exception.h b/arch/powerpc/include/asm/exception.h index 329148b5acc6..d3d4534e3c74 100644 --- a/arch/powerpc/include/asm/exception.h +++ b/arch/powerpc/include/asm/exception.h | |||
@@ -53,14 +53,8 @@ | |||
53 | * low halfword of the address, but for Kdump we need the whole low | 53 | * low halfword of the address, but for Kdump we need the whole low |
54 | * word. | 54 | * word. |
55 | */ | 55 | */ |
56 | #ifdef CONFIG_CRASH_DUMP | ||
57 | #define LOAD_HANDLER(reg, label) \ | 56 | #define LOAD_HANDLER(reg, label) \ |
58 | oris reg,reg,(label)@h; /* virt addr of handler ... */ \ | 57 | addi reg,reg,(label)-_stext; /* virt addr of handler ... */ |
59 | ori reg,reg,(label)@l; /* .. and the rest */ | ||
60 | #else | ||
61 | #define LOAD_HANDLER(reg, label) \ | ||
62 | ori reg,reg,(label)@l; /* virt addr of handler ... */ | ||
63 | #endif | ||
64 | 58 | ||
65 | #define EXCEPTION_PROLOG_1(area) \ | 59 | #define EXCEPTION_PROLOG_1(area) \ |
66 | mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \ | 60 | mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \ |
@@ -72,37 +66,12 @@ | |||
72 | std r9,area+EX_R13(r13); \ | 66 | std r9,area+EX_R13(r13); \ |
73 | mfcr r9 | 67 | mfcr r9 |
74 | 68 | ||
75 | /* | ||
76 | * Equal to EXCEPTION_PROLOG_PSERIES, except that it forces 64bit mode. | ||
77 | * The firmware calls the registered system_reset_fwnmi and | ||
78 | * machine_check_fwnmi handlers in 32bit mode if the cpu happens to run | ||
79 | * a 32bit application at the time of the event. | ||
80 | * This firmware bug is present on POWER4 and JS20. | ||
81 | */ | ||
82 | #define EXCEPTION_PROLOG_PSERIES_FORCE_64BIT(area, label) \ | ||
83 | EXCEPTION_PROLOG_1(area); \ | ||
84 | clrrdi r12,r13,32; /* get high part of &label */ \ | ||
85 | mfmsr r10; \ | ||
86 | /* force 64bit mode */ \ | ||
87 | li r11,5; /* MSR_SF_LG|MSR_ISF_LG */ \ | ||
88 | rldimi r10,r11,61,0; /* insert into top 3 bits */ \ | ||
89 | /* done 64bit mode */ \ | ||
90 | mfspr r11,SPRN_SRR0; /* save SRR0 */ \ | ||
91 | LOAD_HANDLER(r12,label) \ | ||
92 | ori r10,r10,MSR_IR|MSR_DR|MSR_RI; \ | ||
93 | mtspr SPRN_SRR0,r12; \ | ||
94 | mfspr r12,SPRN_SRR1; /* and SRR1 */ \ | ||
95 | mtspr SPRN_SRR1,r10; \ | ||
96 | rfid; \ | ||
97 | b . /* prevent speculative execution */ | ||
98 | |||
99 | #define EXCEPTION_PROLOG_PSERIES(area, label) \ | 69 | #define EXCEPTION_PROLOG_PSERIES(area, label) \ |
100 | EXCEPTION_PROLOG_1(area); \ | 70 | EXCEPTION_PROLOG_1(area); \ |
101 | clrrdi r12,r13,32; /* get high part of &label */ \ | 71 | ld r12,PACAKBASE(r13); /* get high part of &label */ \ |
102 | mfmsr r10; \ | 72 | ld r10,PACAKMSR(r13); /* get MSR value for kernel */ \ |
103 | mfspr r11,SPRN_SRR0; /* save SRR0 */ \ | 73 | mfspr r11,SPRN_SRR0; /* save SRR0 */ \ |
104 | LOAD_HANDLER(r12,label) \ | 74 | LOAD_HANDLER(r12,label) \ |
105 | ori r10,r10,MSR_IR|MSR_DR|MSR_RI; \ | ||
106 | mtspr SPRN_SRR0,r12; \ | 75 | mtspr SPRN_SRR0,r12; \ |
107 | mfspr r12,SPRN_SRR1; /* and SRR1 */ \ | 76 | mfspr r12,SPRN_SRR1; /* and SRR1 */ \ |
108 | mtspr SPRN_SRR1,r10; \ | 77 | mtspr SPRN_SRR1,r10; \ |
@@ -210,11 +179,10 @@ label##_pSeries: \ | |||
210 | std r10,PACA_EXGEN+EX_R13(r13); \ | 179 | std r10,PACA_EXGEN+EX_R13(r13); \ |
211 | std r11,PACA_EXGEN+EX_R11(r13); \ | 180 | std r11,PACA_EXGEN+EX_R11(r13); \ |
212 | std r12,PACA_EXGEN+EX_R12(r13); \ | 181 | std r12,PACA_EXGEN+EX_R12(r13); \ |
213 | clrrdi r12,r13,32; /* get high part of &label */ \ | 182 | ld r12,PACAKBASE(r13); /* get high part of &label */ \ |
214 | mfmsr r10; \ | 183 | ld r10,PACAKMSR(r13); /* get MSR value for kernel */ \ |
215 | mfspr r11,SPRN_SRR0; /* save SRR0 */ \ | 184 | mfspr r11,SPRN_SRR0; /* save SRR0 */ \ |
216 | LOAD_HANDLER(r12,label##_common) \ | 185 | LOAD_HANDLER(r12,label##_common) \ |
217 | ori r10,r10,MSR_IR|MSR_DR|MSR_RI; \ | ||
218 | mtspr SPRN_SRR0,r12; \ | 186 | mtspr SPRN_SRR0,r12; \ |
219 | mfspr r12,SPRN_SRR1; /* and SRR1 */ \ | 187 | mfspr r12,SPRN_SRR1; /* and SRR1 */ \ |
220 | mtspr SPRN_SRR1,r10; \ | 188 | mtspr SPRN_SRR1,r10; \ |