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-rw-r--r--arch/powerpc/include/asm/cputable.h514
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diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h
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1#ifndef __ASM_POWERPC_CPUTABLE_H
2#define __ASM_POWERPC_CPUTABLE_H
3
4#define PPC_FEATURE_32 0x80000000
5#define PPC_FEATURE_64 0x40000000
6#define PPC_FEATURE_601_INSTR 0x20000000
7#define PPC_FEATURE_HAS_ALTIVEC 0x10000000
8#define PPC_FEATURE_HAS_FPU 0x08000000
9#define PPC_FEATURE_HAS_MMU 0x04000000
10#define PPC_FEATURE_HAS_4xxMAC 0x02000000
11#define PPC_FEATURE_UNIFIED_CACHE 0x01000000
12#define PPC_FEATURE_HAS_SPE 0x00800000
13#define PPC_FEATURE_HAS_EFP_SINGLE 0x00400000
14#define PPC_FEATURE_HAS_EFP_DOUBLE 0x00200000
15#define PPC_FEATURE_NO_TB 0x00100000
16#define PPC_FEATURE_POWER4 0x00080000
17#define PPC_FEATURE_POWER5 0x00040000
18#define PPC_FEATURE_POWER5_PLUS 0x00020000
19#define PPC_FEATURE_CELL 0x00010000
20#define PPC_FEATURE_BOOKE 0x00008000
21#define PPC_FEATURE_SMT 0x00004000
22#define PPC_FEATURE_ICACHE_SNOOP 0x00002000
23#define PPC_FEATURE_ARCH_2_05 0x00001000
24#define PPC_FEATURE_PA6T 0x00000800
25#define PPC_FEATURE_HAS_DFP 0x00000400
26#define PPC_FEATURE_POWER6_EXT 0x00000200
27#define PPC_FEATURE_ARCH_2_06 0x00000100
28#define PPC_FEATURE_HAS_VSX 0x00000080
29
30#define PPC_FEATURE_PSERIES_PERFMON_COMPAT \
31 0x00000040
32
33#define PPC_FEATURE_TRUE_LE 0x00000002
34#define PPC_FEATURE_PPC_LE 0x00000001
35
36#ifdef __KERNEL__
37
38#include <asm/asm-compat.h>
39#include <asm/feature-fixups.h>
40
41#ifndef __ASSEMBLY__
42
43/* This structure can grow, it's real size is used by head.S code
44 * via the mkdefs mechanism.
45 */
46struct cpu_spec;
47
48typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
49typedef void (*cpu_restore_t)(void);
50
51enum powerpc_oprofile_type {
52 PPC_OPROFILE_INVALID = 0,
53 PPC_OPROFILE_RS64 = 1,
54 PPC_OPROFILE_POWER4 = 2,
55 PPC_OPROFILE_G4 = 3,
56 PPC_OPROFILE_FSL_EMB = 4,
57 PPC_OPROFILE_CELL = 5,
58 PPC_OPROFILE_PA6T = 6,
59};
60
61enum powerpc_pmc_type {
62 PPC_PMC_DEFAULT = 0,
63 PPC_PMC_IBM = 1,
64 PPC_PMC_PA6T = 2,
65};
66
67struct pt_regs;
68
69extern int machine_check_generic(struct pt_regs *regs);
70extern int machine_check_4xx(struct pt_regs *regs);
71extern int machine_check_440A(struct pt_regs *regs);
72extern int machine_check_e500(struct pt_regs *regs);
73extern int machine_check_e200(struct pt_regs *regs);
74
75/* NOTE WELL: Update identify_cpu() if fields are added or removed! */
76struct cpu_spec {
77 /* CPU is matched via (PVR & pvr_mask) == pvr_value */
78 unsigned int pvr_mask;
79 unsigned int pvr_value;
80
81 char *cpu_name;
82 unsigned long cpu_features; /* Kernel features */
83 unsigned int cpu_user_features; /* Userland features */
84
85 /* cache line sizes */
86 unsigned int icache_bsize;
87 unsigned int dcache_bsize;
88
89 /* number of performance monitor counters */
90 unsigned int num_pmcs;
91 enum powerpc_pmc_type pmc_type;
92
93 /* this is called to initialize various CPU bits like L1 cache,
94 * BHT, SPD, etc... from head.S before branching to identify_machine
95 */
96 cpu_setup_t cpu_setup;
97 /* Used to restore cpu setup on secondary processors and at resume */
98 cpu_restore_t cpu_restore;
99
100 /* Used by oprofile userspace to select the right counters */
101 char *oprofile_cpu_type;
102
103 /* Processor specific oprofile operations */
104 enum powerpc_oprofile_type oprofile_type;
105
106 /* Bit locations inside the mmcra change */
107 unsigned long oprofile_mmcra_sihv;
108 unsigned long oprofile_mmcra_sipr;
109
110 /* Bits to clear during an oprofile exception */
111 unsigned long oprofile_mmcra_clear;
112
113 /* Name of processor class, for the ELF AT_PLATFORM entry */
114 char *platform;
115
116 /* Processor specific machine check handling. Return negative
117 * if the error is fatal, 1 if it was fully recovered and 0 to
118 * pass up (not CPU originated) */
119 int (*machine_check)(struct pt_regs *regs);
120};
121
122extern struct cpu_spec *cur_cpu_spec;
123
124extern unsigned int __start___ftr_fixup, __stop___ftr_fixup;
125
126extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr);
127extern void do_feature_fixups(unsigned long value, void *fixup_start,
128 void *fixup_end);
129
130extern const char *powerpc_base_platform;
131
132#endif /* __ASSEMBLY__ */
133
134/* CPU kernel features */
135
136/* Retain the 32b definitions all use bottom half of word */
137#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0000000000000001)
138#define CPU_FTR_L2CR ASM_CONST(0x0000000000000002)
139#define CPU_FTR_SPEC7450 ASM_CONST(0x0000000000000004)
140#define CPU_FTR_ALTIVEC ASM_CONST(0x0000000000000008)
141#define CPU_FTR_TAU ASM_CONST(0x0000000000000010)
142#define CPU_FTR_CAN_DOZE ASM_CONST(0x0000000000000020)
143#define CPU_FTR_USE_TB ASM_CONST(0x0000000000000040)
144#define CPU_FTR_L2CSR ASM_CONST(0x0000000000000080)
145#define CPU_FTR_601 ASM_CONST(0x0000000000000100)
146#define CPU_FTR_HPTE_TABLE ASM_CONST(0x0000000000000200)
147#define CPU_FTR_CAN_NAP ASM_CONST(0x0000000000000400)
148#define CPU_FTR_L3CR ASM_CONST(0x0000000000000800)
149#define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x0000000000001000)
150#define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x0000000000002000)
151#define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x0000000000004000)
152#define CPU_FTR_NO_DPM ASM_CONST(0x0000000000008000)
153#define CPU_FTR_HAS_HIGH_BATS ASM_CONST(0x0000000000010000)
154#define CPU_FTR_NEED_COHERENT ASM_CONST(0x0000000000020000)
155#define CPU_FTR_NO_BTIC ASM_CONST(0x0000000000040000)
156#define CPU_FTR_BIG_PHYS ASM_CONST(0x0000000000080000)
157#define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000000000100000)
158#define CPU_FTR_PPC_LE ASM_CONST(0x0000000000200000)
159#define CPU_FTR_REAL_LE ASM_CONST(0x0000000000400000)
160#define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x0000000000800000)
161#define CPU_FTR_UNIFIED_ID_CACHE ASM_CONST(0x0000000001000000)
162#define CPU_FTR_SPE ASM_CONST(0x0000000002000000)
163#define CPU_FTR_NEED_PAIRED_STWCX ASM_CONST(0x0000000004000000)
164#define CPU_FTR_LWSYNC ASM_CONST(0x0000000008000000)
165
166/*
167 * Add the 64-bit processor unique features in the top half of the word;
168 * on 32-bit, make the names available but defined to be 0.
169 */
170#ifdef __powerpc64__
171#define LONG_ASM_CONST(x) ASM_CONST(x)
172#else
173#define LONG_ASM_CONST(x) 0
174#endif
175
176#define CPU_FTR_SLB LONG_ASM_CONST(0x0000000100000000)
177#define CPU_FTR_16M_PAGE LONG_ASM_CONST(0x0000000200000000)
178#define CPU_FTR_TLBIEL LONG_ASM_CONST(0x0000000400000000)
179#define CPU_FTR_NOEXECUTE LONG_ASM_CONST(0x0000000800000000)
180#define CPU_FTR_IABR LONG_ASM_CONST(0x0000002000000000)
181#define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000004000000000)
182#define CPU_FTR_CTRL LONG_ASM_CONST(0x0000008000000000)
183#define CPU_FTR_SMT LONG_ASM_CONST(0x0000010000000000)
184#define CPU_FTR_LOCKLESS_TLBIE LONG_ASM_CONST(0x0000040000000000)
185#define CPU_FTR_CI_LARGE_PAGE LONG_ASM_CONST(0x0000100000000000)
186#define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000200000000000)
187#define CPU_FTR_PURR LONG_ASM_CONST(0x0000400000000000)
188#define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000800000000000)
189#define CPU_FTR_SPURR LONG_ASM_CONST(0x0001000000000000)
190#define CPU_FTR_DSCR LONG_ASM_CONST(0x0002000000000000)
191#define CPU_FTR_1T_SEGMENT LONG_ASM_CONST(0x0004000000000000)
192#define CPU_FTR_NO_SLBIE_B LONG_ASM_CONST(0x0008000000000000)
193#define CPU_FTR_VSX LONG_ASM_CONST(0x0010000000000000)
194#define CPU_FTR_SAO LONG_ASM_CONST(0x0020000000000000)
195
196#ifndef __ASSEMBLY__
197
198#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_SLB | \
199 CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \
200 CPU_FTR_NODSISRALIGN | CPU_FTR_16M_PAGE)
201
202/* We only set the altivec features if the kernel was compiled with altivec
203 * support
204 */
205#ifdef CONFIG_ALTIVEC
206#define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
207#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
208#else
209#define CPU_FTR_ALTIVEC_COMP 0
210#define PPC_FEATURE_HAS_ALTIVEC_COMP 0
211#endif
212
213/* We only set the VSX features if the kernel was compiled with VSX
214 * support
215 */
216#ifdef CONFIG_VSX
217#define CPU_FTR_VSX_COMP CPU_FTR_VSX
218#define PPC_FEATURE_HAS_VSX_COMP PPC_FEATURE_HAS_VSX
219#else
220#define CPU_FTR_VSX_COMP 0
221#define PPC_FEATURE_HAS_VSX_COMP 0
222#endif
223
224/* We only set the spe features if the kernel was compiled with spe
225 * support
226 */
227#ifdef CONFIG_SPE
228#define CPU_FTR_SPE_COMP CPU_FTR_SPE
229#define PPC_FEATURE_HAS_SPE_COMP PPC_FEATURE_HAS_SPE
230#define PPC_FEATURE_HAS_EFP_SINGLE_COMP PPC_FEATURE_HAS_EFP_SINGLE
231#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP PPC_FEATURE_HAS_EFP_DOUBLE
232#else
233#define CPU_FTR_SPE_COMP 0
234#define PPC_FEATURE_HAS_SPE_COMP 0
235#define PPC_FEATURE_HAS_EFP_SINGLE_COMP 0
236#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP 0
237#endif
238
239/* We need to mark all pages as being coherent if we're SMP or we have a
240 * 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II
241 * require it for PCI "streaming/prefetch" to work properly.
242 */
243#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \
244 || defined(CONFIG_PPC_83xx) || defined(CONFIG_8260)
245#define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
246#else
247#define CPU_FTR_COMMON 0
248#endif
249
250/* The powersave features NAP & DOZE seems to confuse BDI when
251 debugging. So if a BDI is used, disable theses
252 */
253#ifndef CONFIG_BDI_SWITCH
254#define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
255#define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
256#else
257#define CPU_FTR_MAYBE_CAN_DOZE 0
258#define CPU_FTR_MAYBE_CAN_NAP 0
259#endif
260
261#define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
262 !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
263 !defined(CONFIG_BOOKE))
264
265#define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | CPU_FTR_HPTE_TABLE | \
266 CPU_FTR_COHERENT_ICACHE | CPU_FTR_UNIFIED_ID_CACHE)
267#define CPU_FTRS_603 (CPU_FTR_COMMON | \
268 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
269 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
270#define CPU_FTRS_604 (CPU_FTR_COMMON | \
271 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_PPC_LE)
272#define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | \
273 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
274 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
275#define CPU_FTRS_740 (CPU_FTR_COMMON | \
276 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
277 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
278 CPU_FTR_PPC_LE)
279#define CPU_FTRS_750 (CPU_FTR_COMMON | \
280 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
281 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
282 CPU_FTR_PPC_LE)
283#define CPU_FTRS_750CL (CPU_FTRS_750 | CPU_FTR_HAS_HIGH_BATS)
284#define CPU_FTRS_750FX1 (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM)
285#define CPU_FTRS_750FX2 (CPU_FTRS_750 | CPU_FTR_NO_DPM)
286#define CPU_FTRS_750FX (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | \
287 CPU_FTR_HAS_HIGH_BATS)
288#define CPU_FTRS_750GX (CPU_FTRS_750FX)
289#define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | \
290 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
291 CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \
292 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
293#define CPU_FTRS_7400 (CPU_FTR_COMMON | \
294 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
295 CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \
296 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
297#define CPU_FTRS_7450_20 (CPU_FTR_COMMON | \
298 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
299 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
300 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
301#define CPU_FTRS_7450_21 (CPU_FTR_COMMON | \
302 CPU_FTR_USE_TB | \
303 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
304 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
305 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
306 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
307#define CPU_FTRS_7450_23 (CPU_FTR_COMMON | \
308 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
309 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
310 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
311 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
312#define CPU_FTRS_7455_1 (CPU_FTR_COMMON | \
313 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
314 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \
315 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS | \
316 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
317#define CPU_FTRS_7455_20 (CPU_FTR_COMMON | \
318 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
319 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
320 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
321 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
322 CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE)
323#define CPU_FTRS_7455 (CPU_FTR_COMMON | \
324 CPU_FTR_USE_TB | \
325 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
326 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
327 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
328 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
329#define CPU_FTRS_7447_10 (CPU_FTR_COMMON | \
330 CPU_FTR_USE_TB | \
331 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
332 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
333 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
334 CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE | \
335 CPU_FTR_NEED_PAIRED_STWCX)
336#define CPU_FTRS_7447 (CPU_FTR_COMMON | \
337 CPU_FTR_USE_TB | \
338 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
339 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
340 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
341 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
342#define CPU_FTRS_7447A (CPU_FTR_COMMON | \
343 CPU_FTR_USE_TB | \
344 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
345 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
346 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
347 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
348#define CPU_FTRS_7448 (CPU_FTR_COMMON | \
349 CPU_FTR_USE_TB | \
350 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
351 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
352 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
353 CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
354#define CPU_FTRS_82XX (CPU_FTR_COMMON | \
355 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB)
356#define CPU_FTRS_G2_LE (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \
357 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS)
358#define CPU_FTRS_E300 (CPU_FTR_MAYBE_CAN_DOZE | \
359 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \
360 CPU_FTR_COMMON)
361#define CPU_FTRS_E300C2 (CPU_FTR_MAYBE_CAN_DOZE | \
362 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \
363 CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE)
364#define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON | \
365 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE)
366#define CPU_FTRS_8XX (CPU_FTR_USE_TB)
367#define CPU_FTRS_40X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN)
368#define CPU_FTRS_44X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN)
369#define CPU_FTRS_E200 (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \
370 CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \
371 CPU_FTR_UNIFIED_ID_CACHE)
372#define CPU_FTRS_E500 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
373 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN)
374#define CPU_FTRS_E500_2 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
375 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_BIG_PHYS | \
376 CPU_FTR_NODSISRALIGN)
377#define CPU_FTRS_E500MC (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
378 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_BIG_PHYS | CPU_FTR_NODSISRALIGN | \
379 CPU_FTR_L2CSR | CPU_FTR_LWSYNC)
380#define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
381
382/* 64-bit CPUs */
383#define CPU_FTRS_POWER3 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
384 CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | CPU_FTR_PPC_LE)
385#define CPU_FTRS_RS64 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
386 CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | \
387 CPU_FTR_MMCRA | CPU_FTR_CTRL)
388#define CPU_FTRS_POWER4 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
389 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
390 CPU_FTR_MMCRA)
391#define CPU_FTRS_PPC970 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
392 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
393 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA)
394#define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
395 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
396 CPU_FTR_MMCRA | CPU_FTR_SMT | \
397 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
398 CPU_FTR_PURR)
399#define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
400 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
401 CPU_FTR_MMCRA | CPU_FTR_SMT | \
402 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
403 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
404 CPU_FTR_DSCR)
405#define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
406 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
407 CPU_FTR_MMCRA | CPU_FTR_SMT | \
408 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
409 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
410 CPU_FTR_DSCR | CPU_FTR_SAO)
411#define CPU_FTRS_CELL (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
412 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
413 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
414 CPU_FTR_PAUSE_ZERO | CPU_FTR_CI_LARGE_PAGE | CPU_FTR_CELL_TB_BUG)
415#define CPU_FTRS_PA6T (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
416 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \
417 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CI_LARGE_PAGE | \
418 CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_NO_SLBIE_B)
419#define CPU_FTRS_COMPATIBLE (CPU_FTR_USE_TB | \
420 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2)
421
422#ifdef __powerpc64__
423#define CPU_FTRS_POSSIBLE \
424 (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 | \
425 CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 | \
426 CPU_FTRS_POWER7 | CPU_FTRS_CELL | CPU_FTRS_PA6T | \
427 CPU_FTR_1T_SEGMENT | CPU_FTR_VSX)
428#else
429enum {
430 CPU_FTRS_POSSIBLE =
431#if CLASSIC_PPC
432 CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
433 CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
434 CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
435 CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
436 CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
437 CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
438 CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
439 CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_E300C2 |
440 CPU_FTRS_CLASSIC32 |
441#else
442 CPU_FTRS_GENERIC_32 |
443#endif
444#ifdef CONFIG_8xx
445 CPU_FTRS_8XX |
446#endif
447#ifdef CONFIG_40x
448 CPU_FTRS_40X |
449#endif
450#ifdef CONFIG_44x
451 CPU_FTRS_44X |
452#endif
453#ifdef CONFIG_E200
454 CPU_FTRS_E200 |
455#endif
456#ifdef CONFIG_E500
457 CPU_FTRS_E500 | CPU_FTRS_E500_2 | CPU_FTRS_E500MC |
458#endif
459 0,
460};
461#endif /* __powerpc64__ */
462
463#ifdef __powerpc64__
464#define CPU_FTRS_ALWAYS \
465 (CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 & \
466 CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_POWER6 & \
467 CPU_FTRS_POWER7 & CPU_FTRS_CELL & CPU_FTRS_PA6T & CPU_FTRS_POSSIBLE)
468#else
469enum {
470 CPU_FTRS_ALWAYS =
471#if CLASSIC_PPC
472 CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
473 CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
474 CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
475 CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
476 CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
477 CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
478 CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
479 CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 &
480 CPU_FTRS_CLASSIC32 &
481#else
482 CPU_FTRS_GENERIC_32 &
483#endif
484#ifdef CONFIG_8xx
485 CPU_FTRS_8XX &
486#endif
487#ifdef CONFIG_40x
488 CPU_FTRS_40X &
489#endif
490#ifdef CONFIG_44x
491 CPU_FTRS_44X &
492#endif
493#ifdef CONFIG_E200
494 CPU_FTRS_E200 &
495#endif
496#ifdef CONFIG_E500
497 CPU_FTRS_E500 & CPU_FTRS_E500_2 & CPU_FTRS_E500MC &
498#endif
499 CPU_FTRS_POSSIBLE,
500};
501#endif /* __powerpc64__ */
502
503static inline int cpu_has_feature(unsigned long feature)
504{
505 return (CPU_FTRS_ALWAYS & feature) ||
506 (CPU_FTRS_POSSIBLE
507 & cur_cpu_spec->cpu_features
508 & feature);
509}
510
511#endif /* !__ASSEMBLY__ */
512
513#endif /* __KERNEL__ */
514#endif /* __ASM_POWERPC_CPUTABLE_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-10 23:21:08 -0500