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-rw-r--r--arch/powerpc/boot/dts/mpc8610_hpcd.dts32
1 files changed, 32 insertions, 0 deletions
diff --git a/arch/powerpc/boot/dts/mpc8610_hpcd.dts b/arch/powerpc/boot/dts/mpc8610_hpcd.dts
index cfc2c60d1f5f..f468d215f716 100644
--- a/arch/powerpc/boot/dts/mpc8610_hpcd.dts
+++ b/arch/powerpc/boot/dts/mpc8610_hpcd.dts
@@ -100,8 +100,18 @@
100 }; 100 };
101 101
102 board-control@3,0 { 102 board-control@3,0 {
103 #address-cells = <1>;
104 #size-cells = <1>;
103 compatible = "fsl,fpga-pixis"; 105 compatible = "fsl,fpga-pixis";
104 reg = <3 0 0x20>; 106 reg = <3 0 0x20>;
107 ranges = <0 3 0 0x20>;
108
109 sdcsr_pio: gpio-controller@a {
110 #gpio-cells = <2>;
111 compatible = "fsl,fpga-pixis-gpio-bank";
112 reg = <0xa 1>;
113 gpio-controller;
114 };
105 }; 115 };
106 }; 116 };
107 117
@@ -176,6 +186,28 @@
176 interrupt-parent = <&mpic>; 186 interrupt-parent = <&mpic>;
177 }; 187 };
178 188
189 spi@7000 {
190 #address-cells = <1>;
191 #size-cells = <0>;
192 compatible = "fsl,mpc8610-spi", "fsl,spi";
193 reg = <0x7000 0x40>;
194 cell-index = <0>;
195 interrupts = <59 2>;
196 interrupt-parent = <&mpic>;
197 mode = "cpu";
198 gpios = <&sdcsr_pio 7 0>;
199
200 mmc-slot@0 {
201 compatible = "fsl,mpc8610hpcd-mmc-slot",
202 "mmc-spi-slot";
203 reg = <0>;
204 gpios = <&sdcsr_pio 0 1 /* nCD */
205 &sdcsr_pio 1 0>; /* WP */
206 voltage-ranges = <3300 3300>;
207 spi-max-frequency = <50000000>;
208 };
209 };
210
179 display@2c000 { 211 display@2c000 {
180 compatible = "fsl,diu"; 212 compatible = "fsl,diu";
181 reg = <0x2c000 100>; 213 reg = <0x2c000 100>;