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-rw-r--r--arch/powerpc/boot/Makefile5
-rw-r--r--arch/powerpc/boot/dts/iss4xx-mpic.dts155
-rw-r--r--arch/powerpc/boot/dts/iss4xx.dts116
-rw-r--r--arch/powerpc/boot/treeboot-iss4xx.c56
-rwxr-xr-xarch/powerpc/boot/wrapper3
5 files changed, 334 insertions, 1 deletions
diff --git a/arch/powerpc/boot/Makefile b/arch/powerpc/boot/Makefile
index 25e889c0c06e..ad0df7d0a643 100644
--- a/arch/powerpc/boot/Makefile
+++ b/arch/powerpc/boot/Makefile
@@ -44,6 +44,7 @@ $(obj)/cuboot-taishan.o: BOOTCFLAGS += -mcpu=405
44$(obj)/cuboot-katmai.o: BOOTCFLAGS += -mcpu=405 44$(obj)/cuboot-katmai.o: BOOTCFLAGS += -mcpu=405
45$(obj)/cuboot-acadia.o: BOOTCFLAGS += -mcpu=405 45$(obj)/cuboot-acadia.o: BOOTCFLAGS += -mcpu=405
46$(obj)/treeboot-walnut.o: BOOTCFLAGS += -mcpu=405 46$(obj)/treeboot-walnut.o: BOOTCFLAGS += -mcpu=405
47$(obj)/treeboot-iss4xx.o: BOOTCFLAGS += -mcpu=405
47$(obj)/virtex405-head.o: BOOTAFLAGS += -mcpu=405 48$(obj)/virtex405-head.o: BOOTAFLAGS += -mcpu=405
48 49
49 50
@@ -77,7 +78,7 @@ src-plat := of.c cuboot-52xx.c cuboot-824x.c cuboot-83xx.c cuboot-85xx.c holly.c
77 cuboot-warp.c cuboot-85xx-cpm2.c cuboot-yosemite.c simpleboot.c \ 78 cuboot-warp.c cuboot-85xx-cpm2.c cuboot-yosemite.c simpleboot.c \
78 virtex405-head.S virtex.c redboot-83xx.c cuboot-sam440ep.c \ 79 virtex405-head.S virtex.c redboot-83xx.c cuboot-sam440ep.c \
79 cuboot-acadia.c cuboot-amigaone.c cuboot-kilauea.c \ 80 cuboot-acadia.c cuboot-amigaone.c cuboot-kilauea.c \
80 gamecube-head.S gamecube.c wii-head.S wii.c 81 gamecube-head.S gamecube.c wii-head.S wii.c treeboot-iss4xx.c
81src-boot := $(src-wlib) $(src-plat) empty.c 82src-boot := $(src-wlib) $(src-plat) empty.c
82 83
83src-boot := $(addprefix $(obj)/, $(src-boot)) 84src-boot := $(addprefix $(obj)/, $(src-boot))
@@ -206,6 +207,8 @@ image-$(CONFIG_TAISHAN) += cuImage.taishan
206image-$(CONFIG_KATMAI) += cuImage.katmai 207image-$(CONFIG_KATMAI) += cuImage.katmai
207image-$(CONFIG_WARP) += cuImage.warp 208image-$(CONFIG_WARP) += cuImage.warp
208image-$(CONFIG_YOSEMITE) += cuImage.yosemite 209image-$(CONFIG_YOSEMITE) += cuImage.yosemite
210image-$(CONFIG_ISS4xx) += treeImage.iss4xx \
211 treeImage.iss4xx-mpic
209 212
210# Board ports in arch/powerpc/platform/8xx/Kconfig 213# Board ports in arch/powerpc/platform/8xx/Kconfig
211image-$(CONFIG_MPC86XADS) += cuImage.mpc866ads 214image-$(CONFIG_MPC86XADS) += cuImage.mpc866ads
diff --git a/arch/powerpc/boot/dts/iss4xx-mpic.dts b/arch/powerpc/boot/dts/iss4xx-mpic.dts
new file mode 100644
index 000000000000..23e9d9b7e400
--- /dev/null
+++ b/arch/powerpc/boot/dts/iss4xx-mpic.dts
@@ -0,0 +1,155 @@
1/*
2 * Device Tree Source for IBM Embedded PPC 476 Platform
3 *
4 * Copyright 2010 Torez Smith, IBM Corporation.
5 *
6 * Based on earlier code:
7 * Copyright (c) 2006, 2007 IBM Corp.
8 * Josh Boyer <jwboyer@linux.vnet.ibm.com>, David Gibson <dwg@au1.ibm.com>
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without
12 * any warranty of any kind, whether express or implied.
13 */
14
15/dts-v1/;
16
17/memreserve/ 0x01f00000 0x00100000;
18
19/ {
20 #address-cells = <2>;
21 #size-cells = <1>;
22 model = "ibm,iss-4xx";
23 compatible = "ibm,iss-4xx";
24 dcr-parent = <&{/cpus/cpu@0}>;
25
26 aliases {
27 serial0 = &UART0;
28 };
29
30 cpus {
31 #address-cells = <1>;
32 #size-cells = <0>;
33
34 cpu@0 {
35 device_type = "cpu";
36 model = "PowerPC,4xx"; // real CPU changed in sim
37 reg = <0>;
38 clock-frequency = <100000000>; // 100Mhz :-)
39 timebase-frequency = <100000000>;
40 i-cache-line-size = <32>;
41 d-cache-line-size = <32>;
42 i-cache-size = <32768>;
43 d-cache-size = <32768>;
44 dcr-controller;
45 dcr-access-method = "native";
46 status = "ok";
47 };
48 cpu@1 {
49 device_type = "cpu";
50 model = "PowerPC,4xx"; // real CPU changed in sim
51 reg = <1>;
52 clock-frequency = <100000000>; // 100Mhz :-)
53 timebase-frequency = <100000000>;
54 i-cache-line-size = <32>;
55 d-cache-line-size = <32>;
56 i-cache-size = <32768>;
57 d-cache-size = <32768>;
58 dcr-controller;
59 dcr-access-method = "native";
60 status = "disabled";
61 enable-method = "spin-table";
62 cpu-release-addr = <0 0x01f00100>;
63 };
64 cpu@2 {
65 device_type = "cpu";
66 model = "PowerPC,4xx"; // real CPU changed in sim
67 reg = <2>;
68 clock-frequency = <100000000>; // 100Mhz :-)
69 timebase-frequency = <100000000>;
70 i-cache-line-size = <32>;
71 d-cache-line-size = <32>;
72 i-cache-size = <32768>;
73 d-cache-size = <32768>;
74 dcr-controller;
75 dcr-access-method = "native";
76 status = "disabled";
77 enable-method = "spin-table";
78 cpu-release-addr = <0 0x01f00200>;
79 };
80 cpu@3 {
81 device_type = "cpu";
82 model = "PowerPC,4xx"; // real CPU changed in sim
83 reg = <3>;
84 clock-frequency = <100000000>; // 100Mhz :-)
85 timebase-frequency = <100000000>;
86 i-cache-line-size = <32>;
87 d-cache-line-size = <32>;
88 i-cache-size = <32768>;
89 d-cache-size = <32768>;
90 dcr-controller;
91 dcr-access-method = "native";
92 status = "disabled";
93 enable-method = "spin-table";
94 cpu-release-addr = <0 0x01f00300>;
95 };
96 };
97
98 memory {
99 device_type = "memory";
100 reg = <0x00000000 0x00000000 0x00000000>; // Filled in by zImage
101
102 };
103
104 MPIC: interrupt-controller {
105 compatible = "chrp,open-pic";
106 interrupt-controller;
107 dcr-reg = <0xffc00000 0x00030000>;
108 #address-cells = <0>;
109 #size-cells = <0>;
110 #interrupt-cells = <2>;
111
112 };
113
114 plb {
115 compatible = "ibm,plb-4xx", "ibm,plb4"; /* Could be PLB6, doesn't matter */
116 #address-cells = <2>;
117 #size-cells = <1>;
118 ranges;
119 clock-frequency = <0>; // Filled in by zImage
120
121 POB0: opb {
122 compatible = "ibm,opb-4xx", "ibm,opb";
123 #address-cells = <1>;
124 #size-cells = <1>;
125 /* Wish there was a nicer way of specifying a full 32-bit
126 range */
127 ranges = <0x00000000 0x00000001 0x00000000 0x80000000
128 0x80000000 0x00000001 0x80000000 0x80000000>;
129 clock-frequency = <0>; // Filled in by zImage
130 UART0: serial@40000200 {
131 device_type = "serial";
132 compatible = "ns16550a";
133 reg = <0x40000200 0x00000008>;
134 virtual-reg = <0xe0000200>;
135 clock-frequency = <11059200>;
136 current-speed = <115200>;
137 interrupt-parent = <&MPIC>;
138 interrupts = <0x0 0x2>;
139 };
140 };
141 };
142
143 nvrtc {
144 compatible = "ds1743-nvram", "ds1743", "rtc-ds1743";
145 reg = <0 0xEF703000 0x2000>;
146 };
147 iss-block {
148 compatible = "ibm,iss-sim-block-device";
149 reg = <0 0xEF701000 0x1000>;
150 };
151
152 chosen {
153 linux,stdout-path = "/plb/opb/serial@40000200";
154 };
155};
diff --git a/arch/powerpc/boot/dts/iss4xx.dts b/arch/powerpc/boot/dts/iss4xx.dts
new file mode 100644
index 000000000000..4ff6555c866d
--- /dev/null
+++ b/arch/powerpc/boot/dts/iss4xx.dts
@@ -0,0 +1,116 @@
1/*
2 * Device Tree Source for IBM Embedded PPC 476 Platform
3 *
4 * Copyright 2010 Torez Smith, IBM Corporation.
5 *
6 * Based on earlier code:
7 * Copyright (c) 2006, 2007 IBM Corp.
8 * Josh Boyer <jwboyer@linux.vnet.ibm.com>, David Gibson <dwg@au1.ibm.com>
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without
12 * any warranty of any kind, whether express or implied.
13 */
14
15/dts-v1/;
16
17/ {
18 #address-cells = <2>;
19 #size-cells = <1>;
20 model = "ibm,iss-4xx";
21 compatible = "ibm,iss-4xx";
22 dcr-parent = <&{/cpus/cpu@0}>;
23
24 aliases {
25 serial0 = &UART0;
26 };
27
28 cpus {
29 #address-cells = <1>;
30 #size-cells = <0>;
31
32 cpu@0 {
33 device_type = "cpu";
34 model = "PowerPC,4xx"; // real CPU changed in sim
35 reg = <0x00000000>;
36 clock-frequency = <100000000>; // 100Mhz :-)
37 timebase-frequency = <100000000>;
38 i-cache-line-size = <32>; // may need fixup in sim
39 d-cache-line-size = <32>; // may need fixup in sim
40 i-cache-size = <32768>; /* may need fixup in sim */
41 d-cache-size = <32768>; /* may need fixup in sim */
42 dcr-controller;
43 dcr-access-method = "native";
44 };
45 };
46
47 memory {
48 device_type = "memory";
49 reg = <0x00000000 0x00000000 0x00000000>; // Filled in by zImage
50 };
51
52 UIC0: interrupt-controller0 {
53 compatible = "ibm,uic-4xx", "ibm,uic";
54 interrupt-controller;
55 cell-index = <0>;
56 dcr-reg = <0x0c0 0x009>;
57 #address-cells = <0>;
58 #size-cells = <0>;
59 #interrupt-cells = <2>;
60
61 };
62
63 UIC1: interrupt-controller1 {
64 compatible = "ibm,uic-4xx", "ibm,uic";
65 interrupt-controller;
66 cell-index = <1>;
67 dcr-reg = <0x0d0 0x009>;
68 #address-cells = <0>;
69 #size-cells = <0>;
70 #interrupt-cells = <2>;
71 interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
72 interrupt-parent = <&UIC0>;
73 };
74
75 plb {
76 compatible = "ibm,plb-4xx", "ibm,plb4"; /* Could be PLB6, doesn't matter */
77 #address-cells = <2>;
78 #size-cells = <1>;
79 ranges;
80 clock-frequency = <0>; // Filled in by zImage
81
82 POB0: opb {
83 compatible = "ibm,opb-4xx", "ibm,opb";
84 #address-cells = <1>;
85 #size-cells = <1>;
86 /* Wish there was a nicer way of specifying a full 32-bit
87 range */
88 ranges = <0x00000000 0x00000001 0x00000000 0x80000000
89 0x80000000 0x00000001 0x80000000 0x80000000>;
90 clock-frequency = <0>; // Filled in by zImage
91 UART0: serial@40000200 {
92 device_type = "serial";
93 compatible = "ns16550a";
94 reg = <0x40000200 0x00000008>;
95 virtual-reg = <0xe0000200>;
96 clock-frequency = <11059200>;
97 current-speed = <115200>;
98 interrupt-parent = <&UIC0>;
99 interrupts = <0x0 0x4>;
100 };
101 };
102 };
103
104 nvrtc {
105 compatible = "ds1743-nvram", "ds1743", "rtc-ds1743";
106 reg = <0 0xEF703000 0x2000>;
107 };
108 iss-block {
109 compatible = "ibm,iss-sim-block-device";
110 reg = <0 0xEF701000 0x1000>;
111 };
112
113 chosen {
114 linux,stdout-path = "/plb/opb/serial@40000200";
115 };
116};
diff --git a/arch/powerpc/boot/treeboot-iss4xx.c b/arch/powerpc/boot/treeboot-iss4xx.c
new file mode 100644
index 000000000000..fcc44952874e
--- /dev/null
+++ b/arch/powerpc/boot/treeboot-iss4xx.c
@@ -0,0 +1,56 @@
1/*
2 * Copyright 2010 Ben. Herrenschmidt, IBM Corporation.
3 *
4 * Based on earlier code:
5 * Copyright (C) Paul Mackerras 1997.
6 *
7 * Matt Porter <mporter@kernel.crashing.org>
8 * Copyright 2002-2005 MontaVista Software Inc.
9 *
10 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
11 * Copyright (c) 2003, 2004 Zultys Technologies
12 *
13 * Copyright 2007 David Gibson, IBM Corporation.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
19 */
20#include <stdarg.h>
21#include <stddef.h>
22#include "types.h"
23#include "elf.h"
24#include "string.h"
25#include "stdio.h"
26#include "page.h"
27#include "ops.h"
28#include "reg.h"
29#include "io.h"
30#include "dcr.h"
31#include "4xx.h"
32#include "44x.h"
33#include "libfdt.h"
34
35BSS_STACK(4096);
36
37static void iss_4xx_fixups(void)
38{
39 ibm4xx_sdram_fixup_memsize();
40}
41
42#define SPRN_PIR 0x11E /* Processor Indentification Register */
43void platform_init(void)
44{
45 unsigned long end_of_ram = 0x08000000;
46 unsigned long avail_ram = end_of_ram - (unsigned long)_end;
47 u32 pir_reg;
48
49 simple_alloc_init(_end, avail_ram, 128, 64);
50 platform_ops.fixups = iss_4xx_fixups;
51 platform_ops.exit = ibm44x_dbcr_reset;
52 pir_reg = mfspr(SPRN_PIR);
53 fdt_set_boot_cpuid_phys(_dtb_start, pir_reg);
54 fdt_init(_dtb_start);
55 serial_console_init();
56}
diff --git a/arch/powerpc/boot/wrapper b/arch/powerpc/boot/wrapper
index 7160b3b1fb35..cb97e7511d7e 100755
--- a/arch/powerpc/boot/wrapper
+++ b/arch/powerpc/boot/wrapper
@@ -241,6 +241,9 @@ gamecube|wii)
241 link_address='0x600000' 241 link_address='0x600000'
242 platformo="$object/$platform-head.o $object/$platform.o" 242 platformo="$object/$platform-head.o $object/$platform.o"
243 ;; 243 ;;
244treeboot-iss4xx-mpic)
245 platformo="$object/treeboot-iss4xx.o"
246 ;;
244esac 247esac
245 248
246vmz="$tmpdir/`basename \"$kernel\"`.$ext" 249vmz="$tmpdir/`basename \"$kernel\"`.$ext"
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-12 00:19:11 -0500