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-rw-r--r--arch/powerpc/boot/dts/sbc8548.dts244
1 files changed, 244 insertions, 0 deletions
diff --git a/arch/powerpc/boot/dts/sbc8548.dts b/arch/powerpc/boot/dts/sbc8548.dts
new file mode 100644
index 000000000000..14be38ad5d4b
--- /dev/null
+++ b/arch/powerpc/boot/dts/sbc8548.dts
@@ -0,0 +1,244 @@
1/*
2 * SBC8548 Device Tree Source
3 *
4 * Copyright 2007 Wind River Systems Inc.
5 *
6 * Paul Gortmaker (see MAINTAINERS for contact information)
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14
15/dts-v1/;
16
17/ {
18 model = "SBC8548";
19 compatible = "SBC8548";
20 #address-cells = <1>;
21 #size-cells = <1>;
22
23 aliases {
24 ethernet0 = &enet0;
25 ethernet1 = &enet1;
26 serial0 = &serial0;
27 serial1 = &serial1;
28 pci0 = &pci0;
29 /* pci1 doesn't have a corresponding physical connector */
30 pci2 = &pci2;
31 };
32
33 cpus {
34 #address-cells = <1>;
35 #size-cells = <0>;
36
37 PowerPC,8548@0 {
38 device_type = "cpu";
39 reg = <0>;
40 d-cache-line-size = <0x20>; // 32 bytes
41 i-cache-line-size = <0x20>; // 32 bytes
42 d-cache-size = <0x8000>; // L1, 32K
43 i-cache-size = <0x8000>; // L1, 32K
44 timebase-frequency = <0>; // From uboot
45 bus-frequency = <0>;
46 clock-frequency = <0>;
47 };
48 };
49
50 memory {
51 device_type = "memory";
52 reg = <0x00000000 0x10000000>;
53 };
54
55 soc8548@e0000000 {
56 #address-cells = <1>;
57 #size-cells = <1>;
58 device_type = "soc";
59 ranges = <0x00000000 0xe0000000 0x00100000>;
60 reg = <0xe0000000 0x00001000>; // CCSRBAR
61 bus-frequency = <0>;
62
63 memory-controller@2000 {
64 compatible = "fsl,8548-memory-controller";
65 reg = <0x2000 0x1000>;
66 interrupt-parent = <&mpic>;
67 interrupts = <0x12 0x2>;
68 };
69
70 l2-cache-controller@20000 {
71 compatible = "fsl,8548-l2-cache-controller";
72 reg = <0x20000 0x1000>;
73 cache-line-size = <0x20>; // 32 bytes
74 cache-size = <0x80000>; // L2, 512K
75 interrupt-parent = <&mpic>;
76 interrupts = <0x10 0x2>;
77 };
78
79 i2c@3000 {
80 #address-cells = <1>;
81 #size-cells = <0>;
82 cell-index = <0>;
83 compatible = "fsl-i2c";
84 reg = <0x3000 0x100>;
85 interrupts = <0x2b 0x2>;
86 interrupt-parent = <&mpic>;
87 dfsrr;
88 };
89
90 i2c@3100 {
91 #address-cells = <1>;
92 #size-cells = <0>;
93 cell-index = <1>;
94 compatible = "fsl-i2c";
95 reg = <0x3100 0x100>;
96 interrupts = <0x2b 0x2>;
97 interrupt-parent = <&mpic>;
98 dfsrr;
99 };
100
101 mdio@24520 {
102 #address-cells = <1>;
103 #size-cells = <0>;
104 compatible = "fsl,gianfar-mdio";
105 reg = <0x24520 0x20>;
106
107 phy0: ethernet-phy@19 {
108 interrupt-parent = <&mpic>;
109 interrupts = <0x6 0x1>;
110 reg = <0x19>;
111 device_type = "ethernet-phy";
112 };
113 phy1: ethernet-phy@1a {
114 interrupt-parent = <&mpic>;
115 interrupts = <0x7 0x1>;
116 reg = <0x1a>;
117 device_type = "ethernet-phy";
118 };
119 };
120
121 enet0: ethernet@24000 {
122 cell-index = <0>;
123 device_type = "network";
124 model = "eTSEC";
125 compatible = "gianfar";
126 reg = <0x24000 0x1000>;
127 local-mac-address = [ 00 00 00 00 00 00 ];
128 interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>;
129 interrupt-parent = <&mpic>;
130 phy-handle = <&phy0>;
131 };
132
133 enet1: ethernet@25000 {
134 cell-index = <1>;
135 device_type = "network";
136 model = "eTSEC";
137 compatible = "gianfar";
138 reg = <0x25000 0x1000>;
139 local-mac-address = [ 00 00 00 00 00 00 ];
140 interrupts = <0x23 0x2 0x24 0x2 0x28 0x2>;
141 interrupt-parent = <&mpic>;
142 phy-handle = <&phy1>;
143 };
144
145 serial0: serial@4500 {
146 cell-index = <0>;
147 device_type = "serial";
148 compatible = "ns16550";
149 reg = <0x4500 0x100>; // reg base, size
150 clock-frequency = <0>; // should we fill in in uboot?
151 interrupts = <0x2a 0x2>;
152 interrupt-parent = <&mpic>;
153 };
154
155 serial1: serial@4600 {
156 cell-index = <1>;
157 device_type = "serial";
158 compatible = "ns16550";
159 reg = <0x4600 0x100>; // reg base, size
160 clock-frequency = <0>; // should we fill in in uboot?
161 interrupts = <0x2a 0x2>;
162 interrupt-parent = <&mpic>;
163 };
164
165 global-utilities@e0000 { //global utilities reg
166 compatible = "fsl,mpc8548-guts";
167 reg = <0xe0000 0x1000>;
168 fsl,has-rstcr;
169 };
170
171 mpic: pic@40000 {
172 interrupt-controller;
173 #address-cells = <0>;
174 #size-cells = <0>;
175 #interrupt-cells = <2>;
176 reg = <0x40000 0x40000>;
177 compatible = "chrp,open-pic";
178 device_type = "open-pic";
179 big-endian;
180 };
181 };
182
183 pci0: pci@e0008000 {
184 cell-index = <0>;
185 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
186 interrupt-map = <
187 /* IDSEL 0x01 (PCI-X slot) */
188 0x0800 0x0 0x0 0x1 &mpic 0x0 0x1
189 0x0800 0x0 0x0 0x2 &mpic 0x1 0x1
190 0x0800 0x0 0x0 0x3 &mpic 0x2 0x1
191 0x0800 0x0 0x0 0x4 &mpic 0x3 0x1>;
192
193 interrupt-parent = <&mpic>;
194 interrupts = <0x18 0x2>;
195 bus-range = <0 0>;
196 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x10000000
197 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00800000>;
198 clock-frequency = <66666666>;
199 #interrupt-cells = <1>;
200 #size-cells = <2>;
201 #address-cells = <3>;
202 reg = <0xe0008000 0x1000>;
203 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
204 device_type = "pci";
205 };
206
207 pci2: pcie@e000a000 {
208 cell-index = <2>;
209 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
210 interrupt-map = <
211
212 /* IDSEL 0x0 (PEX) */
213 0x0000 0x0 0x0 0x1 &mpic 0x0 0x1
214 0x0000 0x0 0x0 0x2 &mpic 0x1 0x1
215 0x0000 0x0 0x0 0x3 &mpic 0x2 0x1
216 0x0000 0x0 0x0 0x4 &mpic 0x3 0x1>;
217
218 interrupt-parent = <&mpic>;
219 interrupts = <0x1a 0x2>;
220 bus-range = <0x0 0xff>;
221 ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
222 0x01000000 0x0 0x00000000 0xe3000000 0x0 0x08000000>;
223 clock-frequency = <33333333>;
224 #interrupt-cells = <1>;
225 #size-cells = <2>;
226 #address-cells = <3>;
227 reg = <0xe000a000 0x1000>;
228 compatible = "fsl,mpc8548-pcie";
229 device_type = "pci";
230 pcie@0 {
231 reg = <0x0 0x0 0x0 0x0 0x0>;
232 #size-cells = <2>;
233 #address-cells = <3>;
234 device_type = "pci";
235 ranges = <0x02000000 0x0 0xa0000000
236 0x02000000 0x0 0xa0000000
237 0x0 0x20000000
238
239 0x01000000 0x0 0x00000000
240 0x01000000 0x0 0x00000000
241 0x0 0x08000000>;
242 };
243 };
244};
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-29 06:18:59 -0500