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-rw-r--r--arch/powerpc/boot/4xx.c142
-rw-r--r--arch/powerpc/boot/4xx.h1
-rw-r--r--arch/powerpc/boot/Makefile6
-rw-r--r--arch/powerpc/boot/cuboot-hotfoot.c142
-rw-r--r--arch/powerpc/boot/cuboot-kilauea.c49
-rw-r--r--arch/powerpc/boot/dcr.h4
-rw-r--r--arch/powerpc/boot/dts/arches.dts50
-rw-r--r--arch/powerpc/boot/dts/canyonlands.dts49
-rw-r--r--arch/powerpc/boot/dts/eiger.dts421
-rw-r--r--arch/powerpc/boot/dts/gef_sbc310.dts64
-rw-r--r--arch/powerpc/boot/dts/hotfoot.dts294
-rw-r--r--arch/powerpc/boot/dts/kilauea.dts44
-rw-r--r--arch/powerpc/boot/dts/mgcoge.dts53
-rw-r--r--arch/powerpc/boot/dts/mpc8272ads.dts8
-rw-r--r--arch/powerpc/boot/dts/mpc8377_rdb.dts2
-rw-r--r--arch/powerpc/boot/dts/mpc8377_wlan.dts464
-rw-r--r--arch/powerpc/boot/dts/mpc8378_rdb.dts2
-rw-r--r--arch/powerpc/boot/dts/mpc8379_rdb.dts2
-rw-r--r--arch/powerpc/boot/dts/mpc8536ds.dts40
-rw-r--r--arch/powerpc/boot/dts/mpc8536ds_36b.dts475
-rw-r--r--arch/powerpc/boot/dts/mpc8548cds.dts20
-rw-r--r--arch/powerpc/boot/dts/mpc8569mds.dts45
-rw-r--r--arch/powerpc/boot/dts/p2020rdb.dts586
-rw-r--r--arch/powerpc/boot/dts/sbc8349.dts60
-rw-r--r--arch/powerpc/boot/dts/sbc8560.dts1
-rw-r--r--arch/powerpc/boot/mktree.c10
-rw-r--r--arch/powerpc/boot/ppcboot-hotfoot.h133
-rwxr-xr-xarch/powerpc/boot/wrapper3
28 files changed, 3092 insertions, 78 deletions
diff --git a/arch/powerpc/boot/4xx.c b/arch/powerpc/boot/4xx.c
index 325b310573b9..27db8938827a 100644
--- a/arch/powerpc/boot/4xx.c
+++ b/arch/powerpc/boot/4xx.c
@@ -8,6 +8,10 @@
8 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net> 8 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
9 * Copyright (c) 2003, 2004 Zultys Technologies 9 * Copyright (c) 2003, 2004 Zultys Technologies
10 * 10 *
11 * Copyright (C) 2009 Wind River Systems, Inc.
12 * Updated for supporting PPC405EX on Kilauea.
13 * Tiejun Chen <tiejun.chen@windriver.com>
14 *
11 * This program is free software; you can redistribute it and/or 15 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License 16 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version 17 * as published by the Free Software Foundation; either version
@@ -659,3 +663,141 @@ void ibm405ep_fixup_clocks(unsigned int sys_clk)
659 dt_fixup_clock("/plb/opb/serial@ef600300", uart0); 663 dt_fixup_clock("/plb/opb/serial@ef600300", uart0);
660 dt_fixup_clock("/plb/opb/serial@ef600400", uart1); 664 dt_fixup_clock("/plb/opb/serial@ef600400", uart1);
661} 665}
666
667static u8 ibm405ex_fwdv_multi_bits[] = {
668 /* values for: 1 - 16 */
669 0x01, 0x02, 0x0e, 0x09, 0x04, 0x0b, 0x10, 0x0d, 0x0c, 0x05,
670 0x06, 0x0f, 0x0a, 0x07, 0x08, 0x03
671};
672
673u32 ibm405ex_get_fwdva(unsigned long cpr_fwdv)
674{
675 u32 index;
676
677 for (index = 0; index < ARRAY_SIZE(ibm405ex_fwdv_multi_bits); index++)
678 if (cpr_fwdv == (u32)ibm405ex_fwdv_multi_bits[index])
679 return index + 1;
680
681 return 0;
682}
683
684static u8 ibm405ex_fbdv_multi_bits[] = {
685 /* values for: 1 - 100 */
686 0x00, 0xff, 0x7e, 0xfd, 0x7a, 0xf5, 0x6a, 0xd5, 0x2a, 0xd4,
687 0x29, 0xd3, 0x26, 0xcc, 0x19, 0xb3, 0x67, 0xce, 0x1d, 0xbb,
688 0x77, 0xee, 0x5d, 0xba, 0x74, 0xe9, 0x52, 0xa5, 0x4b, 0x96,
689 0x2c, 0xd8, 0x31, 0xe3, 0x46, 0x8d, 0x1b, 0xb7, 0x6f, 0xde,
690 0x3d, 0xfb, 0x76, 0xed, 0x5a, 0xb5, 0x6b, 0xd6, 0x2d, 0xdb,
691 0x36, 0xec, 0x59, 0xb2, 0x64, 0xc9, 0x12, 0xa4, 0x48, 0x91,
692 0x23, 0xc7, 0x0e, 0x9c, 0x38, 0xf0, 0x61, 0xc2, 0x05, 0x8b,
693 0x17, 0xaf, 0x5f, 0xbe, 0x7c, 0xf9, 0x72, 0xe5, 0x4a, 0x95,
694 0x2b, 0xd7, 0x2e, 0xdc, 0x39, 0xf3, 0x66, 0xcd, 0x1a, 0xb4,
695 0x68, 0xd1, 0x22, 0xc4, 0x09, 0x93, 0x27, 0xcf, 0x1e, 0xbc,
696 /* values for: 101 - 200 */
697 0x78, 0xf1, 0x62, 0xc5, 0x0a, 0x94, 0x28, 0xd0, 0x21, 0xc3,
698 0x06, 0x8c, 0x18, 0xb0, 0x60, 0xc1, 0x02, 0x84, 0x08, 0x90,
699 0x20, 0xc0, 0x01, 0x83, 0x07, 0x8f, 0x1f, 0xbf, 0x7f, 0xfe,
700 0x7d, 0xfa, 0x75, 0xea, 0x55, 0xaa, 0x54, 0xa9, 0x53, 0xa6,
701 0x4c, 0x99, 0x33, 0xe7, 0x4e, 0x9d, 0x3b, 0xf7, 0x6e, 0xdd,
702 0x3a, 0xf4, 0x69, 0xd2, 0x25, 0xcb, 0x16, 0xac, 0x58, 0xb1,
703 0x63, 0xc6, 0x0d, 0x9b, 0x37, 0xef, 0x5e, 0xbd, 0x7b, 0xf6,
704 0x6d, 0xda, 0x35, 0xeb, 0x56, 0xad, 0x5b, 0xb6, 0x6c, 0xd9,
705 0x32, 0xe4, 0x49, 0x92, 0x24, 0xc8, 0x11, 0xa3, 0x47, 0x8e,
706 0x1c, 0xb8, 0x70, 0xe1, 0x42, 0x85, 0x0b, 0x97, 0x2f, 0xdf,
707 /* values for: 201 - 255 */
708 0x3e, 0xfc, 0x79, 0xf2, 0x65, 0xca, 0x15, 0xab, 0x57, 0xae,
709 0x5c, 0xb9, 0x73, 0xe6, 0x4d, 0x9a, 0x34, 0xe8, 0x51, 0xa2,
710 0x44, 0x89, 0x13, 0xa7, 0x4f, 0x9e, 0x3c, 0xf8, 0x71, 0xe2,
711 0x45, 0x8a, 0x14, 0xa8, 0x50, 0xa1, 0x43, 0x86, 0x0c, 0x98,
712 0x30, 0xe0, 0x41, 0x82, 0x04, 0x88, 0x10, 0xa0, 0x40, 0x81,
713 0x03, 0x87, 0x0f, 0x9f, 0x3f /* END */
714};
715
716u32 ibm405ex_get_fbdv(unsigned long cpr_fbdv)
717{
718 u32 index;
719
720 for (index = 0; index < ARRAY_SIZE(ibm405ex_fbdv_multi_bits); index++)
721 if (cpr_fbdv == (u32)ibm405ex_fbdv_multi_bits[index])
722 return index + 1;
723
724 return 0;
725}
726
727void ibm405ex_fixup_clocks(unsigned int sys_clk, unsigned int uart_clk)
728{
729 /* PLL config */
730 u32 pllc = CPR0_READ(DCRN_CPR0_PLLC);
731 u32 plld = CPR0_READ(DCRN_CPR0_PLLD);
732 u32 cpud = CPR0_READ(DCRN_CPR0_PRIMAD);
733 u32 plbd = CPR0_READ(DCRN_CPR0_PRIMBD);
734 u32 opbd = CPR0_READ(DCRN_CPR0_OPBD);
735 u32 perd = CPR0_READ(DCRN_CPR0_PERD);
736
737 /* Dividers */
738 u32 fbdv = ibm405ex_get_fbdv(__fix_zero((plld >> 24) & 0xff, 1));
739
740 u32 fwdva = ibm405ex_get_fwdva(__fix_zero((plld >> 16) & 0x0f, 1));
741
742 u32 cpudv0 = __fix_zero((cpud >> 24) & 7, 8);
743
744 /* PLBDV0 is hardwared to 010. */
745 u32 plbdv0 = 2;
746 u32 plb2xdv0 = __fix_zero((plbd >> 16) & 7, 8);
747
748 u32 opbdv0 = __fix_zero((opbd >> 24) & 3, 4);
749
750 u32 perdv0 = __fix_zero((perd >> 24) & 3, 4);
751
752 /* Resulting clocks */
753 u32 cpu, plb, opb, ebc, vco, tb, uart0, uart1;
754
755 /* PLL's VCO is the source for primary forward ? */
756 if (pllc & 0x40000000) {
757 u32 m;
758
759 /* Feedback path */
760 switch ((pllc >> 24) & 7) {
761 case 0:
762 /* PLLOUTx */
763 m = fbdv;
764 break;
765 case 1:
766 /* CPU */
767 m = fbdv * fwdva * cpudv0;
768 break;
769 case 5:
770 /* PERClk */
771 m = fbdv * fwdva * plb2xdv0 * plbdv0 * opbdv0 * perdv0;
772 break;
773 default:
774 printf("WARNING ! Invalid PLL feedback source !\n");
775 goto bypass;
776 }
777
778 vco = (unsigned int)(sys_clk * m);
779 } else {
780bypass:
781 /* Bypass system PLL */
782 vco = 0;
783 }
784
785 /* CPU = VCO / ( FWDVA x CPUDV0) */
786 cpu = vco / (fwdva * cpudv0);
787 /* PLB = VCO / ( FWDVA x PLB2XDV0 x PLBDV0) */
788 plb = vco / (fwdva * plb2xdv0 * plbdv0);
789 /* OPB = PLB / OPBDV0 */
790 opb = plb / opbdv0;
791 /* EBC = OPB / PERDV0 */
792 ebc = opb / perdv0;
793
794 tb = cpu;
795 uart0 = uart1 = uart_clk;
796
797 dt_fixup_cpu_clocks(cpu, tb, 0);
798 dt_fixup_clock("/plb", plb);
799 dt_fixup_clock("/plb/opb", opb);
800 dt_fixup_clock("/plb/opb/ebc", ebc);
801 dt_fixup_clock("/plb/opb/serial@ef600200", uart0);
802 dt_fixup_clock("/plb/opb/serial@ef600300", uart1);
803}
diff --git a/arch/powerpc/boot/4xx.h b/arch/powerpc/boot/4xx.h
index 2606e64f0c4b..7dc5d45361bc 100644
--- a/arch/powerpc/boot/4xx.h
+++ b/arch/powerpc/boot/4xx.h
@@ -21,6 +21,7 @@ void ibm4xx_fixup_ebc_ranges(const char *ebc);
21 21
22void ibm405gp_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk); 22void ibm405gp_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk);
23void ibm405ep_fixup_clocks(unsigned int sys_clk); 23void ibm405ep_fixup_clocks(unsigned int sys_clk);
24void ibm405ex_fixup_clocks(unsigned int sys_clk, unsigned int uart_clk);
24void ibm440gp_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk); 25void ibm440gp_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk);
25void ibm440ep_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk, 26void ibm440ep_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk,
26 unsigned int tmr_clk); 27 unsigned int tmr_clk);
diff --git a/arch/powerpc/boot/Makefile b/arch/powerpc/boot/Makefile
index 9ae7b7e2ba71..7bfc8ad87798 100644
--- a/arch/powerpc/boot/Makefile
+++ b/arch/powerpc/boot/Makefile
@@ -39,6 +39,7 @@ DTS_FLAGS ?= -p 1024
39 39
40$(obj)/4xx.o: BOOTCFLAGS += -mcpu=405 40$(obj)/4xx.o: BOOTCFLAGS += -mcpu=405
41$(obj)/ebony.o: BOOTCFLAGS += -mcpu=405 41$(obj)/ebony.o: BOOTCFLAGS += -mcpu=405
42$(obj)/cuboot-hotfoot.o: BOOTCFLAGS += -mcpu=405
42$(obj)/cuboot-taishan.o: BOOTCFLAGS += -mcpu=405 43$(obj)/cuboot-taishan.o: BOOTCFLAGS += -mcpu=405
43$(obj)/cuboot-katmai.o: BOOTCFLAGS += -mcpu=405 44$(obj)/cuboot-katmai.o: BOOTCFLAGS += -mcpu=405
44$(obj)/cuboot-acadia.o: BOOTCFLAGS += -mcpu=405 45$(obj)/cuboot-acadia.o: BOOTCFLAGS += -mcpu=405
@@ -67,7 +68,7 @@ src-wlib := string.S crt0.S crtsavres.S stdio.c main.c \
67 cpm-serial.c stdlib.c mpc52xx-psc.c planetcore.c uartlite.c \ 68 cpm-serial.c stdlib.c mpc52xx-psc.c planetcore.c uartlite.c \
68 fsl-soc.c mpc8xx.c pq2.c 69 fsl-soc.c mpc8xx.c pq2.c
69src-plat := of.c cuboot-52xx.c cuboot-824x.c cuboot-83xx.c cuboot-85xx.c holly.c \ 70src-plat := of.c cuboot-52xx.c cuboot-824x.c cuboot-83xx.c cuboot-85xx.c holly.c \
70 cuboot-ebony.c treeboot-ebony.c prpmc2800.c \ 71 cuboot-ebony.c cuboot-hotfoot.c treeboot-ebony.c prpmc2800.c \
71 ps3-head.S ps3-hvcall.S ps3.c treeboot-bamboo.c cuboot-8xx.c \ 72 ps3-head.S ps3-hvcall.S ps3.c treeboot-bamboo.c cuboot-8xx.c \
72 cuboot-pq2.c cuboot-sequoia.c treeboot-walnut.c \ 73 cuboot-pq2.c cuboot-sequoia.c treeboot-walnut.c \
73 cuboot-bamboo.c cuboot-mpc7448hpc2.c cuboot-taishan.c \ 74 cuboot-bamboo.c cuboot-mpc7448hpc2.c cuboot-taishan.c \
@@ -75,7 +76,7 @@ src-plat := of.c cuboot-52xx.c cuboot-824x.c cuboot-83xx.c cuboot-85xx.c holly.c
75 cuboot-katmai.c cuboot-rainier.c redboot-8xx.c ep8248e.c \ 76 cuboot-katmai.c cuboot-rainier.c redboot-8xx.c ep8248e.c \
76 cuboot-warp.c cuboot-85xx-cpm2.c cuboot-yosemite.c simpleboot.c \ 77 cuboot-warp.c cuboot-85xx-cpm2.c cuboot-yosemite.c simpleboot.c \
77 virtex405-head.S virtex.c redboot-83xx.c cuboot-sam440ep.c \ 78 virtex405-head.S virtex.c redboot-83xx.c cuboot-sam440ep.c \
78 cuboot-acadia.c cuboot-amigaone.c 79 cuboot-acadia.c cuboot-amigaone.c cuboot-kilauea.c
79src-boot := $(src-wlib) $(src-plat) empty.c 80src-boot := $(src-wlib) $(src-plat) empty.c
80 81
81src-boot := $(addprefix $(obj)/, $(src-boot)) 82src-boot := $(addprefix $(obj)/, $(src-boot))
@@ -190,6 +191,7 @@ image-$(CONFIG_DEFAULT_UIMAGE) += uImage
190 191
191# Board ports in arch/powerpc/platform/40x/Kconfig 192# Board ports in arch/powerpc/platform/40x/Kconfig
192image-$(CONFIG_EP405) += dtbImage.ep405 193image-$(CONFIG_EP405) += dtbImage.ep405
194image-$(CONFIG_HOTFOOT) += cuImage.hotfoot
193image-$(CONFIG_WALNUT) += treeImage.walnut 195image-$(CONFIG_WALNUT) += treeImage.walnut
194image-$(CONFIG_ACADIA) += cuImage.acadia 196image-$(CONFIG_ACADIA) += cuImage.acadia
195 197
diff --git a/arch/powerpc/boot/cuboot-hotfoot.c b/arch/powerpc/boot/cuboot-hotfoot.c
new file mode 100644
index 000000000000..8f697b958e45
--- /dev/null
+++ b/arch/powerpc/boot/cuboot-hotfoot.c
@@ -0,0 +1,142 @@
1/*
2 * Old U-boot compatibility for Esteem 195E Hotfoot CPU Board
3 *
4 * Author: Solomon Peachy <solomon@linux-wlan.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 */
10
11#include "ops.h"
12#include "stdio.h"
13#include "reg.h"
14#include "dcr.h"
15#include "4xx.h"
16#include "cuboot.h"
17
18#define TARGET_4xx
19#define TARGET_HOTFOOT
20
21#include "ppcboot-hotfoot.h"
22
23static bd_t bd;
24
25#define NUM_REGS 3
26
27static void hotfoot_fixups(void)
28{
29 u32 uart = mfdcr(DCRN_CPC0_UCR) & 0x7f;
30
31 dt_fixup_memory(bd.bi_memstart, bd.bi_memsize);
32
33 dt_fixup_cpu_clocks(bd.bi_procfreq, bd.bi_procfreq, 0);
34 dt_fixup_clock("/plb", bd.bi_plb_busfreq);
35 dt_fixup_clock("/plb/opb", bd.bi_opbfreq);
36 dt_fixup_clock("/plb/ebc", bd.bi_pci_busfreq);
37 dt_fixup_clock("/plb/opb/serial@ef600300", bd.bi_procfreq / uart);
38 dt_fixup_clock("/plb/opb/serial@ef600400", bd.bi_procfreq / uart);
39
40 dt_fixup_mac_address_by_alias("ethernet0", bd.bi_enetaddr);
41 dt_fixup_mac_address_by_alias("ethernet1", bd.bi_enet1addr);
42
43 /* Is this a single eth/serial board? */
44 if ((bd.bi_enet1addr[0] == 0) &&
45 (bd.bi_enet1addr[1] == 0) &&
46 (bd.bi_enet1addr[2] == 0) &&
47 (bd.bi_enet1addr[3] == 0) &&
48 (bd.bi_enet1addr[4] == 0) &&
49 (bd.bi_enet1addr[5] == 0)) {
50 void *devp;
51
52 printf("Trimming devtree for single serial/eth board\n");
53
54 devp = finddevice("/plb/opb/serial@ef600300");
55 if (!devp)
56 fatal("Can't find node for /plb/opb/serial@ef600300");
57 del_node(devp);
58
59 devp = finddevice("/plb/opb/ethernet@ef600900");
60 if (!devp)
61 fatal("Can't find node for /plb/opb/ethernet@ef600900");
62 del_node(devp);
63 }
64
65 ibm4xx_quiesce_eth((u32 *)0xef600800, (u32 *)0xef600900);
66
67 /* Fix up flash size in fdt for 4M boards. */
68 if (bd.bi_flashsize < 0x800000) {
69 u32 regs[NUM_REGS];
70 void *devp = finddevice("/plb/ebc/nor_flash@0");
71 if (!devp)
72 fatal("Can't find FDT node for nor_flash!??");
73
74 printf("Fixing devtree for 4M Flash\n");
75
76 /* First fix up the base addresse */
77 getprop(devp, "reg", regs, sizeof(regs));
78 regs[0] = 0;
79 regs[1] = 0xffc00000;
80 regs[2] = 0x00400000;
81 setprop(devp, "reg", regs, sizeof(regs));
82
83 /* Then the offsets */
84 devp = finddevice("/plb/ebc/nor_flash@0/partition@0");
85 if (!devp)
86 fatal("Can't find FDT node for partition@0");
87 getprop(devp, "reg", regs, 2*sizeof(u32));
88 regs[0] -= 0x400000;
89 setprop(devp, "reg", regs, 2*sizeof(u32));
90
91 devp = finddevice("/plb/ebc/nor_flash@0/partition@1");
92 if (!devp)
93 fatal("Can't find FDT node for partition@1");
94 getprop(devp, "reg", regs, 2*sizeof(u32));
95 regs[0] -= 0x400000;
96 setprop(devp, "reg", regs, 2*sizeof(u32));
97
98 devp = finddevice("/plb/ebc/nor_flash@0/partition@2");
99 if (!devp)
100 fatal("Can't find FDT node for partition@2");
101 getprop(devp, "reg", regs, 2*sizeof(u32));
102 regs[0] -= 0x400000;
103 setprop(devp, "reg", regs, 2*sizeof(u32));
104
105 devp = finddevice("/plb/ebc/nor_flash@0/partition@3");
106 if (!devp)
107 fatal("Can't find FDT node for partition@3");
108 getprop(devp, "reg", regs, 2*sizeof(u32));
109 regs[0] -= 0x400000;
110 setprop(devp, "reg", regs, 2*sizeof(u32));
111
112 devp = finddevice("/plb/ebc/nor_flash@0/partition@4");
113 if (!devp)
114 fatal("Can't find FDT node for partition@4");
115 getprop(devp, "reg", regs, 2*sizeof(u32));
116 regs[0] -= 0x400000;
117 setprop(devp, "reg", regs, 2*sizeof(u32));
118
119 devp = finddevice("/plb/ebc/nor_flash@0/partition@6");
120 if (!devp)
121 fatal("Can't find FDT node for partition@6");
122 getprop(devp, "reg", regs, 2*sizeof(u32));
123 regs[0] -= 0x400000;
124 setprop(devp, "reg", regs, 2*sizeof(u32));
125
126 /* Delete the FeatFS node */
127 devp = finddevice("/plb/ebc/nor_flash@0/partition@5");
128 if (!devp)
129 fatal("Can't find FDT node for partition@5");
130 del_node(devp);
131 }
132}
133
134void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
135 unsigned long r6, unsigned long r7)
136{
137 CUBOOT_INIT();
138 platform_ops.fixups = hotfoot_fixups;
139 platform_ops.exit = ibm40x_dbcr_reset;
140 fdt_init(_dtb_start);
141 serial_console_init();
142}
diff --git a/arch/powerpc/boot/cuboot-kilauea.c b/arch/powerpc/boot/cuboot-kilauea.c
new file mode 100644
index 000000000000..80cdad6bbc3f
--- /dev/null
+++ b/arch/powerpc/boot/cuboot-kilauea.c
@@ -0,0 +1,49 @@
1/*
2 * Old U-boot compatibility for PPC405EX. This image is already included
3 * a dtb.
4 *
5 * Author: Tiejun Chen <tiejun.chen@windriver.com>
6 *
7 * Copyright (C) 2009 Wind River Systems, Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14#include "ops.h"
15#include "io.h"
16#include "dcr.h"
17#include "stdio.h"
18#include "4xx.h"
19#include "44x.h"
20#include "cuboot.h"
21
22#define TARGET_4xx
23#define TARGET_44x
24#include "ppcboot.h"
25
26#define KILAUEA_SYS_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */
27
28static bd_t bd;
29
30static void kilauea_fixups(void)
31{
32 unsigned long sysclk = 33333333;
33
34 ibm405ex_fixup_clocks(sysclk, KILAUEA_SYS_EXT_SERIAL_CLOCK);
35 dt_fixup_memory(bd.bi_memstart, bd.bi_memsize);
36 ibm4xx_fixup_ebc_ranges("/plb/opb/ebc");
37 dt_fixup_mac_address_by_alias("ethernet0", bd.bi_enetaddr);
38 dt_fixup_mac_address_by_alias("ethernet1", bd.bi_enet1addr);
39}
40
41void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
42 unsigned long r6, unsigned long r7)
43{
44 CUBOOT_INIT();
45 platform_ops.fixups = kilauea_fixups;
46 platform_ops.exit = ibm40x_dbcr_reset;
47 fdt_init(_dtb_start);
48 serial_console_init();
49}
diff --git a/arch/powerpc/boot/dcr.h b/arch/powerpc/boot/dcr.h
index 95b9f5344016..645a7c964e5f 100644
--- a/arch/powerpc/boot/dcr.h
+++ b/arch/powerpc/boot/dcr.h
@@ -153,9 +153,7 @@ static const unsigned long sdram_bxcr[] = { SDRAM0_B0CR, SDRAM0_B1CR,
153#define DCRN_CPC0_PLLMR1 0xf4 153#define DCRN_CPC0_PLLMR1 0xf4
154#define DCRN_CPC0_UCR 0xf5 154#define DCRN_CPC0_UCR 0xf5
155 155
156/* 440GX Clock control etc */ 156/* 440GX/405EX Clock Control reg */
157
158
159#define DCRN_CPR0_CLKUPD 0x020 157#define DCRN_CPR0_CLKUPD 0x020
160#define DCRN_CPR0_PLLC 0x040 158#define DCRN_CPR0_PLLC 0x040
161#define DCRN_CPR0_PLLD 0x060 159#define DCRN_CPR0_PLLD 0x060
diff --git a/arch/powerpc/boot/dts/arches.dts b/arch/powerpc/boot/dts/arches.dts
index d9113b1e8c1d..414ef8b7e575 100644
--- a/arch/powerpc/boot/dts/arches.dts
+++ b/arch/powerpc/boot/dts/arches.dts
@@ -124,6 +124,16 @@
124 dcr-reg = <0x00c 0x002>; 124 dcr-reg = <0x00c 0x002>;
125 }; 125 };
126 126
127 L2C0: l2c {
128 compatible = "ibm,l2-cache-460gt", "ibm,l2-cache";
129 dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */
130 0x030 0x008>; /* L2 cache DCR's */
131 cache-line-size = <32>; /* 32 bytes */
132 cache-size = <262144>; /* L2, 256K */
133 interrupt-parent = <&UIC1>;
134 interrupts = <11 1>;
135 };
136
127 plb { 137 plb {
128 compatible = "ibm,plb-460gt", "ibm,plb4"; 138 compatible = "ibm,plb-460gt", "ibm,plb4";
129 #address-cells = <2>; 139 #address-cells = <2>;
@@ -168,6 +178,38 @@
168 /* ranges property is supplied by U-Boot */ 178 /* ranges property is supplied by U-Boot */
169 interrupts = <0x6 0x4>; 179 interrupts = <0x6 0x4>;
170 interrupt-parent = <&UIC1>; 180 interrupt-parent = <&UIC1>;
181
182 nor_flash@0,0 {
183 compatible = "amd,s29gl256n", "cfi-flash";
184 bank-width = <2>;
185 reg = <0x00000000 0x00000000 0x02000000>;
186 #address-cells = <1>;
187 #size-cells = <1>;
188 partition@0 {
189 label = "kernel";
190 reg = <0x00000000 0x001e0000>;
191 };
192 partition@1e0000 {
193 label = "dtb";
194 reg = <0x001e0000 0x00020000>;
195 };
196 partition@200000 {
197 label = "root";
198 reg = <0x00200000 0x00200000>;
199 };
200 partition@400000 {
201 label = "user";
202 reg = <0x00400000 0x01b60000>;
203 };
204 partition@1f60000 {
205 label = "env";
206 reg = <0x01f60000 0x00040000>;
207 };
208 partition@1fa0000 {
209 label = "u-boot";
210 reg = <0x01fa0000 0x00060000>;
211 };
212 };
171 }; 213 };
172 214
173 UART0: serial@ef600300 { 215 UART0: serial@ef600300 {
@@ -186,6 +228,14 @@
186 reg = <0xef600700 0x00000014>; 228 reg = <0xef600700 0x00000014>;
187 interrupt-parent = <&UIC0>; 229 interrupt-parent = <&UIC0>;
188 interrupts = <0x2 0x4>; 230 interrupts = <0x2 0x4>;
231 #address-cells = <1>;
232 #size-cells = <0>;
233 sttm@4a {
234 compatible = "ad,ad7414";
235 reg = <0x4a>;
236 interrupt-parent = <&UIC1>;
237 interrupts = <0x0 0x8>;
238 };
189 }; 239 };
190 240
191 IIC1: i2c@ef600800 { 241 IIC1: i2c@ef600800 {
diff --git a/arch/powerpc/boot/dts/canyonlands.dts b/arch/powerpc/boot/dts/canyonlands.dts
index 5fd1ad09bdf2..c920170b7dfe 100644
--- a/arch/powerpc/boot/dts/canyonlands.dts
+++ b/arch/powerpc/boot/dts/canyonlands.dts
@@ -1,7 +1,7 @@
1/* 1/*
2 * Device Tree Source for AMCC Canyonlands (460EX) 2 * Device Tree Source for AMCC Canyonlands (460EX)
3 * 3 *
4 * Copyright 2008 DENX Software Engineering, Stefan Roese <sr@denx.de> 4 * Copyright 2008-2009 DENX Software Engineering, Stefan Roese <sr@denx.de>
5 * 5 *
6 * This file is licensed under the terms of the GNU General Public 6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without 7 * License version 2. This program is licensed "as is" without
@@ -149,19 +149,19 @@
149 /*RXDE*/ 0x5 0x4>; 149 /*RXDE*/ 0x5 0x4>;
150 }; 150 };
151 151
152 USB0: ehci@bffd0400 { 152 USB0: ehci@bffd0400 {
153 compatible = "ibm,usb-ehci-460ex", "usb-ehci"; 153 compatible = "ibm,usb-ehci-460ex", "usb-ehci";
154 interrupt-parent = <&UIC2>; 154 interrupt-parent = <&UIC2>;
155 interrupts = <0x1d 4>; 155 interrupts = <0x1d 4>;
156 reg = <4 0xbffd0400 0x90 4 0xbffd0490 0x70>; 156 reg = <4 0xbffd0400 0x90 4 0xbffd0490 0x70>;
157 }; 157 };
158 158
159 USB1: usb@bffd0000 { 159 USB1: usb@bffd0000 {
160 compatible = "ohci-le"; 160 compatible = "ohci-le";
161 reg = <4 0xbffd0000 0x60>; 161 reg = <4 0xbffd0000 0x60>;
162 interrupt-parent = <&UIC2>; 162 interrupt-parent = <&UIC2>;
163 interrupts = <0x1e 4>; 163 interrupts = <0x1e 4>;
164 }; 164 };
165 165
166 POB0: opb { 166 POB0: opb {
167 compatible = "ibm,opb-460ex", "ibm,opb"; 167 compatible = "ibm,opb-460ex", "ibm,opb";
@@ -215,6 +215,29 @@
215 reg = <0x03fa0000 0x00060000>; 215 reg = <0x03fa0000 0x00060000>;
216 }; 216 };
217 }; 217 };
218
219 ndfc@3,0 {
220 compatible = "ibm,ndfc";
221 reg = <0x00000003 0x00000000 0x00002000>;
222 ccr = <0x00001000>;
223 bank-settings = <0x80002222>;
224 #address-cells = <1>;
225 #size-cells = <1>;
226
227 nand {
228 #address-cells = <1>;
229 #size-cells = <1>;
230
231 partition@0 {
232 label = "u-boot";
233 reg = <0x00000000 0x00100000>;
234 };
235 partition@100000 {
236 label = "user";
237 reg = <0x00000000 0x03f00000>;
238 };
239 };
240 };
218 }; 241 };
219 242
220 UART0: serial@ef600300 { 243 UART0: serial@ef600300 {
diff --git a/arch/powerpc/boot/dts/eiger.dts b/arch/powerpc/boot/dts/eiger.dts
new file mode 100644
index 000000000000..c4a934f2e886
--- /dev/null
+++ b/arch/powerpc/boot/dts/eiger.dts
@@ -0,0 +1,421 @@
1/*
2 * Device Tree Source for AMCC (AppliedMicro) Eiger(460SX)
3 *
4 * Copyright 2009 AMCC (AppliedMicro) <ttnguyen@amcc.com>
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without
8 * any warranty of any kind, whether express or implied.
9 */
10
11/dts-v1/;
12
13/ {
14 #address-cells = <2>;
15 #size-cells = <1>;
16 model = "amcc,eiger";
17 compatible = "amcc,eiger";
18 dcr-parent = <&{/cpus/cpu@0}>;
19
20 aliases {
21 ethernet0 = &EMAC0;
22 ethernet1 = &EMAC1;
23 ethernet2 = &EMAC2;
24 ethernet3 = &EMAC3;
25 serial0 = &UART0;
26 serial1 = &UART1;
27 };
28
29 cpus {
30 #address-cells = <1>;
31 #size-cells = <0>;
32
33 cpu@0 {
34 device_type = "cpu";
35 model = "PowerPC,460SX";
36 reg = <0x00000000>;
37 clock-frequency = <0>; /* Filled in by U-Boot */
38 timebase-frequency = <0>; /* Filled in by U-Boot */
39 i-cache-line-size = <32>;
40 d-cache-line-size = <32>;
41 i-cache-size = <32768>;
42 d-cache-size = <32768>;
43 dcr-controller;
44 dcr-access-method = "native";
45 };
46 };
47
48 memory {
49 device_type = "memory";
50 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
51 };
52
53 UIC0: interrupt-controller0 {
54 compatible = "ibm,uic-460sx","ibm,uic";
55 interrupt-controller;
56 cell-index = <0>;
57 dcr-reg = <0x0c0 0x009>;
58 #address-cells = <0>;
59 #size-cells = <0>;
60 #interrupt-cells = <2>;
61 };
62
63 UIC1: interrupt-controller1 {
64 compatible = "ibm,uic-460sx","ibm,uic";
65 interrupt-controller;
66 cell-index = <1>;
67 dcr-reg = <0x0d0 0x009>;
68 #address-cells = <0>;
69 #size-cells = <0>;
70 #interrupt-cells = <2>;
71 interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
72 interrupt-parent = <&UIC0>;
73 };
74
75 UIC2: interrupt-controller2 {
76 compatible = "ibm,uic-460sx","ibm,uic";
77 interrupt-controller;
78 cell-index = <2>;
79 dcr-reg = <0x0e0 0x009>;
80 #address-cells = <0>;
81 #size-cells = <0>;
82 #interrupt-cells = <2>;
83 interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
84 interrupt-parent = <&UIC0>;
85 };
86
87 UIC3: interrupt-controller3 {
88 compatible = "ibm,uic-460sx","ibm,uic";
89 interrupt-controller;
90 cell-index = <3>;
91 dcr-reg = <0x0f0 0x009>;
92 #address-cells = <0>;
93 #size-cells = <0>;
94 #interrupt-cells = <2>;
95 interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
96 interrupt-parent = <&UIC0>;
97 };
98
99 SDR0: sdr {
100 compatible = "ibm,sdr-460sx";
101 dcr-reg = <0x00e 0x002>;
102 };
103
104 CPR0: cpr {
105 compatible = "ibm,cpr-460sx";
106 dcr-reg = <0x00c 0x002>;
107 };
108
109 plb {
110 compatible = "ibm,plb-460sx", "ibm,plb4";
111 #address-cells = <2>;
112 #size-cells = <1>;
113 ranges;
114 clock-frequency = <0>; /* Filled in by U-Boot */
115
116 SDRAM0: sdram {
117 compatible = "ibm,sdram-460sx", "ibm,sdram-405gp";
118 dcr-reg = <0x010 0x002>;
119 };
120
121 MAL0: mcmal {
122 compatible = "ibm,mcmal-460sx", "ibm,mcmal2";
123 dcr-reg = <0x180 0x62>;
124 num-tx-chans = <4>;
125 num-rx-chans = <32>;
126 #address-cells = <1>;
127 #size-cells = <1>;
128 interrupt-parent = <&UIC1>;
129 interrupts = < /*TXEOB*/ 0x6 0x4
130 /*RXEOB*/ 0x7 0x4
131 /*SERR*/ 0x1 0x4
132 /*TXDE*/ 0x2 0x4
133 /*RXDE*/ 0x3 0x4
134 /*COAL TX0*/ 0x18 0x2
135 /*COAL TX1*/ 0x19 0x2
136 /*COAL TX2*/ 0x1a 0x2
137 /*COAL TX3*/ 0x1b 0x2
138 /*COAL RX0*/ 0x1c 0x2
139 /*COAL RX1*/ 0x1d 0x2
140 /*COAL RX2*/ 0x1e 0x2
141 /*COAL RX3*/ 0x1f 0x2>;
142 };
143
144 POB0: opb {
145 compatible = "ibm,opb-460sx", "ibm,opb";
146 #address-cells = <1>;
147 #size-cells = <1>;
148 ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>;
149 clock-frequency = <0>; /* Filled in by U-Boot */
150
151 EBC0: ebc {
152 compatible = "ibm,ebc-460sx", "ibm,ebc";
153 dcr-reg = <0x012 0x002>;
154 #address-cells = <2>;
155 #size-cells = <1>;
156 clock-frequency = <0>; /* Filled in by U-Boot */
157 /* ranges property is supplied by U-Boot */
158 interrupts = <0x6 0x4>;
159 interrupt-parent = <&UIC1>;
160
161 nor_flash@0,0 {
162 compatible = "amd,s29gl512n", "cfi-flash";
163 bank-width = <2>;
164 /* reg property is supplied in by U-Boot */
165 #address-cells = <1>;
166 #size-cells = <1>;
167 partition@0 {
168 label = "kernel";
169 reg = <0x00000000 0x001e0000>;
170 };
171 partition@1e0000 {
172 label = "dtb";
173 reg = <0x001e0000 0x00020000>;
174 };
175 partition@200000 {
176 label = "ramdisk";
177 reg = <0x00200000 0x01400000>;
178 };
179 partition@1600000 {
180 label = "jffs2";
181 reg = <0x01600000 0x00400000>;
182 };
183 partition@1a00000 {
184 label = "user";
185 reg = <0x01a00000 0x02560000>;
186 };
187 partition@3f60000 {
188 label = "env";
189 reg = <0x03f60000 0x00040000>;
190 };
191 partition@3fa0000 {
192 label = "u-boot";
193 reg = <0x03fa0000 0x00060000>;
194 };
195 };
196
197 ndfc@1,0 {
198 compatible = "ibm,ndfc";
199 /* reg property is supplied by U-boot */
200 ccr = <0x00003000>;
201 bank-settings = <0x80002222>;
202 #address-cells = <1>;
203 #size-cells = <1>;
204
205 nand {
206 #address-cells = <1>;
207 #size-cells = <1>;
208 partition@0 {
209 label = "uboot";
210 reg = <0x00000000 0x00200000>;
211 };
212 partition@200000 {
213 label = "uboot-environment";
214 reg = <0x00200000 0x00100000>;
215 };
216 partition@300000 {
217 label = "linux";
218 reg = <0x00300000 0x00300000>;
219 };
220 partition@600000 {
221 label = "root-file-system";
222 reg = <0x00600000 0x01900000>;
223 };
224 partition@1f00000 {
225 label = "device-tree";
226 reg = <0x01f00000 0x00020000>;
227 };
228 partition@1f20000 {
229 label = "data";
230 reg = <0x01f20000 0x060E0000>;
231 };
232 };
233 };
234 };
235
236 UART0: serial@ef600200 {
237 device_type = "serial";
238 compatible = "ns16550";
239 reg = <0xef600200 0x00000008>;
240 virtual-reg = <0xef600200>;
241 clock-frequency = <0>; /* Filled in by U-Boot */
242 current-speed = <0>; /* Filled in by U-Boot */
243 interrupt-parent = <&UIC0>;
244 interrupts = <0x0 0x4>;
245 };
246
247 UART1: serial@ef600300 {
248 device_type = "serial";
249 compatible = "ns16550";
250 reg = <0xef600300 0x00000008>;
251 virtual-reg = <0xef600300>;
252 clock-frequency = <0>; /* Filled in by U-Boot */
253 current-speed = <0>; /* Filled in by U-Boot */
254 interrupt-parent = <&UIC0>;
255 interrupts = <0x1 0x4>;
256 };
257
258 IIC0: i2c@ef600400 {
259 compatible = "ibm,iic-460sx", "ibm,iic";
260 reg = <0xef600400 0x00000014>;
261 interrupt-parent = <&UIC0>;
262 interrupts = <0x2 0x4>;
263 #address-cells = <1>;
264 #size-cells = <0>;
265 index = <0>;
266 };
267
268 IIC1: i2c@ef600500 {
269 compatible = "ibm,iic-460sx", "ibm,iic";
270 reg = <0xef600500 0x00000014>;
271 interrupt-parent = <&UIC0>;
272 interrupts = <0x3 0x4>;
273 #address-cells = <1>;
274 #size-cells = <0>;
275 index = <1>;
276 };
277
278 RGMII0: emac-rgmii@ef600900 {
279 compatible = "ibm,rgmii-460sx", "ibm,rgmii";
280 reg = <0xef600900 0x00000008>;
281 has-mdio;
282 };
283
284 RGMII1: emac-rgmii@ef600920 {
285 compatible = "ibm,rgmii-460sx", "ibm,rgmii";
286 reg = <0xef600920 0x00000008>;
287 has-mdio;
288 };
289
290 TAH0: emac-tah@ef600e50 {
291 compatible = "ibm,tah-460sx", "ibm,tah";
292 reg = <0xef600e50 0x00000030>;
293 };
294
295 TAH1: emac-tah@ef600f50 {
296 compatible = "ibm,tah-460sx", "ibm,tah";
297 reg = <0xef600f50 0x00000030>;
298 };
299
300 EMAC0: ethernet@ef600a00 {
301 device_type = "network";
302 compatible = "ibm,emac-460sx", "ibm,emac4";
303 interrupt-parent = <&EMAC0>;
304 interrupts = <0x0 0x1>;
305 #interrupt-cells = <1>;
306 #address-cells = <0>;
307 #size-cells = <0>;
308 interrupt-map = </*Status*/ 0x0 &UIC0 0x13 0x4
309 /*Wake*/ 0x1 &UIC2 0x1d 0x4>;
310 reg = <0xef600a00 0x00000070>;
311 local-mac-address = [000000000000]; /* Filled in by U-Boot */
312 mal-device = <&MAL0>;
313 mal-tx-channel = <0>;
314 mal-rx-channel = <0>;
315 cell-index = <0>;
316 max-frame-size = <9000>;
317 rx-fifo-size = <4096>;
318 tx-fifo-size = <2048>;
319 phy-mode = "rgmii";
320 phy-map = <0x00000000>;
321 rgmii-device = <&RGMII0>;
322 rgmii-channel = <0>;
323 tah-device = <&TAH0>;
324 tah-channel = <0>;
325 has-inverted-stacr-oc;
326 has-new-stacr-staopc;
327 };
328
329 EMAC1: ethernet@ef600b00 {
330 device_type = "network";
331 compatible = "ibm,emac-460sx", "ibm,emac4";
332 interrupt-parent = <&EMAC1>;
333 interrupts = <0x0 0x1>;
334 #interrupt-cells = <1>;
335 #address-cells = <0>;
336 #size-cells = <0>;
337 interrupt-map = </*Status*/ 0x0 &UIC0 0x14 0x4
338 /*Wake*/ 0x1 &UIC2 0x1d 0x4>;
339 reg = <0xef600b00 0x00000070>;
340 local-mac-address = [000000000000]; /* Filled in by U-Boot */
341 mal-device = <&MAL0>;
342 mal-tx-channel = <1>;
343 mal-rx-channel = <8>;
344 cell-index = <1>;
345 max-frame-size = <9000>;
346 rx-fifo-size = <4096>;
347 tx-fifo-size = <2048>;
348 phy-mode = "rgmii";
349 phy-map = <0x00000000>;
350 rgmii-device = <&RGMII0>;
351 rgmii-channel = <1>;
352 tah-device = <&TAH1>;
353 tah-channel = <1>;
354 has-inverted-stacr-oc;
355 has-new-stacr-staopc;
356 mdio-device = <&EMAC0>;
357 };
358
359 EMAC2: ethernet@ef600c00 {
360 device_type = "network";
361 compatible = "ibm,emac-460sx", "ibm,emac4";
362 interrupt-parent = <&EMAC2>;
363 interrupts = <0x0 0x1>;
364 #interrupt-cells = <1>;
365 #address-cells = <0>;
366 #size-cells = <0>;
367 interrupt-map = </*Status*/ 0x0 &UIC0 0x15 0x4
368 /*Wake*/ 0x1 &UIC2 0x1d 0x4>;
369 reg = <0xef600c00 0x00000070>;
370 local-mac-address = [000000000000]; /* Filled in by U-Boot */
371 mal-device = <&MAL0>;
372 mal-tx-channel = <2>;
373 mal-rx-channel = <16>;
374 cell-index = <2>;
375 max-frame-size = <9000>;
376 rx-fifo-size = <4096>;
377 tx-fifo-size = <2048>;
378 phy-mode = "rgmii";
379 phy-map = <0x00000000>;
380 rgmii-device = <&RGMII1>;
381 rgmii-channel = <0>;
382 has-inverted-stacr-oc;
383 has-new-stacr-staopc;
384 mdio-device = <&EMAC0>;
385 };
386
387 EMAC3: ethernet@ef600d00 {
388 device_type = "network";
389 compatible = "ibm,emac-460sx", "ibm,emac4";
390 interrupt-parent = <&EMAC3>;
391 interrupts = <0x0 0x1>;
392 #interrupt-cells = <1>;
393 #address-cells = <0>;
394 #size-cells = <0>;
395 interrupt-map = </*Status*/ 0x0 &UIC0 0x16 0x4
396 /*Wake*/ 0x1 &UIC2 0x1d 0x4>;
397 reg = <0xef600d00 0x00000070>;
398 local-mac-address = [000000000000]; /* Filled in by U-Boot */
399 mal-device = <&MAL0>;
400 mal-tx-channel = <3>;
401 mal-rx-channel = <24>;
402 cell-index = <3>;
403 max-frame-size = <9000>;
404 rx-fifo-size = <4096>;
405 tx-fifo-size = <2048>;
406 phy-mode = "rgmii";
407 phy-map = <0x00000000>;
408 rgmii-device = <&RGMII1>;
409 rgmii-channel = <1>;
410 has-inverted-stacr-oc;
411 has-new-stacr-staopc;
412 mdio-device = <&EMAC0>;
413 };
414 };
415
416 };
417 chosen {
418 linux,stdout-path = "/plb/opb/serial@ef600200";
419 };
420
421};
diff --git a/arch/powerpc/boot/dts/gef_sbc310.dts b/arch/powerpc/boot/dts/gef_sbc310.dts
index 0f4c9ec2c3a6..2107d3c7cfe1 100644
--- a/arch/powerpc/boot/dts/gef_sbc310.dts
+++ b/arch/powerpc/boot/dts/gef_sbc310.dts
@@ -83,34 +83,34 @@
83 83
84 /* flash@0,0 is a mirror of part of the memory in flash@1,0 84 /* flash@0,0 is a mirror of part of the memory in flash@1,0
85 flash@0,0 { 85 flash@0,0 {
86 compatible = "cfi-flash"; 86 compatible = "gef,sbc310-firmware-mirror", "cfi-flash";
87 reg = <0 0 0x01000000>; 87 reg = <0x0 0x0 0x01000000>;
88 bank-width = <2>; 88 bank-width = <2>;
89 device-width = <2>; 89 device-width = <2>;
90 #address-cells = <1>; 90 #address-cells = <1>;
91 #size-cells = <1>; 91 #size-cells = <1>;
92 partition@0 { 92 partition@0 {
93 label = "firmware"; 93 label = "firmware";
94 reg = <0x00000000 0x01000000>; 94 reg = <0x0 0x01000000>;
95 read-only; 95 read-only;
96 }; 96 };
97 }; 97 };
98 */ 98 */
99 99
100 flash@1,0 { 100 flash@1,0 {
101 compatible = "cfi-flash"; 101 compatible = "gef,sbc310-paged-flash", "cfi-flash";
102 reg = <1 0 0x8000000>; 102 reg = <0x1 0x0 0x8000000>;
103 bank-width = <2>; 103 bank-width = <2>;
104 device-width = <2>; 104 device-width = <2>;
105 #address-cells = <1>; 105 #address-cells = <1>;
106 #size-cells = <1>; 106 #size-cells = <1>;
107 partition@0 { 107 partition@0 {
108 label = "user"; 108 label = "user";
109 reg = <0x00000000 0x07800000>; 109 reg = <0x0 0x7800000>;
110 }; 110 };
111 partition@7800000 { 111 partition@7800000 {
112 label = "firmware"; 112 label = "firmware";
113 reg = <0x07800000 0x00800000>; 113 reg = <0x7800000 0x800000>;
114 read-only; 114 read-only;
115 }; 115 };
116 }; 116 };
@@ -121,18 +121,16 @@
121 }; 121 };
122 122
123 wdt@4,2000 { 123 wdt@4,2000 {
124 #interrupt-cells = <2>; 124 compatible = "gef,sbc310-fpga-wdt", "gef,fpga-wdt-1.00",
125 device_type = "watchdog"; 125 "gef,fpga-wdt";
126 compatible = "gef,fpga-wdt";
127 reg = <0x4 0x2000 0x8>; 126 reg = <0x4 0x2000 0x8>;
128 interrupts = <0x1a 0x4>; 127 interrupts = <0x1a 0x4>;
129 interrupt-parent = <&gef_pic>; 128 interrupt-parent = <&gef_pic>;
130 }; 129 };
131/* 130/*
132 wdt@4,2010 { 131 wdt@4,2010 {
133 #interrupt-cells = <2>; 132 compatible = "gef,sbc310-fpga-wdt", "gef,fpga-wdt-1.00",
134 device_type = "watchdog"; 133 "gef,fpga-wdt";
135 compatible = "gef,fpga-wdt";
136 reg = <0x4 0x2010 0x8>; 134 reg = <0x4 0x2010 0x8>;
137 interrupts = <0x1b 0x4>; 135 interrupts = <0x1b 0x4>;
138 interrupt-parent = <&gef_pic>; 136 interrupt-parent = <&gef_pic>;
@@ -141,7 +139,7 @@
141 gef_pic: pic@4,4000 { 139 gef_pic: pic@4,4000 {
142 #interrupt-cells = <1>; 140 #interrupt-cells = <1>;
143 interrupt-controller; 141 interrupt-controller;
144 compatible = "gef,fpga-pic"; 142 compatible = "gef,sbc310-fpga-pic", "gef,fpga-pic";
145 reg = <0x4 0x4000 0x20>; 143 reg = <0x4 0x4000 0x20>;
146 interrupts = <0x8 144 interrupts = <0x8
147 0x9>; 145 0x9>;
@@ -161,7 +159,7 @@
161 #size-cells = <1>; 159 #size-cells = <1>;
162 #interrupt-cells = <2>; 160 #interrupt-cells = <2>;
163 device_type = "soc"; 161 device_type = "soc";
164 compatible = "simple-bus"; 162 compatible = "fsl,mpc8641-soc", "simple-bus";
165 ranges = <0x0 0xfef00000 0x00100000>; 163 ranges = <0x0 0xfef00000 0x00100000>;
166 bus-frequency = <33333333>; 164 bus-frequency = <33333333>;
167 165
@@ -376,4 +374,40 @@
376 0x0 0x00400000>; 374 0x0 0x00400000>;
377 }; 375 };
378 }; 376 };
377
378 pci1: pcie@fef09000 {
379 compatible = "fsl,mpc8641-pcie";
380 device_type = "pci";
381 #interrupt-cells = <1>;
382 #size-cells = <2>;
383 #address-cells = <3>;
384 reg = <0xfef09000 0x1000>;
385 bus-range = <0x0 0xff>;
386 ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0x0 0x20000000
387 0x01000000 0x0 0x00000000 0xfe400000 0x0 0x00400000>;
388 clock-frequency = <33333333>;
389 interrupt-parent = <&mpic>;
390 interrupts = <0x19 0x2>;
391 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
392 interrupt-map = <
393 0x0000 0x0 0x0 0x1 &mpic 0x4 0x2
394 0x0000 0x0 0x0 0x2 &mpic 0x5 0x2
395 0x0000 0x0 0x0 0x3 &mpic 0x6 0x2
396 0x0000 0x0 0x0 0x4 &mpic 0x7 0x2
397 >;
398
399 pcie@0 {
400 reg = <0 0 0 0 0>;
401 #size-cells = <2>;
402 #address-cells = <3>;
403 device_type = "pci";
404 ranges = <0x02000000 0x0 0xc0000000
405 0x02000000 0x0 0xc0000000
406 0x0 0x20000000
407
408 0x01000000 0x0 0x00000000
409 0x01000000 0x0 0x00000000
410 0x0 0x00400000>;
411 };
412 };
379}; 413};
diff --git a/arch/powerpc/boot/dts/hotfoot.dts b/arch/powerpc/boot/dts/hotfoot.dts
new file mode 100644
index 000000000000..cad9c3840afc
--- /dev/null
+++ b/arch/powerpc/boot/dts/hotfoot.dts
@@ -0,0 +1,294 @@
1/*
2 * Device Tree Source for ESTeem 195E Hotfoot
3 *
4 * Copyright 2009 AbsoluteValue Systems <solomon@linux-wlan.com>
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without
8 * any warranty of any kind, whether express or implied.
9 */
10
11/dts-v1/;
12
13/ {
14 #address-cells = <1>;
15 #size-cells = <1>;
16 model = "est,hotfoot";
17 compatible = "est,hotfoot";
18 dcr-parent = <&{/cpus/cpu@0}>;
19
20 aliases {
21 ethernet0 = &EMAC0;
22 ethernet1 = &EMAC1;
23 serial0 = &UART0;
24 serial1 = &UART1;
25 };
26
27 cpus {
28 #address-cells = <1>;
29 #size-cells = <0>;
30
31 cpu@0 {
32 device_type = "cpu";
33 model = "PowerPC,405EP";
34 reg = <0x00000000>;
35 clock-frequency = <0>; /* Filled in by zImage */
36 timebase-frequency = <0>; /* Filled in by zImage */
37 i-cache-line-size = <0x20>;
38 d-cache-line-size = <0x20>;
39 i-cache-size = <0x4000>;
40 d-cache-size = <0x4000>;
41 dcr-controller;
42 dcr-access-method = "native";
43 };
44 };
45
46 memory {
47 device_type = "memory";
48 reg = <0x00000000 0x00000000>; /* Filled in by zImage */
49 };
50
51 UIC0: interrupt-controller {
52 compatible = "ibm,uic";
53 interrupt-controller;
54 cell-index = <0>;
55 dcr-reg = <0x0c0 0x009>;
56 #address-cells = <0>;
57 #size-cells = <0>;
58 #interrupt-cells = <2>;
59 };
60
61 plb {
62 compatible = "ibm,plb3";
63 #address-cells = <1>;
64 #size-cells = <1>;
65 ranges;
66 clock-frequency = <0>; /* Filled in by zImage */
67
68 SDRAM0: memory-controller {
69 compatible = "ibm,sdram-405ep";
70 dcr-reg = <0x010 0x002>;
71 };
72
73 MAL: mcmal {
74 compatible = "ibm,mcmal-405ep", "ibm,mcmal";
75 dcr-reg = <0x180 0x062>;
76 num-tx-chans = <4>;
77 num-rx-chans = <2>;
78 interrupt-parent = <&UIC0>;
79 interrupts = <
80 0xb 0x4 /* TXEOB */
81 0xc 0x4 /* RXEOB */
82 0xa 0x4 /* SERR */
83 0xd 0x4 /* TXDE */
84 0xe 0x4 /* RXDE */>;
85 };
86
87 POB0: opb {
88 compatible = "ibm,opb-405ep", "ibm,opb";
89 #address-cells = <1>;
90 #size-cells = <1>;
91 ranges = <0xef600000 0xef600000 0x00a00000>;
92 dcr-reg = <0x0a0 0x005>;
93 clock-frequency = <0>; /* Filled in by zImage */
94
95 /* Hotfoot has UART0/UART1 swapped */
96
97 UART0: serial@ef600400 {
98 device_type = "serial";
99 compatible = "ns16550";
100 reg = <0xef600400 0x00000008>;
101 virtual-reg = <0xef600400>;
102 clock-frequency = <0>; /* Filled in by zImage */
103 current-speed = <0x9600>;
104 interrupt-parent = <&UIC0>;
105 interrupts = <0x1 0x4>;
106 };
107
108 UART1: serial@ef600300 {
109 device_type = "serial";
110 compatible = "ns16550";
111 reg = <0xef600300 0x00000008>;
112 virtual-reg = <0xef600300>;
113 clock-frequency = <0>; /* Filled in by zImage */
114 current-speed = <0x9600>;
115 interrupt-parent = <&UIC0>;
116 interrupts = <0x0 0x4>;
117 };
118
119 IIC: i2c@ef600500 {
120 compatible = "ibm,iic-405ep", "ibm,iic";
121 reg = <0xef600500 0x00000011>;
122 interrupt-parent = <&UIC0>;
123 interrupts = <0x2 0x4>;
124
125 rtc@68 {
126 /* Actually a DS1339 */
127 compatible = "dallas,ds1307";
128 reg = <0x68>;
129 };
130
131 temp@4a {
132 /* Not present on all boards */
133 compatible = "national,lm75";
134 reg = <0x4a>;
135 };
136 };
137
138 GPIO: gpio@ef600700 {
139 #gpio-cells = <2>;
140 compatible = "ibm,ppc4xx-gpio";
141 reg = <0xef600700 0x00000020>;
142 gpio-controller;
143 };
144
145 gpio-leds {
146 compatible = "gpio-leds";
147 status {
148 label = "Status";
149 gpios = <&GPIO 1 0>;
150 };
151 radiorx {
152 label = "Rx";
153 gpios = <&GPIO 0xe 0>;
154 };
155 };
156
157 EMAC0: ethernet@ef600800 {
158 linux,network-index = <0x0>;
159 device_type = "network";
160 compatible = "ibm,emac-405ep", "ibm,emac";
161 interrupt-parent = <&UIC0>;
162 interrupts = <
163 0xf 0x4 /* Ethernet */
164 0x9 0x4 /* Ethernet Wake Up */>;
165 local-mac-address = [000000000000]; /* Filled in by zImage */
166 reg = <0xef600800 0x00000070>;
167 mal-device = <&MAL>;
168 mal-tx-channel = <0>;
169 mal-rx-channel = <0>;
170 cell-index = <0>;
171 max-frame-size = <0x5dc>;
172 rx-fifo-size = <0x1000>;
173 tx-fifo-size = <0x800>;
174 phy-mode = "mii";
175 phy-map = <0x00000000>;
176 };
177
178 EMAC1: ethernet@ef600900 {
179 linux,network-index = <0x1>;
180 device_type = "network";
181 compatible = "ibm,emac-405ep", "ibm,emac";
182 interrupt-parent = <&UIC0>;
183 interrupts = <
184 0x11 0x4 /* Ethernet */
185 0x9 0x4 /* Ethernet Wake Up */>;
186 local-mac-address = [000000000000]; /* Filled in by zImage */
187 reg = <0xef600900 0x00000070>;
188 mal-device = <&MAL>;
189 mal-tx-channel = <2>;
190 mal-rx-channel = <1>;
191 cell-index = <1>;
192 max-frame-size = <0x5dc>;
193 rx-fifo-size = <0x1000>;
194 tx-fifo-size = <0x800>;
195 mdio-device = <&EMAC0>;
196 phy-mode = "mii";
197 phy-map = <0x0000001>;
198 };
199 };
200
201 EBC0: ebc {
202 compatible = "ibm,ebc-405ep", "ibm,ebc";
203 dcr-reg = <0x012 0x002>;
204 #address-cells = <2>;
205 #size-cells = <1>;
206
207 /* The ranges property is supplied by the bootwrapper
208 * and is based on the firmware's configuration of the
209 * EBC bridge
210 */
211 clock-frequency = <0>; /* Filled in by zImage */
212
213 nor_flash@0 {
214 compatible = "cfi-flash";
215 bank-width = <2>;
216 reg = <0x0 0xff800000 0x00800000>;
217 #address-cells = <1>;
218 #size-cells = <1>;
219
220 /* This mapping is for the 8M flash
221 4M flash has all ofssets -= 4M,
222 and FeatFS partition is not present */
223 partition@0 {
224 label = "Bootloader";
225 reg = <0x7c0000 0x40000>;
226 /* read-only; */
227 };
228 partition@1 {
229 label = "Env_and_Config_Primary";
230 reg = <0x400000 0x10000>;
231 };
232 partition@2 {
233 label = "Kernel";
234 reg = <0x420000 0x100000>;
235 };
236 partition@3 {
237 label = "Filesystem";
238 reg = <0x520000 0x2a0000>;
239 };
240 partition@4 {
241 label = "Env_and_Config_Secondary";
242 reg = <0x410000 0x10000>;
243 };
244 partition@5 {
245 label = "FeatFS";
246 reg = <0x000000 0x400000>;
247 };
248 partition@6 {
249 label = "Bootloader_Env";
250 reg = <0x7d0000 0x10000>;
251 };
252 };
253 };
254
255 PCI0: pci@ec000000 {
256 device_type = "pci";
257 #interrupt-cells = <1>;
258 #size-cells = <2>;
259 #address-cells = <3>;
260 compatible = "ibm,plb405ep-pci", "ibm,plb-pci";
261 primary;
262 reg = <0xeec00000 0x00000008 /* Config space access */
263 0xeed80000 0x00000004 /* IACK */
264 0xeed80000 0x00000004 /* Special cycle */
265 0xef480000 0x00000040>; /* Internal registers */
266
267 /* Outbound ranges, one memory and one IO,
268 * later cannot be changed. Chip supports a second
269 * IO range but we don't use it for now
270 */
271 ranges = <0x02000000 0x00000000 0x80000000 0x80000000 0x00000000 0x20000000
272 0x01000000 0x00000000 0x00000000 0xe8000000 0x00000000 0x00010000>;
273
274 /* Inbound 2GB range starting at 0 */
275 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>;
276
277 interrupt-parent = <&UIC0>;
278 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
279 interrupt-map = <
280 /* IDSEL 3 -- slot1 (optional) 27/29 A/B IRQ2/4 */
281 0x1800 0x0 0x0 0x1 &UIC0 0x1b 0x8
282 0x1800 0x0 0x0 0x2 &UIC0 0x1d 0x8
283
284 /* IDSEL 4 -- slot0, 26/28 A/B IRQ1/3 */
285 0x2000 0x0 0x0 0x1 &UIC0 0x1a 0x8
286 0x2000 0x0 0x0 0x2 &UIC0 0x1c 0x8
287 >;
288 };
289 };
290
291 chosen {
292 linux,stdout-path = &UART0;
293 };
294};
diff --git a/arch/powerpc/boot/dts/kilauea.dts b/arch/powerpc/boot/dts/kilauea.dts
index 5e6b08ff6f67..c46561456ede 100644
--- a/arch/powerpc/boot/dts/kilauea.dts
+++ b/arch/powerpc/boot/dts/kilauea.dts
@@ -1,7 +1,7 @@
1/* 1/*
2 * Device Tree Source for AMCC Kilauea (405EX) 2 * Device Tree Source for AMCC Kilauea (405EX)
3 * 3 *
4 * Copyright 2007 DENX Software Engineering, Stefan Roese <sr@denx.de> 4 * Copyright 2007-2009 DENX Software Engineering, Stefan Roese <sr@denx.de>
5 * 5 *
6 * This file is licensed under the terms of the GNU General Public 6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without 7 * License version 2. This program is licensed "as is" without
@@ -150,7 +150,11 @@
150 #size-cells = <1>; 150 #size-cells = <1>;
151 partition@0 { 151 partition@0 {
152 label = "kernel"; 152 label = "kernel";
153 reg = <0x00000000 0x00200000>; 153 reg = <0x00000000 0x001e0000>;
154 };
155 partition@1e0000 {
156 label = "dtb";
157 reg = <0x001e0000 0x00020000>;
154 }; 158 };
155 partition@200000 { 159 partition@200000 {
156 label = "root"; 160 label = "root";
@@ -169,6 +173,29 @@
169 reg = <0x03fa0000 0x00060000>; 173 reg = <0x03fa0000 0x00060000>;
170 }; 174 };
171 }; 175 };
176
177 ndfc@1,0 {
178 compatible = "ibm,ndfc";
179 reg = <0x00000001 0x00000000 0x00002000>;
180 ccr = <0x00001000>;
181 bank-settings = <0x80002222>;
182 #address-cells = <1>;
183 #size-cells = <1>;
184
185 nand {
186 #address-cells = <1>;
187 #size-cells = <1>;
188
189 partition@0 {
190 label = "u-boot";
191 reg = <0x00000000 0x00100000>;
192 };
193 partition@100000 {
194 label = "user";
195 reg = <0x00000000 0x03f00000>;
196 };
197 };
198 };
172 }; 199 };
173 200
174 UART0: serial@ef600200 { 201 UART0: serial@ef600200 {
@@ -198,6 +225,18 @@
198 reg = <0xef600400 0x00000014>; 225 reg = <0xef600400 0x00000014>;
199 interrupt-parent = <&UIC0>; 226 interrupt-parent = <&UIC0>;
200 interrupts = <0x2 0x4>; 227 interrupts = <0x2 0x4>;
228 #address-cells = <1>;
229 #size-cells = <0>;
230
231 rtc@68 {
232 compatible = "dallas,ds1338";
233 reg = <0x68>;
234 };
235
236 dtt@48 {
237 compatible = "dallas,ds1775";
238 reg = <0x48>;
239 };
201 }; 240 };
202 241
203 IIC1: i2c@ef600500 { 242 IIC1: i2c@ef600500 {
@@ -207,7 +246,6 @@
207 interrupts = <0x7 0x4>; 246 interrupts = <0x7 0x4>;
208 }; 247 };
209 248
210
211 RGMII0: emac-rgmii@ef600b00 { 249 RGMII0: emac-rgmii@ef600b00 {
212 compatible = "ibm,rgmii-405ex", "ibm,rgmii"; 250 compatible = "ibm,rgmii-405ex", "ibm,rgmii";
213 reg = <0xef600b00 0x00000104>; 251 reg = <0xef600b00 0x00000104>;
diff --git a/arch/powerpc/boot/dts/mgcoge.dts b/arch/powerpc/boot/dts/mgcoge.dts
index 633255a97557..0ce96644176d 100644
--- a/arch/powerpc/boot/dts/mgcoge.dts
+++ b/arch/powerpc/boot/dts/mgcoge.dts
@@ -162,6 +162,59 @@
162 fixed-link = <0 0 10 0 0>; 162 fixed-link = <0 0 10 0 0>;
163 }; 163 };
164 164
165 i2c@11860 {
166 compatible = "fsl,mpc8272-i2c",
167 "fsl,cpm2-i2c";
168 reg = <0x11860 0x20 0x8afc 0x2>;
169 interrupts = <1 8>;
170 interrupt-parent = <&PIC>;
171 fsl,cpm-command = <0x29600000>;
172 #address-cells = <1>;
173 #size-cells = <0>;
174 };
175
176 mdio@10d40 {
177 compatible = "fsl,cpm2-mdio-bitbang";
178 reg = <0x10d00 0x14>;
179 #address-cells = <1>;
180 #size-cells = <0>;
181 fsl,mdio-pin = <12>;
182 fsl,mdc-pin = <13>;
183
184 phy0: ethernet-phy@0 {
185 reg = <0x0>;
186 };
187
188 phy1: ethernet-phy@1 {
189 reg = <0x1>;
190 };
191 };
192
193 /* FCC1 management to switch */
194 ethernet@11300 {
195 device_type = "network";
196 compatible = "fsl,cpm2-fcc-enet";
197 reg = <0x11300 0x20 0x8400 0x100 0x11390 0x1>;
198 local-mac-address = [ 00 01 02 03 04 07 ];
199 interrupts = <32 8>;
200 interrupt-parent = <&PIC>;
201 phy-handle = <&phy0>;
202 linux,network-index = <1>;
203 fsl,cpm-command = <0x12000300>;
204 };
205
206 /* FCC2 to redundant core unit over backplane */
207 ethernet@11320 {
208 device_type = "network";
209 compatible = "fsl,cpm2-fcc-enet";
210 reg = <0x11320 0x20 0x8500 0x100 0x113b0 0x1>;
211 local-mac-address = [ 00 01 02 03 04 08 ];
212 interrupts = <33 8>;
213 interrupt-parent = <&PIC>;
214 phy-handle = <&phy1>;
215 linux,network-index = <2>;
216 fsl,cpm-command = <0x16200300>;
217 };
165 }; 218 };
166 219
167 PIC: interrupt-controller@10c00 { 220 PIC: interrupt-controller@10c00 {
diff --git a/arch/powerpc/boot/dts/mpc8272ads.dts b/arch/powerpc/boot/dts/mpc8272ads.dts
index 60f332778e41..e802ebd88cb1 100644
--- a/arch/powerpc/boot/dts/mpc8272ads.dts
+++ b/arch/powerpc/boot/dts/mpc8272ads.dts
@@ -173,6 +173,14 @@
173 fsl,cpm-command = <0xce00000>; 173 fsl,cpm-command = <0xce00000>;
174 }; 174 };
175 175
176 usb@11b60 {
177 compatible = "fsl,mpc8272-cpm-usb";
178 reg = <0x11b60 0x40 0x8b00 0x100>;
179 interrupts = <11 8>;
180 interrupt-parent = <&PIC>;
181 mode = "peripheral";
182 };
183
176 mdio@10d40 { 184 mdio@10d40 {
177 device_type = "mdio"; 185 device_type = "mdio";
178 compatible = "fsl,mpc8272ads-mdio-bitbang", 186 compatible = "fsl,mpc8272ads-mdio-bitbang",
diff --git a/arch/powerpc/boot/dts/mpc8377_rdb.dts b/arch/powerpc/boot/dts/mpc8377_rdb.dts
index 4f06dbc0d27e..28e022ac4179 100644
--- a/arch/powerpc/boot/dts/mpc8377_rdb.dts
+++ b/arch/powerpc/boot/dts/mpc8377_rdb.dts
@@ -174,7 +174,7 @@
174 interrupts = <42 0x8>; 174 interrupts = <42 0x8>;
175 interrupt-parent = <&ipic>; 175 interrupt-parent = <&ipic>;
176 /* Filled in by U-Boot */ 176 /* Filled in by U-Boot */
177 clock-frequency = <0>; 177 clock-frequency = <111111111>;
178 }; 178 };
179 }; 179 };
180 180
diff --git a/arch/powerpc/boot/dts/mpc8377_wlan.dts b/arch/powerpc/boot/dts/mpc8377_wlan.dts
new file mode 100644
index 000000000000..3febc4e91b10
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc8377_wlan.dts
@@ -0,0 +1,464 @@
1/*
2 * MPC8377E WLAN Device Tree Source
3 *
4 * Copyright 2007-2009 Freescale Semiconductor Inc.
5 * Copyright 2009 MontaVista Software, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13/dts-v1/;
14
15/ {
16 compatible = "fsl,mpc8377wlan";
17 #address-cells = <1>;
18 #size-cells = <1>;
19
20 aliases {
21 ethernet0 = &enet0;
22 ethernet1 = &enet1;
23 serial0 = &serial0;
24 serial1 = &serial1;
25 pci0 = &pci0;
26 pci1 = &pci1;
27 pci2 = &pci2;
28 };
29
30 cpus {
31 #address-cells = <1>;
32 #size-cells = <0>;
33
34 PowerPC,8377@0 {
35 device_type = "cpu";
36 reg = <0x0>;
37 d-cache-line-size = <32>;
38 i-cache-line-size = <32>;
39 d-cache-size = <32768>;
40 i-cache-size = <32768>;
41 timebase-frequency = <0>;
42 bus-frequency = <0>;
43 clock-frequency = <0>;
44 };
45 };
46
47 memory {
48 device_type = "memory";
49 reg = <0x00000000 0x20000000>; // 512MB at 0
50 };
51
52 localbus@e0005000 {
53 #address-cells = <2>;
54 #size-cells = <1>;
55 compatible = "fsl,mpc8377-elbc", "fsl,elbc", "simple-bus";
56 reg = <0xe0005000 0x1000>;
57 interrupts = <77 0x8>;
58 interrupt-parent = <&ipic>;
59 ranges = <0x0 0x0 0xfc000000 0x04000000>;
60
61 flash@0,0 {
62 #address-cells = <1>;
63 #size-cells = <1>;
64 compatible = "cfi-flash";
65 reg = <0x0 0x0 0x4000000>;
66 bank-width = <2>;
67 device-width = <1>;
68
69 partition@0 {
70 reg = <0 0x8000>;
71 label = "u-boot";
72 read-only;
73 };
74
75 partition@a0000 {
76 reg = <0xa0000 0x300000>;
77 label = "kernel";
78 };
79
80 partition@3a0000 {
81 reg = <0x3a0000 0x3c60000>;
82 label = "rootfs";
83 };
84 };
85 };
86
87 immr@e0000000 {
88 #address-cells = <1>;
89 #size-cells = <1>;
90 device_type = "soc";
91 compatible = "simple-bus";
92 ranges = <0x0 0xe0000000 0x00100000>;
93 reg = <0xe0000000 0x00000200>;
94 bus-frequency = <0>;
95
96 wdt@200 {
97 device_type = "watchdog";
98 compatible = "mpc83xx_wdt";
99 reg = <0x200 0x100>;
100 };
101
102 gpio1: gpio-controller@c00 {
103 #gpio-cells = <2>;
104 compatible = "fsl,mpc8377-gpio", "fsl,mpc8349-gpio";
105 reg = <0xc00 0x100>;
106 interrupts = <74 0x8>;
107 interrupt-parent = <&ipic>;
108 gpio-controller;
109 };
110
111 gpio2: gpio-controller@d00 {
112 #gpio-cells = <2>;
113 compatible = "fsl,mpc8377-gpio", "fsl,mpc8349-gpio";
114 reg = <0xd00 0x100>;
115 interrupts = <75 0x8>;
116 interrupt-parent = <&ipic>;
117 gpio-controller;
118 };
119
120 sleep-nexus {
121 #address-cells = <1>;
122 #size-cells = <1>;
123 compatible = "simple-bus";
124 sleep = <&pmc 0x0c000000>;
125 ranges;
126
127 i2c@3000 {
128 #address-cells = <1>;
129 #size-cells = <0>;
130 cell-index = <0>;
131 compatible = "fsl-i2c";
132 reg = <0x3000 0x100>;
133 interrupts = <14 0x8>;
134 interrupt-parent = <&ipic>;
135 dfsrr;
136
137 at24@50 {
138 compatible = "at24,24c256";
139 reg = <0x50>;
140 };
141
142 rtc@68 {
143 compatible = "dallas,ds1339";
144 reg = <0x68>;
145 };
146 };
147
148 sdhci@2e000 {
149 compatible = "fsl,mpc8377-esdhc", "fsl,esdhc";
150 reg = <0x2e000 0x1000>;
151 interrupts = <42 0x8>;
152 interrupt-parent = <&ipic>;
153 clock-frequency = <133333333>;
154 };
155 };
156
157 i2c@3100 {
158 #address-cells = <1>;
159 #size-cells = <0>;
160 cell-index = <1>;
161 compatible = "fsl-i2c";
162 reg = <0x3100 0x100>;
163 interrupts = <15 0x8>;
164 interrupt-parent = <&ipic>;
165 dfsrr;
166 };
167
168 spi@7000 {
169 cell-index = <0>;
170 compatible = "fsl,spi";
171 reg = <0x7000 0x1000>;
172 interrupts = <16 0x8>;
173 interrupt-parent = <&ipic>;
174 mode = "cpu";
175 };
176
177 dma@82a8 {
178 #address-cells = <1>;
179 #size-cells = <1>;
180 compatible = "fsl,mpc8377-dma", "fsl,elo-dma";
181 reg = <0x82a8 4>;
182 ranges = <0 0x8100 0x1a8>;
183 interrupt-parent = <&ipic>;
184 interrupts = <71 8>;
185 cell-index = <0>;
186 dma-channel@0 {
187 compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
188 reg = <0 0x80>;
189 cell-index = <0>;
190 interrupt-parent = <&ipic>;
191 interrupts = <71 8>;
192 };
193 dma-channel@80 {
194 compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
195 reg = <0x80 0x80>;
196 cell-index = <1>;
197 interrupt-parent = <&ipic>;
198 interrupts = <71 8>;
199 };
200 dma-channel@100 {
201 compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
202 reg = <0x100 0x80>;
203 cell-index = <2>;
204 interrupt-parent = <&ipic>;
205 interrupts = <71 8>;
206 };
207 dma-channel@180 {
208 compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
209 reg = <0x180 0x28>;
210 cell-index = <3>;
211 interrupt-parent = <&ipic>;
212 interrupts = <71 8>;
213 };
214 };
215
216 usb@23000 {
217 compatible = "fsl-usb2-dr";
218 reg = <0x23000 0x1000>;
219 #address-cells = <1>;
220 #size-cells = <0>;
221 interrupt-parent = <&ipic>;
222 interrupts = <38 0x8>;
223 phy_type = "ulpi";
224 sleep = <&pmc 0x00c00000>;
225 };
226
227 enet0: ethernet@24000 {
228 #address-cells = <1>;
229 #size-cells = <1>;
230 cell-index = <0>;
231 device_type = "network";
232 model = "eTSEC";
233 compatible = "gianfar";
234 reg = <0x24000 0x1000>;
235 ranges = <0x0 0x24000 0x1000>;
236 local-mac-address = [ 00 00 00 00 00 00 ];
237 interrupts = <32 0x8 33 0x8 34 0x8>;
238 phy-connection-type = "mii";
239 interrupt-parent = <&ipic>;
240 tbi-handle = <&tbi0>;
241 phy-handle = <&phy2>;
242 sleep = <&pmc 0xc0000000>;
243 fsl,magic-packet;
244
245 mdio@520 {
246 #address-cells = <1>;
247 #size-cells = <0>;
248 compatible = "fsl,gianfar-mdio";
249 reg = <0x520 0x20>;
250
251 phy2: ethernet-phy@2 {
252 interrupt-parent = <&ipic>;
253 interrupts = <17 0x8>;
254 reg = <0x2>;
255 device_type = "ethernet-phy";
256 };
257
258 phy3: ethernet-phy@3 {
259 interrupt-parent = <&ipic>;
260 interrupts = <18 0x8>;
261 reg = <0x3>;
262 device_type = "ethernet-phy";
263 };
264
265 tbi0: tbi-phy@11 {
266 reg = <0x11>;
267 device_type = "tbi-phy";
268 };
269 };
270 };
271
272 enet1: ethernet@25000 {
273 #address-cells = <1>;
274 #size-cells = <1>;
275 cell-index = <1>;
276 device_type = "network";
277 model = "eTSEC";
278 compatible = "gianfar";
279 reg = <0x25000 0x1000>;
280 ranges = <0x0 0x25000 0x1000>;
281 local-mac-address = [ 00 00 00 00 00 00 ];
282 interrupts = <35 0x8 36 0x8 37 0x8>;
283 phy-connection-type = "mii";
284 interrupt-parent = <&ipic>;
285 phy-handle = <&phy3>;
286 tbi-handle = <&tbi1>;
287 sleep = <&pmc 0x30000000>;
288 fsl,magic-packet;
289
290 mdio@520 {
291 #address-cells = <1>;
292 #size-cells = <0>;
293 compatible = "fsl,gianfar-tbi";
294 reg = <0x520 0x20>;
295
296 tbi1: tbi-phy@11 {
297 reg = <0x11>;
298 device_type = "tbi-phy";
299 };
300 };
301 };
302
303 serial0: serial@4500 {
304 cell-index = <0>;
305 device_type = "serial";
306 compatible = "ns16550";
307 reg = <0x4500 0x100>;
308 clock-frequency = <0>;
309 interrupts = <9 0x8>;
310 interrupt-parent = <&ipic>;
311 };
312
313 serial1: serial@4600 {
314 cell-index = <1>;
315 device_type = "serial";
316 compatible = "ns16550";
317 reg = <0x4600 0x100>;
318 clock-frequency = <0>;
319 interrupts = <10 0x8>;
320 interrupt-parent = <&ipic>;
321 };
322
323 crypto@30000 {
324 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
325 "fsl,sec2.1", "fsl,sec2.0";
326 reg = <0x30000 0x10000>;
327 interrupts = <11 0x8>;
328 interrupt-parent = <&ipic>;
329 fsl,num-channels = <4>;
330 fsl,channel-fifo-len = <24>;
331 fsl,exec-units-mask = <0x9fe>;
332 fsl,descriptor-types-mask = <0x3ab0ebf>;
333 sleep = <&pmc 0x03000000>;
334 };
335
336 sata@18000 {
337 compatible = "fsl,mpc8377-sata", "fsl,pq-sata";
338 reg = <0x18000 0x1000>;
339 interrupts = <44 0x8>;
340 interrupt-parent = <&ipic>;
341 sleep = <&pmc 0x000000c0>;
342 };
343
344 sata@19000 {
345 compatible = "fsl,mpc8377-sata", "fsl,pq-sata";
346 reg = <0x19000 0x1000>;
347 interrupts = <45 0x8>;
348 interrupt-parent = <&ipic>;
349 sleep = <&pmc 0x00000030>;
350 };
351
352 /* IPIC
353 * interrupts cell = <intr #, sense>
354 * sense values match linux IORESOURCE_IRQ_* defines:
355 * sense == 8: Level, low assertion
356 * sense == 2: Edge, high-to-low change
357 */
358 ipic: interrupt-controller@700 {
359 compatible = "fsl,ipic";
360 interrupt-controller;
361 #address-cells = <0>;
362 #interrupt-cells = <2>;
363 reg = <0x700 0x100>;
364 };
365
366 pmc: power@b00 {
367 compatible = "fsl,mpc8377-pmc", "fsl,mpc8349-pmc";
368 reg = <0xb00 0x100 0xa00 0x100>;
369 interrupts = <80 0x8>;
370 interrupt-parent = <&ipic>;
371 };
372 };
373
374 pci0: pci@e0008500 {
375 interrupt-map-mask = <0xf800 0 0 7>;
376 interrupt-map = <
377 /* IRQ5 = 21 = 0x15, IRQ6 = 0x16, IRQ7 = 23 = 0x17 */
378
379 /* IDSEL AD14 IRQ6 inta */
380 0x7000 0x0 0x0 0x1 &ipic 22 0x8
381
382 /* IDSEL AD15 IRQ5 inta */
383 0x7800 0x0 0x0 0x1 &ipic 21 0x8>;
384 interrupt-parent = <&ipic>;
385 interrupts = <66 0x8>;
386 bus-range = <0 0>;
387 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
388 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
389 0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>;
390 sleep = <&pmc 0x00010000>;
391 clock-frequency = <66666666>;
392 #interrupt-cells = <1>;
393 #size-cells = <2>;
394 #address-cells = <3>;
395 reg = <0xe0008500 0x100 /* internal registers */
396 0xe0008300 0x8>; /* config space access registers */
397 compatible = "fsl,mpc8349-pci";
398 device_type = "pci";
399 };
400
401 pci1: pcie@e0009000 {
402 #address-cells = <3>;
403 #size-cells = <2>;
404 #interrupt-cells = <1>;
405 device_type = "pci";
406 compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie";
407 reg = <0xe0009000 0x00001000>;
408 ranges = <0x02000000 0 0xa8000000 0xa8000000 0 0x10000000
409 0x01000000 0 0x00000000 0xb8000000 0 0x00800000>;
410 bus-range = <0 255>;
411 interrupt-map-mask = <0xf800 0 0 7>;
412 interrupt-map = <0 0 0 1 &ipic 1 8
413 0 0 0 2 &ipic 1 8
414 0 0 0 3 &ipic 1 8
415 0 0 0 4 &ipic 1 8>;
416 sleep = <&pmc 0x00300000>;
417 clock-frequency = <0>;
418
419 pcie@0 {
420 #address-cells = <3>;
421 #size-cells = <2>;
422 device_type = "pci";
423 reg = <0 0 0 0 0>;
424 ranges = <0x02000000 0 0xa8000000
425 0x02000000 0 0xa8000000
426 0 0x10000000
427 0x01000000 0 0x00000000
428 0x01000000 0 0x00000000
429 0 0x00800000>;
430 };
431 };
432
433 pci2: pcie@e000a000 {
434 #address-cells = <3>;
435 #size-cells = <2>;
436 #interrupt-cells = <1>;
437 device_type = "pci";
438 compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie";
439 reg = <0xe000a000 0x00001000>;
440 ranges = <0x02000000 0 0xc8000000 0xc8000000 0 0x10000000
441 0x01000000 0 0x00000000 0xd8000000 0 0x00800000>;
442 bus-range = <0 255>;
443 interrupt-map-mask = <0xf800 0 0 7>;
444 interrupt-map = <0 0 0 1 &ipic 2 8
445 0 0 0 2 &ipic 2 8
446 0 0 0 3 &ipic 2 8
447 0 0 0 4 &ipic 2 8>;
448 sleep = <&pmc 0x000c0000>;
449 clock-frequency = <0>;
450
451 pcie@0 {
452 #address-cells = <3>;
453 #size-cells = <2>;
454 device_type = "pci";
455 reg = <0 0 0 0 0>;
456 ranges = <0x02000000 0 0xc8000000
457 0x02000000 0 0xc8000000
458 0 0x10000000
459 0x01000000 0 0x00000000
460 0x01000000 0 0x00000000
461 0 0x00800000>;
462 };
463 };
464};
diff --git a/arch/powerpc/boot/dts/mpc8378_rdb.dts b/arch/powerpc/boot/dts/mpc8378_rdb.dts
index aabf3437cadf..a11ead8214b4 100644
--- a/arch/powerpc/boot/dts/mpc8378_rdb.dts
+++ b/arch/powerpc/boot/dts/mpc8378_rdb.dts
@@ -174,7 +174,7 @@
174 interrupts = <42 0x8>; 174 interrupts = <42 0x8>;
175 interrupt-parent = <&ipic>; 175 interrupt-parent = <&ipic>;
176 /* Filled in by U-Boot */ 176 /* Filled in by U-Boot */
177 clock-frequency = <0>; 177 clock-frequency = <111111111>;
178 }; 178 };
179 }; 179 };
180 180
diff --git a/arch/powerpc/boot/dts/mpc8379_rdb.dts b/arch/powerpc/boot/dts/mpc8379_rdb.dts
index 9b1da864d890..e35dfba587c8 100644
--- a/arch/powerpc/boot/dts/mpc8379_rdb.dts
+++ b/arch/powerpc/boot/dts/mpc8379_rdb.dts
@@ -172,7 +172,7 @@
172 interrupts = <42 0x8>; 172 interrupts = <42 0x8>;
173 interrupt-parent = <&ipic>; 173 interrupt-parent = <&ipic>;
174 /* Filled in by U-Boot */ 174 /* Filled in by U-Boot */
175 clock-frequency = <0>; 175 clock-frequency = <111111111>;
176 }; 176 };
177 }; 177 };
178 178
diff --git a/arch/powerpc/boot/dts/mpc8536ds.dts b/arch/powerpc/boot/dts/mpc8536ds.dts
index e781ad2f1f8a..815cebb2e3e5 100644
--- a/arch/powerpc/boot/dts/mpc8536ds.dts
+++ b/arch/powerpc/boot/dts/mpc8536ds.dts
@@ -14,8 +14,8 @@
14/ { 14/ {
15 model = "fsl,mpc8536ds"; 15 model = "fsl,mpc8536ds";
16 compatible = "fsl,mpc8536ds"; 16 compatible = "fsl,mpc8536ds";
17 #address-cells = <1>; 17 #address-cells = <2>;
18 #size-cells = <1>; 18 #size-cells = <2>;
19 19
20 aliases { 20 aliases {
21 ethernet0 = &enet0; 21 ethernet0 = &enet0;
@@ -42,7 +42,7 @@
42 42
43 memory { 43 memory {
44 device_type = "memory"; 44 device_type = "memory";
45 reg = <00000000 00000000>; // Filled by U-Boot 45 reg = <0 0 0 0>; // Filled by U-Boot
46 }; 46 };
47 47
48 soc@ffe00000 { 48 soc@ffe00000 {
@@ -50,7 +50,7 @@
50 #size-cells = <1>; 50 #size-cells = <1>;
51 device_type = "soc"; 51 device_type = "soc";
52 compatible = "simple-bus"; 52 compatible = "simple-bus";
53 ranges = <0x0 0xffe00000 0x100000>; 53 ranges = <0x0 0 0xffe00000 0x100000>;
54 bus-frequency = <0>; // Filled out by uboot. 54 bus-frequency = <0>; // Filled out by uboot.
55 55
56 ecm-law@0 { 56 ecm-law@0 {
@@ -250,6 +250,14 @@
250 phy_type = "ulpi"; 250 phy_type = "ulpi";
251 }; 251 };
252 252
253 sdhci@2e000 {
254 compatible = "fsl,mpc8536-esdhc", "fsl,esdhc";
255 reg = <0x2e000 0x1000>;
256 interrupts = <72 0x2>;
257 interrupt-parent = <&mpic>;
258 clock-frequency = <250000000>;
259 };
260
253 serial0: serial@4500 { 261 serial0: serial@4500 {
254 cell-index = <0>; 262 cell-index = <0>;
255 device_type = "serial"; 263 device_type = "serial";
@@ -347,13 +355,13 @@
347 interrupt-parent = <&mpic>; 355 interrupt-parent = <&mpic>;
348 interrupts = <24 0x2>; 356 interrupts = <24 0x2>;
349 bus-range = <0 0xff>; 357 bus-range = <0 0xff>;
350 ranges = <0x02000000 0 0x80000000 0x80000000 0 0x10000000 358 ranges = <0x02000000 0 0x80000000 0 0x80000000 0 0x10000000
351 0x01000000 0 0x00000000 0xffc00000 0 0x00010000>; 359 0x01000000 0 0x00000000 0 0xffc00000 0 0x00010000>;
352 clock-frequency = <66666666>; 360 clock-frequency = <66666666>;
353 #interrupt-cells = <1>; 361 #interrupt-cells = <1>;
354 #size-cells = <2>; 362 #size-cells = <2>;
355 #address-cells = <3>; 363 #address-cells = <3>;
356 reg = <0xffe08000 0x1000>; 364 reg = <0 0xffe08000 0 0x1000>;
357 }; 365 };
358 366
359 pci1: pcie@ffe09000 { 367 pci1: pcie@ffe09000 {
@@ -362,10 +370,10 @@
362 #interrupt-cells = <1>; 370 #interrupt-cells = <1>;
363 #size-cells = <2>; 371 #size-cells = <2>;
364 #address-cells = <3>; 372 #address-cells = <3>;
365 reg = <0xffe09000 0x1000>; 373 reg = <0 0xffe09000 0 0x1000>;
366 bus-range = <0 0xff>; 374 bus-range = <0 0xff>;
367 ranges = <0x02000000 0 0x98000000 0x98000000 0 0x08000000 375 ranges = <0x02000000 0 0x98000000 0 0x98000000 0 0x08000000
368 0x01000000 0 0x00000000 0xffc20000 0 0x00010000>; 376 0x01000000 0 0x00000000 0 0xffc20000 0 0x00010000>;
369 clock-frequency = <33333333>; 377 clock-frequency = <33333333>;
370 interrupt-parent = <&mpic>; 378 interrupt-parent = <&mpic>;
371 interrupts = <25 0x2>; 379 interrupts = <25 0x2>;
@@ -398,10 +406,10 @@
398 #interrupt-cells = <1>; 406 #interrupt-cells = <1>;
399 #size-cells = <2>; 407 #size-cells = <2>;
400 #address-cells = <3>; 408 #address-cells = <3>;
401 reg = <0xffe0a000 0x1000>; 409 reg = <0 0xffe0a000 0 0x1000>;
402 bus-range = <0 0xff>; 410 bus-range = <0 0xff>;
403 ranges = <0x02000000 0 0x90000000 0x90000000 0 0x08000000 411 ranges = <0x02000000 0 0x90000000 0 0x90000000 0 0x08000000
404 0x01000000 0 0x00000000 0xffc10000 0 0x00010000>; 412 0x01000000 0 0x00000000 0 0xffc10000 0 0x00010000>;
405 clock-frequency = <33333333>; 413 clock-frequency = <33333333>;
406 interrupt-parent = <&mpic>; 414 interrupt-parent = <&mpic>;
407 interrupts = <26 0x2>; 415 interrupts = <26 0x2>;
@@ -434,10 +442,10 @@
434 #interrupt-cells = <1>; 442 #interrupt-cells = <1>;
435 #size-cells = <2>; 443 #size-cells = <2>;
436 #address-cells = <3>; 444 #address-cells = <3>;
437 reg = <0xffe0b000 0x1000>; 445 reg = <0 0xffe0b000 0 0x1000>;
438 bus-range = <0 0xff>; 446 bus-range = <0 0xff>;
439 ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x20000000 447 ranges = <0x02000000 0 0xa0000000 0 0xa0000000 0 0x20000000
440 0x01000000 0 0x00000000 0xffc30000 0 0x00010000>; 448 0x01000000 0 0x00000000 0 0xffc30000 0 0x00010000>;
441 clock-frequency = <33333333>; 449 clock-frequency = <33333333>;
442 interrupt-parent = <&mpic>; 450 interrupt-parent = <&mpic>;
443 interrupts = <27 0x2>; 451 interrupts = <27 0x2>;
diff --git a/arch/powerpc/boot/dts/mpc8536ds_36b.dts b/arch/powerpc/boot/dts/mpc8536ds_36b.dts
new file mode 100644
index 000000000000..d95b26021e62
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc8536ds_36b.dts
@@ -0,0 +1,475 @@
1/*
2 * MPC8536 DS Device Tree Source
3 *
4 * Copyright 2008-2009 Freescale Semiconductor, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/dts-v1/;
13
14/ {
15 model = "fsl,mpc8536ds";
16 compatible = "fsl,mpc8536ds";
17 #address-cells = <2>;
18 #size-cells = <2>;
19
20 aliases {
21 ethernet0 = &enet0;
22 ethernet1 = &enet1;
23 serial0 = &serial0;
24 serial1 = &serial1;
25 pci0 = &pci0;
26 pci1 = &pci1;
27 pci2 = &pci2;
28 pci3 = &pci3;
29 };
30
31 cpus {
32 #cpus = <1>;
33 #address-cells = <1>;
34 #size-cells = <0>;
35
36 PowerPC,8536@0 {
37 device_type = "cpu";
38 reg = <0>;
39 next-level-cache = <&L2>;
40 };
41 };
42
43 memory {
44 device_type = "memory";
45 reg = <0 0 0 0>; // Filled by U-Boot
46 };
47
48 soc@fffe00000 {
49 #address-cells = <1>;
50 #size-cells = <1>;
51 device_type = "soc";
52 compatible = "simple-bus";
53 ranges = <0x0 0xf 0xffe00000 0x100000>;
54 bus-frequency = <0>; // Filled out by uboot.
55
56 ecm-law@0 {
57 compatible = "fsl,ecm-law";
58 reg = <0x0 0x1000>;
59 fsl,num-laws = <12>;
60 };
61
62 ecm@1000 {
63 compatible = "fsl,mpc8536-ecm", "fsl,ecm";
64 reg = <0x1000 0x1000>;
65 interrupts = <17 2>;
66 interrupt-parent = <&mpic>;
67 };
68
69 memory-controller@2000 {
70 compatible = "fsl,mpc8536-memory-controller";
71 reg = <0x2000 0x1000>;
72 interrupt-parent = <&mpic>;
73 interrupts = <18 0x2>;
74 };
75
76 L2: l2-cache-controller@20000 {
77 compatible = "fsl,mpc8536-l2-cache-controller";
78 reg = <0x20000 0x1000>;
79 interrupt-parent = <&mpic>;
80 interrupts = <16 0x2>;
81 };
82
83 i2c@3000 {
84 #address-cells = <1>;
85 #size-cells = <0>;
86 cell-index = <0>;
87 compatible = "fsl-i2c";
88 reg = <0x3000 0x100>;
89 interrupts = <43 0x2>;
90 interrupt-parent = <&mpic>;
91 dfsrr;
92 };
93
94 i2c@3100 {
95 #address-cells = <1>;
96 #size-cells = <0>;
97 cell-index = <1>;
98 compatible = "fsl-i2c";
99 reg = <0x3100 0x100>;
100 interrupts = <43 0x2>;
101 interrupt-parent = <&mpic>;
102 dfsrr;
103 rtc@68 {
104 compatible = "dallas,ds3232";
105 reg = <0x68>;
106 interrupts = <0 0x1>;
107 interrupt-parent = <&mpic>;
108 };
109 };
110
111 dma@21300 {
112 #address-cells = <1>;
113 #size-cells = <1>;
114 compatible = "fsl,mpc8536-dma", "fsl,eloplus-dma";
115 reg = <0x21300 4>;
116 ranges = <0 0x21100 0x200>;
117 cell-index = <0>;
118 dma-channel@0 {
119 compatible = "fsl,mpc8536-dma-channel",
120 "fsl,eloplus-dma-channel";
121 reg = <0x0 0x80>;
122 cell-index = <0>;
123 interrupt-parent = <&mpic>;
124 interrupts = <20 2>;
125 };
126 dma-channel@80 {
127 compatible = "fsl,mpc8536-dma-channel",
128 "fsl,eloplus-dma-channel";
129 reg = <0x80 0x80>;
130 cell-index = <1>;
131 interrupt-parent = <&mpic>;
132 interrupts = <21 2>;
133 };
134 dma-channel@100 {
135 compatible = "fsl,mpc8536-dma-channel",
136 "fsl,eloplus-dma-channel";
137 reg = <0x100 0x80>;
138 cell-index = <2>;
139 interrupt-parent = <&mpic>;
140 interrupts = <22 2>;
141 };
142 dma-channel@180 {
143 compatible = "fsl,mpc8536-dma-channel",
144 "fsl,eloplus-dma-channel";
145 reg = <0x180 0x80>;
146 cell-index = <3>;
147 interrupt-parent = <&mpic>;
148 interrupts = <23 2>;
149 };
150 };
151
152 usb@22000 {
153 compatible = "fsl,mpc8536-usb2-mph", "fsl-usb2-mph";
154 reg = <0x22000 0x1000>;
155 #address-cells = <1>;
156 #size-cells = <0>;
157 interrupt-parent = <&mpic>;
158 interrupts = <28 0x2>;
159 phy_type = "ulpi";
160 };
161
162 usb@23000 {
163 compatible = "fsl,mpc8536-usb2-mph", "fsl-usb2-mph";
164 reg = <0x23000 0x1000>;
165 #address-cells = <1>;
166 #size-cells = <0>;
167 interrupt-parent = <&mpic>;
168 interrupts = <46 0x2>;
169 phy_type = "ulpi";
170 };
171
172 enet0: ethernet@24000 {
173 #address-cells = <1>;
174 #size-cells = <1>;
175 cell-index = <0>;
176 device_type = "network";
177 model = "eTSEC";
178 compatible = "gianfar";
179 reg = <0x24000 0x1000>;
180 ranges = <0x0 0x24000 0x1000>;
181 local-mac-address = [ 00 00 00 00 00 00 ];
182 interrupts = <29 2 30 2 34 2>;
183 interrupt-parent = <&mpic>;
184 tbi-handle = <&tbi0>;
185 phy-handle = <&phy1>;
186 phy-connection-type = "rgmii-id";
187
188 mdio@520 {
189 #address-cells = <1>;
190 #size-cells = <0>;
191 compatible = "fsl,gianfar-mdio";
192 reg = <0x520 0x20>;
193
194 phy0: ethernet-phy@0 {
195 interrupt-parent = <&mpic>;
196 interrupts = <10 0x1>;
197 reg = <0>;
198 device_type = "ethernet-phy";
199 };
200 phy1: ethernet-phy@1 {
201 interrupt-parent = <&mpic>;
202 interrupts = <10 0x1>;
203 reg = <1>;
204 device_type = "ethernet-phy";
205 };
206 tbi0: tbi-phy@11 {
207 reg = <0x11>;
208 device_type = "tbi-phy";
209 };
210 };
211 };
212
213 enet1: ethernet@26000 {
214 #address-cells = <1>;
215 #size-cells = <1>;
216 cell-index = <1>;
217 device_type = "network";
218 model = "eTSEC";
219 compatible = "gianfar";
220 reg = <0x26000 0x1000>;
221 ranges = <0x0 0x26000 0x1000>;
222 local-mac-address = [ 00 00 00 00 00 00 ];
223 interrupts = <31 2 32 2 33 2>;
224 interrupt-parent = <&mpic>;
225 tbi-handle = <&tbi1>;
226 phy-handle = <&phy0>;
227 phy-connection-type = "rgmii-id";
228
229 mdio@520 {
230 #address-cells = <1>;
231 #size-cells = <0>;
232 compatible = "fsl,gianfar-tbi";
233 reg = <0x520 0x20>;
234
235 tbi1: tbi-phy@11 {
236 reg = <0x11>;
237 device_type = "tbi-phy";
238 };
239 };
240 };
241
242 usb@2b000 {
243 compatible = "fsl,mpc8536-usb2-dr", "fsl-usb2-dr";
244 reg = <0x2b000 0x1000>;
245 #address-cells = <1>;
246 #size-cells = <0>;
247 interrupt-parent = <&mpic>;
248 interrupts = <60 0x2>;
249 dr_mode = "peripheral";
250 phy_type = "ulpi";
251 };
252
253 sdhci@2e000 {
254 compatible = "fsl,mpc8536-esdhc", "fsl,esdhc";
255 reg = <0x2e000 0x1000>;
256 interrupts = <72 0x2>;
257 interrupt-parent = <&mpic>;
258 clock-frequency = <250000000>;
259 };
260
261 serial0: serial@4500 {
262 cell-index = <0>;
263 device_type = "serial";
264 compatible = "ns16550";
265 reg = <0x4500 0x100>;
266 clock-frequency = <0>;
267 interrupts = <42 0x2>;
268 interrupt-parent = <&mpic>;
269 };
270
271 serial1: serial@4600 {
272 cell-index = <1>;
273 device_type = "serial";
274 compatible = "ns16550";
275 reg = <0x4600 0x100>;
276 clock-frequency = <0>;
277 interrupts = <42 0x2>;
278 interrupt-parent = <&mpic>;
279 };
280
281 crypto@30000 {
282 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
283 "fsl,sec2.1", "fsl,sec2.0";
284 reg = <0x30000 0x10000>;
285 interrupts = <45 2 58 2>;
286 interrupt-parent = <&mpic>;
287 fsl,num-channels = <4>;
288 fsl,channel-fifo-len = <24>;
289 fsl,exec-units-mask = <0x9fe>;
290 fsl,descriptor-types-mask = <0x3ab0ebf>;
291 };
292
293 sata@18000 {
294 compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
295 reg = <0x18000 0x1000>;
296 cell-index = <1>;
297 interrupts = <74 0x2>;
298 interrupt-parent = <&mpic>;
299 };
300
301 sata@19000 {
302 compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
303 reg = <0x19000 0x1000>;
304 cell-index = <2>;
305 interrupts = <41 0x2>;
306 interrupt-parent = <&mpic>;
307 };
308
309 global-utilities@e0000 { //global utilities block
310 compatible = "fsl,mpc8548-guts";
311 reg = <0xe0000 0x1000>;
312 fsl,has-rstcr;
313 };
314
315 mpic: pic@40000 {
316 clock-frequency = <0>;
317 interrupt-controller;
318 #address-cells = <0>;
319 #interrupt-cells = <2>;
320 reg = <0x40000 0x40000>;
321 compatible = "chrp,open-pic";
322 device_type = "open-pic";
323 big-endian;
324 };
325
326 msi@41600 {
327 compatible = "fsl,mpc8536-msi", "fsl,mpic-msi";
328 reg = <0x41600 0x80>;
329 msi-available-ranges = <0 0x100>;
330 interrupts = <
331 0xe0 0
332 0xe1 0
333 0xe2 0
334 0xe3 0
335 0xe4 0
336 0xe5 0
337 0xe6 0
338 0xe7 0>;
339 interrupt-parent = <&mpic>;
340 };
341 };
342
343 pci0: pci@fffe08000 {
344 compatible = "fsl,mpc8540-pci";
345 device_type = "pci";
346 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
347 interrupt-map = <
348
349 /* IDSEL 0x11 J17 Slot 1 */
350 0x8800 0 0 1 &mpic 1 1
351 0x8800 0 0 2 &mpic 2 1
352 0x8800 0 0 3 &mpic 3 1
353 0x8800 0 0 4 &mpic 4 1>;
354
355 interrupt-parent = <&mpic>;
356 interrupts = <24 0x2>;
357 bus-range = <0 0xff>;
358 ranges = <0x02000000 0 0xf0000000 0xc 0x00000000 0 0x10000000
359 0x01000000 0 0x00000000 0xf 0xffc00000 0 0x00010000>;
360 clock-frequency = <66666666>;
361 #interrupt-cells = <1>;
362 #size-cells = <2>;
363 #address-cells = <3>;
364 reg = <0xf 0xffe08000 0 0x1000>;
365 };
366
367 pci1: pcie@fffe09000 {
368 compatible = "fsl,mpc8548-pcie";
369 device_type = "pci";
370 #interrupt-cells = <1>;
371 #size-cells = <2>;
372 #address-cells = <3>;
373 reg = <0xf 0xffe09000 0 0x1000>;
374 bus-range = <0 0xff>;
375 ranges = <0x02000000 0 0xf8000000 0xc 0x18000000 0 0x08000000
376 0x01000000 0 0x00000000 0xf 0xffc20000 0 0x00010000>;
377 clock-frequency = <33333333>;
378 interrupt-parent = <&mpic>;
379 interrupts = <25 0x2>;
380 interrupt-map-mask = <0xf800 0 0 7>;
381 interrupt-map = <
382 /* IDSEL 0x0 */
383 0000 0 0 1 &mpic 4 1
384 0000 0 0 2 &mpic 5 1
385 0000 0 0 3 &mpic 6 1
386 0000 0 0 4 &mpic 7 1
387 >;
388 pcie@0 {
389 reg = <0 0 0 0 0>;
390 #size-cells = <2>;
391 #address-cells = <3>;
392 device_type = "pci";
393 ranges = <0x02000000 0 0xf8000000
394 0x02000000 0 0xf8000000
395 0 0x08000000
396
397 0x01000000 0 0x00000000
398 0x01000000 0 0x00000000
399 0 0x00010000>;
400 };
401 };
402
403 pci2: pcie@fffe0a000 {
404 compatible = "fsl,mpc8548-pcie";
405 device_type = "pci";
406 #interrupt-cells = <1>;
407 #size-cells = <2>;
408 #address-cells = <3>;
409 reg = <0xf 0xffe0a000 0 0x1000>;
410 bus-range = <0 0xff>;
411 ranges = <0x02000000 0 0xf8000000 0xc 0x10000000 0 0x08000000
412 0x01000000 0 0x00000000 0xf 0xffc10000 0 0x00010000>;
413 clock-frequency = <33333333>;
414 interrupt-parent = <&mpic>;
415 interrupts = <26 0x2>;
416 interrupt-map-mask = <0xf800 0 0 7>;
417 interrupt-map = <
418 /* IDSEL 0x0 */
419 0000 0 0 1 &mpic 0 1
420 0000 0 0 2 &mpic 1 1
421 0000 0 0 3 &mpic 2 1
422 0000 0 0 4 &mpic 3 1
423 >;
424 pcie@0 {
425 reg = <0 0 0 0 0>;
426 #size-cells = <2>;
427 #address-cells = <3>;
428 device_type = "pci";
429 ranges = <0x02000000 0 0xf8000000
430 0x02000000 0 0xf8000000
431 0 0x08000000
432
433 0x01000000 0 0x00000000
434 0x01000000 0 0x00000000
435 0 0x00010000>;
436 };
437 };
438
439 pci3: pcie@fffe0b000 {
440 compatible = "fsl,mpc8548-pcie";
441 device_type = "pci";
442 #interrupt-cells = <1>;
443 #size-cells = <2>;
444 #address-cells = <3>;
445 reg = <0xf 0xffe0b000 0 0x1000>;
446 bus-range = <0 0xff>;
447 ranges = <0x02000000 0 0xe0000000 0xc 0x20000000 0 0x20000000
448 0x01000000 0 0x00000000 0xf 0xffc30000 0 0x00010000>;
449 clock-frequency = <33333333>;
450 interrupt-parent = <&mpic>;
451 interrupts = <27 0x2>;
452 interrupt-map-mask = <0xf800 0 0 7>;
453 interrupt-map = <
454 /* IDSEL 0x0 */
455 0000 0 0 1 &mpic 8 1
456 0000 0 0 2 &mpic 9 1
457 0000 0 0 3 &mpic 10 1
458 0000 0 0 4 &mpic 11 1
459 >;
460
461 pcie@0 {
462 reg = <0 0 0 0 0>;
463 #size-cells = <2>;
464 #address-cells = <3>;
465 device_type = "pci";
466 ranges = <0x02000000 0 0xe0000000
467 0x02000000 0 0xe0000000
468 0 0x20000000
469
470 0x01000000 0 0x00000000
471 0x01000000 0 0x00000000
472 0 0x00100000>;
473 };
474 };
475};
diff --git a/arch/powerpc/boot/dts/mpc8548cds.dts b/arch/powerpc/boot/dts/mpc8548cds.dts
index 475be1433fe1..4173af387c63 100644
--- a/arch/powerpc/boot/dts/mpc8548cds.dts
+++ b/arch/powerpc/boot/dts/mpc8548cds.dts
@@ -100,6 +100,21 @@
100 interrupts = <43 2>; 100 interrupts = <43 2>;
101 interrupt-parent = <&mpic>; 101 interrupt-parent = <&mpic>;
102 dfsrr; 102 dfsrr;
103
104 eeprom@50 {
105 compatible = "atmel,24c64";
106 reg = <0x50>;
107 };
108
109 eeprom@56 {
110 compatible = "atmel,24c64";
111 reg = <0x56>;
112 };
113
114 eeprom@57 {
115 compatible = "atmel,24c64";
116 reg = <0x57>;
117 };
103 }; 118 };
104 119
105 i2c@3100 { 120 i2c@3100 {
@@ -111,6 +126,11 @@
111 interrupts = <43 2>; 126 interrupts = <43 2>;
112 interrupt-parent = <&mpic>; 127 interrupt-parent = <&mpic>;
113 dfsrr; 128 dfsrr;
129
130 eeprom@50 {
131 compatible = "atmel,24c64";
132 reg = <0x50>;
133 };
114 }; 134 };
115 135
116 dma@21300 { 136 dma@21300 {
diff --git a/arch/powerpc/boot/dts/mpc8569mds.dts b/arch/powerpc/boot/dts/mpc8569mds.dts
index 9e4ce99e1613..06332d61830a 100644
--- a/arch/powerpc/boot/dts/mpc8569mds.dts
+++ b/arch/powerpc/boot/dts/mpc8569mds.dts
@@ -99,8 +99,18 @@
99 }; 99 };
100 100
101 bcsr@1,0 { 101 bcsr@1,0 {
102 #address-cells = <1>;
103 #size-cells = <1>;
102 compatible = "fsl,mpc8569mds-bcsr"; 104 compatible = "fsl,mpc8569mds-bcsr";
103 reg = <1 0 0x8000>; 105 reg = <1 0 0x8000>;
106 ranges = <0 1 0 0x8000>;
107
108 bcsr17: gpio-controller@11 {
109 #gpio-cells = <2>;
110 compatible = "fsl,mpc8569mds-bcsr-gpio";
111 reg = <0x11 0x1>;
112 gpio-controller;
113 };
104 }; 114 };
105 115
106 nand@3,0 { 116 nand@3,0 {
@@ -315,6 +325,14 @@
315 gpio-controller; 325 gpio-controller;
316 }; 326 };
317 327
328 qe_pio_f: gpio-controller@a0 {
329 #gpio-cells = <2>;
330 compatible = "fsl,mpc8569-qe-pario-bank",
331 "fsl,mpc8323-qe-pario-bank";
332 reg = <0xa0 0x18>;
333 gpio-controller;
334 };
335
318 pio1: ucc_pin@01 { 336 pio1: ucc_pin@01 {
319 pio-map = < 337 pio-map = <
320 /* port pin dir open_drain assignment has_irq */ 338 /* port pin dir open_drain assignment has_irq */
@@ -419,6 +437,16 @@
419 interrupt-parent = <&mpic>; 437 interrupt-parent = <&mpic>;
420 }; 438 };
421 439
440 timer@440 {
441 compatible = "fsl,mpc8569-qe-gtm",
442 "fsl,qe-gtm", "fsl,gtm";
443 reg = <0x440 0x40>;
444 interrupts = <12 13 14 15>;
445 interrupt-parent = <&qeic>;
446 /* Filled in by U-Boot */
447 clock-frequency = <0>;
448 };
449
422 spi@4c0 { 450 spi@4c0 {
423 #address-cells = <1>; 451 #address-cells = <1>;
424 #size-cells = <0>; 452 #size-cells = <0>;
@@ -446,6 +474,23 @@
446 mode = "cpu"; 474 mode = "cpu";
447 }; 475 };
448 476
477 usb@6c0 {
478 compatible = "fsl,mpc8569-qe-usb",
479 "fsl,mpc8323-qe-usb";
480 reg = <0x6c0 0x40 0x8b00 0x100>;
481 interrupts = <11>;
482 interrupt-parent = <&qeic>;
483 fsl,fullspeed-clock = "clk5";
484 fsl,lowspeed-clock = "brg10";
485 gpios = <&qe_pio_f 3 0 /* USBOE */
486 &qe_pio_f 4 0 /* USBTP */
487 &qe_pio_f 5 0 /* USBTN */
488 &qe_pio_f 6 0 /* USBRP */
489 &qe_pio_f 8 0 /* USBRN */
490 &bcsr17 6 0 /* SPEED */
491 &bcsr17 5 1>; /* POWER */
492 };
493
449 enet0: ucc@2000 { 494 enet0: ucc@2000 {
450 device_type = "network"; 495 device_type = "network";
451 compatible = "ucc_geth"; 496 compatible = "ucc_geth";
diff --git a/arch/powerpc/boot/dts/p2020rdb.dts b/arch/powerpc/boot/dts/p2020rdb.dts
new file mode 100644
index 000000000000..da4cb0d8d215
--- /dev/null
+++ b/arch/powerpc/boot/dts/p2020rdb.dts
@@ -0,0 +1,586 @@
1/*
2 * P2020 RDB Device Tree Source
3 *
4 * Copyright 2009 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/dts-v1/;
13/ {
14 model = "fsl,P2020";
15 compatible = "fsl,P2020RDB";
16 #address-cells = <2>;
17 #size-cells = <2>;
18
19 aliases {
20 ethernet0 = &enet0;
21 ethernet1 = &enet1;
22 ethernet2 = &enet2;
23 serial0 = &serial0;
24 serial1 = &serial1;
25 pci0 = &pci0;
26 pci1 = &pci1;
27 };
28
29 cpus {
30 #address-cells = <1>;
31 #size-cells = <0>;
32
33 PowerPC,P2020@0 {
34 device_type = "cpu";
35 reg = <0x0>;
36 next-level-cache = <&L2>;
37 };
38
39 PowerPC,P2020@1 {
40 device_type = "cpu";
41 reg = <0x1>;
42 next-level-cache = <&L2>;
43 };
44 };
45
46 memory {
47 device_type = "memory";
48 };
49
50 localbus@ffe05000 {
51 #address-cells = <2>;
52 #size-cells = <1>;
53 compatible = "fsl,p2020-elbc", "fsl,elbc", "simple-bus";
54 reg = <0 0xffe05000 0 0x1000>;
55 interrupts = <19 2>;
56 interrupt-parent = <&mpic>;
57
58 /* NOR and NAND Flashes */
59 ranges = <0x0 0x0 0x0 0xef000000 0x01000000
60 0x1 0x0 0x0 0xffa00000 0x00040000
61 0x2 0x0 0x0 0xffb00000 0x00020000>;
62
63 nor@0,0 {
64 #address-cells = <1>;
65 #size-cells = <1>;
66 compatible = "cfi-flash";
67 reg = <0x0 0x0 0x1000000>;
68 bank-width = <2>;
69 device-width = <1>;
70
71 partition@0 {
72 /* This location must not be altered */
73 /* 256KB for Vitesse 7385 Switch firmware */
74 reg = <0x0 0x00040000>;
75 label = "NOR (RO) Vitesse-7385 Firmware";
76 read-only;
77 };
78
79 partition@40000 {
80 /* 256KB for DTB Image */
81 reg = <0x00040000 0x00040000>;
82 label = "NOR (RO) DTB Image";
83 read-only;
84 };
85
86 partition@80000 {
87 /* 3.5 MB for Linux Kernel Image */
88 reg = <0x00080000 0x00380000>;
89 label = "NOR (RO) Linux Kernel Image";
90 read-only;
91 };
92
93 partition@400000 {
94 /* 11MB for JFFS2 based Root file System */
95 reg = <0x00400000 0x00b00000>;
96 label = "NOR (RW) JFFS2 Root File System";
97 };
98
99 partition@f00000 {
100 /* This location must not be altered */
101 /* 512KB for u-boot Bootloader Image */
102 /* 512KB for u-boot Environment Variables */
103 reg = <0x00f00000 0x00100000>;
104 label = "NOR (RO) U-Boot Image";
105 read-only;
106 };
107 };
108
109 nand@1,0 {
110 #address-cells = <1>;
111 #size-cells = <1>;
112 compatible = "fsl,p2020-fcm-nand",
113 "fsl,elbc-fcm-nand";
114 reg = <0x1 0x0 0x40000>;
115
116 partition@0 {
117 /* This location must not be altered */
118 /* 1MB for u-boot Bootloader Image */
119 reg = <0x0 0x00100000>;
120 label = "NAND (RO) U-Boot Image";
121 read-only;
122 };
123
124 partition@100000 {
125 /* 1MB for DTB Image */
126 reg = <0x00100000 0x00100000>;
127 label = "NAND (RO) DTB Image";
128 read-only;
129 };
130
131 partition@200000 {
132 /* 4MB for Linux Kernel Image */
133 reg = <0x00200000 0x00400000>;
134 label = "NAND (RO) Linux Kernel Image";
135 read-only;
136 };
137
138 partition@600000 {
139 /* 4MB for Compressed Root file System Image */
140 reg = <0x00600000 0x00400000>;
141 label = "NAND (RO) Compressed RFS Image";
142 read-only;
143 };
144
145 partition@a00000 {
146 /* 7MB for JFFS2 based Root file System */
147 reg = <0x00a00000 0x00700000>;
148 label = "NAND (RW) JFFS2 Root File System";
149 };
150
151 partition@1100000 {
152 /* 15MB for JFFS2 based Root file System */
153 reg = <0x01100000 0x00f00000>;
154 label = "NAND (RW) Writable User area";
155 };
156 };
157
158 L2switch@2,0 {
159 #address-cells = <1>;
160 #size-cells = <1>;
161 compatible = "vitesse-7385";
162 reg = <0x2 0x0 0x20000>;
163 };
164
165 };
166
167 soc@ffe00000 {
168 #address-cells = <1>;
169 #size-cells = <1>;
170 device_type = "soc";
171 compatible = "fsl,p2020-immr", "simple-bus";
172 ranges = <0x0 0x0 0xffe00000 0x100000>;
173 bus-frequency = <0>; // Filled out by uboot.
174
175 ecm-law@0 {
176 compatible = "fsl,ecm-law";
177 reg = <0x0 0x1000>;
178 fsl,num-laws = <12>;
179 };
180
181 ecm@1000 {
182 compatible = "fsl,p2020-ecm", "fsl,ecm";
183 reg = <0x1000 0x1000>;
184 interrupts = <17 2>;
185 interrupt-parent = <&mpic>;
186 };
187
188 memory-controller@2000 {
189 compatible = "fsl,p2020-memory-controller";
190 reg = <0x2000 0x1000>;
191 interrupt-parent = <&mpic>;
192 interrupts = <18 2>;
193 };
194
195 i2c@3000 {
196 #address-cells = <1>;
197 #size-cells = <0>;
198 cell-index = <0>;
199 compatible = "fsl-i2c";
200 reg = <0x3000 0x100>;
201 interrupts = <43 2>;
202 interrupt-parent = <&mpic>;
203 dfsrr;
204 rtc@68 {
205 compatible = "dallas,ds1339";
206 reg = <0x68>;
207 };
208 };
209
210 i2c@3100 {
211 #address-cells = <1>;
212 #size-cells = <0>;
213 cell-index = <1>;
214 compatible = "fsl-i2c";
215 reg = <0x3100 0x100>;
216 interrupts = <43 2>;
217 interrupt-parent = <&mpic>;
218 dfsrr;
219 };
220
221 serial0: serial@4500 {
222 cell-index = <0>;
223 device_type = "serial";
224 compatible = "ns16550";
225 reg = <0x4500 0x100>;
226 clock-frequency = <0>;
227 interrupts = <42 2>;
228 interrupt-parent = <&mpic>;
229 };
230
231 serial1: serial@4600 {
232 cell-index = <1>;
233 device_type = "serial";
234 compatible = "ns16550";
235 reg = <0x4600 0x100>;
236 clock-frequency = <0>;
237 interrupts = <42 2>;
238 interrupt-parent = <&mpic>;
239 };
240
241 spi@7000 {
242 cell-index = <0>;
243 #address-cells = <1>;
244 #size-cells = <0>;
245 compatible = "fsl,espi";
246 reg = <0x7000 0x1000>;
247 interrupts = <59 0x2>;
248 interrupt-parent = <&mpic>;
249 mode = "cpu";
250
251 fsl_m25p80@0 {
252 #address-cells = <1>;
253 #size-cells = <1>;
254 compatible = "fsl,espi-flash";
255 reg = <0>;
256 linux,modalias = "fsl_m25p80";
257 modal = "s25sl128b";
258 spi-max-frequency = <50000000>;
259 mode = <0>;
260
261 partition@0 {
262 /* 512KB for u-boot Bootloader Image */
263 reg = <0x0 0x00080000>;
264 label = "SPI (RO) U-Boot Image";
265 read-only;
266 };
267
268 partition@80000 {
269 /* 512KB for DTB Image */
270 reg = <0x00080000 0x00080000>;
271 label = "SPI (RO) DTB Image";
272 read-only;
273 };
274
275 partition@100000 {
276 /* 4MB for Linux Kernel Image */
277 reg = <0x00100000 0x00400000>;
278 label = "SPI (RO) Linux Kernel Image";
279 read-only;
280 };
281
282 partition@500000 {
283 /* 4MB for Compressed RFS Image */
284 reg = <0x00500000 0x00400000>;
285 label = "SPI (RO) Compressed RFS Image";
286 read-only;
287 };
288
289 partition@900000 {
290 /* 7MB for JFFS2 based RFS */
291 reg = <0x00900000 0x00700000>;
292 label = "SPI (RW) JFFS2 RFS";
293 };
294 };
295 };
296
297 dma@c300 {
298 #address-cells = <1>;
299 #size-cells = <1>;
300 compatible = "fsl,eloplus-dma";
301 reg = <0xc300 0x4>;
302 ranges = <0x0 0xc100 0x200>;
303 cell-index = <1>;
304 dma-channel@0 {
305 compatible = "fsl,eloplus-dma-channel";
306 reg = <0x0 0x80>;
307 cell-index = <0>;
308 interrupt-parent = <&mpic>;
309 interrupts = <76 2>;
310 };
311 dma-channel@80 {
312 compatible = "fsl,eloplus-dma-channel";
313 reg = <0x80 0x80>;
314 cell-index = <1>;
315 interrupt-parent = <&mpic>;
316 interrupts = <77 2>;
317 };
318 dma-channel@100 {
319 compatible = "fsl,eloplus-dma-channel";
320 reg = <0x100 0x80>;
321 cell-index = <2>;
322 interrupt-parent = <&mpic>;
323 interrupts = <78 2>;
324 };
325 dma-channel@180 {
326 compatible = "fsl,eloplus-dma-channel";
327 reg = <0x180 0x80>;
328 cell-index = <3>;
329 interrupt-parent = <&mpic>;
330 interrupts = <79 2>;
331 };
332 };
333
334 gpio: gpio-controller@f000 {
335 #gpio-cells = <2>;
336 compatible = "fsl,mpc8572-gpio";
337 reg = <0xf000 0x100>;
338 interrupts = <47 0x2>;
339 interrupt-parent = <&mpic>;
340 gpio-controller;
341 };
342
343 L2: l2-cache-controller@20000 {
344 compatible = "fsl,p2020-l2-cache-controller";
345 reg = <0x20000 0x1000>;
346 cache-line-size = <32>; // 32 bytes
347 cache-size = <0x80000>; // L2,512K
348 interrupt-parent = <&mpic>;
349 interrupts = <16 2>;
350 };
351
352 dma@21300 {
353 #address-cells = <1>;
354 #size-cells = <1>;
355 compatible = "fsl,eloplus-dma";
356 reg = <0x21300 0x4>;
357 ranges = <0x0 0x21100 0x200>;
358 cell-index = <0>;
359 dma-channel@0 {
360 compatible = "fsl,eloplus-dma-channel";
361 reg = <0x0 0x80>;
362 cell-index = <0>;
363 interrupt-parent = <&mpic>;
364 interrupts = <20 2>;
365 };
366 dma-channel@80 {
367 compatible = "fsl,eloplus-dma-channel";
368 reg = <0x80 0x80>;
369 cell-index = <1>;
370 interrupt-parent = <&mpic>;
371 interrupts = <21 2>;
372 };
373 dma-channel@100 {
374 compatible = "fsl,eloplus-dma-channel";
375 reg = <0x100 0x80>;
376 cell-index = <2>;
377 interrupt-parent = <&mpic>;
378 interrupts = <22 2>;
379 };
380 dma-channel@180 {
381 compatible = "fsl,eloplus-dma-channel";
382 reg = <0x180 0x80>;
383 cell-index = <3>;
384 interrupt-parent = <&mpic>;
385 interrupts = <23 2>;
386 };
387 };
388
389 usb@22000 {
390 #address-cells = <1>;
391 #size-cells = <0>;
392 compatible = "fsl-usb2-dr";
393 reg = <0x22000 0x1000>;
394 interrupt-parent = <&mpic>;
395 interrupts = <28 0x2>;
396 phy_type = "ulpi";
397 };
398
399 enet0: ethernet@24000 {
400 #address-cells = <1>;
401 #size-cells = <1>;
402 cell-index = <0>;
403 device_type = "network";
404 model = "eTSEC";
405 compatible = "gianfar";
406 reg = <0x24000 0x1000>;
407 ranges = <0x0 0x24000 0x1000>;
408 local-mac-address = [ 00 00 00 00 00 00 ];
409 interrupts = <29 2 30 2 34 2>;
410 interrupt-parent = <&mpic>;
411 fixed-link = <1 1 1000 0 0>;
412 phy-connection-type = "rgmii-id";
413
414 mdio@520 {
415 #address-cells = <1>;
416 #size-cells = <0>;
417 compatible = "fsl,gianfar-mdio";
418 reg = <0x520 0x20>;
419
420 phy0: ethernet-phy@0 {
421 interrupt-parent = <&mpic>;
422 interrupts = <3 1>;
423 reg = <0x0>;
424 };
425 phy1: ethernet-phy@1 {
426 interrupt-parent = <&mpic>;
427 interrupts = <3 1>;
428 reg = <0x1>;
429 };
430 };
431 };
432
433 enet1: ethernet@25000 {
434 #address-cells = <1>;
435 #size-cells = <1>;
436 cell-index = <1>;
437 device_type = "network";
438 model = "eTSEC";
439 compatible = "gianfar";
440 reg = <0x25000 0x1000>;
441 ranges = <0x0 0x25000 0x1000>;
442 local-mac-address = [ 00 00 00 00 00 00 ];
443 interrupts = <35 2 36 2 40 2>;
444 interrupt-parent = <&mpic>;
445 tbi-handle = <&tbi0>;
446 phy-handle = <&phy0>;
447 phy-connection-type = "sgmii";
448
449 mdio@520 {
450 #address-cells = <1>;
451 #size-cells = <0>;
452 compatible = "fsl,gianfar-tbi";
453 reg = <0x520 0x20>;
454
455 tbi0: tbi-phy@11 {
456 reg = <0x11>;
457 device_type = "tbi-phy";
458 };
459 };
460 };
461
462 enet2: ethernet@26000 {
463 #address-cells = <1>;
464 #size-cells = <1>;
465 cell-index = <2>;
466 device_type = "network";
467 model = "eTSEC";
468 compatible = "gianfar";
469 reg = <0x26000 0x1000>;
470 ranges = <0x0 0x26000 0x1000>;
471 local-mac-address = [ 00 00 00 00 00 00 ];
472 interrupts = <31 2 32 2 33 2>;
473 interrupt-parent = <&mpic>;
474 phy-handle = <&phy1>;
475 phy-connection-type = "rgmii-id";
476 };
477
478 sdhci@2e000 {
479 compatible = "fsl,p2020-esdhc", "fsl,esdhc";
480 reg = <0x2e000 0x1000>;
481 interrupts = <72 0x2>;
482 interrupt-parent = <&mpic>;
483 /* Filled in by U-Boot */
484 clock-frequency = <0>;
485 };
486
487 crypto@30000 {
488 compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
489 "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
490 reg = <0x30000 0x10000>;
491 interrupts = <45 2 58 2>;
492 interrupt-parent = <&mpic>;
493 fsl,num-channels = <4>;
494 fsl,channel-fifo-len = <24>;
495 fsl,exec-units-mask = <0xbfe>;
496 fsl,descriptor-types-mask = <0x3ab0ebf>;
497 };
498
499 mpic: pic@40000 {
500 interrupt-controller;
501 #address-cells = <0>;
502 #interrupt-cells = <2>;
503 reg = <0x40000 0x40000>;
504 compatible = "chrp,open-pic";
505 device_type = "open-pic";
506 };
507
508 msi@41600 {
509 compatible = "fsl,p2020-msi", "fsl,mpic-msi";
510 reg = <0x41600 0x80>;
511 msi-available-ranges = <0 0x100>;
512 interrupts = <
513 0xe0 0
514 0xe1 0
515 0xe2 0
516 0xe3 0
517 0xe4 0
518 0xe5 0
519 0xe6 0
520 0xe7 0>;
521 interrupt-parent = <&mpic>;
522 };
523
524 global-utilities@e0000 { //global utilities block
525 compatible = "fsl,p2020-guts";
526 reg = <0xe0000 0x1000>;
527 fsl,has-rstcr;
528 };
529 };
530
531 pci0: pcie@ffe09000 {
532 compatible = "fsl,mpc8548-pcie";
533 device_type = "pci";
534 #interrupt-cells = <1>;
535 #size-cells = <2>;
536 #address-cells = <3>;
537 reg = <0 0xffe09000 0 0x1000>;
538 bus-range = <0 255>;
539 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
540 0x1000000 0x0 0x00000000 0 0xffc30000 0x0 0x10000>;
541 clock-frequency = <33333333>;
542 interrupt-parent = <&mpic>;
543 interrupts = <25 2>;
544 pcie@0 {
545 reg = <0x0 0x0 0x0 0x0 0x0>;
546 #size-cells = <2>;
547 #address-cells = <3>;
548 device_type = "pci";
549 ranges = <0x2000000 0x0 0xa0000000
550 0x2000000 0x0 0xa0000000
551 0x0 0x20000000
552
553 0x1000000 0x0 0x0
554 0x1000000 0x0 0x0
555 0x0 0x100000>;
556 };
557 };
558
559 pci1: pcie@ffe0a000 {
560 compatible = "fsl,mpc8548-pcie";
561 device_type = "pci";
562 #interrupt-cells = <1>;
563 #size-cells = <2>;
564 #address-cells = <3>;
565 reg = <0 0xffe0a000 0 0x1000>;
566 bus-range = <0 255>;
567 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
568 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
569 clock-frequency = <33333333>;
570 interrupt-parent = <&mpic>;
571 interrupts = <26 2>;
572 pcie@0 {
573 reg = <0x0 0x0 0x0 0x0 0x0>;
574 #size-cells = <2>;
575 #address-cells = <3>;
576 device_type = "pci";
577 ranges = <0x2000000 0x0 0xc0000000
578 0x2000000 0x0 0xc0000000
579 0x0 0x20000000
580
581 0x1000000 0x0 0x0
582 0x1000000 0x0 0x0
583 0x0 0x100000>;
584 };
585 };
586};
diff --git a/arch/powerpc/boot/dts/sbc8349.dts b/arch/powerpc/boot/dts/sbc8349.dts
index 2d9fa68f641c..0dc90f9bd814 100644
--- a/arch/powerpc/boot/dts/sbc8349.dts
+++ b/arch/powerpc/boot/dts/sbc8349.dts
@@ -146,18 +146,6 @@
146 phy_type = "ulpi"; 146 phy_type = "ulpi";
147 port0; 147 port0;
148 }; 148 };
149 /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
150 usb@23000 {
151 device_type = "usb";
152 compatible = "fsl-usb2-dr";
153 reg = <0x23000 0x1000>;
154 #address-cells = <1>;
155 #size-cells = <0>;
156 interrupt-parent = <&ipic>;
157 interrupts = <38 0x8>;
158 dr_mode = "otg";
159 phy_type = "ulpi";
160 };
161 149
162 enet0: ethernet@24000 { 150 enet0: ethernet@24000 {
163 #address-cells = <1>; 151 #address-cells = <1>;
@@ -277,15 +265,55 @@
277 }; 265 };
278 }; 266 };
279 267
268 localbus@e0005000 {
269 #address-cells = <2>;
270 #size-cells = <1>;
271 compatible = "fsl,mpc8349-localbus", "simple-bus";
272 reg = <0xe0005000 0x1000>;
273 interrupts = <77 0x8>;
274 interrupt-parent = <&ipic>;
275 ranges = <0x0 0x0 0xff800000 0x00800000 /* 8MB Flash */
276 0x1 0x0 0xf8000000 0x00002000 /* 8KB EEPROM */
277 0x2 0x0 0x10000000 0x04000000 /* 64MB SDRAM */
278 0x3 0x0 0x10000000 0x04000000>; /* 64MB SDRAM */
279
280 flash@0,0 {
281 #address-cells = <1>;
282 #size-cells = <1>;
283 compatible = "intel,28F640J3A", "cfi-flash";
284 reg = <0x0 0x0 0x800000>;
285 bank-width = <2>;
286 device-width = <1>;
287
288 partition@0 {
289 label = "u-boot";
290 reg = <0x00000000 0x00040000>;
291 read-only;
292 };
293
294 partition@40000 {
295 label = "user";
296 reg = <0x00040000 0x006c0000>;
297 };
298
299 partition@700000 {
300 label = "legacy u-boot";
301 reg = <0x00700000 0x00100000>;
302 read-only;
303 };
304
305 };
306 };
307
280 pci0: pci@e0008500 { 308 pci0: pci@e0008500 {
281 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 309 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
282 interrupt-map = < 310 interrupt-map = <
283 311
284 /* IDSEL 0x11 */ 312 /* IDSEL 0x11 */
285 0x8800 0x0 0x0 0x1 &ipic 20 0x8 313 0x8800 0x0 0x0 0x1 &ipic 48 0x8
286 0x8800 0x0 0x0 0x2 &ipic 21 0x8 314 0x8800 0x0 0x0 0x2 &ipic 17 0x8
287 0x8800 0x0 0x0 0x3 &ipic 22 0x8 315 0x8800 0x0 0x0 0x3 &ipic 18 0x8
288 0x8800 0x0 0x0 0x4 &ipic 23 0x8>; 316 0x8800 0x0 0x0 0x4 &ipic 19 0x8>;
289 317
290 interrupt-parent = <&ipic>; 318 interrupt-parent = <&ipic>;
291 interrupts = <0x42 0x8>; 319 interrupts = <0x42 0x8>;
diff --git a/arch/powerpc/boot/dts/sbc8560.dts b/arch/powerpc/boot/dts/sbc8560.dts
index 239d57a55cf4..9e13ed8a1193 100644
--- a/arch/powerpc/boot/dts/sbc8560.dts
+++ b/arch/powerpc/boot/dts/sbc8560.dts
@@ -303,7 +303,6 @@
303 global-utilities@e0000 { 303 global-utilities@e0000 {
304 compatible = "fsl,mpc8560-guts"; 304 compatible = "fsl,mpc8560-guts";
305 reg = <0xe0000 0x1000>; 305 reg = <0xe0000 0x1000>;
306 fsl,has-rstcr;
307 }; 306 };
308 }; 307 };
309 308
diff --git a/arch/powerpc/boot/mktree.c b/arch/powerpc/boot/mktree.c
index c2baae0a3d89..e2ae24340fc8 100644
--- a/arch/powerpc/boot/mktree.c
+++ b/arch/powerpc/boot/mktree.c
@@ -36,7 +36,7 @@ typedef struct boot_block {
36} boot_block_t; 36} boot_block_t;
37 37
38#define IMGBLK 512 38#define IMGBLK 512
39char tmpbuf[IMGBLK]; 39unsigned int tmpbuf[IMGBLK / sizeof(unsigned int)];
40 40
41int main(int argc, char *argv[]) 41int main(int argc, char *argv[])
42{ 42{
@@ -95,13 +95,13 @@ int main(int argc, char *argv[])
95 95
96 /* Assume zImage is an ELF file, and skip the 64K header. 96 /* Assume zImage is an ELF file, and skip the 64K header.
97 */ 97 */
98 if (read(in_fd, tmpbuf, IMGBLK) != IMGBLK) { 98 if (read(in_fd, tmpbuf, sizeof(tmpbuf)) != sizeof(tmpbuf)) {
99 fprintf(stderr, "%s is too small to be an ELF image\n", 99 fprintf(stderr, "%s is too small to be an ELF image\n",
100 argv[1]); 100 argv[1]);
101 exit(4); 101 exit(4);
102 } 102 }
103 103
104 if ((*(unsigned int *)tmpbuf) != htonl(0x7f454c46)) { 104 if (tmpbuf[0] != htonl(0x7f454c46)) {
105 fprintf(stderr, "%s is not an ELF image\n", argv[1]); 105 fprintf(stderr, "%s is not an ELF image\n", argv[1]);
106 exit(4); 106 exit(4);
107 } 107 }
@@ -121,11 +121,11 @@ int main(int argc, char *argv[])
121 } 121 }
122 122
123 while (nblks-- > 0) { 123 while (nblks-- > 0) {
124 if (read(in_fd, tmpbuf, IMGBLK) < 0) { 124 if (read(in_fd, tmpbuf, sizeof(tmpbuf)) < 0) {
125 perror("zImage read"); 125 perror("zImage read");
126 exit(5); 126 exit(5);
127 } 127 }
128 cp = (unsigned int *)tmpbuf; 128 cp = tmpbuf;
129 for (i = 0; i < sizeof(tmpbuf) / sizeof(unsigned int); i++) 129 for (i = 0; i < sizeof(tmpbuf) / sizeof(unsigned int); i++)
130 cksum += *cp++; 130 cksum += *cp++;
131 if (write(out_fd, tmpbuf, sizeof(tmpbuf)) != sizeof(tmpbuf)) { 131 if (write(out_fd, tmpbuf, sizeof(tmpbuf)) != sizeof(tmpbuf)) {
diff --git a/arch/powerpc/boot/ppcboot-hotfoot.h b/arch/powerpc/boot/ppcboot-hotfoot.h
new file mode 100644
index 000000000000..1a3e80b533da
--- /dev/null
+++ b/arch/powerpc/boot/ppcboot-hotfoot.h
@@ -0,0 +1,133 @@
1/*
2 * This interface is used for compatibility with old U-boots *ONLY*.
3 * Please do not imitate or extend this.
4 */
5
6/*
7 * Unfortunately, the ESTeem Hotfoot board uses a mangled version of
8 * ppcboot.h for historical reasons, and in the interest of having a
9 * mainline kernel boot on the production board+bootloader, this was the
10 * least-offensive solution. Please direct all flames to:
11 *
12 * Solomon Peachy <solomon@linux-wlan.com>
13 *
14 * (This header is identical to ppcboot.h except for the
15 * TARGET_HOTFOOT bits)
16 */
17
18/*
19 * (C) Copyright 2000, 2001
20 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
21 *
22 * This program is free software; you can redistribute it and/or
23 * modify it under the terms of the GNU General Public License as
24 * published by the Free Software Foundation; either version 2 of
25 * the License, or (at your option) any later version.
26 *
27 * This program is distributed in the hope that it will be useful,
28 * but WITHOUT ANY WARRANTY; without even the implied warranty of
29 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
30 * GNU General Public License for more details.
31 *
32 * You should have received a copy of the GNU General Public License
33 * along with this program; if not, write to the Free Software
34 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
35 * MA 02111-1307 USA
36 */
37
38#ifndef __PPCBOOT_H__
39#define __PPCBOOT_H__
40
41/*
42 * Board information passed to kernel from PPCBoot
43 *
44 * include/asm-ppc/ppcboot.h
45 */
46
47#include "types.h"
48
49typedef struct bd_info {
50 unsigned long bi_memstart; /* start of DRAM memory */
51 unsigned long bi_memsize; /* size of DRAM memory in bytes */
52 unsigned long bi_flashstart; /* start of FLASH memory */
53 unsigned long bi_flashsize; /* size of FLASH memory */
54 unsigned long bi_flashoffset; /* reserved area for startup monitor */
55 unsigned long bi_sramstart; /* start of SRAM memory */
56 unsigned long bi_sramsize; /* size of SRAM memory */
57#if defined(TARGET_8xx) || defined(TARGET_CPM2) || defined(TARGET_85xx) ||\
58 defined(TARGET_83xx)
59 unsigned long bi_immr_base; /* base of IMMR register */
60#endif
61#if defined(TARGET_PPC_MPC52xx)
62 unsigned long bi_mbar_base; /* base of internal registers */
63#endif
64 unsigned long bi_bootflags; /* boot / reboot flag (for LynxOS) */
65 unsigned long bi_ip_addr; /* IP Address */
66 unsigned char bi_enetaddr[6]; /* Ethernet address */
67#if defined(TARGET_HOTFOOT)
68 /* second onboard ethernet port */
69 unsigned char bi_enet1addr[6];
70#define HAVE_ENET1ADDR
71#endif /* TARGET_HOOTFOOT */
72 unsigned short bi_ethspeed; /* Ethernet speed in Mbps */
73 unsigned long bi_intfreq; /* Internal Freq, in MHz */
74 unsigned long bi_busfreq; /* Bus Freq, in MHz */
75#if defined(TARGET_CPM2)
76 unsigned long bi_cpmfreq; /* CPM_CLK Freq, in MHz */
77 unsigned long bi_brgfreq; /* BRG_CLK Freq, in MHz */
78 unsigned long bi_sccfreq; /* SCC_CLK Freq, in MHz */
79 unsigned long bi_vco; /* VCO Out from PLL, in MHz */
80#endif
81#if defined(TARGET_PPC_MPC52xx)
82 unsigned long bi_ipbfreq; /* IPB Bus Freq, in MHz */
83 unsigned long bi_pcifreq; /* PCI Bus Freq, in MHz */
84#endif
85 unsigned long bi_baudrate; /* Console Baudrate */
86#if defined(TARGET_4xx)
87 unsigned char bi_s_version[4]; /* Version of this structure */
88 unsigned char bi_r_version[32]; /* Version of the ROM (IBM) */
89 unsigned int bi_procfreq; /* CPU (Internal) Freq, in Hz */
90 unsigned int bi_plb_busfreq; /* PLB Bus speed, in Hz */
91 unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */
92 unsigned char bi_pci_enetaddr[6]; /* PCI Ethernet MAC address */
93#endif
94#if defined(TARGET_HOTFOOT)
95 unsigned int bi_pllouta_freq; /* PLL OUTA speed, in Hz */
96#endif
97#if defined(TARGET_HYMOD)
98 hymod_conf_t bi_hymod_conf; /* hymod configuration information */
99#endif
100#if defined(TARGET_EVB64260) || defined(TARGET_405EP) || defined(TARGET_44x) || \
101 defined(TARGET_85xx) || defined(TARGET_83xx) || defined(TARGET_HAS_ETH1)
102 /* second onboard ethernet port */
103 unsigned char bi_enet1addr[6];
104#define HAVE_ENET1ADDR
105#endif
106#if defined(TARGET_EVB64260) || defined(TARGET_440GX) || \
107 defined(TARGET_85xx) || defined(TARGET_HAS_ETH2)
108 /* third onboard ethernet ports */
109 unsigned char bi_enet2addr[6];
110#define HAVE_ENET2ADDR
111#endif
112#if defined(TARGET_440GX) || defined(TARGET_HAS_ETH3)
113 /* fourth onboard ethernet ports */
114 unsigned char bi_enet3addr[6];
115#define HAVE_ENET3ADDR
116#endif
117#if defined(TARGET_HOTFOOT)
118 int bi_phynum[2]; /* Determines phy mapping */
119 int bi_phymode[2]; /* Determines phy mode */
120#endif
121#if defined(TARGET_4xx)
122 unsigned int bi_opbfreq; /* OB clock in Hz */
123 int bi_iic_fast[2]; /* Use fast i2c mode */
124#endif
125#if defined(TARGET_440GX)
126 int bi_phynum[4]; /* phy mapping */
127 int bi_phymode[4]; /* phy mode */
128#endif
129} bd_t;
130
131#define bi_tbfreq bi_intfreq
132
133#endif /* __PPCBOOT_H__ */
diff --git a/arch/powerpc/boot/wrapper b/arch/powerpc/boot/wrapper
index 4db487d1d2a8..ac9e9a58b2b0 100755
--- a/arch/powerpc/boot/wrapper
+++ b/arch/powerpc/boot/wrapper
@@ -46,6 +46,7 @@ CROSS=
46# directory for object and other files used by this script 46# directory for object and other files used by this script
47object=arch/powerpc/boot 47object=arch/powerpc/boot
48objbin=$object 48objbin=$object
49dtc=scripts/dtc/dtc
49 50
50# directory for working files 51# directory for working files
51tmpdir=. 52tmpdir=.
@@ -124,7 +125,7 @@ if [ -n "$dts" ]; then
124 if [ -z "$dtb" ]; then 125 if [ -z "$dtb" ]; then
125 dtb="$platform.dtb" 126 dtb="$platform.dtb"
126 fi 127 fi
127 $object/dtc -O dtb -o "$dtb" -b 0 "$dts" 128 $dtc -O dtb -o "$dtb" -b 0 "$dts"
128fi 129fi
129 130
130if [ -z "$kernel" ]; then 131if [ -z "$kernel" ]; then
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-20 23:41:20 -0500