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-rw-r--r--arch/powerpc/boot/dts/mpc832x_rdb.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc8349emitx.dts16
-rw-r--r--arch/powerpc/boot/dts/mpc8572ds.dts2
3 files changed, 11 insertions, 11 deletions
diff --git a/arch/powerpc/boot/dts/mpc832x_rdb.dts b/arch/powerpc/boot/dts/mpc832x_rdb.dts
index 226ff066652b..dea30910c136 100644
--- a/arch/powerpc/boot/dts/mpc832x_rdb.dts
+++ b/arch/powerpc/boot/dts/mpc832x_rdb.dts
@@ -18,8 +18,8 @@
18 #size-cells = <1>; 18 #size-cells = <1>;
19 19
20 aliases { 20 aliases {
21 ethernet0 = &enet0; 21 ethernet0 = &enet1;
22 ethernet1 = &enet1; 22 ethernet1 = &enet0;
23 serial0 = &serial0; 23 serial0 = &serial0;
24 serial1 = &serial1; 24 serial1 = &serial1;
25 pci0 = &pci0; 25 pci0 = &pci0;
diff --git a/arch/powerpc/boot/dts/mpc8349emitx.dts b/arch/powerpc/boot/dts/mpc8349emitx.dts
index 2c9d54a35bc3..4bdbaf4993a1 100644
--- a/arch/powerpc/boot/dts/mpc8349emitx.dts
+++ b/arch/powerpc/boot/dts/mpc8349emitx.dts
@@ -91,6 +91,14 @@
91 interrupts = <18 0x8>; 91 interrupts = <18 0x8>;
92 interrupt-parent = <&ipic>; 92 interrupt-parent = <&ipic>;
93 }; 93 };
94
95 mcu_pio: mcu@a {
96 #gpio-cells = <2>;
97 compatible = "fsl,mc9s08qg8-mpc8349emitx",
98 "fsl,mcu-mpc8349emitx";
99 reg = <0x0a>;
100 gpio-controller;
101 };
94 }; 102 };
95 103
96 spi@7000 { 104 spi@7000 {
@@ -139,14 +147,6 @@
139 interrupt-parent = <&ipic>; 147 interrupt-parent = <&ipic>;
140 interrupts = <71 8>; 148 interrupts = <71 8>;
141 }; 149 };
142
143 mcu_pio: mcu@a {
144 #gpio-cells = <2>;
145 compatible = "fsl,mc9s08qg8-mpc8349emitx",
146 "fsl,mcu-mpc8349emitx";
147 reg = <0x0a>;
148 gpio-controller;
149 };
150 }; 150 };
151 151
152 usb@22000 { 152 usb@22000 {
diff --git a/arch/powerpc/boot/dts/mpc8572ds.dts b/arch/powerpc/boot/dts/mpc8572ds.dts
index cadd4652a695..5c69b2fafd32 100644
--- a/arch/powerpc/boot/dts/mpc8572ds.dts
+++ b/arch/powerpc/boot/dts/mpc8572ds.dts
@@ -90,7 +90,7 @@
90 compatible = "fsl,mpc8572-l2-cache-controller"; 90 compatible = "fsl,mpc8572-l2-cache-controller";
91 reg = <0x20000 0x1000>; 91 reg = <0x20000 0x1000>;
92 cache-line-size = <32>; // 32 bytes 92 cache-line-size = <32>; // 32 bytes
93 cache-size = <0x80000>; // L2, 512K 93 cache-size = <0x100000>; // L2, 1M
94 interrupt-parent = <&mpic>; 94 interrupt-parent = <&mpic>;
95 interrupts = <16 2>; 95 interrupts = <16 2>;
96 }; 96 };