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-rw-r--r--arch/powerpc/boot/Makefile40
-rw-r--r--arch/powerpc/boot/bamboo.c3
-rw-r--r--arch/powerpc/boot/cpm-serial.c117
-rw-r--r--arch/powerpc/boot/cuboot-pq2.c27
-rw-r--r--arch/powerpc/boot/cuboot-rainier.c3
-rw-r--r--arch/powerpc/boot/cuboot-sequoia.c3
-rw-r--r--arch/powerpc/boot/cuboot-taishan.c3
-rw-r--r--arch/powerpc/boot/cuboot-warp.c2
-rw-r--r--arch/powerpc/boot/cuboot-yosemite.c44
-rw-r--r--arch/powerpc/boot/devtree.c20
-rw-r--r--arch/powerpc/boot/dts/bamboo.dts2
-rw-r--r--arch/powerpc/boot/dts/canyonlands.dts402
-rw-r--r--arch/powerpc/boot/dts/ebony.dts2
-rw-r--r--arch/powerpc/boot/dts/ep8248e.dts5
-rw-r--r--arch/powerpc/boot/dts/ep88xc.dts73
-rw-r--r--arch/powerpc/boot/dts/glacier.dts467
-rw-r--r--arch/powerpc/boot/dts/haleakala.dts4
-rw-r--r--arch/powerpc/boot/dts/katmai.dts2
-rw-r--r--arch/powerpc/boot/dts/kilauea.dts4
-rw-r--r--arch/powerpc/boot/dts/ksi8560.dts267
-rw-r--r--arch/powerpc/boot/dts/kuroboxHD.dts83
-rw-r--r--arch/powerpc/boot/dts/kuroboxHG.dts83
-rw-r--r--arch/powerpc/boot/dts/makalu.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc7448hpc2.dts97
-rw-r--r--arch/powerpc/boot/dts/mpc8272ads.dts132
-rw-r--r--arch/powerpc/boot/dts/mpc832x_mds.dts7
-rw-r--r--arch/powerpc/boot/dts/mpc832x_rdb.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc836x_mds.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc8540ads.dts173
-rw-r--r--arch/powerpc/boot/dts/mpc8541cds.dts161
-rw-r--r--arch/powerpc/boot/dts/mpc8544ds.dts299
-rw-r--r--arch/powerpc/boot/dts/mpc8548cds.dts289
-rw-r--r--arch/powerpc/boot/dts/mpc8555cds.dts161
-rw-r--r--arch/powerpc/boot/dts/mpc8560ads.dts209
-rw-r--r--arch/powerpc/boot/dts/mpc8568mds.dts291
-rw-r--r--arch/powerpc/boot/dts/mpc8572ds.dts383
-rw-r--r--arch/powerpc/boot/dts/mpc8641_hpcn.dts2
-rw-r--r--arch/powerpc/boot/dts/mpc866ads.dts58
-rw-r--r--arch/powerpc/boot/dts/mpc885ads.dts77
-rw-r--r--arch/powerpc/boot/dts/pq2fads.dts126
-rw-r--r--arch/powerpc/boot/dts/prpmc2800.dts336
-rw-r--r--arch/powerpc/boot/dts/rainier.dts6
-rw-r--r--arch/powerpc/boot/dts/sbc8641d.dts352
-rw-r--r--arch/powerpc/boot/dts/sequoia.dts6
-rw-r--r--arch/powerpc/boot/dts/taishan.dts31
-rw-r--r--arch/powerpc/boot/dts/walnut.dts1
-rw-r--r--arch/powerpc/boot/dts/warp.dts1
-rw-r--r--arch/powerpc/boot/dts/yosemite.dts304
-rw-r--r--arch/powerpc/boot/ebony.c3
-rw-r--r--arch/powerpc/boot/libfdt-wrapper.c2
-rw-r--r--arch/powerpc/boot/mpc52xx-psc.c9
-rw-r--r--arch/powerpc/boot/mpsc.c2
-rw-r--r--arch/powerpc/boot/mv64x60.c4
-rw-r--r--arch/powerpc/boot/mv64x60_i2c.c2
-rw-r--r--arch/powerpc/boot/ns16550.c10
-rw-r--r--arch/powerpc/boot/ops.h1
-rw-r--r--arch/powerpc/boot/prpmc2800.c23
-rw-r--r--arch/powerpc/boot/ps3-head.S25
-rw-r--r--arch/powerpc/boot/ps3.c23
-rw-r--r--arch/powerpc/boot/serial.c2
-rw-r--r--arch/powerpc/boot/simpleboot.c84
-rw-r--r--arch/powerpc/boot/treeboot-walnut.c2
-rw-r--r--arch/powerpc/boot/virtex405-head.S30
-rwxr-xr-xarch/powerpc/boot/wrapper32
64 files changed, 3749 insertions, 1675 deletions
diff --git a/arch/powerpc/boot/Makefile b/arch/powerpc/boot/Makefile
index 1aded8f759d0..5ba50c673390 100644
--- a/arch/powerpc/boot/Makefile
+++ b/arch/powerpc/boot/Makefile
@@ -40,6 +40,7 @@ $(obj)/ebony.o: BOOTCFLAGS += -mcpu=405
40$(obj)/cuboot-taishan.o: BOOTCFLAGS += -mcpu=405 40$(obj)/cuboot-taishan.o: BOOTCFLAGS += -mcpu=405
41$(obj)/cuboot-katmai.o: BOOTCFLAGS += -mcpu=405 41$(obj)/cuboot-katmai.o: BOOTCFLAGS += -mcpu=405
42$(obj)/treeboot-walnut.o: BOOTCFLAGS += -mcpu=405 42$(obj)/treeboot-walnut.o: BOOTCFLAGS += -mcpu=405
43$(obj)/virtex405-head.o: BOOTCFLAGS += -mcpu=405
43 44
44 45
45zlib := inffast.c inflate.c inftrees.c 46zlib := inffast.c inflate.c inftrees.c
@@ -64,7 +65,8 @@ src-plat := of.c cuboot-52xx.c cuboot-824x.c cuboot-83xx.c cuboot-85xx.c holly.c
64 cuboot-bamboo.c cuboot-mpc7448hpc2.c cuboot-taishan.c \ 65 cuboot-bamboo.c cuboot-mpc7448hpc2.c cuboot-taishan.c \
65 fixed-head.S ep88xc.c ep405.c \ 66 fixed-head.S ep88xc.c ep405.c \
66 cuboot-katmai.c cuboot-rainier.c redboot-8xx.c ep8248e.c \ 67 cuboot-katmai.c cuboot-rainier.c redboot-8xx.c ep8248e.c \
67 cuboot-warp.c cuboot-85xx-cpm2.c 68 cuboot-warp.c cuboot-85xx-cpm2.c cuboot-yosemite.c simpleboot.c \
69 virtex405-head.S
68src-boot := $(src-wlib) $(src-plat) empty.c 70src-boot := $(src-wlib) $(src-plat) empty.c
69 71
70src-boot := $(addprefix $(obj)/, $(src-boot)) 72src-boot := $(addprefix $(obj)/, $(src-boot))
@@ -192,7 +194,7 @@ image-$(CONFIG_PPC_CHRP) += zImage.chrp
192image-$(CONFIG_PPC_EFIKA) += zImage.chrp 194image-$(CONFIG_PPC_EFIKA) += zImage.chrp
193image-$(CONFIG_PPC_PMAC) += zImage.pmac 195image-$(CONFIG_PPC_PMAC) += zImage.pmac
194image-$(CONFIG_PPC_HOLLY) += zImage.holly 196image-$(CONFIG_PPC_HOLLY) += zImage.holly
195image-$(CONFIG_PPC_PRPMC2800) += zImage.prpmc2800 197image-$(CONFIG_PPC_PRPMC2800) += dtbImage.prpmc2800
196image-$(CONFIG_PPC_ISERIES) += zImage.iseries 198image-$(CONFIG_PPC_ISERIES) += zImage.iseries
197image-$(CONFIG_DEFAULT_UIMAGE) += uImage 199image-$(CONFIG_DEFAULT_UIMAGE) += uImage
198 200
@@ -216,6 +218,7 @@ image-$(CONFIG_RAINIER) += cuImage.rainier
216image-$(CONFIG_TAISHAN) += cuImage.taishan 218image-$(CONFIG_TAISHAN) += cuImage.taishan
217image-$(CONFIG_KATMAI) += cuImage.katmai 219image-$(CONFIG_KATMAI) += cuImage.katmai
218image-$(CONFIG_WARP) += cuImage.warp 220image-$(CONFIG_WARP) += cuImage.warp
221image-$(CONFIG_YOSEMITE) += cuImage.yosemite
219 222
220# Board ports in arch/powerpc/platform/8xx/Kconfig 223# Board ports in arch/powerpc/platform/8xx/Kconfig
221image-$(CONFIG_PPC_MPC86XADS) += cuImage.mpc866ads 224image-$(CONFIG_PPC_MPC86XADS) += cuImage.mpc866ads
@@ -255,6 +258,7 @@ image-$(CONFIG_TQM8555) += cuImage.tqm8555
255image-$(CONFIG_TQM8560) += cuImage.tqm8560 258image-$(CONFIG_TQM8560) += cuImage.tqm8560
256image-$(CONFIG_SBC8548) += cuImage.sbc8548 259image-$(CONFIG_SBC8548) += cuImage.sbc8548
257image-$(CONFIG_SBC8560) += cuImage.sbc8560 260image-$(CONFIG_SBC8560) += cuImage.sbc8560
261image-$(CONFIG_KSI8560) += cuImage.ksi8560
258 262
259# Board ports in arch/powerpc/platform/embedded6xx/Kconfig 263# Board ports in arch/powerpc/platform/embedded6xx/Kconfig
260image-$(CONFIG_STORCENTER) += cuImage.storcenter 264image-$(CONFIG_STORCENTER) += cuImage.storcenter
@@ -285,11 +289,11 @@ $(obj)/zImage.%: vmlinux $(wrapperbits)
285 $(call if_changed,wrap,$*) 289 $(call if_changed,wrap,$*)
286 290
287# dtbImage% - a dtbImage is a zImage with an embedded device tree blob 291# dtbImage% - a dtbImage is a zImage with an embedded device tree blob
288$(obj)/dtbImage.initrd.%: vmlinux $(wrapperbits) $(dtstree)/%.dts 292$(obj)/dtbImage.initrd.%: vmlinux $(wrapperbits) $(obj)/%.dtb
289 $(call if_changed,wrap,$*,$(dtstree)/$*.dts,,$(obj)/ramdisk.image.gz) 293 $(call if_changed,wrap,$*,,$(obj)/$*.dtb,$(obj)/ramdisk.image.gz)
290 294
291$(obj)/dtbImage.%: vmlinux $(wrapperbits) $(dtstree)/%.dts 295$(obj)/dtbImage.%: vmlinux $(wrapperbits) $(obj)/%.dtb
292 $(call if_changed,wrap,$*,$(dtstree)/$*.dts) 296 $(call if_changed,wrap,$*,,$(obj)/$*.dtb)
293 297
294# This cannot be in the root of $(src) as the zImage rule always adds a $(obj) 298# This cannot be in the root of $(src) as the zImage rule always adds a $(obj)
295# prefix 299# prefix
@@ -302,14 +306,24 @@ $(obj)/zImage.iseries: vmlinux
302$(obj)/uImage: vmlinux $(wrapperbits) 306$(obj)/uImage: vmlinux $(wrapperbits)
303 $(call if_changed,wrap,uboot) 307 $(call if_changed,wrap,uboot)
304 308
305$(obj)/cuImage.%: vmlinux $(dtstree)/%.dts $(wrapperbits) 309$(obj)/cuImage.%: vmlinux $(obj)/%.dtb $(wrapperbits)
306 $(call if_changed,wrap,cuboot-$*,$(dtstree)/$*.dts) 310 $(call if_changed,wrap,cuboot-$*,,$(obj)/$*.dtb)
307 311
308$(obj)/treeImage.initrd.%: vmlinux $(dtstree)/%.dts $(wrapperbits) 312$(obj)/simpleImage.initrd.%: vmlinux $(obj)/%.dtb $(wrapperbits)
309 $(call if_changed,wrap,treeboot-$*,$(dtstree)/$*.dts,,$(obj)/ramdisk.image.gz) 313 $(call if_changed,wrap,simpleboot-$*,,$(obj)/$*.dtb,$(obj)/ramdisk.image.gz)
310 314
311$(obj)/treeImage.%: vmlinux $(dtstree)/%.dts $(wrapperbits) 315$(obj)/simpleImage.%: vmlinux $(obj)/%.dtb $(wrapperbits)
312 $(call if_changed,wrap,treeboot-$*,$(dtstree)/$*.dts) 316 $(call if_changed,wrap,simpleboot-$*,,$(obj)/$*.dtb)
317
318$(obj)/treeImage.initrd.%: vmlinux $(obj)/%.dtb $(wrapperbits)
319 $(call if_changed,wrap,treeboot-$*,,$(obj)/$*.dtb,$(obj)/ramdisk.image.gz)
320
321$(obj)/treeImage.%: vmlinux $(obj)/%.dtb $(wrapperbits)
322 $(call if_changed,wrap,treeboot-$*,,$(obj)/$*.dtb)
323
324# Rule to build device tree blobs
325$(obj)/%.dtb: $(dtstree)/%.dts $(obj)/dtc
326 $(obj)/dtc -O dtb -o $(obj)/$*.dtb -b 0 $(DTS_FLAGS) $(dtstree)/$*.dts
313 327
314# If there isn't a platform selected then just strip the vmlinux. 328# If there isn't a platform selected then just strip the vmlinux.
315ifeq (,$(image-y)) 329ifeq (,$(image-y))
@@ -326,7 +340,7 @@ install: $(CONFIGURE) $(addprefix $(obj)/, $(image-y))
326 340
327# anything not in $(targets) 341# anything not in $(targets)
328clean-files += $(image-) $(initrd-) zImage zImage.initrd cuImage.* treeImage.* \ 342clean-files += $(image-) $(initrd-) zImage zImage.initrd cuImage.* treeImage.* \
329 otheros.bld 343 otheros.bld *.dtb
330 344
331# clean up files cached by wrapper 345# clean up files cached by wrapper
332clean-kernel := vmlinux.strip vmlinux.bin 346clean-kernel := vmlinux.strip vmlinux.bin
diff --git a/arch/powerpc/boot/bamboo.c b/arch/powerpc/boot/bamboo.c
index 54b33f1500e2..b82cacbc60db 100644
--- a/arch/powerpc/boot/bamboo.c
+++ b/arch/powerpc/boot/bamboo.c
@@ -33,7 +33,8 @@ static void bamboo_fixups(void)
33 ibm440ep_fixup_clocks(sysclk, 11059200, 25000000); 33 ibm440ep_fixup_clocks(sysclk, 11059200, 25000000);
34 ibm4xx_sdram_fixup_memsize(); 34 ibm4xx_sdram_fixup_memsize();
35 ibm4xx_quiesce_eth((u32 *)0xef600e00, (u32 *)0xef600f00); 35 ibm4xx_quiesce_eth((u32 *)0xef600e00, (u32 *)0xef600f00);
36 dt_fixup_mac_addresses(bamboo_mac0, bamboo_mac1); 36 dt_fixup_mac_address_by_alias("ethernet0", bamboo_mac0);
37 dt_fixup_mac_address_by_alias("ethernet1", bamboo_mac1);
37} 38}
38 39
39void bamboo_init(void *mac0, void *mac1) 40void bamboo_init(void *mac0, void *mac1)
diff --git a/arch/powerpc/boot/cpm-serial.c b/arch/powerpc/boot/cpm-serial.c
index 28296facb2ae..19dc15abe43d 100644
--- a/arch/powerpc/boot/cpm-serial.c
+++ b/arch/powerpc/boot/cpm-serial.c
@@ -11,6 +11,7 @@
11#include "types.h" 11#include "types.h"
12#include "io.h" 12#include "io.h"
13#include "ops.h" 13#include "ops.h"
14#include "page.h"
14 15
15struct cpm_scc { 16struct cpm_scc {
16 u32 gsmrl; 17 u32 gsmrl;
@@ -42,6 +43,22 @@ struct cpm_param {
42 u16 tbase; 43 u16 tbase;
43 u8 rfcr; 44 u8 rfcr;
44 u8 tfcr; 45 u8 tfcr;
46 u16 mrblr;
47 u32 rstate;
48 u8 res1[4];
49 u16 rbptr;
50 u8 res2[6];
51 u32 tstate;
52 u8 res3[4];
53 u16 tbptr;
54 u8 res4[6];
55 u16 maxidl;
56 u16 idlc;
57 u16 brkln;
58 u16 brkec;
59 u16 brkcr;
60 u16 rmask;
61 u8 res5[4];
45}; 62};
46 63
47struct cpm_bd { 64struct cpm_bd {
@@ -54,10 +71,10 @@ static void *cpcr;
54static struct cpm_param *param; 71static struct cpm_param *param;
55static struct cpm_smc *smc; 72static struct cpm_smc *smc;
56static struct cpm_scc *scc; 73static struct cpm_scc *scc;
57struct cpm_bd *tbdf, *rbdf; 74static struct cpm_bd *tbdf, *rbdf;
58static u32 cpm_cmd; 75static u32 cpm_cmd;
59static u8 *muram_start; 76static void *cbd_addr;
60static u32 muram_offset; 77static u32 cbd_offset;
61 78
62static void (*do_cmd)(int op); 79static void (*do_cmd)(int op);
63static void (*enable_port)(void); 80static void (*enable_port)(void);
@@ -119,20 +136,25 @@ static int cpm_serial_open(void)
119 136
120 out_8(&param->rfcr, 0x10); 137 out_8(&param->rfcr, 0x10);
121 out_8(&param->tfcr, 0x10); 138 out_8(&param->tfcr, 0x10);
122 139 out_be16(&param->mrblr, 1);
123 rbdf = (struct cpm_bd *)muram_start; 140 out_be16(&param->maxidl, 0);
124 rbdf->addr = (u8 *)(rbdf + 2); 141 out_be16(&param->brkec, 0);
142 out_be16(&param->brkln, 0);
143 out_be16(&param->brkcr, 0);
144
145 rbdf = cbd_addr;
146 rbdf->addr = (u8 *)rbdf - 1;
125 rbdf->sc = 0xa000; 147 rbdf->sc = 0xa000;
126 rbdf->len = 1; 148 rbdf->len = 1;
127 149
128 tbdf = rbdf + 1; 150 tbdf = rbdf + 1;
129 tbdf->addr = (u8 *)(rbdf + 2) + 1; 151 tbdf->addr = (u8 *)rbdf - 2;
130 tbdf->sc = 0x2000; 152 tbdf->sc = 0x2000;
131 tbdf->len = 1; 153 tbdf->len = 1;
132 154
133 sync(); 155 sync();
134 out_be16(&param->rbase, muram_offset); 156 out_be16(&param->rbase, cbd_offset);
135 out_be16(&param->tbase, muram_offset + sizeof(struct cpm_bd)); 157 out_be16(&param->tbase, cbd_offset + sizeof(struct cpm_bd));
136 158
137 do_cmd(CPM_CMD_INIT_RX_TX); 159 do_cmd(CPM_CMD_INIT_RX_TX);
138 160
@@ -175,10 +197,12 @@ static unsigned char cpm_serial_getc(void)
175 197
176int cpm_console_init(void *devp, struct serial_console_data *scdp) 198int cpm_console_init(void *devp, struct serial_console_data *scdp)
177{ 199{
178 void *reg_virt[2]; 200 void *vreg[2];
179 int is_smc = 0, is_cpm2 = 0, n; 201 u32 reg[2];
180 unsigned long reg_phys; 202 int is_smc = 0, is_cpm2 = 0;
181 void *parent, *muram; 203 void *parent, *muram;
204 void *muram_addr;
205 unsigned long muram_offset, muram_size;
182 206
183 if (dt_is_compatible(devp, "fsl,cpm1-smc-uart")) { 207 if (dt_is_compatible(devp, "fsl,cpm1-smc-uart")) {
184 is_smc = 1; 208 is_smc = 1;
@@ -202,63 +226,64 @@ int cpm_console_init(void *devp, struct serial_console_data *scdp)
202 else 226 else
203 do_cmd = cpm1_cmd; 227 do_cmd = cpm1_cmd;
204 228
205 n = getprop(devp, "fsl,cpm-command", &cpm_cmd, 4); 229 if (getprop(devp, "fsl,cpm-command", &cpm_cmd, 4) < 4)
206 if (n < 4)
207 return -1; 230 return -1;
208 231
209 n = getprop(devp, "virtual-reg", reg_virt, sizeof(reg_virt)); 232 if (dt_get_virtual_reg(devp, vreg, 2) < 2)
210 if (n < (int)sizeof(reg_virt)) { 233 return -1;
211 for (n = 0; n < 2; n++) {
212 if (!dt_xlate_reg(devp, n, &reg_phys, NULL))
213 return -1;
214
215 reg_virt[n] = (void *)reg_phys;
216 }
217 }
218 234
219 if (is_smc) 235 if (is_smc)
220 smc = reg_virt[0]; 236 smc = vreg[0];
221 else 237 else
222 scc = reg_virt[0]; 238 scc = vreg[0];
223 239
224 param = reg_virt[1]; 240 param = vreg[1];
225 241
226 parent = get_parent(devp); 242 parent = get_parent(devp);
227 if (!parent) 243 if (!parent)
228 return -1; 244 return -1;
229 245
230 n = getprop(parent, "virtual-reg", reg_virt, sizeof(reg_virt)); 246 if (dt_get_virtual_reg(parent, &cpcr, 1) < 1)
231 if (n < (int)sizeof(reg_virt)) { 247 return -1;
232 if (!dt_xlate_reg(parent, 0, &reg_phys, NULL))
233 return -1;
234
235 reg_virt[0] = (void *)reg_phys;
236 }
237
238 cpcr = reg_virt[0];
239 248
240 muram = finddevice("/soc/cpm/muram/data"); 249 muram = finddevice("/soc/cpm/muram/data");
241 if (!muram) 250 if (!muram)
242 return -1; 251 return -1;
243 252
244 /* For bootwrapper-compatible device trees, we assume that the first 253 /* For bootwrapper-compatible device trees, we assume that the first
245 * entry has at least 18 bytes, and that #address-cells/#data-cells 254 * entry has at least 128 bytes, and that #address-cells/#data-cells
246 * is one for both parent and child. 255 * is one for both parent and child.
247 */ 256 */
248 257
249 n = getprop(muram, "virtual-reg", reg_virt, sizeof(reg_virt)); 258 if (dt_get_virtual_reg(muram, &muram_addr, 1) < 1)
250 if (n < (int)sizeof(reg_virt)) { 259 return -1;
251 if (!dt_xlate_reg(muram, 0, &reg_phys, NULL))
252 return -1;
253 260
254 reg_virt[0] = (void *)reg_phys; 261 if (getprop(muram, "reg", reg, 8) < 8)
255 } 262 return -1;
256 263
257 muram_start = reg_virt[0]; 264 muram_offset = reg[0];
265 muram_size = reg[1];
258 266
259 n = getprop(muram, "reg", &muram_offset, 4); 267 /* Store the buffer descriptors at the end of the first muram chunk.
260 if (n < 4) 268 * For SMC ports on CPM2-based platforms, relocate the parameter RAM
261 return -1; 269 * just before the buffer descriptors.
270 */
271
272 cbd_offset = muram_offset + muram_size - 2 * sizeof(struct cpm_bd);
273
274 if (is_cpm2 && is_smc) {
275 u16 *smc_base = (u16 *)param;
276 u16 pram_offset;
277
278 pram_offset = cbd_offset - 64;
279 pram_offset = _ALIGN_DOWN(pram_offset, 64);
280
281 disable_port();
282 out_be16(smc_base, pram_offset);
283 param = muram_addr - muram_offset + pram_offset;
284 }
285
286 cbd_addr = muram_addr - muram_offset + cbd_offset;
262 287
263 scdp->open = cpm_serial_open; 288 scdp->open = cpm_serial_open;
264 scdp->putc = cpm_serial_putc; 289 scdp->putc = cpm_serial_putc;
diff --git a/arch/powerpc/boot/cuboot-pq2.c b/arch/powerpc/boot/cuboot-pq2.c
index f56ac6cae9f3..9c7d13428293 100644
--- a/arch/powerpc/boot/cuboot-pq2.c
+++ b/arch/powerpc/boot/cuboot-pq2.c
@@ -128,7 +128,7 @@ static void fixup_pci(void)
128 u8 *soc_regs; 128 u8 *soc_regs;
129 int i, len; 129 int i, len;
130 void *node, *parent_node; 130 void *node, *parent_node;
131 u32 naddr, nsize, mem_log2; 131 u32 naddr, nsize, mem_pow2, mem_mask;
132 132
133 node = finddevice("/pci"); 133 node = finddevice("/pci");
134 if (!node || !dt_is_compatible(node, "fsl,pq2-pci")) 134 if (!node || !dt_is_compatible(node, "fsl,pq2-pci"))
@@ -141,7 +141,7 @@ static void fixup_pci(void)
141 141
142 soc_regs = (u8 *)fsl_get_immr(); 142 soc_regs = (u8 *)fsl_get_immr();
143 if (!soc_regs) 143 if (!soc_regs)
144 goto err; 144 goto unhandled;
145 145
146 dt_get_reg_format(node, &naddr, &nsize); 146 dt_get_reg_format(node, &naddr, &nsize);
147 if (naddr != 3 || nsize != 2) 147 if (naddr != 3 || nsize != 2)
@@ -153,7 +153,7 @@ static void fixup_pci(void)
153 153
154 dt_get_reg_format(parent_node, &naddr, &nsize); 154 dt_get_reg_format(parent_node, &naddr, &nsize);
155 if (naddr != 1 || nsize != 1) 155 if (naddr != 1 || nsize != 1)
156 goto err; 156 goto unhandled;
157 157
158 len = getprop(node, "ranges", pci_ranges_buf, 158 len = getprop(node, "ranges", pci_ranges_buf,
159 sizeof(pci_ranges_buf)); 159 sizeof(pci_ranges_buf));
@@ -170,14 +170,20 @@ static void fixup_pci(void)
170 } 170 }
171 171
172 if (!mem || !mmio || !io) 172 if (!mem || !mmio || !io)
173 goto err; 173 goto unhandled;
174 if (mem->size[1] != mmio->size[1])
175 goto unhandled;
176 if (mem->size[1] & (mem->size[1] - 1))
177 goto unhandled;
178 if (io->size[1] & (io->size[1] - 1))
179 goto unhandled;
174 180
175 if (mem->phys_addr + mem->size[1] == mmio->phys_addr) 181 if (mem->phys_addr + mem->size[1] == mmio->phys_addr)
176 mem_base = mem; 182 mem_base = mem;
177 else if (mmio->phys_addr + mmio->size[1] == mem->phys_addr) 183 else if (mmio->phys_addr + mmio->size[1] == mem->phys_addr)
178 mem_base = mmio; 184 mem_base = mmio;
179 else 185 else
180 goto err; 186 goto unhandled;
181 187
182 out_be32(&pci_regs[1][0], mem_base->phys_addr | 1); 188 out_be32(&pci_regs[1][0], mem_base->phys_addr | 1);
183 out_be32(&pci_regs[2][0], ~(mem->size[1] + mmio->size[1] - 1)); 189 out_be32(&pci_regs[2][0], ~(mem->size[1] + mmio->size[1] - 1));
@@ -201,8 +207,9 @@ static void fixup_pci(void)
201 out_le32(&pci_regs[0][58], 0); 207 out_le32(&pci_regs[0][58], 0);
202 out_le32(&pci_regs[0][60], 0); 208 out_le32(&pci_regs[0][60], 0);
203 209
204 mem_log2 = 1 << (__ilog2_u32(bd.bi_memsize - 1) + 1); 210 mem_pow2 = 1 << (__ilog2_u32(bd.bi_memsize - 1) + 1);
205 out_le32(&pci_regs[0][62], 0xa0000000 | ~((1 << (mem_log2 - 12)) - 1)); 211 mem_mask = ~(mem_pow2 - 1) >> 12;
212 out_le32(&pci_regs[0][62], 0xa0000000 | mem_mask);
206 213
207 /* If PCI is disabled, drive RST high to enable. */ 214 /* If PCI is disabled, drive RST high to enable. */
208 if (!(in_le32(&pci_regs[0][32]) & 1)) { 215 if (!(in_le32(&pci_regs[0][32]) & 1)) {
@@ -228,7 +235,11 @@ static void fixup_pci(void)
228 return; 235 return;
229 236
230err: 237err:
231 printf("Bad PCI node\r\n"); 238 printf("Bad PCI node -- using existing firmware setup.\r\n");
239 return;
240
241unhandled:
242 printf("Unsupported PCI node -- using existing firmware setup.\r\n");
232} 243}
233 244
234static void pq2_platform_fixups(void) 245static void pq2_platform_fixups(void)
diff --git a/arch/powerpc/boot/cuboot-rainier.c b/arch/powerpc/boot/cuboot-rainier.c
index cf452b66dce8..0a3fddee54df 100644
--- a/arch/powerpc/boot/cuboot-rainier.c
+++ b/arch/powerpc/boot/cuboot-rainier.c
@@ -42,7 +42,8 @@ static void rainier_fixups(void)
42 ibm440ep_fixup_clocks(sysclk, 11059200, 50000000); 42 ibm440ep_fixup_clocks(sysclk, 11059200, 50000000);
43 ibm4xx_fixup_ebc_ranges("/plb/opb/ebc"); 43 ibm4xx_fixup_ebc_ranges("/plb/opb/ebc");
44 ibm4xx_denali_fixup_memsize(); 44 ibm4xx_denali_fixup_memsize();
45 dt_fixup_mac_addresses(&bd.bi_enetaddr, &bd.bi_enet1addr); 45 dt_fixup_mac_address_by_alias("ethernet0", bd.bi_enetaddr);
46 dt_fixup_mac_address_by_alias("ethernet1", bd.bi_enet1addr);
46} 47}
47 48
48void platform_init(unsigned long r3, unsigned long r4, unsigned long r5, 49void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
diff --git a/arch/powerpc/boot/cuboot-sequoia.c b/arch/powerpc/boot/cuboot-sequoia.c
index f555575a44de..caf8f2e842ea 100644
--- a/arch/powerpc/boot/cuboot-sequoia.c
+++ b/arch/powerpc/boot/cuboot-sequoia.c
@@ -42,7 +42,8 @@ static void sequoia_fixups(void)
42 ibm440ep_fixup_clocks(sysclk, 11059200, 50000000); 42 ibm440ep_fixup_clocks(sysclk, 11059200, 50000000);
43 ibm4xx_fixup_ebc_ranges("/plb/opb/ebc"); 43 ibm4xx_fixup_ebc_ranges("/plb/opb/ebc");
44 ibm4xx_denali_fixup_memsize(); 44 ibm4xx_denali_fixup_memsize();
45 dt_fixup_mac_addresses(&bd.bi_enetaddr, &bd.bi_enet1addr); 45 dt_fixup_mac_address_by_alias("ethernet0", bd.bi_enetaddr);
46 dt_fixup_mac_address_by_alias("ethernet1", bd.bi_enet1addr);
46} 47}
47 48
48void platform_init(unsigned long r3, unsigned long r4, unsigned long r5, 49void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
diff --git a/arch/powerpc/boot/cuboot-taishan.c b/arch/powerpc/boot/cuboot-taishan.c
index b55b80467eed..9bc906a754dd 100644
--- a/arch/powerpc/boot/cuboot-taishan.c
+++ b/arch/powerpc/boot/cuboot-taishan.c
@@ -40,7 +40,8 @@ static void taishan_fixups(void)
40 40
41 ibm4xx_sdram_fixup_memsize(); 41 ibm4xx_sdram_fixup_memsize();
42 42
43 dt_fixup_mac_addresses(bd.bi_enetaddr, bd.bi_enet1addr); 43 dt_fixup_mac_address_by_alias("ethernet0", bd.bi_enetaddr);
44 dt_fixup_mac_address_by_alias("ethernet1", bd.bi_enet1addr);
44 45
45 ibm4xx_fixup_ebc_ranges("/plb/opb/ebc"); 46 ibm4xx_fixup_ebc_ranges("/plb/opb/ebc");
46} 47}
diff --git a/arch/powerpc/boot/cuboot-warp.c b/arch/powerpc/boot/cuboot-warp.c
index 3db93e85e9ea..eb108a877492 100644
--- a/arch/powerpc/boot/cuboot-warp.c
+++ b/arch/powerpc/boot/cuboot-warp.c
@@ -24,7 +24,7 @@ static void warp_fixups(void)
24 ibm440ep_fixup_clocks(sysclk, 11059200, 50000000); 24 ibm440ep_fixup_clocks(sysclk, 11059200, 50000000);
25 ibm4xx_sdram_fixup_memsize(); 25 ibm4xx_sdram_fixup_memsize();
26 ibm4xx_fixup_ebc_ranges("/plb/opb/ebc"); 26 ibm4xx_fixup_ebc_ranges("/plb/opb/ebc");
27 dt_fixup_mac_addresses(&bd.bi_enetaddr); 27 dt_fixup_mac_address_by_alias("ethernet0", bd.bi_enetaddr);
28} 28}
29 29
30 30
diff --git a/arch/powerpc/boot/cuboot-yosemite.c b/arch/powerpc/boot/cuboot-yosemite.c
new file mode 100644
index 000000000000..cc6e338c5d0d
--- /dev/null
+++ b/arch/powerpc/boot/cuboot-yosemite.c
@@ -0,0 +1,44 @@
1/*
2 * Old U-boot compatibility for Yosemite
3 *
4 * Author: Josh Boyer <jwboyer@linux.vnet.ibm.com>
5 *
6 * Copyright 2008 IBM Corporation
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 as published
10 * by the Free Software Foundation.
11 */
12
13#include "ops.h"
14#include "stdio.h"
15#include "4xx.h"
16#include "44x.h"
17#include "cuboot.h"
18
19#define TARGET_4xx
20#define TARGET_44x
21#include "ppcboot.h"
22
23static bd_t bd;
24
25static void yosemite_fixups(void)
26{
27 unsigned long sysclk = 66666666;
28
29 ibm440ep_fixup_clocks(sysclk, 11059200, 50000000);
30 ibm4xx_sdram_fixup_memsize();
31 ibm4xx_quiesce_eth((u32 *)0xef600e00, (u32 *)0xef600f00);
32 dt_fixup_mac_address_by_alias("ethernet0", bd.bi_enetaddr);
33 dt_fixup_mac_address_by_alias("ethernet1", bd.bi_enet1addr);
34}
35
36void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
37 unsigned long r6, unsigned long r7)
38{
39 CUBOOT_INIT();
40 platform_ops.fixups = yosemite_fixups;
41 platform_ops.exit = ibm44x_dbcr_reset;
42 fdt_init(_dtb_start);
43 serial_console_init();
44}
diff --git a/arch/powerpc/boot/devtree.c b/arch/powerpc/boot/devtree.c
index 60f561e307a9..5d12336dc360 100644
--- a/arch/powerpc/boot/devtree.c
+++ b/arch/powerpc/boot/devtree.c
@@ -350,3 +350,23 @@ int dt_is_compatible(void *node, const char *compat)
350 350
351 return 0; 351 return 0;
352} 352}
353
354int dt_get_virtual_reg(void *node, void **addr, int nres)
355{
356 unsigned long xaddr;
357 int n;
358
359 n = getprop(node, "virtual-reg", addr, nres * 4);
360 if (n > 0)
361 return n / 4;
362
363 for (n = 0; n < nres; n++) {
364 if (!dt_xlate_reg(node, n, &xaddr, NULL))
365 break;
366
367 addr[n] = (void *)xaddr;
368 }
369
370 return n;
371}
372
diff --git a/arch/powerpc/boot/dts/bamboo.dts b/arch/powerpc/boot/dts/bamboo.dts
index 7dc37c9a7446..ba2521bdaab1 100644
--- a/arch/powerpc/boot/dts/bamboo.dts
+++ b/arch/powerpc/boot/dts/bamboo.dts
@@ -204,7 +204,6 @@
204 }; 204 };
205 205
206 EMAC0: ethernet@ef600e00 { 206 EMAC0: ethernet@ef600e00 {
207 linux,network-index = <0>;
208 device_type = "network"; 207 device_type = "network";
209 compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac"; 208 compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac";
210 interrupt-parent = <&UIC1>; 209 interrupt-parent = <&UIC1>;
@@ -225,7 +224,6 @@
225 }; 224 };
226 225
227 EMAC1: ethernet@ef600f00 { 226 EMAC1: ethernet@ef600f00 {
228 linux,network-index = <1>;
229 device_type = "network"; 227 device_type = "network";
230 compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac"; 228 compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac";
231 interrupt-parent = <&UIC1>; 229 interrupt-parent = <&UIC1>;
diff --git a/arch/powerpc/boot/dts/canyonlands.dts b/arch/powerpc/boot/dts/canyonlands.dts
new file mode 100644
index 000000000000..6f3d38a1554f
--- /dev/null
+++ b/arch/powerpc/boot/dts/canyonlands.dts
@@ -0,0 +1,402 @@
1/*
2 * Device Tree Source for AMCC Canyonlands (460EX)
3 *
4 * Copyright 2008 DENX Software Engineering, Stefan Roese <sr@denx.de>
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without
8 * any warranty of any kind, whether express or implied.
9 */
10
11/ {
12 #address-cells = <2>;
13 #size-cells = <1>;
14 model = "amcc,canyonlands";
15 compatible = "amcc,canyonlands";
16 dcr-parent = <&/cpus/cpu@0>;
17
18 aliases {
19 ethernet0 = &EMAC0;
20 ethernet1 = &EMAC1;
21 serial0 = &UART0;
22 serial1 = &UART1;
23 };
24
25 cpus {
26 #address-cells = <1>;
27 #size-cells = <0>;
28
29 cpu@0 {
30 device_type = "cpu";
31 model = "PowerPC,460EX";
32 reg = <0>;
33 clock-frequency = <0>; /* Filled in by U-Boot */
34 timebase-frequency = <0>; /* Filled in by U-Boot */
35 i-cache-line-size = <20>;
36 d-cache-line-size = <20>;
37 i-cache-size = <8000>;
38 d-cache-size = <8000>;
39 dcr-controller;
40 dcr-access-method = "native";
41 };
42 };
43
44 memory {
45 device_type = "memory";
46 reg = <0 0 0>; /* Filled in by U-Boot */
47 };
48
49 UIC0: interrupt-controller0 {
50 compatible = "ibm,uic-460ex","ibm,uic";
51 interrupt-controller;
52 cell-index = <0>;
53 dcr-reg = <0c0 009>;
54 #address-cells = <0>;
55 #size-cells = <0>;
56 #interrupt-cells = <2>;
57 };
58
59 UIC1: interrupt-controller1 {
60 compatible = "ibm,uic-460ex","ibm,uic";
61 interrupt-controller;
62 cell-index = <1>;
63 dcr-reg = <0d0 009>;
64 #address-cells = <0>;
65 #size-cells = <0>;
66 #interrupt-cells = <2>;
67 interrupts = <1e 4 1f 4>; /* cascade */
68 interrupt-parent = <&UIC0>;
69 };
70
71 UIC2: interrupt-controller2 {
72 compatible = "ibm,uic-460ex","ibm,uic";
73 interrupt-controller;
74 cell-index = <2>;
75 dcr-reg = <0e0 009>;
76 #address-cells = <0>;
77 #size-cells = <0>;
78 #interrupt-cells = <2>;
79 interrupts = <a 4 b 4>; /* cascade */
80 interrupt-parent = <&UIC0>;
81 };
82
83 UIC3: interrupt-controller3 {
84 compatible = "ibm,uic-460ex","ibm,uic";
85 interrupt-controller;
86 cell-index = <3>;
87 dcr-reg = <0f0 009>;
88 #address-cells = <0>;
89 #size-cells = <0>;
90 #interrupt-cells = <2>;
91 interrupts = <10 4 11 4>; /* cascade */
92 interrupt-parent = <&UIC0>;
93 };
94
95 SDR0: sdr {
96 compatible = "ibm,sdr-460ex";
97 dcr-reg = <00e 002>;
98 };
99
100 CPR0: cpr {
101 compatible = "ibm,cpr-460ex";
102 dcr-reg = <00c 002>;
103 };
104
105 plb {
106 compatible = "ibm,plb-460ex", "ibm,plb4";
107 #address-cells = <2>;
108 #size-cells = <1>;
109 ranges;
110 clock-frequency = <0>; /* Filled in by U-Boot */
111
112 SDRAM0: sdram {
113 compatible = "ibm,sdram-460ex", "ibm,sdram-405gp";
114 dcr-reg = <010 2>;
115 };
116
117 MAL0: mcmal {
118 compatible = "ibm,mcmal-460ex", "ibm,mcmal2";
119 dcr-reg = <180 62>;
120 num-tx-chans = <2>;
121 num-rx-chans = <10>;
122 #address-cells = <0>;
123 #size-cells = <0>;
124 interrupt-parent = <&UIC2>;
125 interrupts = < /*TXEOB*/ 6 4
126 /*RXEOB*/ 7 4
127 /*SERR*/ 3 4
128 /*TXDE*/ 4 4
129 /*RXDE*/ 5 4>;
130 };
131
132 POB0: opb {
133 compatible = "ibm,opb-460ex", "ibm,opb";
134 #address-cells = <1>;
135 #size-cells = <1>;
136 ranges = <b0000000 4 b0000000 50000000>;
137 clock-frequency = <0>; /* Filled in by U-Boot */
138
139 EBC0: ebc {
140 compatible = "ibm,ebc-460ex", "ibm,ebc";
141 dcr-reg = <012 2>;
142 #address-cells = <2>;
143 #size-cells = <1>;
144 clock-frequency = <0>; /* Filled in by U-Boot */
145 interrupts = <6 4>;
146 interrupt-parent = <&UIC1>;
147 };
148
149 UART0: serial@ef600300 {
150 device_type = "serial";
151 compatible = "ns16550";
152 reg = <ef600300 8>;
153 virtual-reg = <ef600300>;
154 clock-frequency = <0>; /* Filled in by U-Boot */
155 current-speed = <0>; /* Filled in by U-Boot */
156 interrupt-parent = <&UIC1>;
157 interrupts = <1 4>;
158 };
159
160 UART1: serial@ef600400 {
161 device_type = "serial";
162 compatible = "ns16550";
163 reg = <ef600400 8>;
164 virtual-reg = <ef600400>;
165 clock-frequency = <0>; /* Filled in by U-Boot */
166 current-speed = <0>; /* Filled in by U-Boot */
167 interrupt-parent = <&UIC0>;
168 interrupts = <1 4>;
169 };
170
171 UART2: serial@ef600500 {
172 device_type = "serial";
173 compatible = "ns16550";
174 reg = <ef600500 8>;
175 virtual-reg = <ef600500>;
176 clock-frequency = <0>; /* Filled in by U-Boot */
177 current-speed = <0>; /* Filled in by U-Boot */
178 interrupt-parent = <&UIC1>;
179 interrupts = <1d 4>;
180 };
181
182 UART3: serial@ef600600 {
183 device_type = "serial";
184 compatible = "ns16550";
185 reg = <ef600600 8>;
186 virtual-reg = <ef600600>;
187 clock-frequency = <0>; /* Filled in by U-Boot */
188 current-speed = <0>; /* Filled in by U-Boot */
189 interrupt-parent = <&UIC1>;
190 interrupts = <1e 4>;
191 };
192
193 IIC0: i2c@ef600700 {
194 compatible = "ibm,iic-460ex", "ibm,iic";
195 reg = <ef600700 14>;
196 interrupt-parent = <&UIC0>;
197 interrupts = <2 4>;
198 };
199
200 IIC1: i2c@ef600800 {
201 compatible = "ibm,iic-460ex", "ibm,iic";
202 reg = <ef600800 14>;
203 interrupt-parent = <&UIC0>;
204 interrupts = <3 4>;
205 };
206
207 ZMII0: emac-zmii@ef600d00 {
208 compatible = "ibm,zmii-460ex", "ibm,zmii";
209 reg = <ef600d00 c>;
210 };
211
212 RGMII0: emac-rgmii@ef601500 {
213 compatible = "ibm,rgmii-460ex", "ibm,rgmii";
214 reg = <ef601500 8>;
215 has-mdio;
216 };
217
218 TAH0: emac-tah@ef601350 {
219 compatible = "ibm,tah-460ex", "ibm,tah";
220 reg = <ef601350 30>;
221 };
222
223 TAH1: emac-tah@ef601450 {
224 compatible = "ibm,tah-460ex", "ibm,tah";
225 reg = <ef601450 30>;
226 };
227
228 EMAC0: ethernet@ef600e00 {
229 device_type = "network";
230 compatible = "ibm,emac-460ex", "ibm,emac4";
231 interrupt-parent = <&EMAC0>;
232 interrupts = <0 1>;
233 #interrupt-cells = <1>;
234 #address-cells = <0>;
235 #size-cells = <0>;
236 interrupt-map = </*Status*/ 0 &UIC2 10 4
237 /*Wake*/ 1 &UIC2 14 4>;
238 reg = <ef600e00 70>;
239 local-mac-address = [000000000000]; /* Filled in by U-Boot */
240 mal-device = <&MAL0>;
241 mal-tx-channel = <0>;
242 mal-rx-channel = <0>;
243 cell-index = <0>;
244 max-frame-size = <2328>;
245 rx-fifo-size = <1000>;
246 tx-fifo-size = <800>;
247 phy-mode = "rgmii";
248 phy-map = <00000000>;
249 rgmii-device = <&RGMII0>;
250 rgmii-channel = <0>;
251 tah-device = <&TAH0>;
252 tah-channel = <0>;
253 has-inverted-stacr-oc;
254 has-new-stacr-staopc;
255 };
256
257 EMAC1: ethernet@ef600f00 {
258 device_type = "network";
259 compatible = "ibm,emac-460ex", "ibm,emac4";
260 interrupt-parent = <&EMAC1>;
261 interrupts = <0 1>;
262 #interrupt-cells = <1>;
263 #address-cells = <0>;
264 #size-cells = <0>;
265 interrupt-map = </*Status*/ 0 &UIC2 11 4
266 /*Wake*/ 1 &UIC2 15 4>;
267 reg = <ef600f00 70>;
268 local-mac-address = [000000000000]; /* Filled in by U-Boot */
269 mal-device = <&MAL0>;
270 mal-tx-channel = <1>;
271 mal-rx-channel = <8>;
272 cell-index = <1>;
273 max-frame-size = <2328>;
274 rx-fifo-size = <1000>;
275 tx-fifo-size = <800>;
276 phy-mode = "rgmii";
277 phy-map = <00000000>;
278 rgmii-device = <&RGMII0>;
279 rgmii-channel = <1>;
280 tah-device = <&TAH1>;
281 tah-channel = <1>;
282 has-inverted-stacr-oc;
283 has-new-stacr-staopc;
284 mdio-device = <&EMAC0>;
285 };
286 };
287
288 PCIX0: pci@c0ec00000 {
289 device_type = "pci";
290 #interrupt-cells = <1>;
291 #size-cells = <2>;
292 #address-cells = <3>;
293 compatible = "ibm,plb-pcix-460ex", "ibm,plb-pcix";
294 primary;
295 large-inbound-windows;
296 enable-msi-hole;
297 reg = <c 0ec00000 8 /* Config space access */
298 0 0 0 /* no IACK cycles */
299 c 0ed00000 4 /* Special cycles */
300 c 0ec80000 100 /* Internal registers */
301 c 0ec80100 fc>; /* Internal messaging registers */
302
303 /* Outbound ranges, one memory and one IO,
304 * later cannot be changed
305 */
306 ranges = <02000000 0 80000000 0000000d 80000000 0 80000000
307 01000000 0 00000000 0000000c 08000000 0 00010000>;
308
309 /* Inbound 2GB range starting at 0 */
310 dma-ranges = <42000000 0 0 0 0 0 80000000>;
311
312 /* This drives busses 0 to 0x3f */
313 bus-range = <0 3f>;
314
315 /* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */
316 interrupt-map-mask = <0000 0 0 0>;
317 interrupt-map = < 0000 0 0 0 &UIC1 0 8 >;
318 };
319
320 PCIE0: pciex@d00000000 {
321 device_type = "pci";
322 #interrupt-cells = <1>;
323 #size-cells = <2>;
324 #address-cells = <3>;
325 compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
326 primary;
327 port = <0>; /* port number */
328 reg = <d 00000000 20000000 /* Config space access */
329 c 08010000 00001000>; /* Registers */
330 dcr-reg = <100 020>;
331 sdr-base = <300>;
332
333 /* Outbound ranges, one memory and one IO,
334 * later cannot be changed
335 */
336 ranges = <02000000 0 80000000 0000000e 00000000 0 80000000
337 01000000 0 00000000 0000000f 80000000 0 00010000>;
338
339 /* Inbound 2GB range starting at 0 */
340 dma-ranges = <42000000 0 0 0 0 0 80000000>;
341
342 /* This drives busses 40 to 0x7f */
343 bus-range = <40 7f>;
344
345 /* Legacy interrupts (note the weird polarity, the bridge seems
346 * to invert PCIe legacy interrupts).
347 * We are de-swizzling here because the numbers are actually for
348 * port of the root complex virtual P2P bridge. But I want
349 * to avoid putting a node for it in the tree, so the numbers
350 * below are basically de-swizzled numbers.
351 * The real slot is on idsel 0, so the swizzling is 1:1
352 */
353 interrupt-map-mask = <0000 0 0 7>;
354 interrupt-map = <
355 0000 0 0 1 &UIC3 c 4 /* swizzled int A */
356 0000 0 0 2 &UIC3 d 4 /* swizzled int B */
357 0000 0 0 3 &UIC3 e 4 /* swizzled int C */
358 0000 0 0 4 &UIC3 f 4 /* swizzled int D */>;
359 };
360
361 PCIE1: pciex@d20000000 {
362 device_type = "pci";
363 #interrupt-cells = <1>;
364 #size-cells = <2>;
365 #address-cells = <3>;
366 compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
367 primary;
368 port = <1>; /* port number */
369 reg = <d 20000000 20000000 /* Config space access */
370 c 08011000 00001000>; /* Registers */
371 dcr-reg = <120 020>;
372 sdr-base = <340>;
373
374 /* Outbound ranges, one memory and one IO,
375 * later cannot be changed
376 */
377 ranges = <02000000 0 80000000 0000000e 80000000 0 80000000
378 01000000 0 00000000 0000000f 80010000 0 00010000>;
379
380 /* Inbound 2GB range starting at 0 */
381 dma-ranges = <42000000 0 0 0 0 0 80000000>;
382
383 /* This drives busses 80 to 0xbf */
384 bus-range = <80 bf>;
385
386 /* Legacy interrupts (note the weird polarity, the bridge seems
387 * to invert PCIe legacy interrupts).
388 * We are de-swizzling here because the numbers are actually for
389 * port of the root complex virtual P2P bridge. But I want
390 * to avoid putting a node for it in the tree, so the numbers
391 * below are basically de-swizzled numbers.
392 * The real slot is on idsel 0, so the swizzling is 1:1
393 */
394 interrupt-map-mask = <0000 0 0 7>;
395 interrupt-map = <
396 0000 0 0 1 &UIC3 10 4 /* swizzled int A */
397 0000 0 0 2 &UIC3 11 4 /* swizzled int B */
398 0000 0 0 3 &UIC3 12 4 /* swizzled int C */
399 0000 0 0 4 &UIC3 13 4 /* swizzled int D */>;
400 };
401 };
402};
diff --git a/arch/powerpc/boot/dts/ebony.dts b/arch/powerpc/boot/dts/ebony.dts
index 0b000cb7ed8b..5079dc890e0e 100644
--- a/arch/powerpc/boot/dts/ebony.dts
+++ b/arch/powerpc/boot/dts/ebony.dts
@@ -241,7 +241,6 @@
241 }; 241 };
242 242
243 EMAC0: ethernet@40000800 { 243 EMAC0: ethernet@40000800 {
244 linux,network-index = <0>;
245 device_type = "network"; 244 device_type = "network";
246 compatible = "ibm,emac-440gp", "ibm,emac"; 245 compatible = "ibm,emac-440gp", "ibm,emac";
247 interrupt-parent = <&UIC1>; 246 interrupt-parent = <&UIC1>;
@@ -261,7 +260,6 @@
261 zmii-channel = <0>; 260 zmii-channel = <0>;
262 }; 261 };
263 EMAC1: ethernet@40000900 { 262 EMAC1: ethernet@40000900 {
264 linux,network-index = <1>;
265 device_type = "network"; 263 device_type = "network";
266 compatible = "ibm,emac-440gp", "ibm,emac"; 264 compatible = "ibm,emac-440gp", "ibm,emac";
267 interrupt-parent = <&UIC1>; 265 interrupt-parent = <&UIC1>;
diff --git a/arch/powerpc/boot/dts/ep8248e.dts b/arch/powerpc/boot/dts/ep8248e.dts
index 5d2fb76a72c1..756758fb5b7b 100644
--- a/arch/powerpc/boot/dts/ep8248e.dts
+++ b/arch/powerpc/boot/dts/ep8248e.dts
@@ -121,8 +121,7 @@
121 121
122 data@0 { 122 data@0 {
123 compatible = "fsl,cpm-muram-data"; 123 compatible = "fsl,cpm-muram-data";
124 reg = <0 0x1100 0x1140 124 reg = <0 0x2000 0x9800 0x800>;
125 0xec0 0x9800 0x800>;
126 }; 125 };
127 }; 126 };
128 127
@@ -138,7 +137,7 @@
138 device_type = "serial"; 137 device_type = "serial";
139 compatible = "fsl,mpc8248-smc-uart", 138 compatible = "fsl,mpc8248-smc-uart",
140 "fsl,cpm2-smc-uart"; 139 "fsl,cpm2-smc-uart";
141 reg = <0x11a80 0x20 0x1100 0x40>; 140 reg = <0x11a80 0x20 0x87fc 2>;
142 interrupts = <4 8>; 141 interrupts = <4 8>;
143 interrupt-parent = <&PIC>; 142 interrupt-parent = <&PIC>;
144 fsl,cpm-brg = <7>; 143 fsl,cpm-brg = <7>;
diff --git a/arch/powerpc/boot/dts/ep88xc.dts b/arch/powerpc/boot/dts/ep88xc.dts
index 02705f299790..ae57d6240120 100644
--- a/arch/powerpc/boot/dts/ep88xc.dts
+++ b/arch/powerpc/boot/dts/ep88xc.dts
@@ -2,7 +2,7 @@
2 * EP88xC Device Tree Source 2 * EP88xC Device Tree Source
3 * 3 *
4 * Copyright 2006 MontaVista Software, Inc. 4 * Copyright 2006 MontaVista Software, Inc.
5 * Copyright 2007 Freescale Semiconductor, Inc. 5 * Copyright 2007,2008 Freescale Semiconductor, Inc.
6 * 6 *
7 * This program is free software; you can redistribute it and/or modify it 7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the 8 * under the terms of the GNU General Public License as published by the
@@ -10,6 +10,7 @@
10 * option) any later version. 10 * option) any later version.
11 */ 11 */
12 12
13/dts-v1/;
13 14
14/ { 15/ {
15 model = "EP88xC"; 16 model = "EP88xC";
@@ -23,44 +24,44 @@
23 24
24 PowerPC,885@0 { 25 PowerPC,885@0 {
25 device_type = "cpu"; 26 device_type = "cpu";
26 reg = <0>; 27 reg = <0x0>;
27 d-cache-line-size = <d#16>; 28 d-cache-line-size = <16>;
28 i-cache-line-size = <d#16>; 29 i-cache-line-size = <16>;
29 d-cache-size = <d#8192>; 30 d-cache-size = <8192>;
30 i-cache-size = <d#8192>; 31 i-cache-size = <8192>;
31 timebase-frequency = <0>; 32 timebase-frequency = <0>;
32 bus-frequency = <0>; 33 bus-frequency = <0>;
33 clock-frequency = <0>; 34 clock-frequency = <0>;
34 interrupts = <f 2>; // decrementer interrupt 35 interrupts = <15 2>; // decrementer interrupt
35 interrupt-parent = <&PIC>; 36 interrupt-parent = <&PIC>;
36 }; 37 };
37 }; 38 };
38 39
39 memory { 40 memory {
40 device_type = "memory"; 41 device_type = "memory";
41 reg = <0 0>; 42 reg = <0x0 0x0>;
42 }; 43 };
43 44
44 localbus@fa200100 { 45 localbus@fa200100 {
45 compatible = "fsl,mpc885-localbus", "fsl,pq1-localbus"; 46 compatible = "fsl,mpc885-localbus", "fsl,pq1-localbus";
46 #address-cells = <2>; 47 #address-cells = <2>;
47 #size-cells = <1>; 48 #size-cells = <1>;
48 reg = <fa200100 40>; 49 reg = <0xfa200100 0x40>;
49 50
50 ranges = < 51 ranges = <
51 0 0 fc000000 04000000 52 0x0 0x0 0xfc000000 0x4000000
52 3 0 fa000000 01000000 53 0x3 0x0 0xfa000000 0x1000000
53 >; 54 >;
54 55
55 flash@0,2000000 { 56 flash@0,2000000 {
56 compatible = "cfi-flash"; 57 compatible = "cfi-flash";
57 reg = <0 2000000 2000000>; 58 reg = <0x0 0x2000000 0x2000000>;
58 bank-width = <4>; 59 bank-width = <4>;
59 device-width = <2>; 60 device-width = <2>;
60 }; 61 };
61 62
62 board-control@3,400000 { 63 board-control@3,400000 {
63 reg = <3 400000 10>; 64 reg = <0x3 0x400000 0x10>;
64 compatible = "fsl,ep88xc-bcsr"; 65 compatible = "fsl,ep88xc-bcsr";
65 }; 66 };
66 }; 67 };
@@ -70,25 +71,25 @@
70 #address-cells = <1>; 71 #address-cells = <1>;
71 #size-cells = <1>; 72 #size-cells = <1>;
72 device_type = "soc"; 73 device_type = "soc";
73 ranges = <0 fa200000 00004000>; 74 ranges = <0x0 0xfa200000 0x4000>;
74 bus-frequency = <0>; 75 bus-frequency = <0>;
75 76
76 // Temporary -- will go away once kernel uses ranges for get_immrbase(). 77 // Temporary -- will go away once kernel uses ranges for get_immrbase().
77 reg = <fa200000 4000>; 78 reg = <0xfa200000 0x4000>;
78 79
79 mdio@e00 { 80 mdio@e00 {
80 compatible = "fsl,mpc885-fec-mdio", "fsl,pq1-fec-mdio"; 81 compatible = "fsl,mpc885-fec-mdio", "fsl,pq1-fec-mdio";
81 reg = <e00 188>; 82 reg = <0xe00 0x188>;
82 #address-cells = <1>; 83 #address-cells = <1>;
83 #size-cells = <0>; 84 #size-cells = <0>;
84 85
85 PHY0: ethernet-phy@0 { 86 PHY0: ethernet-phy@0 {
86 reg = <0>; 87 reg = <0x0>;
87 device_type = "ethernet-phy"; 88 device_type = "ethernet-phy";
88 }; 89 };
89 90
90 PHY1: ethernet-phy@1 { 91 PHY1: ethernet-phy@1 {
91 reg = <1>; 92 reg = <0x1>;
92 device_type = "ethernet-phy"; 93 device_type = "ethernet-phy";
93 }; 94 };
94 }; 95 };
@@ -97,7 +98,7 @@
97 device_type = "network"; 98 device_type = "network";
98 compatible = "fsl,mpc885-fec-enet", 99 compatible = "fsl,mpc885-fec-enet",
99 "fsl,pq1-fec-enet"; 100 "fsl,pq1-fec-enet";
100 reg = <e00 188>; 101 reg = <0xe00 0x188>;
101 local-mac-address = [ 00 00 00 00 00 00 ]; 102 local-mac-address = [ 00 00 00 00 00 00 ];
102 interrupts = <3 1>; 103 interrupts = <3 1>;
103 interrupt-parent = <&PIC>; 104 interrupt-parent = <&PIC>;
@@ -109,7 +110,7 @@
109 device_type = "network"; 110 device_type = "network";
110 compatible = "fsl,mpc885-fec-enet", 111 compatible = "fsl,mpc885-fec-enet",
111 "fsl,pq1-fec-enet"; 112 "fsl,pq1-fec-enet";
112 reg = <1e00 188>; 113 reg = <0x1e00 0x188>;
113 local-mac-address = [ 00 00 00 00 00 00 ]; 114 local-mac-address = [ 00 00 00 00 00 00 ];
114 interrupts = <7 1>; 115 interrupts = <7 1>;
115 interrupt-parent = <&PIC>; 116 interrupt-parent = <&PIC>;
@@ -120,7 +121,7 @@
120 PIC: interrupt-controller@0 { 121 PIC: interrupt-controller@0 {
121 interrupt-controller; 122 interrupt-controller;
122 #interrupt-cells = <2>; 123 #interrupt-cells = <2>;
123 reg = <0 24>; 124 reg = <0x0 0x24>;
124 compatible = "fsl,mpc885-pic", "fsl,pq1-pic"; 125 compatible = "fsl,mpc885-pic", "fsl,pq1-pic";
125 }; 126 };
126 127
@@ -130,29 +131,29 @@
130 #size-cells = <2>; 131 #size-cells = <2>;
131 compatible = "fsl,pq-pcmcia"; 132 compatible = "fsl,pq-pcmcia";
132 device_type = "pcmcia"; 133 device_type = "pcmcia";
133 reg = <80 80>; 134 reg = <0x80 0x80>;
134 interrupt-parent = <&PIC>; 135 interrupt-parent = <&PIC>;
135 interrupts = <d 1>; 136 interrupts = <13 1>;
136 }; 137 };
137 138
138 cpm@9c0 { 139 cpm@9c0 {
139 #address-cells = <1>; 140 #address-cells = <1>;
140 #size-cells = <1>; 141 #size-cells = <1>;
141 compatible = "fsl,mpc885-cpm", "fsl,cpm1"; 142 compatible = "fsl,mpc885-cpm", "fsl,cpm1";
142 command-proc = <9c0>; 143 command-proc = <0x9c0>;
143 interrupts = <0>; // cpm error interrupt 144 interrupts = <0>; // cpm error interrupt
144 interrupt-parent = <&CPM_PIC>; 145 interrupt-parent = <&CPM_PIC>;
145 reg = <9c0 40>; 146 reg = <0x9c0 0x40>;
146 ranges; 147 ranges;
147 148
148 muram@2000 { 149 muram@2000 {
149 #address-cells = <1>; 150 #address-cells = <1>;
150 #size-cells = <1>; 151 #size-cells = <1>;
151 ranges = <0 2000 2000>; 152 ranges = <0x0 0x2000 0x2000>;
152 153
153 data@0 { 154 data@0 {
154 compatible = "fsl,cpm-muram-data"; 155 compatible = "fsl,cpm-muram-data";
155 reg = <0 1c00>; 156 reg = <0x0 0x1c00>;
156 }; 157 };
157 }; 158 };
158 159
@@ -160,7 +161,7 @@
160 compatible = "fsl,mpc885-brg", 161 compatible = "fsl,mpc885-brg",
161 "fsl,cpm1-brg", 162 "fsl,cpm1-brg",
162 "fsl,cpm-brg"; 163 "fsl,cpm-brg";
163 reg = <9f0 10>; 164 reg = <0x9f0 0x10>;
164 }; 165 };
165 166
166 CPM_PIC: interrupt-controller@930 { 167 CPM_PIC: interrupt-controller@930 {
@@ -168,7 +169,7 @@
168 #interrupt-cells = <1>; 169 #interrupt-cells = <1>;
169 interrupts = <5 2 0 2>; 170 interrupts = <5 2 0 2>;
170 interrupt-parent = <&PIC>; 171 interrupt-parent = <&PIC>;
171 reg = <930 20>; 172 reg = <0x930 0x20>;
172 compatible = "fsl,mpc885-cpm-pic", 173 compatible = "fsl,mpc885-cpm-pic",
173 "fsl,cpm1-pic"; 174 "fsl,cpm1-pic";
174 }; 175 };
@@ -178,11 +179,11 @@
178 device_type = "serial"; 179 device_type = "serial";
179 compatible = "fsl,mpc885-smc-uart", 180 compatible = "fsl,mpc885-smc-uart",
180 "fsl,cpm1-smc-uart"; 181 "fsl,cpm1-smc-uart";
181 reg = <a80 10 3e80 40>; 182 reg = <0xa80 0x10 0x3e80 0x40>;
182 interrupts = <4>; 183 interrupts = <4>;
183 interrupt-parent = <&CPM_PIC>; 184 interrupt-parent = <&CPM_PIC>;
184 fsl,cpm-brg = <1>; 185 fsl,cpm-brg = <1>;
185 fsl,cpm-command = <0090>; 186 fsl,cpm-command = <0x90>;
186 linux,planetcore-label = "SMC1"; 187 linux,planetcore-label = "SMC1";
187 }; 188 };
188 189
@@ -191,11 +192,11 @@
191 device_type = "serial"; 192 device_type = "serial";
192 compatible = "fsl,mpc885-scc-uart", 193 compatible = "fsl,mpc885-scc-uart",
193 "fsl,cpm1-scc-uart"; 194 "fsl,cpm1-scc-uart";
194 reg = <a20 20 3d00 80>; 195 reg = <0xa20 0x20 0x3d00 0x80>;
195 interrupts = <1d>; 196 interrupts = <29>;
196 interrupt-parent = <&CPM_PIC>; 197 interrupt-parent = <&CPM_PIC>;
197 fsl,cpm-brg = <2>; 198 fsl,cpm-brg = <2>;
198 fsl,cpm-command = <0040>; 199 fsl,cpm-command = <0x40>;
199 linux,planetcore-label = "SCC2"; 200 linux,planetcore-label = "SCC2";
200 }; 201 };
201 202
@@ -204,9 +205,9 @@
204 #size-cells = <0>; 205 #size-cells = <0>;
205 compatible = "fsl,mpc885-usb", 206 compatible = "fsl,mpc885-usb",
206 "fsl,cpm1-usb"; 207 "fsl,cpm1-usb";
207 reg = <a00 18 1c00 80>; 208 reg = <0xa00 0x18 0x1c00 0x80>;
208 interrupt-parent = <&CPM_PIC>; 209 interrupt-parent = <&CPM_PIC>;
209 interrupts = <1e>; 210 interrupts = <30>;
210 fsl,cpm-command = <0000>; 211 fsl,cpm-command = <0000>;
211 }; 212 };
212 }; 213 };
diff --git a/arch/powerpc/boot/dts/glacier.dts b/arch/powerpc/boot/dts/glacier.dts
new file mode 100644
index 000000000000..958a5ca53d35
--- /dev/null
+++ b/arch/powerpc/boot/dts/glacier.dts
@@ -0,0 +1,467 @@
1/*
2 * Device Tree Source for AMCC Glacier (460GT)
3 *
4 * Copyright 2008 DENX Software Engineering, Stefan Roese <sr@denx.de>
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without
8 * any warranty of any kind, whether express or implied.
9 */
10
11/ {
12 #address-cells = <2>;
13 #size-cells = <1>;
14 model = "amcc,glacier";
15 compatible = "amcc,glacier", "amcc,canyonlands";
16 dcr-parent = <&/cpus/cpu@0>;
17
18 aliases {
19 ethernet0 = &EMAC0;
20 ethernet1 = &EMAC1;
21 ethernet2 = &EMAC2;
22 ethernet3 = &EMAC3;
23 serial0 = &UART0;
24 serial1 = &UART1;
25 };
26
27 cpus {
28 #address-cells = <1>;
29 #size-cells = <0>;
30
31 cpu@0 {
32 device_type = "cpu";
33 model = "PowerPC,460GT";
34 reg = <0>;
35 clock-frequency = <0>; /* Filled in by U-Boot */
36 timebase-frequency = <0>; /* Filled in by U-Boot */
37 i-cache-line-size = <20>;
38 d-cache-line-size = <20>;
39 i-cache-size = <8000>;
40 d-cache-size = <8000>;
41 dcr-controller;
42 dcr-access-method = "native";
43 };
44 };
45
46 memory {
47 device_type = "memory";
48 reg = <0 0 0>; /* Filled in by U-Boot */
49 };
50
51 UIC0: interrupt-controller0 {
52 compatible = "ibm,uic-460gt","ibm,uic";
53 interrupt-controller;
54 cell-index = <0>;
55 dcr-reg = <0c0 009>;
56 #address-cells = <0>;
57 #size-cells = <0>;
58 #interrupt-cells = <2>;
59 };
60
61 UIC1: interrupt-controller1 {
62 compatible = "ibm,uic-460gt","ibm,uic";
63 interrupt-controller;
64 cell-index = <1>;
65 dcr-reg = <0d0 009>;
66 #address-cells = <0>;
67 #size-cells = <0>;
68 #interrupt-cells = <2>;
69 interrupts = <1e 4 1f 4>; /* cascade */
70 interrupt-parent = <&UIC0>;
71 };
72
73 UIC2: interrupt-controller2 {
74 compatible = "ibm,uic-460gt","ibm,uic";
75 interrupt-controller;
76 cell-index = <2>;
77 dcr-reg = <0e0 009>;
78 #address-cells = <0>;
79 #size-cells = <0>;
80 #interrupt-cells = <2>;
81 interrupts = <a 4 b 4>; /* cascade */
82 interrupt-parent = <&UIC0>;
83 };
84
85 UIC3: interrupt-controller3 {
86 compatible = "ibm,uic-460gt","ibm,uic";
87 interrupt-controller;
88 cell-index = <3>;
89 dcr-reg = <0f0 009>;
90 #address-cells = <0>;
91 #size-cells = <0>;
92 #interrupt-cells = <2>;
93 interrupts = <10 4 11 4>; /* cascade */
94 interrupt-parent = <&UIC0>;
95 };
96
97 SDR0: sdr {
98 compatible = "ibm,sdr-460gt";
99 dcr-reg = <00e 002>;
100 };
101
102 CPR0: cpr {
103 compatible = "ibm,cpr-460gt";
104 dcr-reg = <00c 002>;
105 };
106
107 plb {
108 compatible = "ibm,plb-460gt", "ibm,plb4";
109 #address-cells = <2>;
110 #size-cells = <1>;
111 ranges;
112 clock-frequency = <0>; /* Filled in by U-Boot */
113
114 SDRAM0: sdram {
115 compatible = "ibm,sdram-460gt", "ibm,sdram-405gp";
116 dcr-reg = <010 2>;
117 };
118
119 MAL0: mcmal {
120 compatible = "ibm,mcmal-460gt", "ibm,mcmal2";
121 dcr-reg = <180 62>;
122 num-tx-chans = <4>;
123 num-rx-chans = <20>;
124 #address-cells = <0>;
125 #size-cells = <0>;
126 interrupt-parent = <&UIC2>;
127 interrupts = < /*TXEOB*/ 6 4
128 /*RXEOB*/ 7 4
129 /*SERR*/ 3 4
130 /*TXDE*/ 4 4
131 /*RXDE*/ 5 4>;
132 desc-base-addr-high = <8>;
133 };
134
135 POB0: opb {
136 compatible = "ibm,opb-460gt", "ibm,opb";
137 #address-cells = <1>;
138 #size-cells = <1>;
139 ranges = <b0000000 4 b0000000 50000000>;
140 clock-frequency = <0>; /* Filled in by U-Boot */
141
142 EBC0: ebc {
143 compatible = "ibm,ebc-460gt", "ibm,ebc";
144 dcr-reg = <012 2>;
145 #address-cells = <2>;
146 #size-cells = <1>;
147 clock-frequency = <0>; /* Filled in by U-Boot */
148 interrupts = <6 4>;
149 interrupt-parent = <&UIC1>;
150 };
151
152 UART0: serial@ef600300 {
153 device_type = "serial";
154 compatible = "ns16550";
155 reg = <ef600300 8>;
156 virtual-reg = <ef600300>;
157 clock-frequency = <0>; /* Filled in by U-Boot */
158 current-speed = <0>; /* Filled in by U-Boot */
159 interrupt-parent = <&UIC1>;
160 interrupts = <1 4>;
161 };
162
163 UART1: serial@ef600400 {
164 device_type = "serial";
165 compatible = "ns16550";
166 reg = <ef600400 8>;
167 virtual-reg = <ef600400>;
168 clock-frequency = <0>; /* Filled in by U-Boot */
169 current-speed = <0>; /* Filled in by U-Boot */
170 interrupt-parent = <&UIC0>;
171 interrupts = <1 4>;
172 };
173
174 UART2: serial@ef600500 {
175 device_type = "serial";
176 compatible = "ns16550";
177 reg = <ef600500 8>;
178 virtual-reg = <ef600500>;
179 clock-frequency = <0>; /* Filled in by U-Boot */
180 current-speed = <0>; /* Filled in by U-Boot */
181 interrupt-parent = <&UIC1>;
182 interrupts = <1d 4>;
183 };
184
185 UART3: serial@ef600600 {
186 device_type = "serial";
187 compatible = "ns16550";
188 reg = <ef600600 8>;
189 virtual-reg = <ef600600>;
190 clock-frequency = <0>; /* Filled in by U-Boot */
191 current-speed = <0>; /* Filled in by U-Boot */
192 interrupt-parent = <&UIC1>;
193 interrupts = <1e 4>;
194 };
195
196 IIC0: i2c@ef600700 {
197 compatible = "ibm,iic-460gt", "ibm,iic";
198 reg = <ef600700 14>;
199 interrupt-parent = <&UIC0>;
200 interrupts = <2 4>;
201 };
202
203 IIC1: i2c@ef600800 {
204 compatible = "ibm,iic-460gt", "ibm,iic";
205 reg = <ef600800 14>;
206 interrupt-parent = <&UIC0>;
207 interrupts = <3 4>;
208 };
209
210 ZMII0: emac-zmii@ef600d00 {
211 compatible = "ibm,zmii-460gt", "ibm,zmii";
212 reg = <ef600d00 c>;
213 };
214
215 RGMII0: emac-rgmii@ef601500 {
216 compatible = "ibm,rgmii-460gt", "ibm,rgmii";
217 reg = <ef601500 8>;
218 has-mdio;
219 };
220
221 RGMII1: emac-rgmii@ef601600 {
222 compatible = "ibm,rgmii-460gt", "ibm,rgmii";
223 reg = <ef601600 8>;
224 has-mdio;
225 };
226
227 TAH0: emac-tah@ef601350 {
228 compatible = "ibm,tah-460gt", "ibm,tah";
229 reg = <ef601350 30>;
230 };
231
232 TAH1: emac-tah@ef601450 {
233 compatible = "ibm,tah-460gt", "ibm,tah";
234 reg = <ef601450 30>;
235 };
236
237 EMAC0: ethernet@ef600e00 {
238 device_type = "network";
239 compatible = "ibm,emac-460gt", "ibm,emac4";
240 interrupt-parent = <&EMAC0>;
241 interrupts = <0 1>;
242 #interrupt-cells = <1>;
243 #address-cells = <0>;
244 #size-cells = <0>;
245 interrupt-map = </*Status*/ 0 &UIC2 10 4
246 /*Wake*/ 1 &UIC2 14 4>;
247 reg = <ef600e00 70>;
248 local-mac-address = [000000000000]; /* Filled in by U-Boot */
249 mal-device = <&MAL0>;
250 mal-tx-channel = <0>;
251 mal-rx-channel = <0>;
252 cell-index = <0>;
253 max-frame-size = <2328>;
254 rx-fifo-size = <1000>;
255 tx-fifo-size = <800>;
256 phy-mode = "rgmii";
257 phy-map = <00000000>;
258 rgmii-device = <&RGMII0>;
259 rgmii-channel = <0>;
260 tah-device = <&TAH0>;
261 tah-channel = <0>;
262 has-inverted-stacr-oc;
263 has-new-stacr-staopc;
264 };
265
266 EMAC1: ethernet@ef600f00 {
267 device_type = "network";
268 compatible = "ibm,emac-460gt", "ibm,emac4";
269 interrupt-parent = <&EMAC1>;
270 interrupts = <0 1>;
271 #interrupt-cells = <1>;
272 #address-cells = <0>;
273 #size-cells = <0>;
274 interrupt-map = </*Status*/ 0 &UIC2 11 4
275 /*Wake*/ 1 &UIC2 15 4>;
276 reg = <ef600f00 70>;
277 local-mac-address = [000000000000]; /* Filled in by U-Boot */
278 mal-device = <&MAL0>;
279 mal-tx-channel = <1>;
280 mal-rx-channel = <8>;
281 cell-index = <1>;
282 max-frame-size = <2328>;
283 rx-fifo-size = <1000>;
284 tx-fifo-size = <800>;
285 phy-mode = "rgmii";
286 phy-map = <00000000>;
287 rgmii-device = <&RGMII0>;
288 rgmii-channel = <1>;
289 tah-device = <&TAH1>;
290 tah-channel = <1>;
291 has-inverted-stacr-oc;
292 has-new-stacr-staopc;
293 mdio-device = <&EMAC0>;
294 };
295
296 EMAC2: ethernet@ef601100 {
297 device_type = "network";
298 compatible = "ibm,emac-460gt", "ibm,emac4";
299 interrupt-parent = <&EMAC2>;
300 interrupts = <0 1>;
301 #interrupt-cells = <1>;
302 #address-cells = <0>;
303 #size-cells = <0>;
304 interrupt-map = </*Status*/ 0 &UIC2 12 4
305 /*Wake*/ 1 &UIC2 16 4>;
306 reg = <ef601100 70>;
307 local-mac-address = [000000000000]; /* Filled in by U-Boot */
308 mal-device = <&MAL0>;
309 mal-tx-channel = <2>;
310 mal-rx-channel = <10>;
311 cell-index = <2>;
312 max-frame-size = <2328>;
313 rx-fifo-size = <1000>;
314 tx-fifo-size = <800>;
315 phy-mode = "rgmii";
316 phy-map = <00000000>;
317 rgmii-device = <&RGMII1>;
318 rgmii-channel = <0>;
319 has-inverted-stacr-oc;
320 has-new-stacr-staopc;
321 mdio-device = <&EMAC0>;
322 };
323
324 EMAC3: ethernet@ef601200 {
325 device_type = "network";
326 compatible = "ibm,emac-460gt", "ibm,emac4";
327 interrupt-parent = <&EMAC3>;
328 interrupts = <0 1>;
329 #interrupt-cells = <1>;
330 #address-cells = <0>;
331 #size-cells = <0>;
332 interrupt-map = </*Status*/ 0 &UIC2 13 4
333 /*Wake*/ 1 &UIC2 17 4>;
334 reg = <ef601200 70>;
335 local-mac-address = [000000000000]; /* Filled in by U-Boot */
336 mal-device = <&MAL0>;
337 mal-tx-channel = <3>;
338 mal-rx-channel = <18>;
339 cell-index = <3>;
340 max-frame-size = <2328>;
341 rx-fifo-size = <1000>;
342 tx-fifo-size = <800>;
343 phy-mode = "rgmii";
344 phy-map = <00000000>;
345 rgmii-device = <&RGMII1>;
346 rgmii-channel = <1>;
347 has-inverted-stacr-oc;
348 has-new-stacr-staopc;
349 mdio-device = <&EMAC0>;
350 };
351 };
352
353 PCIX0: pci@c0ec00000 {
354 device_type = "pci";
355 #interrupt-cells = <1>;
356 #size-cells = <2>;
357 #address-cells = <3>;
358 compatible = "ibm,plb-pcix-460gt", "ibm,plb-pcix";
359 primary;
360 large-inbound-windows;
361 enable-msi-hole;
362 reg = <c 0ec00000 8 /* Config space access */
363 0 0 0 /* no IACK cycles */
364 c 0ed00000 4 /* Special cycles */
365 c 0ec80000 100 /* Internal registers */
366 c 0ec80100 fc>; /* Internal messaging registers */
367
368 /* Outbound ranges, one memory and one IO,
369 * later cannot be changed
370 */
371 ranges = <02000000 0 80000000 0000000d 80000000 0 80000000
372 01000000 0 00000000 0000000c 08000000 0 00010000>;
373
374 /* Inbound 2GB range starting at 0 */
375 dma-ranges = <42000000 0 0 0 0 0 80000000>;
376
377 /* This drives busses 0 to 0x3f */
378 bus-range = <0 3f>;
379
380 /* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */
381 interrupt-map-mask = <0000 0 0 0>;
382 interrupt-map = < 0000 0 0 0 &UIC1 0 8 >;
383 };
384
385 PCIE0: pciex@d00000000 {
386 device_type = "pci";
387 #interrupt-cells = <1>;
388 #size-cells = <2>;
389 #address-cells = <3>;
390 compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
391 primary;
392 port = <0>; /* port number */
393 reg = <d 00000000 20000000 /* Config space access */
394 c 08010000 00001000>; /* Registers */
395 dcr-reg = <100 020>;
396 sdr-base = <300>;
397
398 /* Outbound ranges, one memory and one IO,
399 * later cannot be changed
400 */
401 ranges = <02000000 0 80000000 0000000e 00000000 0 80000000
402 01000000 0 00000000 0000000f 80000000 0 00010000>;
403
404 /* Inbound 2GB range starting at 0 */
405 dma-ranges = <42000000 0 0 0 0 0 80000000>;
406
407 /* This drives busses 40 to 0x7f */
408 bus-range = <40 7f>;
409
410 /* Legacy interrupts (note the weird polarity, the bridge seems
411 * to invert PCIe legacy interrupts).
412 * We are de-swizzling here because the numbers are actually for
413 * port of the root complex virtual P2P bridge. But I want
414 * to avoid putting a node for it in the tree, so the numbers
415 * below are basically de-swizzled numbers.
416 * The real slot is on idsel 0, so the swizzling is 1:1
417 */
418 interrupt-map-mask = <0000 0 0 7>;
419 interrupt-map = <
420 0000 0 0 1 &UIC3 c 4 /* swizzled int A */
421 0000 0 0 2 &UIC3 d 4 /* swizzled int B */
422 0000 0 0 3 &UIC3 e 4 /* swizzled int C */
423 0000 0 0 4 &UIC3 f 4 /* swizzled int D */>;
424 };
425
426 PCIE1: pciex@d20000000 {
427 device_type = "pci";
428 #interrupt-cells = <1>;
429 #size-cells = <2>;
430 #address-cells = <3>;
431 compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
432 primary;
433 port = <1>; /* port number */
434 reg = <d 20000000 20000000 /* Config space access */
435 c 08011000 00001000>; /* Registers */
436 dcr-reg = <120 020>;
437 sdr-base = <340>;
438
439 /* Outbound ranges, one memory and one IO,
440 * later cannot be changed
441 */
442 ranges = <02000000 0 80000000 0000000e 80000000 0 80000000
443 01000000 0 00000000 0000000f 80010000 0 00010000>;
444
445 /* Inbound 2GB range starting at 0 */
446 dma-ranges = <42000000 0 0 0 0 0 80000000>;
447
448 /* This drives busses 80 to 0xbf */
449 bus-range = <80 bf>;
450
451 /* Legacy interrupts (note the weird polarity, the bridge seems
452 * to invert PCIe legacy interrupts).
453 * We are de-swizzling here because the numbers are actually for
454 * port of the root complex virtual P2P bridge. But I want
455 * to avoid putting a node for it in the tree, so the numbers
456 * below are basically de-swizzled numbers.
457 * The real slot is on idsel 0, so the swizzling is 1:1
458 */
459 interrupt-map-mask = <0000 0 0 7>;
460 interrupt-map = <
461 0000 0 0 1 &UIC3 10 4 /* swizzled int A */
462 0000 0 0 2 &UIC3 11 4 /* swizzled int B */
463 0000 0 0 3 &UIC3 12 4 /* swizzled int C */
464 0000 0 0 4 &UIC3 13 4 /* swizzled int D */>;
465 };
466 };
467};
diff --git a/arch/powerpc/boot/dts/haleakala.dts b/arch/powerpc/boot/dts/haleakala.dts
index ae68fefc01b6..b5d95ac24dbf 100644
--- a/arch/powerpc/boot/dts/haleakala.dts
+++ b/arch/powerpc/boot/dts/haleakala.dts
@@ -12,7 +12,7 @@
12 #address-cells = <1>; 12 #address-cells = <1>;
13 #size-cells = <1>; 13 #size-cells = <1>;
14 model = "amcc,haleakala"; 14 model = "amcc,haleakala";
15 compatible = "amcc,kilauea"; 15 compatible = "amcc,haleakala", "amcc,kilauea";
16 dcr-parent = <&/cpus/cpu@0>; 16 dcr-parent = <&/cpus/cpu@0>;
17 17
18 aliases { 18 aliases {
@@ -218,7 +218,7 @@
218 mal-tx-channel = <0>; 218 mal-tx-channel = <0>;
219 mal-rx-channel = <0>; 219 mal-rx-channel = <0>;
220 cell-index = <0>; 220 cell-index = <0>;
221 max-frame-size = <5dc>; 221 max-frame-size = <2328>;
222 rx-fifo-size = <1000>; 222 rx-fifo-size = <1000>;
223 tx-fifo-size = <800>; 223 tx-fifo-size = <800>;
224 phy-mode = "rgmii"; 224 phy-mode = "rgmii";
diff --git a/arch/powerpc/boot/dts/katmai.dts b/arch/powerpc/boot/dts/katmai.dts
index fc86e5a3afc4..cc2873a531d2 100644
--- a/arch/powerpc/boot/dts/katmai.dts
+++ b/arch/powerpc/boot/dts/katmai.dts
@@ -212,7 +212,7 @@
212 mal-tx-channel = <0>; 212 mal-tx-channel = <0>;
213 mal-rx-channel = <0>; 213 mal-rx-channel = <0>;
214 cell-index = <0>; 214 cell-index = <0>;
215 max-frame-size = <5dc>; 215 max-frame-size = <2328>;
216 rx-fifo-size = <1000>; 216 rx-fifo-size = <1000>;
217 tx-fifo-size = <800>; 217 tx-fifo-size = <800>;
218 phy-mode = "gmii"; 218 phy-mode = "gmii";
diff --git a/arch/powerpc/boot/dts/kilauea.dts b/arch/powerpc/boot/dts/kilauea.dts
index 8baef61f31cd..48c9a6e71f1a 100644
--- a/arch/powerpc/boot/dts/kilauea.dts
+++ b/arch/powerpc/boot/dts/kilauea.dts
@@ -219,7 +219,7 @@
219 mal-tx-channel = <0>; 219 mal-tx-channel = <0>;
220 mal-rx-channel = <0>; 220 mal-rx-channel = <0>;
221 cell-index = <0>; 221 cell-index = <0>;
222 max-frame-size = <5dc>; 222 max-frame-size = <2328>;
223 rx-fifo-size = <1000>; 223 rx-fifo-size = <1000>;
224 tx-fifo-size = <800>; 224 tx-fifo-size = <800>;
225 phy-mode = "rgmii"; 225 phy-mode = "rgmii";
@@ -247,7 +247,7 @@
247 mal-tx-channel = <1>; 247 mal-tx-channel = <1>;
248 mal-rx-channel = <1>; 248 mal-rx-channel = <1>;
249 cell-index = <1>; 249 cell-index = <1>;
250 max-frame-size = <5dc>; 250 max-frame-size = <2328>;
251 rx-fifo-size = <1000>; 251 rx-fifo-size = <1000>;
252 tx-fifo-size = <800>; 252 tx-fifo-size = <800>;
253 phy-mode = "rgmii"; 253 phy-mode = "rgmii";
diff --git a/arch/powerpc/boot/dts/ksi8560.dts b/arch/powerpc/boot/dts/ksi8560.dts
new file mode 100644
index 000000000000..f869ce3ca0b7
--- /dev/null
+++ b/arch/powerpc/boot/dts/ksi8560.dts
@@ -0,0 +1,267 @@
1/*
2 * Device Tree Source for Emerson KSI8560
3 *
4 * Author: Alexandr Smirnov <asmirnov@ru.mvista.com>
5 *
6 * Based on mpc8560ads.dts
7 *
8 * 2008 (c) MontaVista, Software, Inc. This file is licensed under
9 * the terms of the GNU General Public License version 2. This program
10 * is licensed "as is" without any warranty of any kind, whether express
11 * or implied.
12 *
13 */
14
15/dts-v1/;
16
17/ {
18 model = "KSI8560";
19 compatible = "emerson,KSI8560";
20 #address-cells = <1>;
21 #size-cells = <1>;
22
23 aliases {
24 ethernet0 = &enet0;
25 ethernet1 = &enet1;
26 ethernet2 = &enet2;
27 };
28
29 cpus {
30 #address-cells = <1>;
31 #size-cells = <0>;
32
33 PowerPC,8560@0 {
34 device_type = "cpu";
35 reg = <0>;
36 d-cache-line-size = <32>;
37 i-cache-line-size = <32>;
38 d-cache-size = <0x8000>; /* L1, 32K */
39 i-cache-size = <0x8000>; /* L1, 32K */
40 timebase-frequency = <0>; /* From U-boot */
41 bus-frequency = <0>; /* From U-boot */
42 clock-frequency = <0>; /* From U-boot */
43 };
44 };
45
46 memory {
47 device_type = "memory";
48 reg = <0x00000000 0x10000000>; /* Fixed by bootwrapper */
49 };
50
51 soc@fdf00000 {
52 #address-cells = <1>;
53 #size-cells = <1>;
54 device_type = "soc";
55 ranges = <0x00000000 0xfdf00000 0x00100000>;
56 bus-frequency = <0>; /* Fixed by bootwrapper */
57
58 memory-controller@2000 {
59 compatible = "fsl,8540-memory-controller";
60 reg = <0x2000 0x1000>;
61 interrupt-parent = <&MPIC>;
62 interrupts = <0x12 0x2>;
63 };
64
65 l2-cache-controller@20000 {
66 compatible = "fsl,8540-l2-cache-controller";
67 reg = <0x20000 0x1000>;
68 cache-line-size = <0x20>; /* 32 bytes */
69 cache-size = <0x40000>; /* L2, 256K */
70 interrupt-parent = <&MPIC>;
71 interrupts = <0x10 0x2>;
72 };
73
74 i2c@3000 {
75 #address-cells = <1>;
76 #size-cells = <0>;
77 cell-index = <0>;
78 compatible = "fsl-i2c";
79 reg = <0x3000 0x100>;
80 interrupts = <0x2b 0x2>;
81 interrupt-parent = <&MPIC>;
82 dfsrr;
83 };
84
85 mdio@24520 { /* For TSECs */
86 #address-cells = <1>;
87 #size-cells = <0>;
88 compatible = "fsl,gianfar-mdio";
89 reg = <0x24520 0x20>;
90
91 PHY1: ethernet-phy@1 {
92 interrupt-parent = <&MPIC>;
93 reg = <0x1>;
94 device_type = "ethernet-phy";
95 };
96
97 PHY2: ethernet-phy@2 {
98 interrupt-parent = <&MPIC>;
99 reg = <0x2>;
100 device_type = "ethernet-phy";
101 };
102 };
103
104 enet0: ethernet@24000 {
105 device_type = "network";
106 model = "TSEC";
107 compatible = "gianfar";
108 reg = <0x24000 0x1000>;
109 /* Mac address filled in by bootwrapper */
110 local-mac-address = [ 00 00 00 00 00 00 ];
111 interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>;
112 interrupt-parent = <&MPIC>;
113 phy-handle = <&PHY1>;
114 };
115
116 enet1: ethernet@25000 {
117 device_type = "network";
118 model = "TSEC";
119 compatible = "gianfar";
120 reg = <0x25000 0x1000>;
121 /* Mac address filled in by bootwrapper */
122 local-mac-address = [ 00 00 00 00 00 00 ];
123 interrupts = <0x23 0x2 0x24 0x2 0x28 0x2>;
124 interrupt-parent = <&MPIC>;
125 phy-handle = <&PHY2>;
126 };
127
128 MPIC: pic@40000 {
129 #address-cells = <0>;
130 #interrupt-cells = <2>;
131 interrupt-controller;
132 reg = <0x40000 0x40000>;
133 device_type = "open-pic";
134 };
135
136 cpm@919c0 {
137 #address-cells = <1>;
138 #size-cells = <1>;
139 compatible = "fsl,mpc8560-cpm", "fsl,cpm2";
140 reg = <0x919c0 0x30>;
141 ranges;
142
143 muram@80000 {
144 #address-cells = <1>;
145 #size-cells = <1>;
146 ranges = <0x0 0x80000 0x10000>;
147
148 data@0 {
149 compatible = "fsl,cpm-muram-data";
150 reg = <0x0 0x4000 0x9000 0x2000>;
151 };
152 };
153
154 brg@919f0 {
155 compatible = "fsl,mpc8560-brg",
156 "fsl,cpm2-brg",
157 "fsl,cpm-brg";
158 reg = <0x919f0 0x10 0x915f0 0x10>;
159 clock-frequency = <165000000>; /* 166MHz */
160 };
161
162 CPMPIC: pic@90c00 {
163 #address-cells = <0>;
164 #interrupt-cells = <2>;
165 interrupt-controller;
166 interrupts = <0x2e 0x2>;
167 interrupt-parent = <&MPIC>;
168 reg = <0x90c00 0x80>;
169 compatible = "fsl,mpc8560-cpm-pic", "fsl,cpm2-pic";
170 };
171
172 serial@91a00 {
173 device_type = "serial";
174 compatible = "fsl,mpc8560-scc-uart",
175 "fsl,cpm2-scc-uart";
176 reg = <0x91a00 0x20 0x88000 0x100>;
177 fsl,cpm-brg = <1>;
178 fsl,cpm-command = <0x800000>;
179 current-speed = <0x1c200>;
180 interrupts = <0x28 0x8>;
181 interrupt-parent = <&CPMPIC>;
182 };
183
184 serial@91a20 {
185 device_type = "serial";
186 compatible = "fsl,mpc8560-scc-uart",
187 "fsl,cpm2-scc-uart";
188 reg = <0x91a20 0x20 0x88100 0x100>;
189 fsl,cpm-brg = <2>;
190 fsl,cpm-command = <0x4a00000>;
191 current-speed = <0x1c200>;
192 interrupts = <0x29 0x8>;
193 interrupt-parent = <&CPMPIC>;
194 };
195
196 mdio@90d00 { /* For FCCs */
197 #address-cells = <1>;
198 #size-cells = <0>;
199 compatible = "fsl,cpm2-mdio-bitbang";
200 reg = <0x90d00 0x14>;
201 fsl,mdio-pin = <24>;
202 fsl,mdc-pin = <25>;
203
204 PHY0: ethernet-phy@0 {
205 interrupt-parent = <&MPIC>;
206 reg = <0x0>;
207 device_type = "ethernet-phy";
208 };
209 };
210
211 enet2: ethernet@91300 {
212 device_type = "network";
213 compatible = "fsl,mpc8560-fcc-enet",
214 "fsl,cpm2-fcc-enet";
215 reg = <0x91300 0x20 0x88400 0x100 0x91390 0x1>;
216 /* Mac address filled in by bootwrapper */
217 local-mac-address = [ 00 00 00 00 00 00 ];
218 fsl,cpm-command = <0x12000300>;
219 interrupts = <0x20 0x8>;
220 interrupt-parent = <&CPMPIC>;
221 phy-handle = <&PHY0>;
222 };
223 };
224 };
225
226 localbus@fdf05000 {
227 #address-cells = <2>;
228 #size-cells = <1>;
229 compatible = "fsl,mpc8560-localbus";
230 reg = <0xfdf05000 0x68>;
231
232 ranges = <0x0 0x0 0xe0000000 0x00800000
233 0x4 0x0 0xe8080000 0x00080000>;
234
235 flash@0,0 {
236 #address-cells = <1>;
237 #size-cells = <1>;
238 compatible = "jedec-flash";
239 reg = <0x0 0x0 0x800000>;
240 bank-width = <0x2>;
241
242 partition@0 {
243 label = "Primary Kernel";
244 reg = <0x0 0x180000>;
245 };
246 partition@180000 {
247 label = "Primary Filesystem";
248 reg = <0x180000 0x580000>;
249 };
250 partition@700000 {
251 label = "Monitor";
252 reg = <0x300000 0x100000>;
253 read-only;
254 };
255 };
256
257 cpld@4,0 {
258 compatible = "emerson,KSI8560-cpld";
259 reg = <0x4 0x0 0x80000>;
260 };
261 };
262
263
264 chosen {
265 linux,stdout-path = "/soc/cpm/serial@91a00";
266 };
267};
diff --git a/arch/powerpc/boot/dts/kuroboxHD.dts b/arch/powerpc/boot/dts/kuroboxHD.dts
index 446958854519..2e5a1a1812b6 100644
--- a/arch/powerpc/boot/dts/kuroboxHD.dts
+++ b/arch/powerpc/boot/dts/kuroboxHD.dts
@@ -7,6 +7,7 @@
7 * Based on sandpoint.dts 7 * Based on sandpoint.dts
8 * 8 *
9 * 2006 (c) G. Liakhovetski <g.liakhovetski@gmx.de> 9 * 2006 (c) G. Liakhovetski <g.liakhovetski@gmx.de>
10 * Copyright 2008 Freescale Semiconductor, Inc.
10 * 11 *
11 * This file is licensed under 12 * This file is licensed under
12 * the terms of the GNU General Public License version 2. This program 13 * the terms of the GNU General Public License version 2. This program
@@ -17,6 +18,8 @@ XXXX add flash parts, rtc, ??
17 18
18 */ 19 */
19 20
21/dts-v1/;
22
20/ { 23/ {
21 model = "KuroboxHD"; 24 model = "KuroboxHD";
22 compatible = "linkstation"; 25 compatible = "linkstation";
@@ -35,19 +38,19 @@ XXXX add flash parts, rtc, ??
35 38
36 PowerPC,603e { /* Really 8241 */ 39 PowerPC,603e { /* Really 8241 */
37 device_type = "cpu"; 40 device_type = "cpu";
38 reg = <0>; 41 reg = <0x0>;
39 clock-frequency = <bebc200>; /* Fixed by bootloader */ 42 clock-frequency = <200000000>; /* Fixed by bootloader */
40 timebase-frequency = <1743000>; /* Fixed by bootloader */ 43 timebase-frequency = <24391680>; /* Fixed by bootloader */
41 bus-frequency = <0>; /* Fixed by bootloader */ 44 bus-frequency = <0>; /* Fixed by bootloader */
42 /* Following required by dtc but not used */ 45 /* Following required by dtc but not used */
43 i-cache-size = <4000>; 46 i-cache-size = <0x4000>;
44 d-cache-size = <4000>; 47 d-cache-size = <0x4000>;
45 }; 48 };
46 }; 49 };
47 50
48 memory { 51 memory {
49 device_type = "memory"; 52 device_type = "memory";
50 reg = <00000000 04000000>; 53 reg = <0x0 0x4000000>;
51 }; 54 };
52 55
53 soc10x { /* AFAICT need to make soc for 8245's uarts to be defined */ 56 soc10x { /* AFAICT need to make soc for 8245's uarts to be defined */
@@ -56,26 +59,26 @@ XXXX add flash parts, rtc, ??
56 device_type = "soc"; 59 device_type = "soc";
57 compatible = "mpc10x"; 60 compatible = "mpc10x";
58 store-gathering = <0>; /* 0 == off, !0 == on */ 61 store-gathering = <0>; /* 0 == off, !0 == on */
59 reg = <80000000 00100000>; 62 reg = <0x80000000 0x100000>;
60 ranges = <80000000 80000000 70000000 /* pci mem space */ 63 ranges = <0x80000000 0x80000000 0x70000000 /* pci mem space */
61 fc000000 fc000000 00100000 /* EUMB */ 64 0xfc000000 0xfc000000 0x100000 /* EUMB */
62 fe000000 fe000000 00c00000 /* pci i/o space */ 65 0xfe000000 0xfe000000 0xc00000 /* pci i/o space */
63 fec00000 fec00000 00300000 /* pci cfg regs */ 66 0xfec00000 0xfec00000 0x300000 /* pci cfg regs */
64 fef00000 fef00000 00100000>; /* pci iack */ 67 0xfef00000 0xfef00000 0x100000>; /* pci iack */
65 68
66 i2c@80003000 { 69 i2c@80003000 {
67 #address-cells = <1>; 70 #address-cells = <1>;
68 #size-cells = <0>; 71 #size-cells = <0>;
69 cell-index = <0>; 72 cell-index = <0>;
70 compatible = "fsl-i2c"; 73 compatible = "fsl-i2c";
71 reg = <80003000 1000>; 74 reg = <0x80003000 0x1000>;
72 interrupts = <5 2>; 75 interrupts = <5 2>;
73 interrupt-parent = <&mpic>; 76 interrupt-parent = <&mpic>;
74 77
75 rtc@32 { 78 rtc@32 {
76 device_type = "rtc"; 79 device_type = "rtc";
77 compatible = "ricoh,rs5c372a"; 80 compatible = "ricoh,rs5c372a";
78 reg = <32>; 81 reg = <0x32>;
79 }; 82 };
80 }; 83 };
81 84
@@ -83,9 +86,9 @@ XXXX add flash parts, rtc, ??
83 cell-index = <0>; 86 cell-index = <0>;
84 device_type = "serial"; 87 device_type = "serial";
85 compatible = "ns16550"; 88 compatible = "ns16550";
86 reg = <80004500 8>; 89 reg = <0x80004500 0x8>;
87 clock-frequency = <5d08d88>; 90 clock-frequency = <97553800>;
88 current-speed = <2580>; 91 current-speed = <9600>;
89 interrupts = <9 0>; 92 interrupts = <9 0>;
90 interrupt-parent = <&mpic>; 93 interrupt-parent = <&mpic>;
91 }; 94 };
@@ -94,10 +97,10 @@ XXXX add flash parts, rtc, ??
94 cell-index = <1>; 97 cell-index = <1>;
95 device_type = "serial"; 98 device_type = "serial";
96 compatible = "ns16550"; 99 compatible = "ns16550";
97 reg = <80004600 8>; 100 reg = <0x80004600 0x8>;
98 clock-frequency = <5d08d88>; 101 clock-frequency = <97553800>;
99 current-speed = <e100>; 102 current-speed = <57600>;
100 interrupts = <a 0>; 103 interrupts = <10 0>;
101 interrupt-parent = <&mpic>; 104 interrupt-parent = <&mpic>;
102 }; 105 };
103 106
@@ -107,7 +110,7 @@ XXXX add flash parts, rtc, ??
107 device_type = "open-pic"; 110 device_type = "open-pic";
108 compatible = "chrp,open-pic"; 111 compatible = "chrp,open-pic";
109 interrupt-controller; 112 interrupt-controller;
110 reg = <80040000 40000>; 113 reg = <0x80040000 0x40000>;
111 }; 114 };
112 115
113 pci0: pci@fec00000 { 116 pci0: pci@fec00000 {
@@ -116,29 +119,29 @@ XXXX add flash parts, rtc, ??
116 #interrupt-cells = <1>; 119 #interrupt-cells = <1>;
117 device_type = "pci"; 120 device_type = "pci";
118 compatible = "mpc10x-pci"; 121 compatible = "mpc10x-pci";
119 reg = <fec00000 400000>; 122 reg = <0xfec00000 0x400000>;
120 ranges = <01000000 0 0 fe000000 0 00c00000 123 ranges = <0x1000000 0x0 0x0 0xfe000000 0x0 0xc00000
121 02000000 0 80000000 80000000 0 70000000>; 124 0x2000000 0x0 0x80000000 0x80000000 0x0 0x70000000>;
122 bus-range = <0 ff>; 125 bus-range = <0 255>;
123 clock-frequency = <7f28155>; 126 clock-frequency = <133333333>;
124 interrupt-parent = <&mpic>; 127 interrupt-parent = <&mpic>;
125 interrupt-map-mask = <f800 0 0 7>; 128 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
126 interrupt-map = < 129 interrupt-map = <
127 /* IDSEL 11 - IRQ0 ETH */ 130 /* IDSEL 11 - IRQ0 ETH */
128 5800 0 0 1 &mpic 0 1 131 0x5800 0x0 0x0 0x1 &mpic 0x0 0x1
129 5800 0 0 2 &mpic 1 1 132 0x5800 0x0 0x0 0x2 &mpic 0x1 0x1
130 5800 0 0 3 &mpic 2 1 133 0x5800 0x0 0x0 0x3 &mpic 0x2 0x1
131 5800 0 0 4 &mpic 3 1 134 0x5800 0x0 0x0 0x4 &mpic 0x3 0x1
132 /* IDSEL 12 - IRQ1 IDE0 */ 135 /* IDSEL 12 - IRQ1 IDE0 */
133 6000 0 0 1 &mpic 1 1 136 0x6000 0x0 0x0 0x1 &mpic 0x1 0x1
134 6000 0 0 2 &mpic 2 1 137 0x6000 0x0 0x0 0x2 &mpic 0x2 0x1
135 6000 0 0 3 &mpic 3 1 138 0x6000 0x0 0x0 0x3 &mpic 0x3 0x1
136 6000 0 0 4 &mpic 0 1 139 0x6000 0x0 0x0 0x4 &mpic 0x0 0x1
137 /* IDSEL 14 - IRQ3 USB2.0 */ 140 /* IDSEL 14 - IRQ3 USB2.0 */
138 7000 0 0 1 &mpic 3 1 141 0x7000 0x0 0x0 0x1 &mpic 0x3 0x1
139 7000 0 0 2 &mpic 3 1 142 0x7000 0x0 0x0 0x2 &mpic 0x3 0x1
140 7000 0 0 3 &mpic 3 1 143 0x7000 0x0 0x0 0x3 &mpic 0x3 0x1
141 7000 0 0 4 &mpic 3 1 144 0x7000 0x0 0x0 0x4 &mpic 0x3 0x1
142 >; 145 >;
143 }; 146 };
144 }; 147 };
diff --git a/arch/powerpc/boot/dts/kuroboxHG.dts b/arch/powerpc/boot/dts/kuroboxHG.dts
index 8443c85b7b30..e4916e69ad31 100644
--- a/arch/powerpc/boot/dts/kuroboxHG.dts
+++ b/arch/powerpc/boot/dts/kuroboxHG.dts
@@ -7,6 +7,7 @@
7 * Based on sandpoint.dts 7 * Based on sandpoint.dts
8 * 8 *
9 * 2006 (c) G. Liakhovetski <g.liakhovetski@gmx.de> 9 * 2006 (c) G. Liakhovetski <g.liakhovetski@gmx.de>
10 * Copyright 2008 Freescale Semiconductor, Inc.
10 * 11 *
11 * This file is licensed under 12 * This file is licensed under
12 * the terms of the GNU General Public License version 2. This program 13 * the terms of the GNU General Public License version 2. This program
@@ -17,6 +18,8 @@ XXXX add flash parts, rtc, ??
17 18
18 */ 19 */
19 20
21/dts-v1/;
22
20/ { 23/ {
21 model = "KuroboxHG"; 24 model = "KuroboxHG";
22 compatible = "linkstation"; 25 compatible = "linkstation";
@@ -35,19 +38,19 @@ XXXX add flash parts, rtc, ??
35 38
36 PowerPC,603e { /* Really 8241 */ 39 PowerPC,603e { /* Really 8241 */
37 device_type = "cpu"; 40 device_type = "cpu";
38 reg = <0>; 41 reg = <0x0>;
39 clock-frequency = <fdad680>; /* Fixed by bootloader */ 42 clock-frequency = <266000000>; /* Fixed by bootloader */
40 timebase-frequency = <1F04000>; /* Fixed by bootloader */ 43 timebase-frequency = <32522240>; /* Fixed by bootloader */
41 bus-frequency = <0>; /* Fixed by bootloader */ 44 bus-frequency = <0>; /* Fixed by bootloader */
42 /* Following required by dtc but not used */ 45 /* Following required by dtc but not used */
43 i-cache-size = <4000>; 46 i-cache-size = <0x4000>;
44 d-cache-size = <4000>; 47 d-cache-size = <0x4000>;
45 }; 48 };
46 }; 49 };
47 50
48 memory { 51 memory {
49 device_type = "memory"; 52 device_type = "memory";
50 reg = <00000000 08000000>; 53 reg = <0x0 0x8000000>;
51 }; 54 };
52 55
53 soc10x { /* AFAICT need to make soc for 8245's uarts to be defined */ 56 soc10x { /* AFAICT need to make soc for 8245's uarts to be defined */
@@ -56,26 +59,26 @@ XXXX add flash parts, rtc, ??
56 device_type = "soc"; 59 device_type = "soc";
57 compatible = "mpc10x"; 60 compatible = "mpc10x";
58 store-gathering = <0>; /* 0 == off, !0 == on */ 61 store-gathering = <0>; /* 0 == off, !0 == on */
59 reg = <80000000 00100000>; 62 reg = <0x80000000 0x100000>;
60 ranges = <80000000 80000000 70000000 /* pci mem space */ 63 ranges = <0x80000000 0x80000000 0x70000000 /* pci mem space */
61 fc000000 fc000000 00100000 /* EUMB */ 64 0xfc000000 0xfc000000 0x100000 /* EUMB */
62 fe000000 fe000000 00c00000 /* pci i/o space */ 65 0xfe000000 0xfe000000 0xc00000 /* pci i/o space */
63 fec00000 fec00000 00300000 /* pci cfg regs */ 66 0xfec00000 0xfec00000 0x300000 /* pci cfg regs */
64 fef00000 fef00000 00100000>; /* pci iack */ 67 0xfef00000 0xfef00000 0x100000>; /* pci iack */
65 68
66 i2c@80003000 { 69 i2c@80003000 {
67 #address-cells = <1>; 70 #address-cells = <1>;
68 #size-cells = <0>; 71 #size-cells = <0>;
69 cell-index = <0>; 72 cell-index = <0>;
70 compatible = "fsl-i2c"; 73 compatible = "fsl-i2c";
71 reg = <80003000 1000>; 74 reg = <0x80003000 0x1000>;
72 interrupts = <5 2>; 75 interrupts = <5 2>;
73 interrupt-parent = <&mpic>; 76 interrupt-parent = <&mpic>;
74 77
75 rtc@32 { 78 rtc@32 {
76 device_type = "rtc"; 79 device_type = "rtc";
77 compatible = "ricoh,rs5c372a"; 80 compatible = "ricoh,rs5c372a";
78 reg = <32>; 81 reg = <0x32>;
79 }; 82 };
80 }; 83 };
81 84
@@ -83,9 +86,9 @@ XXXX add flash parts, rtc, ??
83 cell-index = <0>; 86 cell-index = <0>;
84 device_type = "serial"; 87 device_type = "serial";
85 compatible = "ns16550"; 88 compatible = "ns16550";
86 reg = <80004500 8>; 89 reg = <0x80004500 0x8>;
87 clock-frequency = <7c044a8>; 90 clock-frequency = <130041000>;
88 current-speed = <2580>; 91 current-speed = <9600>;
89 interrupts = <9 0>; 92 interrupts = <9 0>;
90 interrupt-parent = <&mpic>; 93 interrupt-parent = <&mpic>;
91 }; 94 };
@@ -94,10 +97,10 @@ XXXX add flash parts, rtc, ??
94 cell-index = <1>; 97 cell-index = <1>;
95 device_type = "serial"; 98 device_type = "serial";
96 compatible = "ns16550"; 99 compatible = "ns16550";
97 reg = <80004600 8>; 100 reg = <0x80004600 0x8>;
98 clock-frequency = <7c044a8>; 101 clock-frequency = <130041000>;
99 current-speed = <e100>; 102 current-speed = <57600>;
100 interrupts = <a 0>; 103 interrupts = <10 0>;
101 interrupt-parent = <&mpic>; 104 interrupt-parent = <&mpic>;
102 }; 105 };
103 106
@@ -107,7 +110,7 @@ XXXX add flash parts, rtc, ??
107 device_type = "open-pic"; 110 device_type = "open-pic";
108 compatible = "chrp,open-pic"; 111 compatible = "chrp,open-pic";
109 interrupt-controller; 112 interrupt-controller;
110 reg = <80040000 40000>; 113 reg = <0x80040000 0x40000>;
111 }; 114 };
112 115
113 pci0: pci@fec00000 { 116 pci0: pci@fec00000 {
@@ -116,29 +119,29 @@ XXXX add flash parts, rtc, ??
116 #interrupt-cells = <1>; 119 #interrupt-cells = <1>;
117 device_type = "pci"; 120 device_type = "pci";
118 compatible = "mpc10x-pci"; 121 compatible = "mpc10x-pci";
119 reg = <fec00000 400000>; 122 reg = <0xfec00000 0x400000>;
120 ranges = <01000000 0 0 fe000000 0 00c00000 123 ranges = <0x1000000 0x0 0x0 0xfe000000 0x0 0xc00000
121 02000000 0 80000000 80000000 0 70000000>; 124 0x2000000 0x0 0x80000000 0x80000000 0x0 0x70000000>;
122 bus-range = <0 ff>; 125 bus-range = <0 255>;
123 clock-frequency = <7f28155>; 126 clock-frequency = <133333333>;
124 interrupt-parent = <&mpic>; 127 interrupt-parent = <&mpic>;
125 interrupt-map-mask = <f800 0 0 7>; 128 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
126 interrupt-map = < 129 interrupt-map = <
127 /* IDSEL 11 - IRQ0 ETH */ 130 /* IDSEL 11 - IRQ0 ETH */
128 5800 0 0 1 &mpic 0 1 131 0x5800 0x0 0x0 0x1 &mpic 0x0 0x1
129 5800 0 0 2 &mpic 1 1 132 0x5800 0x0 0x0 0x2 &mpic 0x1 0x1
130 5800 0 0 3 &mpic 2 1 133 0x5800 0x0 0x0 0x3 &mpic 0x2 0x1
131 5800 0 0 4 &mpic 3 1 134 0x5800 0x0 0x0 0x4 &mpic 0x3 0x1
132 /* IDSEL 12 - IRQ1 IDE0 */ 135 /* IDSEL 12 - IRQ1 IDE0 */
133 6000 0 0 1 &mpic 1 1 136 0x6000 0x0 0x0 0x1 &mpic 0x1 0x1
134 6000 0 0 2 &mpic 2 1 137 0x6000 0x0 0x0 0x2 &mpic 0x2 0x1
135 6000 0 0 3 &mpic 3 1 138 0x6000 0x0 0x0 0x3 &mpic 0x3 0x1
136 6000 0 0 4 &mpic 0 1 139 0x6000 0x0 0x0 0x4 &mpic 0x0 0x1
137 /* IDSEL 14 - IRQ3 USB2.0 */ 140 /* IDSEL 14 - IRQ3 USB2.0 */
138 7000 0 0 1 &mpic 3 1 141 0x7000 0x0 0x0 0x1 &mpic 0x3 0x1
139 7000 0 0 2 &mpic 3 1 142 0x7000 0x0 0x0 0x2 &mpic 0x3 0x1
140 7000 0 0 3 &mpic 3 1 143 0x7000 0x0 0x0 0x3 &mpic 0x3 0x1
141 7000 0 0 4 &mpic 3 1 144 0x7000 0x0 0x0 0x4 &mpic 0x3 0x1
142 >; 145 >;
143 }; 146 };
144 }; 147 };
diff --git a/arch/powerpc/boot/dts/makalu.dts b/arch/powerpc/boot/dts/makalu.dts
index 710c01168179..84cc5e72ddd8 100644
--- a/arch/powerpc/boot/dts/makalu.dts
+++ b/arch/powerpc/boot/dts/makalu.dts
@@ -219,7 +219,7 @@
219 mal-tx-channel = <0>; 219 mal-tx-channel = <0>;
220 mal-rx-channel = <0>; 220 mal-rx-channel = <0>;
221 cell-index = <0>; 221 cell-index = <0>;
222 max-frame-size = <5dc>; 222 max-frame-size = <2328>;
223 rx-fifo-size = <1000>; 223 rx-fifo-size = <1000>;
224 tx-fifo-size = <800>; 224 tx-fifo-size = <800>;
225 phy-mode = "rgmii"; 225 phy-mode = "rgmii";
@@ -247,7 +247,7 @@
247 mal-tx-channel = <1>; 247 mal-tx-channel = <1>;
248 mal-rx-channel = <1>; 248 mal-rx-channel = <1>;
249 cell-index = <1>; 249 cell-index = <1>;
250 max-frame-size = <5dc>; 250 max-frame-size = <2328>;
251 rx-fifo-size = <1000>; 251 rx-fifo-size = <1000>;
252 tx-fifo-size = <800>; 252 tx-fifo-size = <800>;
253 phy-mode = "rgmii"; 253 phy-mode = "rgmii";
diff --git a/arch/powerpc/boot/dts/mpc7448hpc2.dts b/arch/powerpc/boot/dts/mpc7448hpc2.dts
index 8fb542387436..4936349b87cd 100644
--- a/arch/powerpc/boot/dts/mpc7448hpc2.dts
+++ b/arch/powerpc/boot/dts/mpc7448hpc2.dts
@@ -1,7 +1,7 @@
1/* 1/*
2 * MPC7448HPC2 (Taiga) board Device Tree Source 2 * MPC7448HPC2 (Taiga) board Device Tree Source
3 * 3 *
4 * Copyright 2006 Freescale Semiconductor Inc. 4 * Copyright 2006, 2008 Freescale Semiconductor Inc.
5 * 2006 Roy Zang <Roy Zang at freescale.com>. 5 * 2006 Roy Zang <Roy Zang at freescale.com>.
6 * 6 *
7 * This program is free software; you can redistribute it and/or modify it 7 * This program is free software; you can redistribute it and/or modify it
@@ -10,6 +10,7 @@
10 * option) any later version. 10 * option) any later version.
11 */ 11 */
12 12
13/dts-v1/;
13 14
14/ { 15/ {
15 model = "mpc7448hpc2"; 16 model = "mpc7448hpc2";
@@ -23,11 +24,11 @@
23 24
24 PowerPC,7448@0 { 25 PowerPC,7448@0 {
25 device_type = "cpu"; 26 device_type = "cpu";
26 reg = <0>; 27 reg = <0x0>;
27 d-cache-line-size = <20>; // 32 bytes 28 d-cache-line-size = <32>; // 32 bytes
28 i-cache-line-size = <20>; // 32 bytes 29 i-cache-line-size = <32>; // 32 bytes
29 d-cache-size = <8000>; // L1, 32K bytes 30 d-cache-size = <0x8000>; // L1, 32K bytes
30 i-cache-size = <8000>; // L1, 32K bytes 31 i-cache-size = <0x8000>; // L1, 32K bytes
31 timebase-frequency = <0>; // 33 MHz, from uboot 32 timebase-frequency = <0>; // 33 MHz, from uboot
32 clock-frequency = <0>; // From U-Boot 33 clock-frequency = <0>; // From U-Boot
33 bus-frequency = <0>; // From U-Boot 34 bus-frequency = <0>; // From U-Boot
@@ -36,7 +37,7 @@
36 37
37 memory { 38 memory {
38 device_type = "memory"; 39 device_type = "memory";
39 reg = <00000000 20000000 // DDR2 512M at 0 40 reg = <0x0 0x20000000 // DDR2 512M at 0
40 >; 41 >;
41 }; 42 };
42 43
@@ -44,14 +45,14 @@
44 #address-cells = <1>; 45 #address-cells = <1>;
45 #size-cells = <1>; 46 #size-cells = <1>;
46 device_type = "tsi-bridge"; 47 device_type = "tsi-bridge";
47 ranges = <00000000 c0000000 00010000>; 48 ranges = <0x0 0xc0000000 0x10000>;
48 reg = <c0000000 00010000>; 49 reg = <0xc0000000 0x10000>;
49 bus-frequency = <0>; 50 bus-frequency = <0>;
50 51
51 i2c@7000 { 52 i2c@7000 {
52 interrupt-parent = <&mpic>; 53 interrupt-parent = <&mpic>;
53 interrupts = <E 0>; 54 interrupts = <14 0>;
54 reg = <7000 400>; 55 reg = <0x7000 0x400>;
55 device_type = "i2c"; 56 device_type = "i2c";
56 compatible = "tsi108-i2c"; 57 compatible = "tsi108-i2c";
57 }; 58 };
@@ -59,20 +60,20 @@
59 MDIO: mdio@6000 { 60 MDIO: mdio@6000 {
60 device_type = "mdio"; 61 device_type = "mdio";
61 compatible = "tsi108-mdio"; 62 compatible = "tsi108-mdio";
62 reg = <6000 50>; 63 reg = <0x6000 0x50>;
63 #address-cells = <1>; 64 #address-cells = <1>;
64 #size-cells = <0>; 65 #size-cells = <0>;
65 66
66 phy8: ethernet-phy@8 { 67 phy8: ethernet-phy@8 {
67 interrupt-parent = <&mpic>; 68 interrupt-parent = <&mpic>;
68 interrupts = <2 1>; 69 interrupts = <2 1>;
69 reg = <8>; 70 reg = <0x8>;
70 }; 71 };
71 72
72 phy9: ethernet-phy@9 { 73 phy9: ethernet-phy@9 {
73 interrupt-parent = <&mpic>; 74 interrupt-parent = <&mpic>;
74 interrupts = <2 1>; 75 interrupts = <2 1>;
75 reg = <9>; 76 reg = <0x9>;
76 }; 77 };
77 78
78 }; 79 };
@@ -82,9 +83,9 @@
82 #size-cells = <0>; 83 #size-cells = <0>;
83 device_type = "network"; 84 device_type = "network";
84 compatible = "tsi108-ethernet"; 85 compatible = "tsi108-ethernet";
85 reg = <6000 200>; 86 reg = <0x6000 0x200>;
86 address = [ 00 06 D2 00 00 01 ]; 87 address = [ 00 06 D2 00 00 01 ];
87 interrupts = <10 2>; 88 interrupts = <16 2>;
88 interrupt-parent = <&mpic>; 89 interrupt-parent = <&mpic>;
89 mdio-handle = <&MDIO>; 90 mdio-handle = <&MDIO>;
90 phy-handle = <&phy8>; 91 phy-handle = <&phy8>;
@@ -96,9 +97,9 @@
96 #size-cells = <0>; 97 #size-cells = <0>;
97 device_type = "network"; 98 device_type = "network";
98 compatible = "tsi108-ethernet"; 99 compatible = "tsi108-ethernet";
99 reg = <6400 200>; 100 reg = <0x6400 0x200>;
100 address = [ 00 06 D2 00 00 02 ]; 101 address = [ 00 06 D2 00 00 02 ];
101 interrupts = <11 2>; 102 interrupts = <17 2>;
102 interrupt-parent = <&mpic>; 103 interrupt-parent = <&mpic>;
103 mdio-handle = <&MDIO>; 104 mdio-handle = <&MDIO>;
104 phy-handle = <&phy9>; 105 phy-handle = <&phy9>;
@@ -107,18 +108,18 @@
107 serial@7808 { 108 serial@7808 {
108 device_type = "serial"; 109 device_type = "serial";
109 compatible = "ns16550"; 110 compatible = "ns16550";
110 reg = <7808 200>; 111 reg = <0x7808 0x200>;
111 clock-frequency = <3f6b5a00>; 112 clock-frequency = <1064000000>;
112 interrupts = <c 0>; 113 interrupts = <12 0>;
113 interrupt-parent = <&mpic>; 114 interrupt-parent = <&mpic>;
114 }; 115 };
115 116
116 serial@7c08 { 117 serial@7c08 {
117 device_type = "serial"; 118 device_type = "serial";
118 compatible = "ns16550"; 119 compatible = "ns16550";
119 reg = <7c08 200>; 120 reg = <0x7c08 0x200>;
120 clock-frequency = <3f6b5a00>; 121 clock-frequency = <1064000000>;
121 interrupts = <d 0>; 122 interrupts = <13 0>;
122 interrupt-parent = <&mpic>; 123 interrupt-parent = <&mpic>;
123 }; 124 };
124 125
@@ -127,7 +128,7 @@
127 interrupt-controller; 128 interrupt-controller;
128 #address-cells = <0>; 129 #address-cells = <0>;
129 #interrupt-cells = <2>; 130 #interrupt-cells = <2>;
130 reg = <7400 400>; 131 reg = <0x7400 0x400>;
131 compatible = "chrp,open-pic"; 132 compatible = "chrp,open-pic";
132 device_type = "open-pic"; 133 device_type = "open-pic";
133 big-endian; 134 big-endian;
@@ -138,39 +139,39 @@
138 #interrupt-cells = <1>; 139 #interrupt-cells = <1>;
139 #size-cells = <2>; 140 #size-cells = <2>;
140 #address-cells = <3>; 141 #address-cells = <3>;
141 reg = <1000 1000>; 142 reg = <0x1000 0x1000>;
142 bus-range = <0 0>; 143 bus-range = <0 0>;
143 ranges = <02000000 0 e0000000 e0000000 0 1A000000 144 ranges = <0x2000000 0x0 0xe0000000 0xe0000000 0x0 0x1a000000
144 01000000 0 00000000 fa000000 0 00010000>; 145 0x1000000 0x0 0x0 0xfa000000 0x0 0x10000>;
145 clock-frequency = <7f28154>; 146 clock-frequency = <133333332>;
146 interrupt-parent = <&mpic>; 147 interrupt-parent = <&mpic>;
147 interrupts = <17 2>; 148 interrupts = <23 2>;
148 interrupt-map-mask = <f800 0 0 7>; 149 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
149 interrupt-map = < 150 interrupt-map = <
150 151
151 /* IDSEL 0x11 */ 152 /* IDSEL 0x11 */
152 0800 0 0 1 &RT0 24 0 153 0x800 0x0 0x0 0x1 &RT0 0x24 0x0
153 0800 0 0 2 &RT0 25 0 154 0x800 0x0 0x0 0x2 &RT0 0x25 0x0
154 0800 0 0 3 &RT0 26 0 155 0x800 0x0 0x0 0x3 &RT0 0x26 0x0
155 0800 0 0 4 &RT0 27 0 156 0x800 0x0 0x0 0x4 &RT0 0x27 0x0
156 157
157 /* IDSEL 0x12 */ 158 /* IDSEL 0x12 */
158 1000 0 0 1 &RT0 25 0 159 0x1000 0x0 0x0 0x1 &RT0 0x25 0x0
159 1000 0 0 2 &RT0 26 0 160 0x1000 0x0 0x0 0x2 &RT0 0x26 0x0
160 1000 0 0 3 &RT0 27 0 161 0x1000 0x0 0x0 0x3 &RT0 0x27 0x0
161 1000 0 0 4 &RT0 24 0 162 0x1000 0x0 0x0 0x4 &RT0 0x24 0x0
162 163
163 /* IDSEL 0x13 */ 164 /* IDSEL 0x13 */
164 1800 0 0 1 &RT0 26 0 165 0x1800 0x0 0x0 0x1 &RT0 0x26 0x0
165 1800 0 0 2 &RT0 27 0 166 0x1800 0x0 0x0 0x2 &RT0 0x27 0x0
166 1800 0 0 3 &RT0 24 0 167 0x1800 0x0 0x0 0x3 &RT0 0x24 0x0
167 1800 0 0 4 &RT0 25 0 168 0x1800 0x0 0x0 0x4 &RT0 0x25 0x0
168 169
169 /* IDSEL 0x14 */ 170 /* IDSEL 0x14 */
170 2000 0 0 1 &RT0 27 0 171 0x2000 0x0 0x0 0x1 &RT0 0x27 0x0
171 2000 0 0 2 &RT0 24 0 172 0x2000 0x0 0x0 0x2 &RT0 0x24 0x0
172 2000 0 0 3 &RT0 25 0 173 0x2000 0x0 0x0 0x3 &RT0 0x25 0x0
173 2000 0 0 4 &RT0 26 0 174 0x2000 0x0 0x0 0x4 &RT0 0x26 0x0
174 >; 175 >;
175 176
176 RT0: router@1180 { 177 RT0: router@1180 {
@@ -180,7 +181,7 @@
180 #address-cells = <0>; 181 #address-cells = <0>;
181 #interrupt-cells = <2>; 182 #interrupt-cells = <2>;
182 big-endian; 183 big-endian;
183 interrupts = <17 2>; 184 interrupts = <23 2>;
184 interrupt-parent = <&mpic>; 185 interrupt-parent = <&mpic>;
185 }; 186 };
186 }; 187 };
diff --git a/arch/powerpc/boot/dts/mpc8272ads.dts b/arch/powerpc/boot/dts/mpc8272ads.dts
index 7285ca1325fd..46e2da30c3dd 100644
--- a/arch/powerpc/boot/dts/mpc8272ads.dts
+++ b/arch/powerpc/boot/dts/mpc8272ads.dts
@@ -1,7 +1,7 @@
1/* 1/*
2 * MPC8272 ADS Device Tree Source 2 * MPC8272 ADS Device Tree Source
3 * 3 *
4 * Copyright 2005 Freescale Semiconductor Inc. 4 * Copyright 2005,2008 Freescale Semiconductor Inc.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the 7 * under the terms of the GNU General Public License as published by the
@@ -9,6 +9,8 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/dts-v1/;
13
12/ { 14/ {
13 model = "MPC8272ADS"; 15 model = "MPC8272ADS";
14 compatible = "fsl,mpc8272ads"; 16 compatible = "fsl,mpc8272ads";
@@ -21,11 +23,11 @@
21 23
22 PowerPC,8272@0 { 24 PowerPC,8272@0 {
23 device_type = "cpu"; 25 device_type = "cpu";
24 reg = <0>; 26 reg = <0x0>;
25 d-cache-line-size = <d#32>; 27 d-cache-line-size = <32>;
26 i-cache-line-size = <d#32>; 28 i-cache-line-size = <32>;
27 d-cache-size = <d#16384>; 29 d-cache-size = <16384>;
28 i-cache-size = <d#16384>; 30 i-cache-size = <16384>;
29 timebase-frequency = <0>; 31 timebase-frequency = <0>;
30 bus-frequency = <0>; 32 bus-frequency = <0>;
31 clock-frequency = <0>; 33 clock-frequency = <0>;
@@ -34,7 +36,7 @@
34 36
35 memory { 37 memory {
36 device_type = "memory"; 38 device_type = "memory";
37 reg = <0 0>; 39 reg = <0x0 0x0>;
38 }; 40 };
39 41
40 localbus@f0010100 { 42 localbus@f0010100 {
@@ -42,21 +44,21 @@
42 "fsl,pq2-localbus"; 44 "fsl,pq2-localbus";
43 #address-cells = <2>; 45 #address-cells = <2>;
44 #size-cells = <1>; 46 #size-cells = <1>;
45 reg = <f0010100 40>; 47 reg = <0xf0010100 0x40>;
46 48
47 ranges = <0 0 fe000000 02000000 49 ranges = <0x0 0x0 0xfe000000 0x2000000
48 1 0 f4500000 00008000 50 0x1 0x0 0xf4500000 0x8000
49 3 0 f8200000 00008000>; 51 0x3 0x0 0xf8200000 0x8000>;
50 52
51 flash@0,0 { 53 flash@0,0 {
52 compatible = "jedec-flash"; 54 compatible = "jedec-flash";
53 reg = <0 0 2000000>; 55 reg = <0x0 0x0 0x2000000>;
54 bank-width = <4>; 56 bank-width = <4>;
55 device-width = <1>; 57 device-width = <1>;
56 }; 58 };
57 59
58 board-control@1,0 { 60 board-control@1,0 {
59 reg = <1 0 20>; 61 reg = <0x1 0x0 0x20>;
60 compatible = "fsl,mpc8272ads-bcsr"; 62 compatible = "fsl,mpc8272ads-bcsr";
61 }; 63 };
62 64
@@ -65,46 +67,46 @@
65 "fsl,pq2ads-pci-pic"; 67 "fsl,pq2ads-pci-pic";
66 #interrupt-cells = <1>; 68 #interrupt-cells = <1>;
67 interrupt-controller; 69 interrupt-controller;
68 reg = <3 0 8>; 70 reg = <0x3 0x0 0x8>;
69 interrupt-parent = <&PIC>; 71 interrupt-parent = <&PIC>;
70 interrupts = <14 8>; 72 interrupts = <20 8>;
71 }; 73 };
72 }; 74 };
73 75
74 76
75 pci@f0010800 { 77 pci@f0010800 {
76 device_type = "pci"; 78 device_type = "pci";
77 reg = <f0010800 10c f00101ac 8 f00101c4 8>; 79 reg = <0xf0010800 0x10c 0xf00101ac 0x8 0xf00101c4 0x8>;
78 compatible = "fsl,mpc8272-pci", "fsl,pq2-pci"; 80 compatible = "fsl,mpc8272-pci", "fsl,pq2-pci";
79 #interrupt-cells = <1>; 81 #interrupt-cells = <1>;
80 #size-cells = <2>; 82 #size-cells = <2>;
81 #address-cells = <3>; 83 #address-cells = <3>;
82 clock-frequency = <d#66666666>; 84 clock-frequency = <66666666>;
83 interrupt-map-mask = <f800 0 0 7>; 85 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
84 interrupt-map = < 86 interrupt-map = <
85 /* IDSEL 0x16 */ 87 /* IDSEL 0x16 */
86 b000 0 0 1 &PCI_PIC 0 88 0xb000 0x0 0x0 0x1 &PCI_PIC 0
87 b000 0 0 2 &PCI_PIC 1 89 0xb000 0x0 0x0 0x2 &PCI_PIC 1
88 b000 0 0 3 &PCI_PIC 2 90 0xb000 0x0 0x0 0x3 &PCI_PIC 2
89 b000 0 0 4 &PCI_PIC 3 91 0xb000 0x0 0x0 0x4 &PCI_PIC 3
90 92
91 /* IDSEL 0x17 */ 93 /* IDSEL 0x17 */
92 b800 0 0 1 &PCI_PIC 4 94 0xb800 0x0 0x0 0x1 &PCI_PIC 4
93 b800 0 0 2 &PCI_PIC 5 95 0xb800 0x0 0x0 0x2 &PCI_PIC 5
94 b800 0 0 3 &PCI_PIC 6 96 0xb800 0x0 0x0 0x3 &PCI_PIC 6
95 b800 0 0 4 &PCI_PIC 7 97 0xb800 0x0 0x0 0x4 &PCI_PIC 7
96 98
97 /* IDSEL 0x18 */ 99 /* IDSEL 0x18 */
98 c000 0 0 1 &PCI_PIC 8 100 0xc000 0x0 0x0 0x1 &PCI_PIC 8
99 c000 0 0 2 &PCI_PIC 9 101 0xc000 0x0 0x0 0x2 &PCI_PIC 9
100 c000 0 0 3 &PCI_PIC a 102 0xc000 0x0 0x0 0x3 &PCI_PIC 10
101 c000 0 0 4 &PCI_PIC b>; 103 0xc000 0x0 0x0 0x4 &PCI_PIC 11>;
102 104
103 interrupt-parent = <&PIC>; 105 interrupt-parent = <&PIC>;
104 interrupts = <12 8>; 106 interrupts = <18 8>;
105 ranges = <42000000 0 80000000 80000000 0 20000000 107 ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x20000000
106 02000000 0 a0000000 a0000000 0 20000000 108 0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
107 01000000 0 00000000 f6000000 0 02000000>; 109 0x1000000 0x0 0x0 0xf6000000 0x0 0x2000000>;
108 }; 110 };
109 111
110 soc@f0000000 { 112 soc@f0000000 {
@@ -112,26 +114,26 @@
112 #size-cells = <1>; 114 #size-cells = <1>;
113 device_type = "soc"; 115 device_type = "soc";
114 compatible = "fsl,mpc8272", "fsl,pq2-soc"; 116 compatible = "fsl,mpc8272", "fsl,pq2-soc";
115 ranges = <00000000 f0000000 00053000>; 117 ranges = <0x0 0xf0000000 0x53000>;
116 118
117 // Temporary -- will go away once kernel uses ranges for get_immrbase(). 119 // Temporary -- will go away once kernel uses ranges for get_immrbase().
118 reg = <f0000000 00053000>; 120 reg = <0xf0000000 0x53000>;
119 121
120 cpm@119c0 { 122 cpm@119c0 {
121 #address-cells = <1>; 123 #address-cells = <1>;
122 #size-cells = <1>; 124 #size-cells = <1>;
123 compatible = "fsl,mpc8272-cpm", "fsl,cpm2"; 125 compatible = "fsl,mpc8272-cpm", "fsl,cpm2";
124 reg = <119c0 30>; 126 reg = <0x119c0 0x30>;
125 ranges; 127 ranges;
126 128
127 muram@0 { 129 muram@0 {
128 #address-cells = <1>; 130 #address-cells = <1>;
129 #size-cells = <1>; 131 #size-cells = <1>;
130 ranges = <0 0 10000>; 132 ranges = <0x0 0x0 0x10000>;
131 133
132 data@0 { 134 data@0 {
133 compatible = "fsl,cpm-muram-data"; 135 compatible = "fsl,cpm-muram-data";
134 reg = <0 2000 9800 800>; 136 reg = <0x0 0x2000 0x9800 0x800>;
135 }; 137 };
136 }; 138 };
137 139
@@ -139,29 +141,29 @@
139 compatible = "fsl,mpc8272-brg", 141 compatible = "fsl,mpc8272-brg",
140 "fsl,cpm2-brg", 142 "fsl,cpm2-brg",
141 "fsl,cpm-brg"; 143 "fsl,cpm-brg";
142 reg = <119f0 10 115f0 10>; 144 reg = <0x119f0 0x10 0x115f0 0x10>;
143 }; 145 };
144 146
145 serial@11a00 { 147 serial@11a00 {
146 device_type = "serial"; 148 device_type = "serial";
147 compatible = "fsl,mpc8272-scc-uart", 149 compatible = "fsl,mpc8272-scc-uart",
148 "fsl,cpm2-scc-uart"; 150 "fsl,cpm2-scc-uart";
149 reg = <11a00 20 8000 100>; 151 reg = <0x11a00 0x20 0x8000 0x100>;
150 interrupts = <28 8>; 152 interrupts = <40 8>;
151 interrupt-parent = <&PIC>; 153 interrupt-parent = <&PIC>;
152 fsl,cpm-brg = <1>; 154 fsl,cpm-brg = <1>;
153 fsl,cpm-command = <00800000>; 155 fsl,cpm-command = <0x800000>;
154 }; 156 };
155 157
156 serial@11a60 { 158 serial@11a60 {
157 device_type = "serial"; 159 device_type = "serial";
158 compatible = "fsl,mpc8272-scc-uart", 160 compatible = "fsl,mpc8272-scc-uart",
159 "fsl,cpm2-scc-uart"; 161 "fsl,cpm2-scc-uart";
160 reg = <11a60 20 8300 100>; 162 reg = <0x11a60 0x20 0x8300 0x100>;
161 interrupts = <2b 8>; 163 interrupts = <43 8>;
162 interrupt-parent = <&PIC>; 164 interrupt-parent = <&PIC>;
163 fsl,cpm-brg = <4>; 165 fsl,cpm-brg = <4>;
164 fsl,cpm-command = <0ce00000>; 166 fsl,cpm-command = <0xce00000>;
165 }; 167 };
166 168
167 mdio@10d40 { 169 mdio@10d40 {
@@ -169,23 +171,23 @@
169 compatible = "fsl,mpc8272ads-mdio-bitbang", 171 compatible = "fsl,mpc8272ads-mdio-bitbang",
170 "fsl,mpc8272-mdio-bitbang", 172 "fsl,mpc8272-mdio-bitbang",
171 "fsl,cpm2-mdio-bitbang"; 173 "fsl,cpm2-mdio-bitbang";
172 reg = <10d40 14>; 174 reg = <0x10d40 0x14>;
173 #address-cells = <1>; 175 #address-cells = <1>;
174 #size-cells = <0>; 176 #size-cells = <0>;
175 fsl,mdio-pin = <12>; 177 fsl,mdio-pin = <18>;
176 fsl,mdc-pin = <13>; 178 fsl,mdc-pin = <19>;
177 179
178 PHY0: ethernet-phy@0 { 180 PHY0: ethernet-phy@0 {
179 interrupt-parent = <&PIC>; 181 interrupt-parent = <&PIC>;
180 interrupts = <17 8>; 182 interrupts = <23 8>;
181 reg = <0>; 183 reg = <0x0>;
182 device_type = "ethernet-phy"; 184 device_type = "ethernet-phy";
183 }; 185 };
184 186
185 PHY1: ethernet-phy@1 { 187 PHY1: ethernet-phy@1 {
186 interrupt-parent = <&PIC>; 188 interrupt-parent = <&PIC>;
187 interrupts = <17 8>; 189 interrupts = <23 8>;
188 reg = <3>; 190 reg = <0x3>;
189 device_type = "ethernet-phy"; 191 device_type = "ethernet-phy";
190 }; 192 };
191 }; 193 };
@@ -194,33 +196,33 @@
194 device_type = "network"; 196 device_type = "network";
195 compatible = "fsl,mpc8272-fcc-enet", 197 compatible = "fsl,mpc8272-fcc-enet",
196 "fsl,cpm2-fcc-enet"; 198 "fsl,cpm2-fcc-enet";
197 reg = <11300 20 8400 100 11390 1>; 199 reg = <0x11300 0x20 0x8400 0x100 0x11390 0x1>;
198 local-mac-address = [ 00 00 00 00 00 00 ]; 200 local-mac-address = [ 00 00 00 00 00 00 ];
199 interrupts = <20 8>; 201 interrupts = <32 8>;
200 interrupt-parent = <&PIC>; 202 interrupt-parent = <&PIC>;
201 phy-handle = <&PHY0>; 203 phy-handle = <&PHY0>;
202 linux,network-index = <0>; 204 linux,network-index = <0>;
203 fsl,cpm-command = <12000300>; 205 fsl,cpm-command = <0x12000300>;
204 }; 206 };
205 207
206 ethernet@11320 { 208 ethernet@11320 {
207 device_type = "network"; 209 device_type = "network";
208 compatible = "fsl,mpc8272-fcc-enet", 210 compatible = "fsl,mpc8272-fcc-enet",
209 "fsl,cpm2-fcc-enet"; 211 "fsl,cpm2-fcc-enet";
210 reg = <11320 20 8500 100 113b0 1>; 212 reg = <0x11320 0x20 0x8500 0x100 0x113b0 0x1>;
211 local-mac-address = [ 00 00 00 00 00 00 ]; 213 local-mac-address = [ 00 00 00 00 00 00 ];
212 interrupts = <21 8>; 214 interrupts = <33 8>;
213 interrupt-parent = <&PIC>; 215 interrupt-parent = <&PIC>;
214 phy-handle = <&PHY1>; 216 phy-handle = <&PHY1>;
215 linux,network-index = <1>; 217 linux,network-index = <1>;
216 fsl,cpm-command = <16200300>; 218 fsl,cpm-command = <0x16200300>;
217 }; 219 };
218 }; 220 };
219 221
220 PIC: interrupt-controller@10c00 { 222 PIC: interrupt-controller@10c00 {
221 #interrupt-cells = <2>; 223 #interrupt-cells = <2>;
222 interrupt-controller; 224 interrupt-controller;
223 reg = <10c00 80>; 225 reg = <0x10c00 0x80>;
224 compatible = "fsl,mpc8272-pic", "fsl,cpm2-pic"; 226 compatible = "fsl,mpc8272-pic", "fsl,cpm2-pic";
225 }; 227 };
226 228
@@ -232,14 +234,14 @@
232 "fsl,talitos-sec2", 234 "fsl,talitos-sec2",
233 "fsl,talitos", 235 "fsl,talitos",
234 "talitos"; 236 "talitos";
235 reg = <30000 10000>; 237 reg = <0x30000 0x10000>;
236 interrupts = <b 8>; 238 interrupts = <11 8>;
237 interrupt-parent = <&PIC>; 239 interrupt-parent = <&PIC>;
238 num-channels = <4>; 240 num-channels = <4>;
239 channel-fifo-len = <18>; 241 channel-fifo-len = <24>;
240 exec-units-mask = <0000007e>; 242 exec-units-mask = <0x7e>;
241/* desc mask is for rev1.x, we need runtime fixup for >=2.x */ 243/* desc mask is for rev1.x, we need runtime fixup for >=2.x */
242 descriptor-types-mask = <01010ebf>; 244 descriptor-types-mask = <0x1010ebf>;
243 }; 245 };
244 }; 246 };
245 247
diff --git a/arch/powerpc/boot/dts/mpc832x_mds.dts b/arch/powerpc/boot/dts/mpc832x_mds.dts
index 9bb408371bcd..539e02fb3526 100644
--- a/arch/powerpc/boot/dts/mpc832x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc832x_mds.dts
@@ -255,9 +255,7 @@
255 enet0: ucc@2200 { 255 enet0: ucc@2200 {
256 device_type = "network"; 256 device_type = "network";
257 compatible = "ucc_geth"; 257 compatible = "ucc_geth";
258 model = "UCC";
259 cell-index = <3>; 258 cell-index = <3>;
260 device-id = <3>;
261 reg = <0x2200 0x200>; 259 reg = <0x2200 0x200>;
262 interrupts = <34>; 260 interrupts = <34>;
263 interrupt-parent = <&qeic>; 261 interrupt-parent = <&qeic>;
@@ -271,9 +269,7 @@
271 enet1: ucc@3200 { 269 enet1: ucc@3200 {
272 device_type = "network"; 270 device_type = "network";
273 compatible = "ucc_geth"; 271 compatible = "ucc_geth";
274 model = "UCC";
275 cell-index = <4>; 272 cell-index = <4>;
276 device-id = <4>;
277 reg = <0x3200 0x200>; 273 reg = <0x3200 0x200>;
278 interrupts = <35>; 274 interrupts = <35>;
279 interrupt-parent = <&qeic>; 275 interrupt-parent = <&qeic>;
@@ -287,8 +283,7 @@
287 ucc@2400 { 283 ucc@2400 {
288 device_type = "serial"; 284 device_type = "serial";
289 compatible = "ucc_uart"; 285 compatible = "ucc_uart";
290 model = "UCC"; 286 cell-index = <5>; /* The UCC number, 1-7*/
291 device-id = <5>; /* The UCC number, 1-7*/
292 port-number = <0>; /* Which ttyQEx device */ 287 port-number = <0>; /* Which ttyQEx device */
293 soft-uart; /* We need Soft-UART */ 288 soft-uart; /* We need Soft-UART */
294 reg = <0x2400 0x200>; 289 reg = <0x2400 0x200>;
diff --git a/arch/powerpc/boot/dts/mpc832x_rdb.dts b/arch/powerpc/boot/dts/mpc832x_rdb.dts
index 94f93d209de8..179c81c6a7ac 100644
--- a/arch/powerpc/boot/dts/mpc832x_rdb.dts
+++ b/arch/powerpc/boot/dts/mpc832x_rdb.dts
@@ -208,9 +208,7 @@
208 enet0: ucc@3000 { 208 enet0: ucc@3000 {
209 device_type = "network"; 209 device_type = "network";
210 compatible = "ucc_geth"; 210 compatible = "ucc_geth";
211 model = "UCC";
212 cell-index = <2>; 211 cell-index = <2>;
213 device-id = <2>;
214 reg = <0x3000 0x200>; 212 reg = <0x3000 0x200>;
215 interrupts = <33>; 213 interrupts = <33>;
216 interrupt-parent = <&qeic>; 214 interrupt-parent = <&qeic>;
@@ -224,9 +222,7 @@
224 enet1: ucc@2200 { 222 enet1: ucc@2200 {
225 device_type = "network"; 223 device_type = "network";
226 compatible = "ucc_geth"; 224 compatible = "ucc_geth";
227 model = "UCC";
228 cell-index = <3>; 225 cell-index = <3>;
229 device-id = <3>;
230 reg = <0x2200 0x200>; 226 reg = <0x2200 0x200>;
231 interrupts = <34>; 227 interrupts = <34>;
232 interrupt-parent = <&qeic>; 228 interrupt-parent = <&qeic>;
diff --git a/arch/powerpc/boot/dts/mpc836x_mds.dts b/arch/powerpc/boot/dts/mpc836x_mds.dts
index 55f03e8dc97f..8160ff24e87e 100644
--- a/arch/powerpc/boot/dts/mpc836x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc836x_mds.dts
@@ -257,9 +257,7 @@
257 enet0: ucc@2000 { 257 enet0: ucc@2000 {
258 device_type = "network"; 258 device_type = "network";
259 compatible = "ucc_geth"; 259 compatible = "ucc_geth";
260 model = "UCC";
261 cell-index = <1>; 260 cell-index = <1>;
262 device-id = <1>;
263 reg = <0x2000 0x200>; 261 reg = <0x2000 0x200>;
264 interrupts = <32>; 262 interrupts = <32>;
265 interrupt-parent = <&qeic>; 263 interrupt-parent = <&qeic>;
@@ -274,9 +272,7 @@
274 enet1: ucc@3000 { 272 enet1: ucc@3000 {
275 device_type = "network"; 273 device_type = "network";
276 compatible = "ucc_geth"; 274 compatible = "ucc_geth";
277 model = "UCC";
278 cell-index = <2>; 275 cell-index = <2>;
279 device-id = <2>;
280 reg = <0x3000 0x200>; 276 reg = <0x3000 0x200>;
281 interrupts = <33>; 277 interrupts = <33>;
282 interrupt-parent = <&qeic>; 278 interrupt-parent = <&qeic>;
diff --git a/arch/powerpc/boot/dts/mpc8540ads.dts b/arch/powerpc/boot/dts/mpc8540ads.dts
index 975248491b7b..18033ed0b535 100644
--- a/arch/powerpc/boot/dts/mpc8540ads.dts
+++ b/arch/powerpc/boot/dts/mpc8540ads.dts
@@ -1,7 +1,7 @@
1/* 1/*
2 * MPC8540 ADS Device Tree Source 2 * MPC8540 ADS Device Tree Source
3 * 3 *
4 * Copyright 2006 Freescale Semiconductor Inc. 4 * Copyright 2006, 2008 Freescale Semiconductor Inc.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the 7 * under the terms of the GNU General Public License as published by the
@@ -9,6 +9,7 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/dts-v1/;
12 13
13/ { 14/ {
14 model = "MPC8540ADS"; 15 model = "MPC8540ADS";
@@ -31,11 +32,11 @@
31 32
32 PowerPC,8540@0 { 33 PowerPC,8540@0 {
33 device_type = "cpu"; 34 device_type = "cpu";
34 reg = <0>; 35 reg = <0x0>;
35 d-cache-line-size = <20>; // 32 bytes 36 d-cache-line-size = <32>; // 32 bytes
36 i-cache-line-size = <20>; // 32 bytes 37 i-cache-line-size = <32>; // 32 bytes
37 d-cache-size = <8000>; // L1, 32K 38 d-cache-size = <0x8000>; // L1, 32K
38 i-cache-size = <8000>; // L1, 32K 39 i-cache-size = <0x8000>; // L1, 32K
39 timebase-frequency = <0>; // 33 MHz, from uboot 40 timebase-frequency = <0>; // 33 MHz, from uboot
40 bus-frequency = <0>; // 166 MHz 41 bus-frequency = <0>; // 166 MHz
41 clock-frequency = <0>; // 825 MHz, from uboot 42 clock-frequency = <0>; // 825 MHz, from uboot
@@ -44,31 +45,31 @@
44 45
45 memory { 46 memory {
46 device_type = "memory"; 47 device_type = "memory";
47 reg = <00000000 08000000>; // 128M at 0x0 48 reg = <0x0 0x8000000>; // 128M at 0x0
48 }; 49 };
49 50
50 soc8540@e0000000 { 51 soc8540@e0000000 {
51 #address-cells = <1>; 52 #address-cells = <1>;
52 #size-cells = <1>; 53 #size-cells = <1>;
53 device_type = "soc"; 54 device_type = "soc";
54 ranges = <0 e0000000 00100000>; 55 ranges = <0x0 0xe0000000 0x100000>;
55 reg = <e0000000 00100000>; // CCSRBAR 1M 56 reg = <0xe0000000 0x100000>; // CCSRBAR 1M
56 bus-frequency = <0>; 57 bus-frequency = <0>;
57 58
58 memory-controller@2000 { 59 memory-controller@2000 {
59 compatible = "fsl,8540-memory-controller"; 60 compatible = "fsl,8540-memory-controller";
60 reg = <2000 1000>; 61 reg = <0x2000 0x1000>;
61 interrupt-parent = <&mpic>; 62 interrupt-parent = <&mpic>;
62 interrupts = <12 2>; 63 interrupts = <18 2>;
63 }; 64 };
64 65
65 l2-cache-controller@20000 { 66 l2-cache-controller@20000 {
66 compatible = "fsl,8540-l2-cache-controller"; 67 compatible = "fsl,8540-l2-cache-controller";
67 reg = <20000 1000>; 68 reg = <0x20000 0x1000>;
68 cache-line-size = <20>; // 32 bytes 69 cache-line-size = <32>; // 32 bytes
69 cache-size = <40000>; // L2, 256K 70 cache-size = <0x40000>; // L2, 256K
70 interrupt-parent = <&mpic>; 71 interrupt-parent = <&mpic>;
71 interrupts = <10 2>; 72 interrupts = <16 2>;
72 }; 73 };
73 74
74 i2c@3000 { 75 i2c@3000 {
@@ -76,8 +77,8 @@
76 #size-cells = <0>; 77 #size-cells = <0>;
77 cell-index = <0>; 78 cell-index = <0>;
78 compatible = "fsl-i2c"; 79 compatible = "fsl-i2c";
79 reg = <3000 100>; 80 reg = <0x3000 0x100>;
80 interrupts = <2b 2>; 81 interrupts = <43 2>;
81 interrupt-parent = <&mpic>; 82 interrupt-parent = <&mpic>;
82 dfsrr; 83 dfsrr;
83 }; 84 };
@@ -86,24 +87,24 @@
86 #address-cells = <1>; 87 #address-cells = <1>;
87 #size-cells = <0>; 88 #size-cells = <0>;
88 compatible = "fsl,gianfar-mdio"; 89 compatible = "fsl,gianfar-mdio";
89 reg = <24520 20>; 90 reg = <0x24520 0x20>;
90 91
91 phy0: ethernet-phy@0 { 92 phy0: ethernet-phy@0 {
92 interrupt-parent = <&mpic>; 93 interrupt-parent = <&mpic>;
93 interrupts = <5 1>; 94 interrupts = <5 1>;
94 reg = <0>; 95 reg = <0x0>;
95 device_type = "ethernet-phy"; 96 device_type = "ethernet-phy";
96 }; 97 };
97 phy1: ethernet-phy@1 { 98 phy1: ethernet-phy@1 {
98 interrupt-parent = <&mpic>; 99 interrupt-parent = <&mpic>;
99 interrupts = <5 1>; 100 interrupts = <5 1>;
100 reg = <1>; 101 reg = <0x1>;
101 device_type = "ethernet-phy"; 102 device_type = "ethernet-phy";
102 }; 103 };
103 phy3: ethernet-phy@3 { 104 phy3: ethernet-phy@3 {
104 interrupt-parent = <&mpic>; 105 interrupt-parent = <&mpic>;
105 interrupts = <7 1>; 106 interrupts = <7 1>;
106 reg = <3>; 107 reg = <0x3>;
107 device_type = "ethernet-phy"; 108 device_type = "ethernet-phy";
108 }; 109 };
109 }; 110 };
@@ -113,9 +114,9 @@
113 device_type = "network"; 114 device_type = "network";
114 model = "TSEC"; 115 model = "TSEC";
115 compatible = "gianfar"; 116 compatible = "gianfar";
116 reg = <24000 1000>; 117 reg = <0x24000 0x1000>;
117 local-mac-address = [ 00 00 00 00 00 00 ]; 118 local-mac-address = [ 00 00 00 00 00 00 ];
118 interrupts = <1d 2 1e 2 22 2>; 119 interrupts = <29 2 30 2 34 2>;
119 interrupt-parent = <&mpic>; 120 interrupt-parent = <&mpic>;
120 phy-handle = <&phy0>; 121 phy-handle = <&phy0>;
121 }; 122 };
@@ -125,9 +126,9 @@
125 device_type = "network"; 126 device_type = "network";
126 model = "TSEC"; 127 model = "TSEC";
127 compatible = "gianfar"; 128 compatible = "gianfar";
128 reg = <25000 1000>; 129 reg = <0x25000 0x1000>;
129 local-mac-address = [ 00 00 00 00 00 00 ]; 130 local-mac-address = [ 00 00 00 00 00 00 ];
130 interrupts = <23 2 24 2 28 2>; 131 interrupts = <35 2 36 2 40 2>;
131 interrupt-parent = <&mpic>; 132 interrupt-parent = <&mpic>;
132 phy-handle = <&phy1>; 133 phy-handle = <&phy1>;
133 }; 134 };
@@ -137,9 +138,9 @@
137 device_type = "network"; 138 device_type = "network";
138 model = "FEC"; 139 model = "FEC";
139 compatible = "gianfar"; 140 compatible = "gianfar";
140 reg = <26000 1000>; 141 reg = <0x26000 0x1000>;
141 local-mac-address = [ 00 00 00 00 00 00 ]; 142 local-mac-address = [ 00 00 00 00 00 00 ];
142 interrupts = <29 2>; 143 interrupts = <41 2>;
143 interrupt-parent = <&mpic>; 144 interrupt-parent = <&mpic>;
144 phy-handle = <&phy3>; 145 phy-handle = <&phy3>;
145 }; 146 };
@@ -148,9 +149,9 @@
148 cell-index = <0>; 149 cell-index = <0>;
149 device_type = "serial"; 150 device_type = "serial";
150 compatible = "ns16550"; 151 compatible = "ns16550";
151 reg = <4500 100>; // reg base, size 152 reg = <0x4500 0x100>; // reg base, size
152 clock-frequency = <0>; // should we fill in in uboot? 153 clock-frequency = <0>; // should we fill in in uboot?
153 interrupts = <2a 2>; 154 interrupts = <42 2>;
154 interrupt-parent = <&mpic>; 155 interrupt-parent = <&mpic>;
155 }; 156 };
156 157
@@ -158,9 +159,9 @@
158 cell-index = <1>; 159 cell-index = <1>;
159 device_type = "serial"; 160 device_type = "serial";
160 compatible = "ns16550"; 161 compatible = "ns16550";
161 reg = <4600 100>; // reg base, size 162 reg = <0x4600 0x100>; // reg base, size
162 clock-frequency = <0>; // should we fill in in uboot? 163 clock-frequency = <0>; // should we fill in in uboot?
163 interrupts = <2a 2>; 164 interrupts = <42 2>;
164 interrupt-parent = <&mpic>; 165 interrupt-parent = <&mpic>;
165 }; 166 };
166 mpic: pic@40000 { 167 mpic: pic@40000 {
@@ -168,7 +169,7 @@
168 interrupt-controller; 169 interrupt-controller;
169 #address-cells = <0>; 170 #address-cells = <0>;
170 #interrupt-cells = <2>; 171 #interrupt-cells = <2>;
171 reg = <40000 40000>; 172 reg = <0x40000 0x40000>;
172 compatible = "chrp,open-pic"; 173 compatible = "chrp,open-pic";
173 device_type = "open-pic"; 174 device_type = "open-pic";
174 big-endian; 175 big-endian;
@@ -177,90 +178,90 @@
177 178
178 pci0: pci@e0008000 { 179 pci0: pci@e0008000 {
179 cell-index = <0>; 180 cell-index = <0>;
180 interrupt-map-mask = <f800 0 0 7>; 181 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
181 interrupt-map = < 182 interrupt-map = <
182 183
183 /* IDSEL 0x02 */ 184 /* IDSEL 0x02 */
184 1000 0 0 1 &mpic 1 1 185 0x1000 0x0 0x0 0x1 &mpic 0x1 0x1
185 1000 0 0 2 &mpic 2 1 186 0x1000 0x0 0x0 0x2 &mpic 0x2 0x1
186 1000 0 0 3 &mpic 3 1 187 0x1000 0x0 0x0 0x3 &mpic 0x3 0x1
187 1000 0 0 4 &mpic 4 1 188 0x1000 0x0 0x0 0x4 &mpic 0x4 0x1
188 189
189 /* IDSEL 0x03 */ 190 /* IDSEL 0x03 */
190 1800 0 0 1 &mpic 4 1 191 0x1800 0x0 0x0 0x1 &mpic 0x4 0x1
191 1800 0 0 2 &mpic 1 1 192 0x1800 0x0 0x0 0x2 &mpic 0x1 0x1
192 1800 0 0 3 &mpic 2 1 193 0x1800 0x0 0x0 0x3 &mpic 0x2 0x1
193 1800 0 0 4 &mpic 3 1 194 0x1800 0x0 0x0 0x4 &mpic 0x3 0x1
194 195
195 /* IDSEL 0x04 */ 196 /* IDSEL 0x04 */
196 2000 0 0 1 &mpic 3 1 197 0x2000 0x0 0x0 0x1 &mpic 0x3 0x1
197 2000 0 0 2 &mpic 4 1 198 0x2000 0x0 0x0 0x2 &mpic 0x4 0x1
198 2000 0 0 3 &mpic 1 1 199 0x2000 0x0 0x0 0x3 &mpic 0x1 0x1
199 2000 0 0 4 &mpic 2 1 200 0x2000 0x0 0x0 0x4 &mpic 0x2 0x1
200 201
201 /* IDSEL 0x05 */ 202 /* IDSEL 0x05 */
202 2800 0 0 1 &mpic 2 1 203 0x2800 0x0 0x0 0x1 &mpic 0x2 0x1
203 2800 0 0 2 &mpic 3 1 204 0x2800 0x0 0x0 0x2 &mpic 0x3 0x1
204 2800 0 0 3 &mpic 4 1 205 0x2800 0x0 0x0 0x3 &mpic 0x4 0x1
205 2800 0 0 4 &mpic 1 1 206 0x2800 0x0 0x0 0x4 &mpic 0x1 0x1
206 207
207 /* IDSEL 0x0c */ 208 /* IDSEL 0x0c */
208 6000 0 0 1 &mpic 1 1 209 0x6000 0x0 0x0 0x1 &mpic 0x1 0x1
209 6000 0 0 2 &mpic 2 1 210 0x6000 0x0 0x0 0x2 &mpic 0x2 0x1
210 6000 0 0 3 &mpic 3 1 211 0x6000 0x0 0x0 0x3 &mpic 0x3 0x1
211 6000 0 0 4 &mpic 4 1 212 0x6000 0x0 0x0 0x4 &mpic 0x4 0x1
212 213
213 /* IDSEL 0x0d */ 214 /* IDSEL 0x0d */
214 6800 0 0 1 &mpic 4 1 215 0x6800 0x0 0x0 0x1 &mpic 0x4 0x1
215 6800 0 0 2 &mpic 1 1 216 0x6800 0x0 0x0 0x2 &mpic 0x1 0x1
216 6800 0 0 3 &mpic 2 1 217 0x6800 0x0 0x0 0x3 &mpic 0x2 0x1
217 6800 0 0 4 &mpic 3 1 218 0x6800 0x0 0x0 0x4 &mpic 0x3 0x1
218 219
219 /* IDSEL 0x0e */ 220 /* IDSEL 0x0e */
220 7000 0 0 1 &mpic 3 1 221 0x7000 0x0 0x0 0x1 &mpic 0x3 0x1
221 7000 0 0 2 &mpic 4 1 222 0x7000 0x0 0x0 0x2 &mpic 0x4 0x1
222 7000 0 0 3 &mpic 1 1 223 0x7000 0x0 0x0 0x3 &mpic 0x1 0x1
223 7000 0 0 4 &mpic 2 1 224 0x7000 0x0 0x0 0x4 &mpic 0x2 0x1
224 225
225 /* IDSEL 0x0f */ 226 /* IDSEL 0x0f */
226 7800 0 0 1 &mpic 2 1 227 0x7800 0x0 0x0 0x1 &mpic 0x2 0x1
227 7800 0 0 2 &mpic 3 1 228 0x7800 0x0 0x0 0x2 &mpic 0x3 0x1
228 7800 0 0 3 &mpic 4 1 229 0x7800 0x0 0x0 0x3 &mpic 0x4 0x1
229 7800 0 0 4 &mpic 1 1 230 0x7800 0x0 0x0 0x4 &mpic 0x1 0x1
230 231
231 /* IDSEL 0x12 */ 232 /* IDSEL 0x12 */
232 9000 0 0 1 &mpic 1 1 233 0x9000 0x0 0x0 0x1 &mpic 0x1 0x1
233 9000 0 0 2 &mpic 2 1 234 0x9000 0x0 0x0 0x2 &mpic 0x2 0x1
234 9000 0 0 3 &mpic 3 1 235 0x9000 0x0 0x0 0x3 &mpic 0x3 0x1
235 9000 0 0 4 &mpic 4 1 236 0x9000 0x0 0x0 0x4 &mpic 0x4 0x1
236 237
237 /* IDSEL 0x13 */ 238 /* IDSEL 0x13 */
238 9800 0 0 1 &mpic 4 1 239 0x9800 0x0 0x0 0x1 &mpic 0x4 0x1
239 9800 0 0 2 &mpic 1 1 240 0x9800 0x0 0x0 0x2 &mpic 0x1 0x1
240 9800 0 0 3 &mpic 2 1 241 0x9800 0x0 0x0 0x3 &mpic 0x2 0x1
241 9800 0 0 4 &mpic 3 1 242 0x9800 0x0 0x0 0x4 &mpic 0x3 0x1
242 243
243 /* IDSEL 0x14 */ 244 /* IDSEL 0x14 */
244 a000 0 0 1 &mpic 3 1 245 0xa000 0x0 0x0 0x1 &mpic 0x3 0x1
245 a000 0 0 2 &mpic 4 1 246 0xa000 0x0 0x0 0x2 &mpic 0x4 0x1
246 a000 0 0 3 &mpic 1 1 247 0xa000 0x0 0x0 0x3 &mpic 0x1 0x1
247 a000 0 0 4 &mpic 2 1 248 0xa000 0x0 0x0 0x4 &mpic 0x2 0x1
248 249
249 /* IDSEL 0x15 */ 250 /* IDSEL 0x15 */
250 a800 0 0 1 &mpic 2 1 251 0xa800 0x0 0x0 0x1 &mpic 0x2 0x1
251 a800 0 0 2 &mpic 3 1 252 0xa800 0x0 0x0 0x2 &mpic 0x3 0x1
252 a800 0 0 3 &mpic 4 1 253 0xa800 0x0 0x0 0x3 &mpic 0x4 0x1
253 a800 0 0 4 &mpic 1 1>; 254 0xa800 0x0 0x0 0x4 &mpic 0x1 0x1>;
254 interrupt-parent = <&mpic>; 255 interrupt-parent = <&mpic>;
255 interrupts = <18 2>; 256 interrupts = <24 2>;
256 bus-range = <0 0>; 257 bus-range = <0 0>;
257 ranges = <02000000 0 80000000 80000000 0 20000000 258 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
258 01000000 0 00000000 e2000000 0 00100000>; 259 0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>;
259 clock-frequency = <3f940aa>; 260 clock-frequency = <66666666>;
260 #interrupt-cells = <1>; 261 #interrupt-cells = <1>;
261 #size-cells = <2>; 262 #size-cells = <2>;
262 #address-cells = <3>; 263 #address-cells = <3>;
263 reg = <e0008000 1000>; 264 reg = <0xe0008000 0x1000>;
264 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; 265 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
265 device_type = "pci"; 266 device_type = "pci";
266 }; 267 };
diff --git a/arch/powerpc/boot/dts/mpc8541cds.dts b/arch/powerpc/boot/dts/mpc8541cds.dts
index fa8d9aaad157..663c7c50ca45 100644
--- a/arch/powerpc/boot/dts/mpc8541cds.dts
+++ b/arch/powerpc/boot/dts/mpc8541cds.dts
@@ -1,7 +1,7 @@
1/* 1/*
2 * MPC8541 CDS Device Tree Source 2 * MPC8541 CDS Device Tree Source
3 * 3 *
4 * Copyright 2006 Freescale Semiconductor Inc. 4 * Copyright 2006, 2008 Freescale Semiconductor Inc.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the 7 * under the terms of the GNU General Public License as published by the
@@ -9,6 +9,7 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/dts-v1/;
12 13
13/ { 14/ {
14 model = "MPC8541CDS"; 15 model = "MPC8541CDS";
@@ -31,11 +32,11 @@
31 32
32 PowerPC,8541@0 { 33 PowerPC,8541@0 {
33 device_type = "cpu"; 34 device_type = "cpu";
34 reg = <0>; 35 reg = <0x0>;
35 d-cache-line-size = <20>; // 32 bytes 36 d-cache-line-size = <32>; // 32 bytes
36 i-cache-line-size = <20>; // 32 bytes 37 i-cache-line-size = <32>; // 32 bytes
37 d-cache-size = <8000>; // L1, 32K 38 d-cache-size = <0x8000>; // L1, 32K
38 i-cache-size = <8000>; // L1, 32K 39 i-cache-size = <0x8000>; // L1, 32K
39 timebase-frequency = <0>; // 33 MHz, from uboot 40 timebase-frequency = <0>; // 33 MHz, from uboot
40 bus-frequency = <0>; // 166 MHz 41 bus-frequency = <0>; // 166 MHz
41 clock-frequency = <0>; // 825 MHz, from uboot 42 clock-frequency = <0>; // 825 MHz, from uboot
@@ -44,31 +45,31 @@
44 45
45 memory { 46 memory {
46 device_type = "memory"; 47 device_type = "memory";
47 reg = <00000000 08000000>; // 128M at 0x0 48 reg = <0x0 0x8000000>; // 128M at 0x0
48 }; 49 };
49 50
50 soc8541@e0000000 { 51 soc8541@e0000000 {
51 #address-cells = <1>; 52 #address-cells = <1>;
52 #size-cells = <1>; 53 #size-cells = <1>;
53 device_type = "soc"; 54 device_type = "soc";
54 ranges = <0 e0000000 00100000>; 55 ranges = <0x0 0xe0000000 0x100000>;
55 reg = <e0000000 00001000>; // CCSRBAR 1M 56 reg = <0xe0000000 0x1000>; // CCSRBAR 1M
56 bus-frequency = <0>; 57 bus-frequency = <0>;
57 58
58 memory-controller@2000 { 59 memory-controller@2000 {
59 compatible = "fsl,8541-memory-controller"; 60 compatible = "fsl,8541-memory-controller";
60 reg = <2000 1000>; 61 reg = <0x2000 0x1000>;
61 interrupt-parent = <&mpic>; 62 interrupt-parent = <&mpic>;
62 interrupts = <12 2>; 63 interrupts = <18 2>;
63 }; 64 };
64 65
65 l2-cache-controller@20000 { 66 l2-cache-controller@20000 {
66 compatible = "fsl,8541-l2-cache-controller"; 67 compatible = "fsl,8541-l2-cache-controller";
67 reg = <20000 1000>; 68 reg = <0x20000 0x1000>;
68 cache-line-size = <20>; // 32 bytes 69 cache-line-size = <32>; // 32 bytes
69 cache-size = <40000>; // L2, 256K 70 cache-size = <0x40000>; // L2, 256K
70 interrupt-parent = <&mpic>; 71 interrupt-parent = <&mpic>;
71 interrupts = <10 2>; 72 interrupts = <16 2>;
72 }; 73 };
73 74
74 i2c@3000 { 75 i2c@3000 {
@@ -76,8 +77,8 @@
76 #size-cells = <0>; 77 #size-cells = <0>;
77 cell-index = <0>; 78 cell-index = <0>;
78 compatible = "fsl-i2c"; 79 compatible = "fsl-i2c";
79 reg = <3000 100>; 80 reg = <0x3000 0x100>;
80 interrupts = <2b 2>; 81 interrupts = <43 2>;
81 interrupt-parent = <&mpic>; 82 interrupt-parent = <&mpic>;
82 dfsrr; 83 dfsrr;
83 }; 84 };
@@ -86,18 +87,18 @@
86 #address-cells = <1>; 87 #address-cells = <1>;
87 #size-cells = <0>; 88 #size-cells = <0>;
88 compatible = "fsl,gianfar-mdio"; 89 compatible = "fsl,gianfar-mdio";
89 reg = <24520 20>; 90 reg = <0x24520 0x20>;
90 91
91 phy0: ethernet-phy@0 { 92 phy0: ethernet-phy@0 {
92 interrupt-parent = <&mpic>; 93 interrupt-parent = <&mpic>;
93 interrupts = <5 1>; 94 interrupts = <5 1>;
94 reg = <0>; 95 reg = <0x0>;
95 device_type = "ethernet-phy"; 96 device_type = "ethernet-phy";
96 }; 97 };
97 phy1: ethernet-phy@1 { 98 phy1: ethernet-phy@1 {
98 interrupt-parent = <&mpic>; 99 interrupt-parent = <&mpic>;
99 interrupts = <5 1>; 100 interrupts = <5 1>;
100 reg = <1>; 101 reg = <0x1>;
101 device_type = "ethernet-phy"; 102 device_type = "ethernet-phy";
102 }; 103 };
103 }; 104 };
@@ -107,9 +108,9 @@
107 device_type = "network"; 108 device_type = "network";
108 model = "TSEC"; 109 model = "TSEC";
109 compatible = "gianfar"; 110 compatible = "gianfar";
110 reg = <24000 1000>; 111 reg = <0x24000 0x1000>;
111 local-mac-address = [ 00 00 00 00 00 00 ]; 112 local-mac-address = [ 00 00 00 00 00 00 ];
112 interrupts = <1d 2 1e 2 22 2>; 113 interrupts = <29 2 30 2 34 2>;
113 interrupt-parent = <&mpic>; 114 interrupt-parent = <&mpic>;
114 phy-handle = <&phy0>; 115 phy-handle = <&phy0>;
115 }; 116 };
@@ -119,9 +120,9 @@
119 device_type = "network"; 120 device_type = "network";
120 model = "TSEC"; 121 model = "TSEC";
121 compatible = "gianfar"; 122 compatible = "gianfar";
122 reg = <25000 1000>; 123 reg = <0x25000 0x1000>;
123 local-mac-address = [ 00 00 00 00 00 00 ]; 124 local-mac-address = [ 00 00 00 00 00 00 ];
124 interrupts = <23 2 24 2 28 2>; 125 interrupts = <35 2 36 2 40 2>;
125 interrupt-parent = <&mpic>; 126 interrupt-parent = <&mpic>;
126 phy-handle = <&phy1>; 127 phy-handle = <&phy1>;
127 }; 128 };
@@ -130,9 +131,9 @@
130 cell-index = <0>; 131 cell-index = <0>;
131 device_type = "serial"; 132 device_type = "serial";
132 compatible = "ns16550"; 133 compatible = "ns16550";
133 reg = <4500 100>; // reg base, size 134 reg = <0x4500 0x100>; // reg base, size
134 clock-frequency = <0>; // should we fill in in uboot? 135 clock-frequency = <0>; // should we fill in in uboot?
135 interrupts = <2a 2>; 136 interrupts = <42 2>;
136 interrupt-parent = <&mpic>; 137 interrupt-parent = <&mpic>;
137 }; 138 };
138 139
@@ -140,9 +141,9 @@
140 cell-index = <1>; 141 cell-index = <1>;
141 device_type = "serial"; 142 device_type = "serial";
142 compatible = "ns16550"; 143 compatible = "ns16550";
143 reg = <4600 100>; // reg base, size 144 reg = <0x4600 0x100>; // reg base, size
144 clock-frequency = <0>; // should we fill in in uboot? 145 clock-frequency = <0>; // should we fill in in uboot?
145 interrupts = <2a 2>; 146 interrupts = <42 2>;
146 interrupt-parent = <&mpic>; 147 interrupt-parent = <&mpic>;
147 }; 148 };
148 149
@@ -151,7 +152,7 @@
151 interrupt-controller; 152 interrupt-controller;
152 #address-cells = <0>; 153 #address-cells = <0>;
153 #interrupt-cells = <2>; 154 #interrupt-cells = <2>;
154 reg = <40000 40000>; 155 reg = <0x40000 0x40000>;
155 compatible = "chrp,open-pic"; 156 compatible = "chrp,open-pic";
156 device_type = "open-pic"; 157 device_type = "open-pic";
157 big-endian; 158 big-endian;
@@ -161,17 +162,17 @@
161 #address-cells = <1>; 162 #address-cells = <1>;
162 #size-cells = <1>; 163 #size-cells = <1>;
163 compatible = "fsl,mpc8541-cpm", "fsl,cpm2"; 164 compatible = "fsl,mpc8541-cpm", "fsl,cpm2";
164 reg = <919c0 30>; 165 reg = <0x919c0 0x30>;
165 ranges; 166 ranges;
166 167
167 muram@80000 { 168 muram@80000 {
168 #address-cells = <1>; 169 #address-cells = <1>;
169 #size-cells = <1>; 170 #size-cells = <1>;
170 ranges = <0 80000 10000>; 171 ranges = <0x0 0x80000 0x10000>;
171 172
172 data@0 { 173 data@0 {
173 compatible = "fsl,cpm-muram-data"; 174 compatible = "fsl,cpm-muram-data";
174 reg = <0 2000 9000 1000>; 175 reg = <0x0 0x2000 0x9000 0x1000>;
175 }; 176 };
176 }; 177 };
177 178
@@ -179,16 +180,16 @@
179 compatible = "fsl,mpc8541-brg", 180 compatible = "fsl,mpc8541-brg",
180 "fsl,cpm2-brg", 181 "fsl,cpm2-brg",
181 "fsl,cpm-brg"; 182 "fsl,cpm-brg";
182 reg = <919f0 10 915f0 10>; 183 reg = <0x919f0 0x10 0x915f0 0x10>;
183 }; 184 };
184 185
185 cpmpic: pic@90c00 { 186 cpmpic: pic@90c00 {
186 interrupt-controller; 187 interrupt-controller;
187 #address-cells = <0>; 188 #address-cells = <0>;
188 #interrupt-cells = <2>; 189 #interrupt-cells = <2>;
189 interrupts = <2e 2>; 190 interrupts = <46 2>;
190 interrupt-parent = <&mpic>; 191 interrupt-parent = <&mpic>;
191 reg = <90c00 80>; 192 reg = <0x90c00 0x80>;
192 compatible = "fsl,mpc8541-cpm-pic", "fsl,cpm2-pic"; 193 compatible = "fsl,mpc8541-cpm-pic", "fsl,cpm2-pic";
193 }; 194 };
194 }; 195 };
@@ -196,68 +197,68 @@
196 197
197 pci0: pci@e0008000 { 198 pci0: pci@e0008000 {
198 cell-index = <0>; 199 cell-index = <0>;
199 interrupt-map-mask = <1f800 0 0 7>; 200 interrupt-map-mask = <0x1f800 0x0 0x0 0x7>;
200 interrupt-map = < 201 interrupt-map = <
201 202
202 /* IDSEL 0x10 */ 203 /* IDSEL 0x10 */
203 08000 0 0 1 &mpic 0 1 204 0x8000 0x0 0x0 0x1 &mpic 0x0 0x1
204 08000 0 0 2 &mpic 1 1 205 0x8000 0x0 0x0 0x2 &mpic 0x1 0x1
205 08000 0 0 3 &mpic 2 1 206 0x8000 0x0 0x0 0x3 &mpic 0x2 0x1
206 08000 0 0 4 &mpic 3 1 207 0x8000 0x0 0x0 0x4 &mpic 0x3 0x1
207 208
208 /* IDSEL 0x11 */ 209 /* IDSEL 0x11 */
209 08800 0 0 1 &mpic 0 1 210 0x8800 0x0 0x0 0x1 &mpic 0x0 0x1
210 08800 0 0 2 &mpic 1 1 211 0x8800 0x0 0x0 0x2 &mpic 0x1 0x1
211 08800 0 0 3 &mpic 2 1 212 0x8800 0x0 0x0 0x3 &mpic 0x2 0x1
212 08800 0 0 4 &mpic 3 1 213 0x8800 0x0 0x0 0x4 &mpic 0x3 0x1
213 214
214 /* IDSEL 0x12 (Slot 1) */ 215 /* IDSEL 0x12 (Slot 1) */
215 09000 0 0 1 &mpic 0 1 216 0x9000 0x0 0x0 0x1 &mpic 0x0 0x1
216 09000 0 0 2 &mpic 1 1 217 0x9000 0x0 0x0 0x2 &mpic 0x1 0x1
217 09000 0 0 3 &mpic 2 1 218 0x9000 0x0 0x0 0x3 &mpic 0x2 0x1
218 09000 0 0 4 &mpic 3 1 219 0x9000 0x0 0x0 0x4 &mpic 0x3 0x1
219 220
220 /* IDSEL 0x13 (Slot 2) */ 221 /* IDSEL 0x13 (Slot 2) */
221 09800 0 0 1 &mpic 1 1 222 0x9800 0x0 0x0 0x1 &mpic 0x1 0x1
222 09800 0 0 2 &mpic 2 1 223 0x9800 0x0 0x0 0x2 &mpic 0x2 0x1
223 09800 0 0 3 &mpic 3 1 224 0x9800 0x0 0x0 0x3 &mpic 0x3 0x1
224 09800 0 0 4 &mpic 0 1 225 0x9800 0x0 0x0 0x4 &mpic 0x0 0x1
225 226
226 /* IDSEL 0x14 (Slot 3) */ 227 /* IDSEL 0x14 (Slot 3) */
227 0a000 0 0 1 &mpic 2 1 228 0xa000 0x0 0x0 0x1 &mpic 0x2 0x1
228 0a000 0 0 2 &mpic 3 1 229 0xa000 0x0 0x0 0x2 &mpic 0x3 0x1
229 0a000 0 0 3 &mpic 0 1 230 0xa000 0x0 0x0 0x3 &mpic 0x0 0x1
230 0a000 0 0 4 &mpic 1 1 231 0xa000 0x0 0x0 0x4 &mpic 0x1 0x1
231 232
232 /* IDSEL 0x15 (Slot 4) */ 233 /* IDSEL 0x15 (Slot 4) */
233 0a800 0 0 1 &mpic 3 1 234 0xa800 0x0 0x0 0x1 &mpic 0x3 0x1
234 0a800 0 0 2 &mpic 0 1 235 0xa800 0x0 0x0 0x2 &mpic 0x0 0x1
235 0a800 0 0 3 &mpic 1 1 236 0xa800 0x0 0x0 0x3 &mpic 0x1 0x1
236 0a800 0 0 4 &mpic 2 1 237 0xa800 0x0 0x0 0x4 &mpic 0x2 0x1
237 238
238 /* Bus 1 (Tundra Bridge) */ 239 /* Bus 1 (Tundra Bridge) */
239 /* IDSEL 0x12 (ISA bridge) */ 240 /* IDSEL 0x12 (ISA bridge) */
240 19000 0 0 1 &mpic 0 1 241 0x19000 0x0 0x0 0x1 &mpic 0x0 0x1
241 19000 0 0 2 &mpic 1 1 242 0x19000 0x0 0x0 0x2 &mpic 0x1 0x1
242 19000 0 0 3 &mpic 2 1 243 0x19000 0x0 0x0 0x3 &mpic 0x2 0x1
243 19000 0 0 4 &mpic 3 1>; 244 0x19000 0x0 0x0 0x4 &mpic 0x3 0x1>;
244 interrupt-parent = <&mpic>; 245 interrupt-parent = <&mpic>;
245 interrupts = <18 2>; 246 interrupts = <24 2>;
246 bus-range = <0 0>; 247 bus-range = <0 0>;
247 ranges = <02000000 0 80000000 80000000 0 20000000 248 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
248 01000000 0 00000000 e2000000 0 00100000>; 249 0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>;
249 clock-frequency = <3f940aa>; 250 clock-frequency = <66666666>;
250 #interrupt-cells = <1>; 251 #interrupt-cells = <1>;
251 #size-cells = <2>; 252 #size-cells = <2>;
252 #address-cells = <3>; 253 #address-cells = <3>;
253 reg = <e0008000 1000>; 254 reg = <0xe0008000 0x1000>;
254 compatible = "fsl,mpc8540-pci"; 255 compatible = "fsl,mpc8540-pci";
255 device_type = "pci"; 256 device_type = "pci";
256 257
257 i8259@19000 { 258 i8259@19000 {
258 interrupt-controller; 259 interrupt-controller;
259 device_type = "interrupt-controller"; 260 device_type = "interrupt-controller";
260 reg = <19000 0 0 0 1>; 261 reg = <0x19000 0x0 0x0 0x0 0x1>;
261 #address-cells = <0>; 262 #address-cells = <0>;
262 #interrupt-cells = <2>; 263 #interrupt-cells = <2>;
263 compatible = "chrp,iic"; 264 compatible = "chrp,iic";
@@ -268,24 +269,24 @@
268 269
269 pci1: pci@e0009000 { 270 pci1: pci@e0009000 {
270 cell-index = <1>; 271 cell-index = <1>;
271 interrupt-map-mask = <f800 0 0 7>; 272 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
272 interrupt-map = < 273 interrupt-map = <
273 274
274 /* IDSEL 0x15 */ 275 /* IDSEL 0x15 */
275 a800 0 0 1 &mpic b 1 276 0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
276 a800 0 0 2 &mpic b 1 277 0xa800 0x0 0x0 0x2 &mpic 0xb 0x1
277 a800 0 0 3 &mpic b 1 278 0xa800 0x0 0x0 0x3 &mpic 0xb 0x1
278 a800 0 0 4 &mpic b 1>; 279 0xa800 0x0 0x0 0x4 &mpic 0xb 0x1>;
279 interrupt-parent = <&mpic>; 280 interrupt-parent = <&mpic>;
280 interrupts = <19 2>; 281 interrupts = <25 2>;
281 bus-range = <0 0>; 282 bus-range = <0 0>;
282 ranges = <02000000 0 a0000000 a0000000 0 20000000 283 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
283 01000000 0 00000000 e3000000 0 00100000>; 284 0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>;
284 clock-frequency = <3f940aa>; 285 clock-frequency = <66666666>;
285 #interrupt-cells = <1>; 286 #interrupt-cells = <1>;
286 #size-cells = <2>; 287 #size-cells = <2>;
287 #address-cells = <3>; 288 #address-cells = <3>;
288 reg = <e0009000 1000>; 289 reg = <0xe0009000 0x1000>;
289 compatible = "fsl,mpc8540-pci"; 290 compatible = "fsl,mpc8540-pci";
290 device_type = "pci"; 291 device_type = "pci";
291 }; 292 };
diff --git a/arch/powerpc/boot/dts/mpc8544ds.dts b/arch/powerpc/boot/dts/mpc8544ds.dts
index 688af9d06382..6a0d8db96d97 100644
--- a/arch/powerpc/boot/dts/mpc8544ds.dts
+++ b/arch/powerpc/boot/dts/mpc8544ds.dts
@@ -1,7 +1,7 @@
1/* 1/*
2 * MPC8544 DS Device Tree Source 2 * MPC8544 DS Device Tree Source
3 * 3 *
4 * Copyright 2007 Freescale Semiconductor Inc. 4 * Copyright 2007, 2008 Freescale Semiconductor Inc.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the 7 * under the terms of the GNU General Public License as published by the
@@ -9,6 +9,7 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/dts-v1/;
12/ { 13/ {
13 model = "MPC8544DS"; 14 model = "MPC8544DS";
14 compatible = "MPC8544DS", "MPC85xxDS"; 15 compatible = "MPC8544DS", "MPC85xxDS";
@@ -27,17 +28,16 @@
27 }; 28 };
28 29
29 cpus { 30 cpus {
30 #cpus = <1>;
31 #address-cells = <1>; 31 #address-cells = <1>;
32 #size-cells = <0>; 32 #size-cells = <0>;
33 33
34 PowerPC,8544@0 { 34 PowerPC,8544@0 {
35 device_type = "cpu"; 35 device_type = "cpu";
36 reg = <0>; 36 reg = <0x0>;
37 d-cache-line-size = <20>; // 32 bytes 37 d-cache-line-size = <32>; // 32 bytes
38 i-cache-line-size = <20>; // 32 bytes 38 i-cache-line-size = <32>; // 32 bytes
39 d-cache-size = <8000>; // L1, 32K 39 d-cache-size = <0x8000>; // L1, 32K
40 i-cache-size = <8000>; // L1, 32K 40 i-cache-size = <0x8000>; // L1, 32K
41 timebase-frequency = <0>; 41 timebase-frequency = <0>;
42 bus-frequency = <0>; 42 bus-frequency = <0>;
43 clock-frequency = <0>; 43 clock-frequency = <0>;
@@ -46,7 +46,7 @@
46 46
47 memory { 47 memory {
48 device_type = "memory"; 48 device_type = "memory";
49 reg = <00000000 00000000>; // Filled by U-Boot 49 reg = <0x0 0x0>; // Filled by U-Boot
50 }; 50 };
51 51
52 soc8544@e0000000 { 52 soc8544@e0000000 {
@@ -54,24 +54,24 @@
54 #size-cells = <1>; 54 #size-cells = <1>;
55 device_type = "soc"; 55 device_type = "soc";
56 56
57 ranges = <00000000 e0000000 00100000>; 57 ranges = <0x0 0xe0000000 0x100000>;
58 reg = <e0000000 00001000>; // CCSRBAR 1M 58 reg = <0xe0000000 0x1000>; // CCSRBAR 1M
59 bus-frequency = <0>; // Filled out by uboot. 59 bus-frequency = <0>; // Filled out by uboot.
60 60
61 memory-controller@2000 { 61 memory-controller@2000 {
62 compatible = "fsl,8544-memory-controller"; 62 compatible = "fsl,8544-memory-controller";
63 reg = <2000 1000>; 63 reg = <0x2000 0x1000>;
64 interrupt-parent = <&mpic>; 64 interrupt-parent = <&mpic>;
65 interrupts = <12 2>; 65 interrupts = <18 2>;
66 }; 66 };
67 67
68 l2-cache-controller@20000 { 68 l2-cache-controller@20000 {
69 compatible = "fsl,8544-l2-cache-controller"; 69 compatible = "fsl,8544-l2-cache-controller";
70 reg = <20000 1000>; 70 reg = <0x20000 0x1000>;
71 cache-line-size = <20>; // 32 bytes 71 cache-line-size = <32>; // 32 bytes
72 cache-size = <40000>; // L2, 256K 72 cache-size = <0x40000>; // L2, 256K
73 interrupt-parent = <&mpic>; 73 interrupt-parent = <&mpic>;
74 interrupts = <10 2>; 74 interrupts = <16 2>;
75 }; 75 };
76 76
77 i2c@3000 { 77 i2c@3000 {
@@ -79,8 +79,8 @@
79 #size-cells = <0>; 79 #size-cells = <0>;
80 cell-index = <0>; 80 cell-index = <0>;
81 compatible = "fsl-i2c"; 81 compatible = "fsl-i2c";
82 reg = <3000 100>; 82 reg = <0x3000 0x100>;
83 interrupts = <2b 2>; 83 interrupts = <43 2>;
84 interrupt-parent = <&mpic>; 84 interrupt-parent = <&mpic>;
85 dfsrr; 85 dfsrr;
86 }; 86 };
@@ -90,8 +90,8 @@
90 #size-cells = <0>; 90 #size-cells = <0>;
91 cell-index = <1>; 91 cell-index = <1>;
92 compatible = "fsl-i2c"; 92 compatible = "fsl-i2c";
93 reg = <3100 100>; 93 reg = <0x3100 0x100>;
94 interrupts = <2b 2>; 94 interrupts = <43 2>;
95 interrupt-parent = <&mpic>; 95 interrupt-parent = <&mpic>;
96 dfsrr; 96 dfsrr;
97 }; 97 };
@@ -100,30 +100,71 @@
100 #address-cells = <1>; 100 #address-cells = <1>;
101 #size-cells = <0>; 101 #size-cells = <0>;
102 compatible = "fsl,gianfar-mdio"; 102 compatible = "fsl,gianfar-mdio";
103 reg = <24520 20>; 103 reg = <0x24520 0x20>;
104 104
105 phy0: ethernet-phy@0 { 105 phy0: ethernet-phy@0 {
106 interrupt-parent = <&mpic>; 106 interrupt-parent = <&mpic>;
107 interrupts = <a 1>; 107 interrupts = <10 1>;
108 reg = <0>; 108 reg = <0x0>;
109 device_type = "ethernet-phy"; 109 device_type = "ethernet-phy";
110 }; 110 };
111 phy1: ethernet-phy@1 { 111 phy1: ethernet-phy@1 {
112 interrupt-parent = <&mpic>; 112 interrupt-parent = <&mpic>;
113 interrupts = <a 1>; 113 interrupts = <10 1>;
114 reg = <1>; 114 reg = <0x1>;
115 device_type = "ethernet-phy"; 115 device_type = "ethernet-phy";
116 }; 116 };
117 }; 117 };
118 118
119 dma@21300 {
120 #address-cells = <1>;
121 #size-cells = <1>;
122 compatible = "fsl,mpc8544-dma", "fsl,eloplus-dma";
123 reg = <0x21300 0x4>;
124 ranges = <0x0 0x21100 0x200>;
125 cell-index = <0>;
126 dma-channel@0 {
127 compatible = "fsl,mpc8544-dma-channel",
128 "fsl,eloplus-dma-channel";
129 reg = <0x0 0x80>;
130 cell-index = <0>;
131 interrupt-parent = <&mpic>;
132 interrupts = <20 2>;
133 };
134 dma-channel@80 {
135 compatible = "fsl,mpc8544-dma-channel",
136 "fsl,eloplus-dma-channel";
137 reg = <0x80 0x80>;
138 cell-index = <1>;
139 interrupt-parent = <&mpic>;
140 interrupts = <21 2>;
141 };
142 dma-channel@100 {
143 compatible = "fsl,mpc8544-dma-channel",
144 "fsl,eloplus-dma-channel";
145 reg = <0x100 0x80>;
146 cell-index = <2>;
147 interrupt-parent = <&mpic>;
148 interrupts = <22 2>;
149 };
150 dma-channel@180 {
151 compatible = "fsl,mpc8544-dma-channel",
152 "fsl,eloplus-dma-channel";
153 reg = <0x180 0x80>;
154 cell-index = <3>;
155 interrupt-parent = <&mpic>;
156 interrupts = <23 2>;
157 };
158 };
159
119 enet0: ethernet@24000 { 160 enet0: ethernet@24000 {
120 cell-index = <0>; 161 cell-index = <0>;
121 device_type = "network"; 162 device_type = "network";
122 model = "TSEC"; 163 model = "TSEC";
123 compatible = "gianfar"; 164 compatible = "gianfar";
124 reg = <24000 1000>; 165 reg = <0x24000 0x1000>;
125 local-mac-address = [ 00 00 00 00 00 00 ]; 166 local-mac-address = [ 00 00 00 00 00 00 ];
126 interrupts = <1d 2 1e 2 22 2>; 167 interrupts = <29 2 30 2 34 2>;
127 interrupt-parent = <&mpic>; 168 interrupt-parent = <&mpic>;
128 phy-handle = <&phy0>; 169 phy-handle = <&phy0>;
129 phy-connection-type = "rgmii-id"; 170 phy-connection-type = "rgmii-id";
@@ -134,9 +175,9 @@
134 device_type = "network"; 175 device_type = "network";
135 model = "TSEC"; 176 model = "TSEC";
136 compatible = "gianfar"; 177 compatible = "gianfar";
137 reg = <26000 1000>; 178 reg = <0x26000 0x1000>;
138 local-mac-address = [ 00 00 00 00 00 00 ]; 179 local-mac-address = [ 00 00 00 00 00 00 ];
139 interrupts = <1f 2 20 2 21 2>; 180 interrupts = <31 2 32 2 33 2>;
140 interrupt-parent = <&mpic>; 181 interrupt-parent = <&mpic>;
141 phy-handle = <&phy1>; 182 phy-handle = <&phy1>;
142 phy-connection-type = "rgmii-id"; 183 phy-connection-type = "rgmii-id";
@@ -146,9 +187,9 @@
146 cell-index = <0>; 187 cell-index = <0>;
147 device_type = "serial"; 188 device_type = "serial";
148 compatible = "ns16550"; 189 compatible = "ns16550";
149 reg = <4500 100>; 190 reg = <0x4500 0x100>;
150 clock-frequency = <0>; 191 clock-frequency = <0>;
151 interrupts = <2a 2>; 192 interrupts = <42 2>;
152 interrupt-parent = <&mpic>; 193 interrupt-parent = <&mpic>;
153 }; 194 };
154 195
@@ -156,15 +197,15 @@
156 cell-index = <1>; 197 cell-index = <1>;
157 device_type = "serial"; 198 device_type = "serial";
158 compatible = "ns16550"; 199 compatible = "ns16550";
159 reg = <4600 100>; 200 reg = <0x4600 0x100>;
160 clock-frequency = <0>; 201 clock-frequency = <0>;
161 interrupts = <2a 2>; 202 interrupts = <42 2>;
162 interrupt-parent = <&mpic>; 203 interrupt-parent = <&mpic>;
163 }; 204 };
164 205
165 global-utilities@e0000 { //global utilities block 206 global-utilities@e0000 { //global utilities block
166 compatible = "fsl,mpc8548-guts"; 207 compatible = "fsl,mpc8548-guts";
167 reg = <e0000 1000>; 208 reg = <0xe0000 0x1000>;
168 fsl,has-rstcr; 209 fsl,has-rstcr;
169 }; 210 };
170 211
@@ -173,7 +214,7 @@
173 interrupt-controller; 214 interrupt-controller;
174 #address-cells = <0>; 215 #address-cells = <0>;
175 #interrupt-cells = <2>; 216 #interrupt-cells = <2>;
176 reg = <40000 40000>; 217 reg = <0x40000 0x40000>;
177 compatible = "chrp,open-pic"; 218 compatible = "chrp,open-pic";
178 device_type = "open-pic"; 219 device_type = "open-pic";
179 big-endian; 220 big-endian;
@@ -184,32 +225,32 @@
184 cell-index = <0>; 225 cell-index = <0>;
185 compatible = "fsl,mpc8540-pci"; 226 compatible = "fsl,mpc8540-pci";
186 device_type = "pci"; 227 device_type = "pci";
187 interrupt-map-mask = <f800 0 0 7>; 228 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
188 interrupt-map = < 229 interrupt-map = <
189 230
190 /* IDSEL 0x11 J17 Slot 1 */ 231 /* IDSEL 0x11 J17 Slot 1 */
191 8800 0 0 1 &mpic 2 1 232 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
192 8800 0 0 2 &mpic 3 1 233 0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
193 8800 0 0 3 &mpic 4 1 234 0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
194 8800 0 0 4 &mpic 1 1 235 0x8800 0x0 0x0 0x4 &mpic 0x1 0x1
195 236
196 /* IDSEL 0x12 J16 Slot 2 */ 237 /* IDSEL 0x12 J16 Slot 2 */
197 238
198 9000 0 0 1 &mpic 3 1 239 0x9000 0x0 0x0 0x1 &mpic 0x3 0x1
199 9000 0 0 2 &mpic 4 1 240 0x9000 0x0 0x0 0x2 &mpic 0x4 0x1
200 9000 0 0 3 &mpic 2 1 241 0x9000 0x0 0x0 0x3 &mpic 0x2 0x1
201 9000 0 0 4 &mpic 1 1>; 242 0x9000 0x0 0x0 0x4 &mpic 0x1 0x1>;
202 243
203 interrupt-parent = <&mpic>; 244 interrupt-parent = <&mpic>;
204 interrupts = <18 2>; 245 interrupts = <24 2>;
205 bus-range = <0 ff>; 246 bus-range = <0 255>;
206 ranges = <02000000 0 c0000000 c0000000 0 20000000 247 ranges = <0x2000000 0x0 0xc0000000 0xc0000000 0x0 0x20000000
207 01000000 0 00000000 e1000000 0 00010000>; 248 0x1000000 0x0 0x0 0xe1000000 0x0 0x10000>;
208 clock-frequency = <3f940aa>; 249 clock-frequency = <66666666>;
209 #interrupt-cells = <1>; 250 #interrupt-cells = <1>;
210 #size-cells = <2>; 251 #size-cells = <2>;
211 #address-cells = <3>; 252 #address-cells = <3>;
212 reg = <e0008000 1000>; 253 reg = <0xe0008000 0x1000>;
213 }; 254 };
214 255
215 pci1: pcie@e0009000 { 256 pci1: pcie@e0009000 {
@@ -219,33 +260,33 @@
219 #interrupt-cells = <1>; 260 #interrupt-cells = <1>;
220 #size-cells = <2>; 261 #size-cells = <2>;
221 #address-cells = <3>; 262 #address-cells = <3>;
222 reg = <e0009000 1000>; 263 reg = <0xe0009000 0x1000>;
223 bus-range = <0 ff>; 264 bus-range = <0 255>;
224 ranges = <02000000 0 80000000 80000000 0 20000000 265 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
225 01000000 0 00000000 e1010000 0 00010000>; 266 0x1000000 0x0 0x0 0xe1010000 0x0 0x10000>;
226 clock-frequency = <1fca055>; 267 clock-frequency = <33333333>;
227 interrupt-parent = <&mpic>; 268 interrupt-parent = <&mpic>;
228 interrupts = <1a 2>; 269 interrupts = <26 2>;
229 interrupt-map-mask = <f800 0 0 7>; 270 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
230 interrupt-map = < 271 interrupt-map = <
231 /* IDSEL 0x0 */ 272 /* IDSEL 0x0 */
232 0000 0 0 1 &mpic 4 1 273 0000 0x0 0x0 0x1 &mpic 0x4 0x1
233 0000 0 0 2 &mpic 5 1 274 0000 0x0 0x0 0x2 &mpic 0x5 0x1
234 0000 0 0 3 &mpic 6 1 275 0000 0x0 0x0 0x3 &mpic 0x6 0x1
235 0000 0 0 4 &mpic 7 1 276 0000 0x0 0x0 0x4 &mpic 0x7 0x1
236 >; 277 >;
237 pcie@0 { 278 pcie@0 {
238 reg = <0 0 0 0 0>; 279 reg = <0x0 0x0 0x0 0x0 0x0>;
239 #size-cells = <2>; 280 #size-cells = <2>;
240 #address-cells = <3>; 281 #address-cells = <3>;
241 device_type = "pci"; 282 device_type = "pci";
242 ranges = <02000000 0 80000000 283 ranges = <0x2000000 0x0 0x80000000
243 02000000 0 80000000 284 0x2000000 0x0 0x80000000
244 0 20000000 285 0x0 0x20000000
245 286
246 01000000 0 00000000 287 0x1000000 0x0 0x0
247 01000000 0 00000000 288 0x1000000 0x0 0x0
248 0 00010000>; 289 0x0 0x10000>;
249 }; 290 };
250 }; 291 };
251 292
@@ -256,33 +297,33 @@
256 #interrupt-cells = <1>; 297 #interrupt-cells = <1>;
257 #size-cells = <2>; 298 #size-cells = <2>;
258 #address-cells = <3>; 299 #address-cells = <3>;
259 reg = <e000a000 1000>; 300 reg = <0xe000a000 0x1000>;
260 bus-range = <0 ff>; 301 bus-range = <0 255>;
261 ranges = <02000000 0 a0000000 a0000000 0 10000000 302 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
262 01000000 0 00000000 e1020000 0 00010000>; 303 0x1000000 0x0 0x0 0xe1020000 0x0 0x10000>;
263 clock-frequency = <1fca055>; 304 clock-frequency = <33333333>;
264 interrupt-parent = <&mpic>; 305 interrupt-parent = <&mpic>;
265 interrupts = <19 2>; 306 interrupts = <25 2>;
266 interrupt-map-mask = <f800 0 0 7>; 307 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
267 interrupt-map = < 308 interrupt-map = <
268 /* IDSEL 0x0 */ 309 /* IDSEL 0x0 */
269 0000 0 0 1 &mpic 0 1 310 0000 0x0 0x0 0x1 &mpic 0x0 0x1
270 0000 0 0 2 &mpic 1 1 311 0000 0x0 0x0 0x2 &mpic 0x1 0x1
271 0000 0 0 3 &mpic 2 1 312 0000 0x0 0x0 0x3 &mpic 0x2 0x1
272 0000 0 0 4 &mpic 3 1 313 0000 0x0 0x0 0x4 &mpic 0x3 0x1
273 >; 314 >;
274 pcie@0 { 315 pcie@0 {
275 reg = <0 0 0 0 0>; 316 reg = <0x0 0x0 0x0 0x0 0x0>;
276 #size-cells = <2>; 317 #size-cells = <2>;
277 #address-cells = <3>; 318 #address-cells = <3>;
278 device_type = "pci"; 319 device_type = "pci";
279 ranges = <02000000 0 a0000000 320 ranges = <0x2000000 0x0 0xa0000000
280 02000000 0 a0000000 321 0x2000000 0x0 0xa0000000
281 0 10000000 322 0x0 0x10000000
282 323
283 01000000 0 00000000 324 0x1000000 0x0 0x0
284 01000000 0 00000000 325 0x1000000 0x0 0x0
285 0 00010000>; 326 0x0 0x10000>;
286 }; 327 };
287 }; 328 };
288 329
@@ -293,72 +334,72 @@
293 #interrupt-cells = <1>; 334 #interrupt-cells = <1>;
294 #size-cells = <2>; 335 #size-cells = <2>;
295 #address-cells = <3>; 336 #address-cells = <3>;
296 reg = <e000b000 1000>; 337 reg = <0xe000b000 0x1000>;
297 bus-range = <0 ff>; 338 bus-range = <0 255>;
298 ranges = <02000000 0 b0000000 b0000000 0 00100000 339 ranges = <0x2000000 0x0 0xb0000000 0xb0000000 0x0 0x100000
299 01000000 0 00000000 b0100000 0 00100000>; 340 0x1000000 0x0 0x0 0xb0100000 0x0 0x100000>;
300 clock-frequency = <1fca055>; 341 clock-frequency = <33333333>;
301 interrupt-parent = <&mpic>; 342 interrupt-parent = <&mpic>;
302 interrupts = <1b 2>; 343 interrupts = <27 2>;
303 interrupt-map-mask = <ff00 0 0 1>; 344 interrupt-map-mask = <0xff00 0x0 0x0 0x1>;
304 interrupt-map = < 345 interrupt-map = <
305 // IDSEL 0x1c USB 346 // IDSEL 0x1c USB
306 e000 0 0 1 &i8259 c 2 347 0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
307 e100 0 0 2 &i8259 9 2 348 0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
308 e200 0 0 3 &i8259 a 2 349 0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
309 e300 0 0 4 &i8259 b 2 350 0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
310 351
311 // IDSEL 0x1d Audio 352 // IDSEL 0x1d Audio
312 e800 0 0 1 &i8259 6 2 353 0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
313 354
314 // IDSEL 0x1e Legacy 355 // IDSEL 0x1e Legacy
315 f000 0 0 1 &i8259 7 2 356 0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
316 f100 0 0 1 &i8259 7 2 357 0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
317 358
318 // IDSEL 0x1f IDE/SATA 359 // IDSEL 0x1f IDE/SATA
319 f800 0 0 1 &i8259 e 2 360 0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
320 f900 0 0 1 &i8259 5 2 361 0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
321 >; 362 >;
322 363
323 pcie@0 { 364 pcie@0 {
324 reg = <0 0 0 0 0>; 365 reg = <0x0 0x0 0x0 0x0 0x0>;
325 #size-cells = <2>; 366 #size-cells = <2>;
326 #address-cells = <3>; 367 #address-cells = <3>;
327 device_type = "pci"; 368 device_type = "pci";
328 ranges = <02000000 0 b0000000 369 ranges = <0x2000000 0x0 0xb0000000
329 02000000 0 b0000000 370 0x2000000 0x0 0xb0000000
330 0 00100000 371 0x0 0x100000
331 372
332 01000000 0 00000000 373 0x1000000 0x0 0x0
333 01000000 0 00000000 374 0x1000000 0x0 0x0
334 0 00100000>; 375 0x0 0x100000>;
335 376
336 uli1575@0 { 377 uli1575@0 {
337 reg = <0 0 0 0 0>; 378 reg = <0x0 0x0 0x0 0x0 0x0>;
338 #size-cells = <2>; 379 #size-cells = <2>;
339 #address-cells = <3>; 380 #address-cells = <3>;
340 ranges = <02000000 0 b0000000 381 ranges = <0x2000000 0x0 0xb0000000
341 02000000 0 b0000000 382 0x2000000 0x0 0xb0000000
342 0 00100000 383 0x0 0x100000
343 384
344 01000000 0 00000000 385 0x1000000 0x0 0x0
345 01000000 0 00000000 386 0x1000000 0x0 0x0
346 0 00100000>; 387 0x0 0x100000>;
347 isa@1e { 388 isa@1e {
348 device_type = "isa"; 389 device_type = "isa";
349 #interrupt-cells = <2>; 390 #interrupt-cells = <2>;
350 #size-cells = <1>; 391 #size-cells = <1>;
351 #address-cells = <2>; 392 #address-cells = <2>;
352 reg = <f000 0 0 0 0>; 393 reg = <0xf000 0x0 0x0 0x0 0x0>;
353 ranges = <1 0 394 ranges = <0x1 0x0
354 01000000 0 0 395 0x1000000 0x0 0x0
355 00001000>; 396 0x1000>;
356 interrupt-parent = <&i8259>; 397 interrupt-parent = <&i8259>;
357 398
358 i8259: interrupt-controller@20 { 399 i8259: interrupt-controller@20 {
359 reg = <1 20 2 400 reg = <0x1 0x20 0x2
360 1 a0 2 401 0x1 0xa0 0x2
361 1 4d0 2>; 402 0x1 0x4d0 0x2>;
362 interrupt-controller; 403 interrupt-controller;
363 device_type = "interrupt-controller"; 404 device_type = "interrupt-controller";
364 #address-cells = <0>; 405 #address-cells = <0>;
@@ -371,28 +412,28 @@
371 i8042@60 { 412 i8042@60 {
372 #size-cells = <0>; 413 #size-cells = <0>;
373 #address-cells = <1>; 414 #address-cells = <1>;
374 reg = <1 60 1 1 64 1>; 415 reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
375 interrupts = <1 3 c 3>; 416 interrupts = <1 3 12 3>;
376 interrupt-parent = <&i8259>; 417 interrupt-parent = <&i8259>;
377 418
378 keyboard@0 { 419 keyboard@0 {
379 reg = <0>; 420 reg = <0x0>;
380 compatible = "pnpPNP,303"; 421 compatible = "pnpPNP,303";
381 }; 422 };
382 423
383 mouse@1 { 424 mouse@1 {
384 reg = <1>; 425 reg = <0x1>;
385 compatible = "pnpPNP,f03"; 426 compatible = "pnpPNP,f03";
386 }; 427 };
387 }; 428 };
388 429
389 rtc@70 { 430 rtc@70 {
390 compatible = "pnpPNP,b00"; 431 compatible = "pnpPNP,b00";
391 reg = <1 70 2>; 432 reg = <0x1 0x70 0x2>;
392 }; 433 };
393 434
394 gpio@400 { 435 gpio@400 {
395 reg = <1 400 80>; 436 reg = <0x1 0x400 0x80>;
396 }; 437 };
397 }; 438 };
398 }; 439 };
diff --git a/arch/powerpc/boot/dts/mpc8548cds.dts b/arch/powerpc/boot/dts/mpc8548cds.dts
index 1f470c6a1c63..fa298a8c81cc 100644
--- a/arch/powerpc/boot/dts/mpc8548cds.dts
+++ b/arch/powerpc/boot/dts/mpc8548cds.dts
@@ -1,7 +1,7 @@
1/* 1/*
2 * MPC8548 CDS Device Tree Source 2 * MPC8548 CDS Device Tree Source
3 * 3 *
4 * Copyright 2006 Freescale Semiconductor Inc. 4 * Copyright 2006, 2008 Freescale Semiconductor Inc.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the 7 * under the terms of the GNU General Public License as published by the
@@ -9,6 +9,7 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/dts-v1/;
12 13
13/ { 14/ {
14 model = "MPC8548CDS"; 15 model = "MPC8548CDS";
@@ -36,11 +37,11 @@
36 37
37 PowerPC,8548@0 { 38 PowerPC,8548@0 {
38 device_type = "cpu"; 39 device_type = "cpu";
39 reg = <0>; 40 reg = <0x0>;
40 d-cache-line-size = <20>; // 32 bytes 41 d-cache-line-size = <32>; // 32 bytes
41 i-cache-line-size = <20>; // 32 bytes 42 i-cache-line-size = <32>; // 32 bytes
42 d-cache-size = <8000>; // L1, 32K 43 d-cache-size = <0x8000>; // L1, 32K
43 i-cache-size = <8000>; // L1, 32K 44 i-cache-size = <0x8000>; // L1, 32K
44 timebase-frequency = <0>; // 33 MHz, from uboot 45 timebase-frequency = <0>; // 33 MHz, from uboot
45 bus-frequency = <0>; // 166 MHz 46 bus-frequency = <0>; // 166 MHz
46 clock-frequency = <0>; // 825 MHz, from uboot 47 clock-frequency = <0>; // 825 MHz, from uboot
@@ -49,31 +50,31 @@
49 50
50 memory { 51 memory {
51 device_type = "memory"; 52 device_type = "memory";
52 reg = <00000000 08000000>; // 128M at 0x0 53 reg = <0x0 0x8000000>; // 128M at 0x0
53 }; 54 };
54 55
55 soc8548@e0000000 { 56 soc8548@e0000000 {
56 #address-cells = <1>; 57 #address-cells = <1>;
57 #size-cells = <1>; 58 #size-cells = <1>;
58 device_type = "soc"; 59 device_type = "soc";
59 ranges = <00000000 e0000000 00100000>; 60 ranges = <0x0 0xe0000000 0x100000>;
60 reg = <e0000000 00001000>; // CCSRBAR 61 reg = <0xe0000000 0x1000>; // CCSRBAR
61 bus-frequency = <0>; 62 bus-frequency = <0>;
62 63
63 memory-controller@2000 { 64 memory-controller@2000 {
64 compatible = "fsl,8548-memory-controller"; 65 compatible = "fsl,8548-memory-controller";
65 reg = <2000 1000>; 66 reg = <0x2000 0x1000>;
66 interrupt-parent = <&mpic>; 67 interrupt-parent = <&mpic>;
67 interrupts = <12 2>; 68 interrupts = <18 2>;
68 }; 69 };
69 70
70 l2-cache-controller@20000 { 71 l2-cache-controller@20000 {
71 compatible = "fsl,8548-l2-cache-controller"; 72 compatible = "fsl,8548-l2-cache-controller";
72 reg = <20000 1000>; 73 reg = <0x20000 0x1000>;
73 cache-line-size = <20>; // 32 bytes 74 cache-line-size = <32>; // 32 bytes
74 cache-size = <80000>; // L2, 512K 75 cache-size = <0x80000>; // L2, 512K
75 interrupt-parent = <&mpic>; 76 interrupt-parent = <&mpic>;
76 interrupts = <10 2>; 77 interrupts = <16 2>;
77 }; 78 };
78 79
79 i2c@3000 { 80 i2c@3000 {
@@ -81,8 +82,8 @@
81 #size-cells = <0>; 82 #size-cells = <0>;
82 cell-index = <0>; 83 cell-index = <0>;
83 compatible = "fsl-i2c"; 84 compatible = "fsl-i2c";
84 reg = <3000 100>; 85 reg = <0x3000 0x100>;
85 interrupts = <2b 2>; 86 interrupts = <43 2>;
86 interrupt-parent = <&mpic>; 87 interrupt-parent = <&mpic>;
87 dfsrr; 88 dfsrr;
88 }; 89 };
@@ -92,8 +93,8 @@
92 #size-cells = <0>; 93 #size-cells = <0>;
93 cell-index = <1>; 94 cell-index = <1>;
94 compatible = "fsl-i2c"; 95 compatible = "fsl-i2c";
95 reg = <3100 100>; 96 reg = <0x3100 0x100>;
96 interrupts = <2b 2>; 97 interrupts = <43 2>;
97 interrupt-parent = <&mpic>; 98 interrupt-parent = <&mpic>;
98 dfsrr; 99 dfsrr;
99 }; 100 };
@@ -102,30 +103,30 @@
102 #address-cells = <1>; 103 #address-cells = <1>;
103 #size-cells = <0>; 104 #size-cells = <0>;
104 compatible = "fsl,gianfar-mdio"; 105 compatible = "fsl,gianfar-mdio";
105 reg = <24520 20>; 106 reg = <0x24520 0x20>;
106 107
107 phy0: ethernet-phy@0 { 108 phy0: ethernet-phy@0 {
108 interrupt-parent = <&mpic>; 109 interrupt-parent = <&mpic>;
109 interrupts = <5 1>; 110 interrupts = <5 1>;
110 reg = <0>; 111 reg = <0x0>;
111 device_type = "ethernet-phy"; 112 device_type = "ethernet-phy";
112 }; 113 };
113 phy1: ethernet-phy@1 { 114 phy1: ethernet-phy@1 {
114 interrupt-parent = <&mpic>; 115 interrupt-parent = <&mpic>;
115 interrupts = <5 1>; 116 interrupts = <5 1>;
116 reg = <1>; 117 reg = <0x1>;
117 device_type = "ethernet-phy"; 118 device_type = "ethernet-phy";
118 }; 119 };
119 phy2: ethernet-phy@2 { 120 phy2: ethernet-phy@2 {
120 interrupt-parent = <&mpic>; 121 interrupt-parent = <&mpic>;
121 interrupts = <5 1>; 122 interrupts = <5 1>;
122 reg = <2>; 123 reg = <0x2>;
123 device_type = "ethernet-phy"; 124 device_type = "ethernet-phy";
124 }; 125 };
125 phy3: ethernet-phy@3 { 126 phy3: ethernet-phy@3 {
126 interrupt-parent = <&mpic>; 127 interrupt-parent = <&mpic>;
127 interrupts = <5 1>; 128 interrupts = <5 1>;
128 reg = <3>; 129 reg = <0x3>;
129 device_type = "ethernet-phy"; 130 device_type = "ethernet-phy";
130 }; 131 };
131 }; 132 };
@@ -135,9 +136,9 @@
135 device_type = "network"; 136 device_type = "network";
136 model = "eTSEC"; 137 model = "eTSEC";
137 compatible = "gianfar"; 138 compatible = "gianfar";
138 reg = <24000 1000>; 139 reg = <0x24000 0x1000>;
139 local-mac-address = [ 00 00 00 00 00 00 ]; 140 local-mac-address = [ 00 00 00 00 00 00 ];
140 interrupts = <1d 2 1e 2 22 2>; 141 interrupts = <29 2 30 2 34 2>;
141 interrupt-parent = <&mpic>; 142 interrupt-parent = <&mpic>;
142 phy-handle = <&phy0>; 143 phy-handle = <&phy0>;
143 }; 144 };
@@ -147,9 +148,9 @@
147 device_type = "network"; 148 device_type = "network";
148 model = "eTSEC"; 149 model = "eTSEC";
149 compatible = "gianfar"; 150 compatible = "gianfar";
150 reg = <25000 1000>; 151 reg = <0x25000 0x1000>;
151 local-mac-address = [ 00 00 00 00 00 00 ]; 152 local-mac-address = [ 00 00 00 00 00 00 ];
152 interrupts = <23 2 24 2 28 2>; 153 interrupts = <35 2 36 2 40 2>;
153 interrupt-parent = <&mpic>; 154 interrupt-parent = <&mpic>;
154 phy-handle = <&phy1>; 155 phy-handle = <&phy1>;
155 }; 156 };
@@ -160,9 +161,9 @@
160 device_type = "network"; 161 device_type = "network";
161 model = "eTSEC"; 162 model = "eTSEC";
162 compatible = "gianfar"; 163 compatible = "gianfar";
163 reg = <26000 1000>; 164 reg = <0x26000 0x1000>;
164 local-mac-address = [ 00 00 00 00 00 00 ]; 165 local-mac-address = [ 00 00 00 00 00 00 ];
165 interrupts = <1f 2 20 2 21 2>; 166 interrupts = <31 2 32 2 33 2>;
166 interrupt-parent = <&mpic>; 167 interrupt-parent = <&mpic>;
167 phy-handle = <&phy2>; 168 phy-handle = <&phy2>;
168 }; 169 };
@@ -172,9 +173,9 @@
172 device_type = "network"; 173 device_type = "network";
173 model = "eTSEC"; 174 model = "eTSEC";
174 compatible = "gianfar"; 175 compatible = "gianfar";
175 reg = <27000 1000>; 176 reg = <0x27000 0x1000>;
176 local-mac-address = [ 00 00 00 00 00 00 ]; 177 local-mac-address = [ 00 00 00 00 00 00 ];
177 interrupts = <25 2 26 2 27 2>; 178 interrupts = <37 2 38 2 39 2>;
178 interrupt-parent = <&mpic>; 179 interrupt-parent = <&mpic>;
179 phy-handle = <&phy3>; 180 phy-handle = <&phy3>;
180 }; 181 };
@@ -184,9 +185,9 @@
184 cell-index = <0>; 185 cell-index = <0>;
185 device_type = "serial"; 186 device_type = "serial";
186 compatible = "ns16550"; 187 compatible = "ns16550";
187 reg = <4500 100>; // reg base, size 188 reg = <0x4500 0x100>; // reg base, size
188 clock-frequency = <0>; // should we fill in in uboot? 189 clock-frequency = <0>; // should we fill in in uboot?
189 interrupts = <2a 2>; 190 interrupts = <42 2>;
190 interrupt-parent = <&mpic>; 191 interrupt-parent = <&mpic>;
191 }; 192 };
192 193
@@ -194,15 +195,15 @@
194 cell-index = <1>; 195 cell-index = <1>;
195 device_type = "serial"; 196 device_type = "serial";
196 compatible = "ns16550"; 197 compatible = "ns16550";
197 reg = <4600 100>; // reg base, size 198 reg = <0x4600 0x100>; // reg base, size
198 clock-frequency = <0>; // should we fill in in uboot? 199 clock-frequency = <0>; // should we fill in in uboot?
199 interrupts = <2a 2>; 200 interrupts = <42 2>;
200 interrupt-parent = <&mpic>; 201 interrupt-parent = <&mpic>;
201 }; 202 };
202 203
203 global-utilities@e0000 { //global utilities reg 204 global-utilities@e0000 { //global utilities reg
204 compatible = "fsl,mpc8548-guts"; 205 compatible = "fsl,mpc8548-guts";
205 reg = <e0000 1000>; 206 reg = <0xe0000 0x1000>;
206 fsl,has-rstcr; 207 fsl,has-rstcr;
207 }; 208 };
208 209
@@ -211,7 +212,7 @@
211 interrupt-controller; 212 interrupt-controller;
212 #address-cells = <0>; 213 #address-cells = <0>;
213 #interrupt-cells = <2>; 214 #interrupt-cells = <2>;
214 reg = <40000 40000>; 215 reg = <0x40000 0x40000>;
215 compatible = "chrp,open-pic"; 216 compatible = "chrp,open-pic";
216 device_type = "open-pic"; 217 device_type = "open-pic";
217 big-endian; 218 big-endian;
@@ -220,139 +221,139 @@
220 221
221 pci0: pci@e0008000 { 222 pci0: pci@e0008000 {
222 cell-index = <0>; 223 cell-index = <0>;
223 interrupt-map-mask = <f800 0 0 7>; 224 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
224 interrupt-map = < 225 interrupt-map = <
225 /* IDSEL 0x4 (PCIX Slot 2) */ 226 /* IDSEL 0x4 (PCIX Slot 2) */
226 02000 0 0 1 &mpic 0 1 227 0x2000 0x0 0x0 0x1 &mpic 0x0 0x1
227 02000 0 0 2 &mpic 1 1 228 0x2000 0x0 0x0 0x2 &mpic 0x1 0x1
228 02000 0 0 3 &mpic 2 1 229 0x2000 0x0 0x0 0x3 &mpic 0x2 0x1
229 02000 0 0 4 &mpic 3 1 230 0x2000 0x0 0x0 0x4 &mpic 0x3 0x1
230 231
231 /* IDSEL 0x5 (PCIX Slot 3) */ 232 /* IDSEL 0x5 (PCIX Slot 3) */
232 02800 0 0 1 &mpic 1 1 233 0x2800 0x0 0x0 0x1 &mpic 0x1 0x1
233 02800 0 0 2 &mpic 2 1 234 0x2800 0x0 0x0 0x2 &mpic 0x2 0x1
234 02800 0 0 3 &mpic 3 1 235 0x2800 0x0 0x0 0x3 &mpic 0x3 0x1
235 02800 0 0 4 &mpic 0 1 236 0x2800 0x0 0x0 0x4 &mpic 0x0 0x1
236 237
237 /* IDSEL 0x6 (PCIX Slot 4) */ 238 /* IDSEL 0x6 (PCIX Slot 4) */
238 03000 0 0 1 &mpic 2 1 239 0x3000 0x0 0x0 0x1 &mpic 0x2 0x1
239 03000 0 0 2 &mpic 3 1 240 0x3000 0x0 0x0 0x2 &mpic 0x3 0x1
240 03000 0 0 3 &mpic 0 1 241 0x3000 0x0 0x0 0x3 &mpic 0x0 0x1
241 03000 0 0 4 &mpic 1 1 242 0x3000 0x0 0x0 0x4 &mpic 0x1 0x1
242 243
243 /* IDSEL 0x8 (PCIX Slot 5) */ 244 /* IDSEL 0x8 (PCIX Slot 5) */
244 04000 0 0 1 &mpic 0 1 245 0x4000 0x0 0x0 0x1 &mpic 0x0 0x1
245 04000 0 0 2 &mpic 1 1 246 0x4000 0x0 0x0 0x2 &mpic 0x1 0x1
246 04000 0 0 3 &mpic 2 1 247 0x4000 0x0 0x0 0x3 &mpic 0x2 0x1
247 04000 0 0 4 &mpic 3 1 248 0x4000 0x0 0x0 0x4 &mpic 0x3 0x1
248 249
249 /* IDSEL 0xC (Tsi310 bridge) */ 250 /* IDSEL 0xC (Tsi310 bridge) */
250 06000 0 0 1 &mpic 0 1 251 0x6000 0x0 0x0 0x1 &mpic 0x0 0x1
251 06000 0 0 2 &mpic 1 1 252 0x6000 0x0 0x0 0x2 &mpic 0x1 0x1
252 06000 0 0 3 &mpic 2 1 253 0x6000 0x0 0x0 0x3 &mpic 0x2 0x1
253 06000 0 0 4 &mpic 3 1 254 0x6000 0x0 0x0 0x4 &mpic 0x3 0x1
254 255
255 /* IDSEL 0x14 (Slot 2) */ 256 /* IDSEL 0x14 (Slot 2) */
256 0a000 0 0 1 &mpic 0 1 257 0xa000 0x0 0x0 0x1 &mpic 0x0 0x1
257 0a000 0 0 2 &mpic 1 1 258 0xa000 0x0 0x0 0x2 &mpic 0x1 0x1
258 0a000 0 0 3 &mpic 2 1 259 0xa000 0x0 0x0 0x3 &mpic 0x2 0x1
259 0a000 0 0 4 &mpic 3 1 260 0xa000 0x0 0x0 0x4 &mpic 0x3 0x1
260 261
261 /* IDSEL 0x15 (Slot 3) */ 262 /* IDSEL 0x15 (Slot 3) */
262 0a800 0 0 1 &mpic 1 1 263 0xa800 0x0 0x0 0x1 &mpic 0x1 0x1
263 0a800 0 0 2 &mpic 2 1 264 0xa800 0x0 0x0 0x2 &mpic 0x2 0x1
264 0a800 0 0 3 &mpic 3 1 265 0xa800 0x0 0x0 0x3 &mpic 0x3 0x1
265 0a800 0 0 4 &mpic 0 1 266 0xa800 0x0 0x0 0x4 &mpic 0x0 0x1
266 267
267 /* IDSEL 0x16 (Slot 4) */ 268 /* IDSEL 0x16 (Slot 4) */
268 0b000 0 0 1 &mpic 2 1 269 0xb000 0x0 0x0 0x1 &mpic 0x2 0x1
269 0b000 0 0 2 &mpic 3 1 270 0xb000 0x0 0x0 0x2 &mpic 0x3 0x1
270 0b000 0 0 3 &mpic 0 1 271 0xb000 0x0 0x0 0x3 &mpic 0x0 0x1
271 0b000 0 0 4 &mpic 1 1 272 0xb000 0x0 0x0 0x4 &mpic 0x1 0x1
272 273
273 /* IDSEL 0x18 (Slot 5) */ 274 /* IDSEL 0x18 (Slot 5) */
274 0c000 0 0 1 &mpic 0 1 275 0xc000 0x0 0x0 0x1 &mpic 0x0 0x1
275 0c000 0 0 2 &mpic 1 1 276 0xc000 0x0 0x0 0x2 &mpic 0x1 0x1
276 0c000 0 0 3 &mpic 2 1 277 0xc000 0x0 0x0 0x3 &mpic 0x2 0x1
277 0c000 0 0 4 &mpic 3 1 278 0xc000 0x0 0x0 0x4 &mpic 0x3 0x1
278 279
279 /* IDSEL 0x1C (Tsi310 bridge PCI primary) */ 280 /* IDSEL 0x1C (Tsi310 bridge PCI primary) */
280 0E000 0 0 1 &mpic 0 1 281 0xe000 0x0 0x0 0x1 &mpic 0x0 0x1
281 0E000 0 0 2 &mpic 1 1 282 0xe000 0x0 0x0 0x2 &mpic 0x1 0x1
282 0E000 0 0 3 &mpic 2 1 283 0xe000 0x0 0x0 0x3 &mpic 0x2 0x1
283 0E000 0 0 4 &mpic 3 1>; 284 0xe000 0x0 0x0 0x4 &mpic 0x3 0x1>;
284 285
285 interrupt-parent = <&mpic>; 286 interrupt-parent = <&mpic>;
286 interrupts = <18 2>; 287 interrupts = <24 2>;
287 bus-range = <0 0>; 288 bus-range = <0 0>;
288 ranges = <02000000 0 80000000 80000000 0 10000000 289 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x10000000
289 01000000 0 00000000 e2000000 0 00800000>; 290 0x1000000 0x0 0x0 0xe2000000 0x0 0x800000>;
290 clock-frequency = <3f940aa>; 291 clock-frequency = <66666666>;
291 #interrupt-cells = <1>; 292 #interrupt-cells = <1>;
292 #size-cells = <2>; 293 #size-cells = <2>;
293 #address-cells = <3>; 294 #address-cells = <3>;
294 reg = <e0008000 1000>; 295 reg = <0xe0008000 0x1000>;
295 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; 296 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
296 device_type = "pci"; 297 device_type = "pci";
297 298
298 pci_bridge@1c { 299 pci_bridge@1c {
299 interrupt-map-mask = <f800 0 0 7>; 300 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
300 interrupt-map = < 301 interrupt-map = <
301 302
302 /* IDSEL 0x00 (PrPMC Site) */ 303 /* IDSEL 0x00 (PrPMC Site) */
303 0000 0 0 1 &mpic 0 1 304 0000 0x0 0x0 0x1 &mpic 0x0 0x1
304 0000 0 0 2 &mpic 1 1 305 0000 0x0 0x0 0x2 &mpic 0x1 0x1
305 0000 0 0 3 &mpic 2 1 306 0000 0x0 0x0 0x3 &mpic 0x2 0x1
306 0000 0 0 4 &mpic 3 1 307 0000 0x0 0x0 0x4 &mpic 0x3 0x1
307 308
308 /* IDSEL 0x04 (VIA chip) */ 309 /* IDSEL 0x04 (VIA chip) */
309 2000 0 0 1 &mpic 0 1 310 0x2000 0x0 0x0 0x1 &mpic 0x0 0x1
310 2000 0 0 2 &mpic 1 1 311 0x2000 0x0 0x0 0x2 &mpic 0x1 0x1
311 2000 0 0 3 &mpic 2 1 312 0x2000 0x0 0x0 0x3 &mpic 0x2 0x1
312 2000 0 0 4 &mpic 3 1 313 0x2000 0x0 0x0 0x4 &mpic 0x3 0x1
313 314
314 /* IDSEL 0x05 (8139) */ 315 /* IDSEL 0x05 (8139) */
315 2800 0 0 1 &mpic 1 1 316 0x2800 0x0 0x0 0x1 &mpic 0x1 0x1
316 317
317 /* IDSEL 0x06 (Slot 6) */ 318 /* IDSEL 0x06 (Slot 6) */
318 3000 0 0 1 &mpic 2 1 319 0x3000 0x0 0x0 0x1 &mpic 0x2 0x1
319 3000 0 0 2 &mpic 3 1 320 0x3000 0x0 0x0 0x2 &mpic 0x3 0x1
320 3000 0 0 3 &mpic 0 1 321 0x3000 0x0 0x0 0x3 &mpic 0x0 0x1
321 3000 0 0 4 &mpic 1 1 322 0x3000 0x0 0x0 0x4 &mpic 0x1 0x1
322 323
323 /* IDESL 0x07 (Slot 7) */ 324 /* IDESL 0x07 (Slot 7) */
324 3800 0 0 1 &mpic 3 1 325 0x3800 0x0 0x0 0x1 &mpic 0x3 0x1
325 3800 0 0 2 &mpic 0 1 326 0x3800 0x0 0x0 0x2 &mpic 0x0 0x1
326 3800 0 0 3 &mpic 1 1 327 0x3800 0x0 0x0 0x3 &mpic 0x1 0x1
327 3800 0 0 4 &mpic 2 1>; 328 0x3800 0x0 0x0 0x4 &mpic 0x2 0x1>;
328 329
329 reg = <e000 0 0 0 0>; 330 reg = <0xe000 0x0 0x0 0x0 0x0>;
330 #interrupt-cells = <1>; 331 #interrupt-cells = <1>;
331 #size-cells = <2>; 332 #size-cells = <2>;
332 #address-cells = <3>; 333 #address-cells = <3>;
333 ranges = <02000000 0 80000000 334 ranges = <0x2000000 0x0 0x80000000
334 02000000 0 80000000 335 0x2000000 0x0 0x80000000
335 0 20000000 336 0x0 0x20000000
336 01000000 0 00000000 337 0x1000000 0x0 0x0
337 01000000 0 00000000 338 0x1000000 0x0 0x0
338 0 00080000>; 339 0x0 0x80000>;
339 clock-frequency = <1fca055>; 340 clock-frequency = <33333333>;
340 341
341 isa@4 { 342 isa@4 {
342 device_type = "isa"; 343 device_type = "isa";
343 #interrupt-cells = <2>; 344 #interrupt-cells = <2>;
344 #size-cells = <1>; 345 #size-cells = <1>;
345 #address-cells = <2>; 346 #address-cells = <2>;
346 reg = <2000 0 0 0 0>; 347 reg = <0x2000 0x0 0x0 0x0 0x0>;
347 ranges = <1 0 01000000 0 0 00001000>; 348 ranges = <0x1 0x0 0x1000000 0x0 0x0 0x1000>;
348 interrupt-parent = <&i8259>; 349 interrupt-parent = <&i8259>;
349 350
350 i8259: interrupt-controller@20 { 351 i8259: interrupt-controller@20 {
351 interrupt-controller; 352 interrupt-controller;
352 device_type = "interrupt-controller"; 353 device_type = "interrupt-controller";
353 reg = <1 20 2 354 reg = <0x1 0x20 0x2
354 1 a0 2 355 0x1 0xa0 0x2
355 1 4d0 2>; 356 0x1 0x4d0 0x2>;
356 #address-cells = <0>; 357 #address-cells = <0>;
357 #interrupt-cells = <2>; 358 #interrupt-cells = <2>;
358 compatible = "chrp,iic"; 359 compatible = "chrp,iic";
@@ -362,7 +363,7 @@
362 363
363 rtc@70 { 364 rtc@70 {
364 compatible = "pnpPNP,b00"; 365 compatible = "pnpPNP,b00";
365 reg = <1 70 2>; 366 reg = <0x1 0x70 0x2>;
366 }; 367 };
367 }; 368 };
368 }; 369 };
@@ -370,64 +371,64 @@
370 371
371 pci1: pci@e0009000 { 372 pci1: pci@e0009000 {
372 cell-index = <1>; 373 cell-index = <1>;
373 interrupt-map-mask = <f800 0 0 7>; 374 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
374 interrupt-map = < 375 interrupt-map = <
375 376
376 /* IDSEL 0x15 */ 377 /* IDSEL 0x15 */
377 a800 0 0 1 &mpic b 1 378 0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
378 a800 0 0 2 &mpic 1 1 379 0xa800 0x0 0x0 0x2 &mpic 0x1 0x1
379 a800 0 0 3 &mpic 2 1 380 0xa800 0x0 0x0 0x3 &mpic 0x2 0x1
380 a800 0 0 4 &mpic 3 1>; 381 0xa800 0x0 0x0 0x4 &mpic 0x3 0x1>;
381 382
382 interrupt-parent = <&mpic>; 383 interrupt-parent = <&mpic>;
383 interrupts = <19 2>; 384 interrupts = <25 2>;
384 bus-range = <0 0>; 385 bus-range = <0 0>;
385 ranges = <02000000 0 90000000 90000000 0 10000000 386 ranges = <0x2000000 0x0 0x90000000 0x90000000 0x0 0x10000000
386 01000000 0 00000000 e2800000 0 00800000>; 387 0x1000000 0x0 0x0 0xe2800000 0x0 0x800000>;
387 clock-frequency = <3f940aa>; 388 clock-frequency = <66666666>;
388 #interrupt-cells = <1>; 389 #interrupt-cells = <1>;
389 #size-cells = <2>; 390 #size-cells = <2>;
390 #address-cells = <3>; 391 #address-cells = <3>;
391 reg = <e0009000 1000>; 392 reg = <0xe0009000 0x1000>;
392 compatible = "fsl,mpc8540-pci"; 393 compatible = "fsl,mpc8540-pci";
393 device_type = "pci"; 394 device_type = "pci";
394 }; 395 };
395 396
396 pci2: pcie@e000a000 { 397 pci2: pcie@e000a000 {
397 cell-index = <2>; 398 cell-index = <2>;
398 interrupt-map-mask = <f800 0 0 7>; 399 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
399 interrupt-map = < 400 interrupt-map = <
400 401
401 /* IDSEL 0x0 (PEX) */ 402 /* IDSEL 0x0 (PEX) */
402 00000 0 0 1 &mpic 0 1 403 00000 0x0 0x0 0x1 &mpic 0x0 0x1
403 00000 0 0 2 &mpic 1 1 404 00000 0x0 0x0 0x2 &mpic 0x1 0x1
404 00000 0 0 3 &mpic 2 1 405 00000 0x0 0x0 0x3 &mpic 0x2 0x1
405 00000 0 0 4 &mpic 3 1>; 406 00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
406 407
407 interrupt-parent = <&mpic>; 408 interrupt-parent = <&mpic>;
408 interrupts = <1a 2>; 409 interrupts = <26 2>;
409 bus-range = <0 ff>; 410 bus-range = <0 255>;
410 ranges = <02000000 0 a0000000 a0000000 0 20000000 411 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
411 01000000 0 00000000 e3000000 0 08000000>; 412 0x1000000 0x0 0x0 0xe3000000 0x0 0x8000000>;
412 clock-frequency = <1fca055>; 413 clock-frequency = <33333333>;
413 #interrupt-cells = <1>; 414 #interrupt-cells = <1>;
414 #size-cells = <2>; 415 #size-cells = <2>;
415 #address-cells = <3>; 416 #address-cells = <3>;
416 reg = <e000a000 1000>; 417 reg = <0xe000a000 0x1000>;
417 compatible = "fsl,mpc8548-pcie"; 418 compatible = "fsl,mpc8548-pcie";
418 device_type = "pci"; 419 device_type = "pci";
419 pcie@0 { 420 pcie@0 {
420 reg = <0 0 0 0 0>; 421 reg = <0x0 0x0 0x0 0x0 0x0>;
421 #size-cells = <2>; 422 #size-cells = <2>;
422 #address-cells = <3>; 423 #address-cells = <3>;
423 device_type = "pci"; 424 device_type = "pci";
424 ranges = <02000000 0 a0000000 425 ranges = <0x2000000 0x0 0xa0000000
425 02000000 0 a0000000 426 0x2000000 0x0 0xa0000000
426 0 20000000 427 0x0 0x20000000
427 428
428 01000000 0 00000000 429 0x1000000 0x0 0x0
429 01000000 0 00000000 430 0x1000000 0x0 0x0
430 0 08000000>; 431 0x0 0x8000000>;
431 }; 432 };
432 }; 433 };
433}; 434};
diff --git a/arch/powerpc/boot/dts/mpc8555cds.dts b/arch/powerpc/boot/dts/mpc8555cds.dts
index 4538f3c38862..b025c566c10d 100644
--- a/arch/powerpc/boot/dts/mpc8555cds.dts
+++ b/arch/powerpc/boot/dts/mpc8555cds.dts
@@ -1,7 +1,7 @@
1/* 1/*
2 * MPC8555 CDS Device Tree Source 2 * MPC8555 CDS Device Tree Source
3 * 3 *
4 * Copyright 2006 Freescale Semiconductor Inc. 4 * Copyright 2006, 2008 Freescale Semiconductor Inc.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the 7 * under the terms of the GNU General Public License as published by the
@@ -9,6 +9,7 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/dts-v1/;
12 13
13/ { 14/ {
14 model = "MPC8555CDS"; 15 model = "MPC8555CDS";
@@ -31,11 +32,11 @@
31 32
32 PowerPC,8555@0 { 33 PowerPC,8555@0 {
33 device_type = "cpu"; 34 device_type = "cpu";
34 reg = <0>; 35 reg = <0x0>;
35 d-cache-line-size = <20>; // 32 bytes 36 d-cache-line-size = <32>; // 32 bytes
36 i-cache-line-size = <20>; // 32 bytes 37 i-cache-line-size = <32>; // 32 bytes
37 d-cache-size = <8000>; // L1, 32K 38 d-cache-size = <0x8000>; // L1, 32K
38 i-cache-size = <8000>; // L1, 32K 39 i-cache-size = <0x8000>; // L1, 32K
39 timebase-frequency = <0>; // 33 MHz, from uboot 40 timebase-frequency = <0>; // 33 MHz, from uboot
40 bus-frequency = <0>; // 166 MHz 41 bus-frequency = <0>; // 166 MHz
41 clock-frequency = <0>; // 825 MHz, from uboot 42 clock-frequency = <0>; // 825 MHz, from uboot
@@ -44,31 +45,31 @@
44 45
45 memory { 46 memory {
46 device_type = "memory"; 47 device_type = "memory";
47 reg = <00000000 08000000>; // 128M at 0x0 48 reg = <0x0 0x8000000>; // 128M at 0x0
48 }; 49 };
49 50
50 soc8555@e0000000 { 51 soc8555@e0000000 {
51 #address-cells = <1>; 52 #address-cells = <1>;
52 #size-cells = <1>; 53 #size-cells = <1>;
53 device_type = "soc"; 54 device_type = "soc";
54 ranges = <0 e0000000 00100000>; 55 ranges = <0x0 0xe0000000 0x100000>;
55 reg = <e0000000 00001000>; // CCSRBAR 1M 56 reg = <0xe0000000 0x1000>; // CCSRBAR 1M
56 bus-frequency = <0>; 57 bus-frequency = <0>;
57 58
58 memory-controller@2000 { 59 memory-controller@2000 {
59 compatible = "fsl,8555-memory-controller"; 60 compatible = "fsl,8555-memory-controller";
60 reg = <2000 1000>; 61 reg = <0x2000 0x1000>;
61 interrupt-parent = <&mpic>; 62 interrupt-parent = <&mpic>;
62 interrupts = <12 2>; 63 interrupts = <18 2>;
63 }; 64 };
64 65
65 l2-cache-controller@20000 { 66 l2-cache-controller@20000 {
66 compatible = "fsl,8555-l2-cache-controller"; 67 compatible = "fsl,8555-l2-cache-controller";
67 reg = <20000 1000>; 68 reg = <0x20000 0x1000>;
68 cache-line-size = <20>; // 32 bytes 69 cache-line-size = <32>; // 32 bytes
69 cache-size = <40000>; // L2, 256K 70 cache-size = <0x40000>; // L2, 256K
70 interrupt-parent = <&mpic>; 71 interrupt-parent = <&mpic>;
71 interrupts = <10 2>; 72 interrupts = <16 2>;
72 }; 73 };
73 74
74 i2c@3000 { 75 i2c@3000 {
@@ -76,8 +77,8 @@
76 #size-cells = <0>; 77 #size-cells = <0>;
77 cell-index = <0>; 78 cell-index = <0>;
78 compatible = "fsl-i2c"; 79 compatible = "fsl-i2c";
79 reg = <3000 100>; 80 reg = <0x3000 0x100>;
80 interrupts = <2b 2>; 81 interrupts = <43 2>;
81 interrupt-parent = <&mpic>; 82 interrupt-parent = <&mpic>;
82 dfsrr; 83 dfsrr;
83 }; 84 };
@@ -86,18 +87,18 @@
86 #address-cells = <1>; 87 #address-cells = <1>;
87 #size-cells = <0>; 88 #size-cells = <0>;
88 compatible = "fsl,gianfar-mdio"; 89 compatible = "fsl,gianfar-mdio";
89 reg = <24520 20>; 90 reg = <0x24520 0x20>;
90 91
91 phy0: ethernet-phy@0 { 92 phy0: ethernet-phy@0 {
92 interrupt-parent = <&mpic>; 93 interrupt-parent = <&mpic>;
93 interrupts = <5 1>; 94 interrupts = <5 1>;
94 reg = <0>; 95 reg = <0x0>;
95 device_type = "ethernet-phy"; 96 device_type = "ethernet-phy";
96 }; 97 };
97 phy1: ethernet-phy@1 { 98 phy1: ethernet-phy@1 {
98 interrupt-parent = <&mpic>; 99 interrupt-parent = <&mpic>;
99 interrupts = <5 1>; 100 interrupts = <5 1>;
100 reg = <1>; 101 reg = <0x1>;
101 device_type = "ethernet-phy"; 102 device_type = "ethernet-phy";
102 }; 103 };
103 }; 104 };
@@ -107,9 +108,9 @@
107 device_type = "network"; 108 device_type = "network";
108 model = "TSEC"; 109 model = "TSEC";
109 compatible = "gianfar"; 110 compatible = "gianfar";
110 reg = <24000 1000>; 111 reg = <0x24000 0x1000>;
111 local-mac-address = [ 00 00 00 00 00 00 ]; 112 local-mac-address = [ 00 00 00 00 00 00 ];
112 interrupts = <1d 2 1e 2 22 2>; 113 interrupts = <29 2 30 2 34 2>;
113 interrupt-parent = <&mpic>; 114 interrupt-parent = <&mpic>;
114 phy-handle = <&phy0>; 115 phy-handle = <&phy0>;
115 }; 116 };
@@ -119,9 +120,9 @@
119 device_type = "network"; 120 device_type = "network";
120 model = "TSEC"; 121 model = "TSEC";
121 compatible = "gianfar"; 122 compatible = "gianfar";
122 reg = <25000 1000>; 123 reg = <0x25000 0x1000>;
123 local-mac-address = [ 00 00 00 00 00 00 ]; 124 local-mac-address = [ 00 00 00 00 00 00 ];
124 interrupts = <23 2 24 2 28 2>; 125 interrupts = <35 2 36 2 40 2>;
125 interrupt-parent = <&mpic>; 126 interrupt-parent = <&mpic>;
126 phy-handle = <&phy1>; 127 phy-handle = <&phy1>;
127 }; 128 };
@@ -130,9 +131,9 @@
130 cell-index = <0>; 131 cell-index = <0>;
131 device_type = "serial"; 132 device_type = "serial";
132 compatible = "ns16550"; 133 compatible = "ns16550";
133 reg = <4500 100>; // reg base, size 134 reg = <0x4500 0x100>; // reg base, size
134 clock-frequency = <0>; // should we fill in in uboot? 135 clock-frequency = <0>; // should we fill in in uboot?
135 interrupts = <2a 2>; 136 interrupts = <42 2>;
136 interrupt-parent = <&mpic>; 137 interrupt-parent = <&mpic>;
137 }; 138 };
138 139
@@ -140,9 +141,9 @@
140 cell-index = <1>; 141 cell-index = <1>;
141 device_type = "serial"; 142 device_type = "serial";
142 compatible = "ns16550"; 143 compatible = "ns16550";
143 reg = <4600 100>; // reg base, size 144 reg = <0x4600 0x100>; // reg base, size
144 clock-frequency = <0>; // should we fill in in uboot? 145 clock-frequency = <0>; // should we fill in in uboot?
145 interrupts = <2a 2>; 146 interrupts = <42 2>;
146 interrupt-parent = <&mpic>; 147 interrupt-parent = <&mpic>;
147 }; 148 };
148 149
@@ -151,7 +152,7 @@
151 interrupt-controller; 152 interrupt-controller;
152 #address-cells = <0>; 153 #address-cells = <0>;
153 #interrupt-cells = <2>; 154 #interrupt-cells = <2>;
154 reg = <40000 40000>; 155 reg = <0x40000 0x40000>;
155 compatible = "chrp,open-pic"; 156 compatible = "chrp,open-pic";
156 device_type = "open-pic"; 157 device_type = "open-pic";
157 big-endian; 158 big-endian;
@@ -161,17 +162,17 @@
161 #address-cells = <1>; 162 #address-cells = <1>;
162 #size-cells = <1>; 163 #size-cells = <1>;
163 compatible = "fsl,mpc8555-cpm", "fsl,cpm2"; 164 compatible = "fsl,mpc8555-cpm", "fsl,cpm2";
164 reg = <919c0 30>; 165 reg = <0x919c0 0x30>;
165 ranges; 166 ranges;
166 167
167 muram@80000 { 168 muram@80000 {
168 #address-cells = <1>; 169 #address-cells = <1>;
169 #size-cells = <1>; 170 #size-cells = <1>;
170 ranges = <0 80000 10000>; 171 ranges = <0x0 0x80000 0x10000>;
171 172
172 data@0 { 173 data@0 {
173 compatible = "fsl,cpm-muram-data"; 174 compatible = "fsl,cpm-muram-data";
174 reg = <0 2000 9000 1000>; 175 reg = <0x0 0x2000 0x9000 0x1000>;
175 }; 176 };
176 }; 177 };
177 178
@@ -179,16 +180,16 @@
179 compatible = "fsl,mpc8555-brg", 180 compatible = "fsl,mpc8555-brg",
180 "fsl,cpm2-brg", 181 "fsl,cpm2-brg",
181 "fsl,cpm-brg"; 182 "fsl,cpm-brg";
182 reg = <919f0 10 915f0 10>; 183 reg = <0x919f0 0x10 0x915f0 0x10>;
183 }; 184 };
184 185
185 cpmpic: pic@90c00 { 186 cpmpic: pic@90c00 {
186 interrupt-controller; 187 interrupt-controller;
187 #address-cells = <0>; 188 #address-cells = <0>;
188 #interrupt-cells = <2>; 189 #interrupt-cells = <2>;
189 interrupts = <2e 2>; 190 interrupts = <46 2>;
190 interrupt-parent = <&mpic>; 191 interrupt-parent = <&mpic>;
191 reg = <90c00 80>; 192 reg = <0x90c00 0x80>;
192 compatible = "fsl,mpc8555-cpm-pic", "fsl,cpm2-pic"; 193 compatible = "fsl,mpc8555-cpm-pic", "fsl,cpm2-pic";
193 }; 194 };
194 }; 195 };
@@ -196,68 +197,68 @@
196 197
197 pci0: pci@e0008000 { 198 pci0: pci@e0008000 {
198 cell-index = <0>; 199 cell-index = <0>;
199 interrupt-map-mask = <1f800 0 0 7>; 200 interrupt-map-mask = <0x1f800 0x0 0x0 0x7>;
200 interrupt-map = < 201 interrupt-map = <
201 202
202 /* IDSEL 0x10 */ 203 /* IDSEL 0x10 */
203 08000 0 0 1 &mpic 0 1 204 0x8000 0x0 0x0 0x1 &mpic 0x0 0x1
204 08000 0 0 2 &mpic 1 1 205 0x8000 0x0 0x0 0x2 &mpic 0x1 0x1
205 08000 0 0 3 &mpic 2 1 206 0x8000 0x0 0x0 0x3 &mpic 0x2 0x1
206 08000 0 0 4 &mpic 3 1 207 0x8000 0x0 0x0 0x4 &mpic 0x3 0x1
207 208
208 /* IDSEL 0x11 */ 209 /* IDSEL 0x11 */
209 08800 0 0 1 &mpic 0 1 210 0x8800 0x0 0x0 0x1 &mpic 0x0 0x1
210 08800 0 0 2 &mpic 1 1 211 0x8800 0x0 0x0 0x2 &mpic 0x1 0x1
211 08800 0 0 3 &mpic 2 1 212 0x8800 0x0 0x0 0x3 &mpic 0x2 0x1
212 08800 0 0 4 &mpic 3 1 213 0x8800 0x0 0x0 0x4 &mpic 0x3 0x1
213 214
214 /* IDSEL 0x12 (Slot 1) */ 215 /* IDSEL 0x12 (Slot 1) */
215 09000 0 0 1 &mpic 0 1 216 0x9000 0x0 0x0 0x1 &mpic 0x0 0x1
216 09000 0 0 2 &mpic 1 1 217 0x9000 0x0 0x0 0x2 &mpic 0x1 0x1
217 09000 0 0 3 &mpic 2 1 218 0x9000 0x0 0x0 0x3 &mpic 0x2 0x1
218 09000 0 0 4 &mpic 3 1 219 0x9000 0x0 0x0 0x4 &mpic 0x3 0x1
219 220
220 /* IDSEL 0x13 (Slot 2) */ 221 /* IDSEL 0x13 (Slot 2) */
221 09800 0 0 1 &mpic 1 1 222 0x9800 0x0 0x0 0x1 &mpic 0x1 0x1
222 09800 0 0 2 &mpic 2 1 223 0x9800 0x0 0x0 0x2 &mpic 0x2 0x1
223 09800 0 0 3 &mpic 3 1 224 0x9800 0x0 0x0 0x3 &mpic 0x3 0x1
224 09800 0 0 4 &mpic 0 1 225 0x9800 0x0 0x0 0x4 &mpic 0x0 0x1
225 226
226 /* IDSEL 0x14 (Slot 3) */ 227 /* IDSEL 0x14 (Slot 3) */
227 0a000 0 0 1 &mpic 2 1 228 0xa000 0x0 0x0 0x1 &mpic 0x2 0x1
228 0a000 0 0 2 &mpic 3 1 229 0xa000 0x0 0x0 0x2 &mpic 0x3 0x1
229 0a000 0 0 3 &mpic 0 1 230 0xa000 0x0 0x0 0x3 &mpic 0x0 0x1
230 0a000 0 0 4 &mpic 1 1 231 0xa000 0x0 0x0 0x4 &mpic 0x1 0x1
231 232
232 /* IDSEL 0x15 (Slot 4) */ 233 /* IDSEL 0x15 (Slot 4) */
233 0a800 0 0 1 &mpic 3 1 234 0xa800 0x0 0x0 0x1 &mpic 0x3 0x1
234 0a800 0 0 2 &mpic 0 1 235 0xa800 0x0 0x0 0x2 &mpic 0x0 0x1
235 0a800 0 0 3 &mpic 1 1 236 0xa800 0x0 0x0 0x3 &mpic 0x1 0x1
236 0a800 0 0 4 &mpic 2 1 237 0xa800 0x0 0x0 0x4 &mpic 0x2 0x1
237 238
238 /* Bus 1 (Tundra Bridge) */ 239 /* Bus 1 (Tundra Bridge) */
239 /* IDSEL 0x12 (ISA bridge) */ 240 /* IDSEL 0x12 (ISA bridge) */
240 19000 0 0 1 &mpic 0 1 241 0x19000 0x0 0x0 0x1 &mpic 0x0 0x1
241 19000 0 0 2 &mpic 1 1 242 0x19000 0x0 0x0 0x2 &mpic 0x1 0x1
242 19000 0 0 3 &mpic 2 1 243 0x19000 0x0 0x0 0x3 &mpic 0x2 0x1
243 19000 0 0 4 &mpic 3 1>; 244 0x19000 0x0 0x0 0x4 &mpic 0x3 0x1>;
244 interrupt-parent = <&mpic>; 245 interrupt-parent = <&mpic>;
245 interrupts = <18 2>; 246 interrupts = <24 2>;
246 bus-range = <0 0>; 247 bus-range = <0 0>;
247 ranges = <02000000 0 80000000 80000000 0 20000000 248 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
248 01000000 0 00000000 e2000000 0 00100000>; 249 0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>;
249 clock-frequency = <3f940aa>; 250 clock-frequency = <66666666>;
250 #interrupt-cells = <1>; 251 #interrupt-cells = <1>;
251 #size-cells = <2>; 252 #size-cells = <2>;
252 #address-cells = <3>; 253 #address-cells = <3>;
253 reg = <e0008000 1000>; 254 reg = <0xe0008000 0x1000>;
254 compatible = "fsl,mpc8540-pci"; 255 compatible = "fsl,mpc8540-pci";
255 device_type = "pci"; 256 device_type = "pci";
256 257
257 i8259@19000 { 258 i8259@19000 {
258 interrupt-controller; 259 interrupt-controller;
259 device_type = "interrupt-controller"; 260 device_type = "interrupt-controller";
260 reg = <19000 0 0 0 1>; 261 reg = <0x19000 0x0 0x0 0x0 0x1>;
261 #address-cells = <0>; 262 #address-cells = <0>;
262 #interrupt-cells = <2>; 263 #interrupt-cells = <2>;
263 compatible = "chrp,iic"; 264 compatible = "chrp,iic";
@@ -268,24 +269,24 @@
268 269
269 pci1: pci@e0009000 { 270 pci1: pci@e0009000 {
270 cell-index = <1>; 271 cell-index = <1>;
271 interrupt-map-mask = <f800 0 0 7>; 272 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
272 interrupt-map = < 273 interrupt-map = <
273 274
274 /* IDSEL 0x15 */ 275 /* IDSEL 0x15 */
275 a800 0 0 1 &mpic b 1 276 0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
276 a800 0 0 2 &mpic b 1 277 0xa800 0x0 0x0 0x2 &mpic 0xb 0x1
277 a800 0 0 3 &mpic b 1 278 0xa800 0x0 0x0 0x3 &mpic 0xb 0x1
278 a800 0 0 4 &mpic b 1>; 279 0xa800 0x0 0x0 0x4 &mpic 0xb 0x1>;
279 interrupt-parent = <&mpic>; 280 interrupt-parent = <&mpic>;
280 interrupts = <19 2>; 281 interrupts = <25 2>;
281 bus-range = <0 0>; 282 bus-range = <0 0>;
282 ranges = <02000000 0 a0000000 a0000000 0 20000000 283 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
283 01000000 0 00000000 e3000000 0 00100000>; 284 0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>;
284 clock-frequency = <3f940aa>; 285 clock-frequency = <66666666>;
285 #interrupt-cells = <1>; 286 #interrupt-cells = <1>;
286 #size-cells = <2>; 287 #size-cells = <2>;
287 #address-cells = <3>; 288 #address-cells = <3>;
288 reg = <e0009000 1000>; 289 reg = <0xe0009000 0x1000>;
289 compatible = "fsl,mpc8540-pci"; 290 compatible = "fsl,mpc8540-pci";
290 device_type = "pci"; 291 device_type = "pci";
291 }; 292 };
diff --git a/arch/powerpc/boot/dts/mpc8560ads.dts b/arch/powerpc/boot/dts/mpc8560ads.dts
index 639ce8a709a6..0cc16ab305d1 100644
--- a/arch/powerpc/boot/dts/mpc8560ads.dts
+++ b/arch/powerpc/boot/dts/mpc8560ads.dts
@@ -1,7 +1,7 @@
1/* 1/*
2 * MPC8560 ADS Device Tree Source 2 * MPC8560 ADS Device Tree Source
3 * 3 *
4 * Copyright 2006 Freescale Semiconductor Inc. 4 * Copyright 2006, 2008 Freescale Semiconductor Inc.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the 7 * under the terms of the GNU General Public License as published by the
@@ -9,6 +9,7 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/dts-v1/;
12 13
13/ { 14/ {
14 model = "MPC8560ADS"; 15 model = "MPC8560ADS";
@@ -32,74 +33,74 @@
32 33
33 PowerPC,8560@0 { 34 PowerPC,8560@0 {
34 device_type = "cpu"; 35 device_type = "cpu";
35 reg = <0>; 36 reg = <0x0>;
36 d-cache-line-size = <20>; // 32 bytes 37 d-cache-line-size = <32>; // 32 bytes
37 i-cache-line-size = <20>; // 32 bytes 38 i-cache-line-size = <32>; // 32 bytes
38 d-cache-size = <8000>; // L1, 32K 39 d-cache-size = <0x8000>; // L1, 32K
39 i-cache-size = <8000>; // L1, 32K 40 i-cache-size = <0x8000>; // L1, 32K
40 timebase-frequency = <04ead9a0>; 41 timebase-frequency = <82500000>;
41 bus-frequency = <13ab6680>; 42 bus-frequency = <330000000>;
42 clock-frequency = <312c8040>; 43 clock-frequency = <825000000>;
43 }; 44 };
44 }; 45 };
45 46
46 memory { 47 memory {
47 device_type = "memory"; 48 device_type = "memory";
48 reg = <00000000 10000000>; 49 reg = <0x0 0x10000000>;
49 }; 50 };
50 51
51 soc8560@e0000000 { 52 soc8560@e0000000 {
52 #address-cells = <1>; 53 #address-cells = <1>;
53 #size-cells = <1>; 54 #size-cells = <1>;
54 device_type = "soc"; 55 device_type = "soc";
55 ranges = <0 e0000000 00100000>; 56 ranges = <0x0 0xe0000000 0x100000>;
56 reg = <e0000000 00000200>; 57 reg = <0xe0000000 0x200>;
57 bus-frequency = <13ab6680>; 58 bus-frequency = <330000000>;
58 59
59 memory-controller@2000 { 60 memory-controller@2000 {
60 compatible = "fsl,8540-memory-controller"; 61 compatible = "fsl,8540-memory-controller";
61 reg = <2000 1000>; 62 reg = <0x2000 0x1000>;
62 interrupt-parent = <&mpic>; 63 interrupt-parent = <&mpic>;
63 interrupts = <12 2>; 64 interrupts = <18 2>;
64 }; 65 };
65 66
66 l2-cache-controller@20000 { 67 l2-cache-controller@20000 {
67 compatible = "fsl,8540-l2-cache-controller"; 68 compatible = "fsl,8540-l2-cache-controller";
68 reg = <20000 1000>; 69 reg = <0x20000 0x1000>;
69 cache-line-size = <20>; // 32 bytes 70 cache-line-size = <32>; // 32 bytes
70 cache-size = <40000>; // L2, 256K 71 cache-size = <0x40000>; // L2, 256K
71 interrupt-parent = <&mpic>; 72 interrupt-parent = <&mpic>;
72 interrupts = <10 2>; 73 interrupts = <16 2>;
73 }; 74 };
74 75
75 mdio@24520 { 76 mdio@24520 {
76 #address-cells = <1>; 77 #address-cells = <1>;
77 #size-cells = <0>; 78 #size-cells = <0>;
78 compatible = "fsl,gianfar-mdio"; 79 compatible = "fsl,gianfar-mdio";
79 reg = <24520 20>; 80 reg = <0x24520 0x20>;
80 81
81 phy0: ethernet-phy@0 { 82 phy0: ethernet-phy@0 {
82 interrupt-parent = <&mpic>; 83 interrupt-parent = <&mpic>;
83 interrupts = <5 1>; 84 interrupts = <5 1>;
84 reg = <0>; 85 reg = <0x0>;
85 device_type = "ethernet-phy"; 86 device_type = "ethernet-phy";
86 }; 87 };
87 phy1: ethernet-phy@1 { 88 phy1: ethernet-phy@1 {
88 interrupt-parent = <&mpic>; 89 interrupt-parent = <&mpic>;
89 interrupts = <5 1>; 90 interrupts = <5 1>;
90 reg = <1>; 91 reg = <0x1>;
91 device_type = "ethernet-phy"; 92 device_type = "ethernet-phy";
92 }; 93 };
93 phy2: ethernet-phy@2 { 94 phy2: ethernet-phy@2 {
94 interrupt-parent = <&mpic>; 95 interrupt-parent = <&mpic>;
95 interrupts = <7 1>; 96 interrupts = <7 1>;
96 reg = <2>; 97 reg = <0x2>;
97 device_type = "ethernet-phy"; 98 device_type = "ethernet-phy";
98 }; 99 };
99 phy3: ethernet-phy@3 { 100 phy3: ethernet-phy@3 {
100 interrupt-parent = <&mpic>; 101 interrupt-parent = <&mpic>;
101 interrupts = <7 1>; 102 interrupts = <7 1>;
102 reg = <3>; 103 reg = <0x3>;
103 device_type = "ethernet-phy"; 104 device_type = "ethernet-phy";
104 }; 105 };
105 }; 106 };
@@ -109,9 +110,9 @@
109 device_type = "network"; 110 device_type = "network";
110 model = "TSEC"; 111 model = "TSEC";
111 compatible = "gianfar"; 112 compatible = "gianfar";
112 reg = <24000 1000>; 113 reg = <0x24000 0x1000>;
113 local-mac-address = [ 00 00 00 00 00 00 ]; 114 local-mac-address = [ 00 00 00 00 00 00 ];
114 interrupts = <1d 2 1e 2 22 2>; 115 interrupts = <29 2 30 2 34 2>;
115 interrupt-parent = <&mpic>; 116 interrupt-parent = <&mpic>;
116 phy-handle = <&phy0>; 117 phy-handle = <&phy0>;
117 }; 118 };
@@ -121,9 +122,9 @@
121 device_type = "network"; 122 device_type = "network";
122 model = "TSEC"; 123 model = "TSEC";
123 compatible = "gianfar"; 124 compatible = "gianfar";
124 reg = <25000 1000>; 125 reg = <0x25000 0x1000>;
125 local-mac-address = [ 00 00 00 00 00 00 ]; 126 local-mac-address = [ 00 00 00 00 00 00 ];
126 interrupts = <23 2 24 2 28 2>; 127 interrupts = <35 2 36 2 40 2>;
127 interrupt-parent = <&mpic>; 128 interrupt-parent = <&mpic>;
128 phy-handle = <&phy1>; 129 phy-handle = <&phy1>;
129 }; 130 };
@@ -132,7 +133,7 @@
132 interrupt-controller; 133 interrupt-controller;
133 #address-cells = <0>; 134 #address-cells = <0>;
134 #interrupt-cells = <2>; 135 #interrupt-cells = <2>;
135 reg = <40000 40000>; 136 reg = <0x40000 0x40000>;
136 device_type = "open-pic"; 137 device_type = "open-pic";
137 }; 138 };
138 139
@@ -140,17 +141,17 @@
140 #address-cells = <1>; 141 #address-cells = <1>;
141 #size-cells = <1>; 142 #size-cells = <1>;
142 compatible = "fsl,mpc8560-cpm", "fsl,cpm2"; 143 compatible = "fsl,mpc8560-cpm", "fsl,cpm2";
143 reg = <919c0 30>; 144 reg = <0x919c0 0x30>;
144 ranges; 145 ranges;
145 146
146 muram@80000 { 147 muram@80000 {
147 #address-cells = <1>; 148 #address-cells = <1>;
148 #size-cells = <1>; 149 #size-cells = <1>;
149 ranges = <0 80000 10000>; 150 ranges = <0x0 0x80000 0x10000>;
150 151
151 data@0 { 152 data@0 {
152 compatible = "fsl,cpm-muram-data"; 153 compatible = "fsl,cpm-muram-data";
153 reg = <0 4000 9000 2000>; 154 reg = <0x0 0x4000 0x9000 0x2000>;
154 }; 155 };
155 }; 156 };
156 157
@@ -158,17 +159,17 @@
158 compatible = "fsl,mpc8560-brg", 159 compatible = "fsl,mpc8560-brg",
159 "fsl,cpm2-brg", 160 "fsl,cpm2-brg",
160 "fsl,cpm-brg"; 161 "fsl,cpm-brg";
161 reg = <919f0 10 915f0 10>; 162 reg = <0x919f0 0x10 0x915f0 0x10>;
162 clock-frequency = <d#165000000>; 163 clock-frequency = <165000000>;
163 }; 164 };
164 165
165 cpmpic: pic@90c00 { 166 cpmpic: pic@90c00 {
166 interrupt-controller; 167 interrupt-controller;
167 #address-cells = <0>; 168 #address-cells = <0>;
168 #interrupt-cells = <2>; 169 #interrupt-cells = <2>;
169 interrupts = <2e 2>; 170 interrupts = <46 2>;
170 interrupt-parent = <&mpic>; 171 interrupt-parent = <&mpic>;
171 reg = <90c00 80>; 172 reg = <0x90c00 0x80>;
172 compatible = "fsl,mpc8560-cpm-pic", "fsl,cpm2-pic"; 173 compatible = "fsl,mpc8560-cpm-pic", "fsl,cpm2-pic";
173 }; 174 };
174 175
@@ -176,11 +177,11 @@
176 device_type = "serial"; 177 device_type = "serial";
177 compatible = "fsl,mpc8560-scc-uart", 178 compatible = "fsl,mpc8560-scc-uart",
178 "fsl,cpm2-scc-uart"; 179 "fsl,cpm2-scc-uart";
179 reg = <91a00 20 88000 100>; 180 reg = <0x91a00 0x20 0x88000 0x100>;
180 fsl,cpm-brg = <1>; 181 fsl,cpm-brg = <1>;
181 fsl,cpm-command = <00800000>; 182 fsl,cpm-command = <0x800000>;
182 current-speed = <1c200>; 183 current-speed = <115200>;
183 interrupts = <28 8>; 184 interrupts = <40 8>;
184 interrupt-parent = <&cpmpic>; 185 interrupt-parent = <&cpmpic>;
185 }; 186 };
186 187
@@ -188,11 +189,11 @@
188 device_type = "serial"; 189 device_type = "serial";
189 compatible = "fsl,mpc8560-scc-uart", 190 compatible = "fsl,mpc8560-scc-uart",
190 "fsl,cpm2-scc-uart"; 191 "fsl,cpm2-scc-uart";
191 reg = <91a20 20 88100 100>; 192 reg = <0x91a20 0x20 0x88100 0x100>;
192 fsl,cpm-brg = <2>; 193 fsl,cpm-brg = <2>;
193 fsl,cpm-command = <04a00000>; 194 fsl,cpm-command = <0x4a00000>;
194 current-speed = <1c200>; 195 current-speed = <115200>;
195 interrupts = <29 8>; 196 interrupts = <41 8>;
196 interrupt-parent = <&cpmpic>; 197 interrupt-parent = <&cpmpic>;
197 }; 198 };
198 199
@@ -200,10 +201,10 @@
200 device_type = "network"; 201 device_type = "network";
201 compatible = "fsl,mpc8560-fcc-enet", 202 compatible = "fsl,mpc8560-fcc-enet",
202 "fsl,cpm2-fcc-enet"; 203 "fsl,cpm2-fcc-enet";
203 reg = <91320 20 88500 100 913b0 1>; 204 reg = <0x91320 0x20 0x88500 0x100 0x913b0 0x1>;
204 local-mac-address = [ 00 00 00 00 00 00 ]; 205 local-mac-address = [ 00 00 00 00 00 00 ];
205 fsl,cpm-command = <16200300>; 206 fsl,cpm-command = <0x16200300>;
206 interrupts = <21 8>; 207 interrupts = <33 8>;
207 interrupt-parent = <&cpmpic>; 208 interrupt-parent = <&cpmpic>;
208 phy-handle = <&phy2>; 209 phy-handle = <&phy2>;
209 }; 210 };
@@ -212,10 +213,10 @@
212 device_type = "network"; 213 device_type = "network";
213 compatible = "fsl,mpc8560-fcc-enet", 214 compatible = "fsl,mpc8560-fcc-enet",
214 "fsl,cpm2-fcc-enet"; 215 "fsl,cpm2-fcc-enet";
215 reg = <91340 20 88600 100 913d0 1>; 216 reg = <0x91340 0x20 0x88600 0x100 0x913d0 0x1>;
216 local-mac-address = [ 00 00 00 00 00 00 ]; 217 local-mac-address = [ 00 00 00 00 00 00 ];
217 fsl,cpm-command = <1a400300>; 218 fsl,cpm-command = <0x1a400300>;
218 interrupts = <22 8>; 219 interrupts = <34 8>;
219 interrupt-parent = <&cpmpic>; 220 interrupt-parent = <&cpmpic>;
220 phy-handle = <&phy3>; 221 phy-handle = <&phy3>;
221 }; 222 };
@@ -229,87 +230,87 @@
229 #address-cells = <3>; 230 #address-cells = <3>;
230 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; 231 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
231 device_type = "pci"; 232 device_type = "pci";
232 reg = <e0008000 1000>; 233 reg = <0xe0008000 0x1000>;
233 clock-frequency = <3f940aa>; 234 clock-frequency = <66666666>;
234 interrupt-map-mask = <f800 0 0 7>; 235 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
235 interrupt-map = < 236 interrupt-map = <
236 237
237 /* IDSEL 0x2 */ 238 /* IDSEL 0x2 */
238 1000 0 0 1 &mpic 1 1 239 0x1000 0x0 0x0 0x1 &mpic 0x1 0x1
239 1000 0 0 2 &mpic 2 1 240 0x1000 0x0 0x0 0x2 &mpic 0x2 0x1
240 1000 0 0 3 &mpic 3 1 241 0x1000 0x0 0x0 0x3 &mpic 0x3 0x1
241 1000 0 0 4 &mpic 4 1 242 0x1000 0x0 0x0 0x4 &mpic 0x4 0x1
242 243
243 /* IDSEL 0x3 */ 244 /* IDSEL 0x3 */
244 1800 0 0 1 &mpic 4 1 245 0x1800 0x0 0x0 0x1 &mpic 0x4 0x1
245 1800 0 0 2 &mpic 1 1 246 0x1800 0x0 0x0 0x2 &mpic 0x1 0x1
246 1800 0 0 3 &mpic 2 1 247 0x1800 0x0 0x0 0x3 &mpic 0x2 0x1
247 1800 0 0 4 &mpic 3 1 248 0x1800 0x0 0x0 0x4 &mpic 0x3 0x1
248 249
249 /* IDSEL 0x4 */ 250 /* IDSEL 0x4 */
250 2000 0 0 1 &mpic 3 1 251 0x2000 0x0 0x0 0x1 &mpic 0x3 0x1
251 2000 0 0 2 &mpic 4 1 252 0x2000 0x0 0x0 0x2 &mpic 0x4 0x1
252 2000 0 0 3 &mpic 1 1 253 0x2000 0x0 0x0 0x3 &mpic 0x1 0x1
253 2000 0 0 4 &mpic 2 1 254 0x2000 0x0 0x0 0x4 &mpic 0x2 0x1
254 255
255 /* IDSEL 0x5 */ 256 /* IDSEL 0x5 */
256 2800 0 0 1 &mpic 2 1 257 0x2800 0x0 0x0 0x1 &mpic 0x2 0x1
257 2800 0 0 2 &mpic 3 1 258 0x2800 0x0 0x0 0x2 &mpic 0x3 0x1
258 2800 0 0 3 &mpic 4 1 259 0x2800 0x0 0x0 0x3 &mpic 0x4 0x1
259 2800 0 0 4 &mpic 1 1 260 0x2800 0x0 0x0 0x4 &mpic 0x1 0x1
260 261
261 /* IDSEL 12 */ 262 /* IDSEL 12 */
262 6000 0 0 1 &mpic 1 1 263 0x6000 0x0 0x0 0x1 &mpic 0x1 0x1
263 6000 0 0 2 &mpic 2 1 264 0x6000 0x0 0x0 0x2 &mpic 0x2 0x1
264 6000 0 0 3 &mpic 3 1 265 0x6000 0x0 0x0 0x3 &mpic 0x3 0x1
265 6000 0 0 4 &mpic 4 1 266 0x6000 0x0 0x0 0x4 &mpic 0x4 0x1
266 267
267 /* IDSEL 13 */ 268 /* IDSEL 13 */
268 6800 0 0 1 &mpic 4 1 269 0x6800 0x0 0x0 0x1 &mpic 0x4 0x1
269 6800 0 0 2 &mpic 1 1 270 0x6800 0x0 0x0 0x2 &mpic 0x1 0x1
270 6800 0 0 3 &mpic 2 1 271 0x6800 0x0 0x0 0x3 &mpic 0x2 0x1
271 6800 0 0 4 &mpic 3 1 272 0x6800 0x0 0x0 0x4 &mpic 0x3 0x1
272 273
273 /* IDSEL 14*/ 274 /* IDSEL 14*/
274 7000 0 0 1 &mpic 3 1 275 0x7000 0x0 0x0 0x1 &mpic 0x3 0x1
275 7000 0 0 2 &mpic 4 1 276 0x7000 0x0 0x0 0x2 &mpic 0x4 0x1
276 7000 0 0 3 &mpic 1 1 277 0x7000 0x0 0x0 0x3 &mpic 0x1 0x1
277 7000 0 0 4 &mpic 2 1 278 0x7000 0x0 0x0 0x4 &mpic 0x2 0x1
278 279
279 /* IDSEL 15 */ 280 /* IDSEL 15 */
280 7800 0 0 1 &mpic 2 1 281 0x7800 0x0 0x0 0x1 &mpic 0x2 0x1
281 7800 0 0 2 &mpic 3 1 282 0x7800 0x0 0x0 0x2 &mpic 0x3 0x1
282 7800 0 0 3 &mpic 4 1 283 0x7800 0x0 0x0 0x3 &mpic 0x4 0x1
283 7800 0 0 4 &mpic 1 1 284 0x7800 0x0 0x0 0x4 &mpic 0x1 0x1
284 285
285 /* IDSEL 18 */ 286 /* IDSEL 18 */
286 9000 0 0 1 &mpic 1 1 287 0x9000 0x0 0x0 0x1 &mpic 0x1 0x1
287 9000 0 0 2 &mpic 2 1 288 0x9000 0x0 0x0 0x2 &mpic 0x2 0x1
288 9000 0 0 3 &mpic 3 1 289 0x9000 0x0 0x0 0x3 &mpic 0x3 0x1
289 9000 0 0 4 &mpic 4 1 290 0x9000 0x0 0x0 0x4 &mpic 0x4 0x1
290 291
291 /* IDSEL 19 */ 292 /* IDSEL 19 */
292 9800 0 0 1 &mpic 4 1 293 0x9800 0x0 0x0 0x1 &mpic 0x4 0x1
293 9800 0 0 2 &mpic 1 1 294 0x9800 0x0 0x0 0x2 &mpic 0x1 0x1
294 9800 0 0 3 &mpic 2 1 295 0x9800 0x0 0x0 0x3 &mpic 0x2 0x1
295 9800 0 0 4 &mpic 3 1 296 0x9800 0x0 0x0 0x4 &mpic 0x3 0x1
296 297
297 /* IDSEL 20 */ 298 /* IDSEL 20 */
298 a000 0 0 1 &mpic 3 1 299 0xa000 0x0 0x0 0x1 &mpic 0x3 0x1
299 a000 0 0 2 &mpic 4 1 300 0xa000 0x0 0x0 0x2 &mpic 0x4 0x1
300 a000 0 0 3 &mpic 1 1 301 0xa000 0x0 0x0 0x3 &mpic 0x1 0x1
301 a000 0 0 4 &mpic 2 1 302 0xa000 0x0 0x0 0x4 &mpic 0x2 0x1
302 303
303 /* IDSEL 21 */ 304 /* IDSEL 21 */
304 a800 0 0 1 &mpic 2 1 305 0xa800 0x0 0x0 0x1 &mpic 0x2 0x1
305 a800 0 0 2 &mpic 3 1 306 0xa800 0x0 0x0 0x2 &mpic 0x3 0x1
306 a800 0 0 3 &mpic 4 1 307 0xa800 0x0 0x0 0x3 &mpic 0x4 0x1
307 a800 0 0 4 &mpic 1 1>; 308 0xa800 0x0 0x0 0x4 &mpic 0x1 0x1>;
308 309
309 interrupt-parent = <&mpic>; 310 interrupt-parent = <&mpic>;
310 interrupts = <18 2>; 311 interrupts = <24 2>;
311 bus-range = <0 0>; 312 bus-range = <0 0>;
312 ranges = <02000000 0 80000000 80000000 0 20000000 313 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
313 01000000 0 00000000 e2000000 0 01000000>; 314 0x1000000 0x0 0x0 0xe2000000 0x0 0x1000000>;
314 }; 315 };
315}; 316};
diff --git a/arch/powerpc/boot/dts/mpc8568mds.dts b/arch/powerpc/boot/dts/mpc8568mds.dts
index 97bc048f2158..a025a8ededc5 100644
--- a/arch/powerpc/boot/dts/mpc8568mds.dts
+++ b/arch/powerpc/boot/dts/mpc8568mds.dts
@@ -1,7 +1,7 @@
1/* 1/*
2 * MPC8568E MDS Device Tree Source 2 * MPC8568E MDS Device Tree Source
3 * 3 *
4 * Copyright 2007 Freescale Semiconductor Inc. 4 * Copyright 2007, 2008 Freescale Semiconductor Inc.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the 7 * under the terms of the GNU General Public License as published by the
@@ -9,10 +9,7 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12 12/dts-v1/;
13/*
14/memreserve/ 00000000 1000000;
15*/
16 13
17/ { 14/ {
18 model = "MPC8568EMDS"; 15 model = "MPC8568EMDS";
@@ -37,11 +34,11 @@
37 34
38 PowerPC,8568@0 { 35 PowerPC,8568@0 {
39 device_type = "cpu"; 36 device_type = "cpu";
40 reg = <0>; 37 reg = <0x0>;
41 d-cache-line-size = <20>; // 32 bytes 38 d-cache-line-size = <32>; // 32 bytes
42 i-cache-line-size = <20>; // 32 bytes 39 i-cache-line-size = <32>; // 32 bytes
43 d-cache-size = <8000>; // L1, 32K 40 d-cache-size = <0x8000>; // L1, 32K
44 i-cache-size = <8000>; // L1, 32K 41 i-cache-size = <0x8000>; // L1, 32K
45 timebase-frequency = <0>; 42 timebase-frequency = <0>;
46 bus-frequency = <0>; 43 bus-frequency = <0>;
47 clock-frequency = <0>; 44 clock-frequency = <0>;
@@ -50,36 +47,36 @@
50 47
51 memory { 48 memory {
52 device_type = "memory"; 49 device_type = "memory";
53 reg = <00000000 10000000>; 50 reg = <0x0 0x10000000>;
54 }; 51 };
55 52
56 bcsr@f8000000 { 53 bcsr@f8000000 {
57 device_type = "board-control"; 54 device_type = "board-control";
58 reg = <f8000000 8000>; 55 reg = <0xf8000000 0x8000>;
59 }; 56 };
60 57
61 soc8568@e0000000 { 58 soc8568@e0000000 {
62 #address-cells = <1>; 59 #address-cells = <1>;
63 #size-cells = <1>; 60 #size-cells = <1>;
64 device_type = "soc"; 61 device_type = "soc";
65 ranges = <0 e0000000 00100000>; 62 ranges = <0x0 0xe0000000 0x100000>;
66 reg = <e0000000 00001000>; 63 reg = <0xe0000000 0x1000>;
67 bus-frequency = <0>; 64 bus-frequency = <0>;
68 65
69 memory-controller@2000 { 66 memory-controller@2000 {
70 compatible = "fsl,8568-memory-controller"; 67 compatible = "fsl,8568-memory-controller";
71 reg = <2000 1000>; 68 reg = <0x2000 0x1000>;
72 interrupt-parent = <&mpic>; 69 interrupt-parent = <&mpic>;
73 interrupts = <12 2>; 70 interrupts = <18 2>;
74 }; 71 };
75 72
76 l2-cache-controller@20000 { 73 l2-cache-controller@20000 {
77 compatible = "fsl,8568-l2-cache-controller"; 74 compatible = "fsl,8568-l2-cache-controller";
78 reg = <20000 1000>; 75 reg = <0x20000 0x1000>;
79 cache-line-size = <20>; // 32 bytes 76 cache-line-size = <32>; // 32 bytes
80 cache-size = <80000>; // L2, 512K 77 cache-size = <0x80000>; // L2, 512K
81 interrupt-parent = <&mpic>; 78 interrupt-parent = <&mpic>;
82 interrupts = <10 2>; 79 interrupts = <16 2>;
83 }; 80 };
84 81
85 i2c@3000 { 82 i2c@3000 {
@@ -87,14 +84,14 @@
87 #size-cells = <0>; 84 #size-cells = <0>;
88 cell-index = <0>; 85 cell-index = <0>;
89 compatible = "fsl-i2c"; 86 compatible = "fsl-i2c";
90 reg = <3000 100>; 87 reg = <0x3000 0x100>;
91 interrupts = <2b 2>; 88 interrupts = <43 2>;
92 interrupt-parent = <&mpic>; 89 interrupt-parent = <&mpic>;
93 dfsrr; 90 dfsrr;
94 91
95 rtc@68 { 92 rtc@68 {
96 compatible = "dallas,ds1374"; 93 compatible = "dallas,ds1374";
97 reg = <68>; 94 reg = <0x68>;
98 }; 95 };
99 }; 96 };
100 97
@@ -103,8 +100,8 @@
103 #size-cells = <0>; 100 #size-cells = <0>;
104 cell-index = <1>; 101 cell-index = <1>;
105 compatible = "fsl-i2c"; 102 compatible = "fsl-i2c";
106 reg = <3100 100>; 103 reg = <0x3100 0x100>;
107 interrupts = <2b 2>; 104 interrupts = <43 2>;
108 interrupt-parent = <&mpic>; 105 interrupt-parent = <&mpic>;
109 dfsrr; 106 dfsrr;
110 }; 107 };
@@ -113,30 +110,30 @@
113 #address-cells = <1>; 110 #address-cells = <1>;
114 #size-cells = <0>; 111 #size-cells = <0>;
115 compatible = "fsl,gianfar-mdio"; 112 compatible = "fsl,gianfar-mdio";
116 reg = <24520 20>; 113 reg = <0x24520 0x20>;
117 114
118 phy0: ethernet-phy@7 { 115 phy0: ethernet-phy@7 {
119 interrupt-parent = <&mpic>; 116 interrupt-parent = <&mpic>;
120 interrupts = <1 1>; 117 interrupts = <1 1>;
121 reg = <7>; 118 reg = <0x7>;
122 device_type = "ethernet-phy"; 119 device_type = "ethernet-phy";
123 }; 120 };
124 phy1: ethernet-phy@1 { 121 phy1: ethernet-phy@1 {
125 interrupt-parent = <&mpic>; 122 interrupt-parent = <&mpic>;
126 interrupts = <2 1>; 123 interrupts = <2 1>;
127 reg = <1>; 124 reg = <0x1>;
128 device_type = "ethernet-phy"; 125 device_type = "ethernet-phy";
129 }; 126 };
130 phy2: ethernet-phy@2 { 127 phy2: ethernet-phy@2 {
131 interrupt-parent = <&mpic>; 128 interrupt-parent = <&mpic>;
132 interrupts = <1 1>; 129 interrupts = <1 1>;
133 reg = <2>; 130 reg = <0x2>;
134 device_type = "ethernet-phy"; 131 device_type = "ethernet-phy";
135 }; 132 };
136 phy3: ethernet-phy@3 { 133 phy3: ethernet-phy@3 {
137 interrupt-parent = <&mpic>; 134 interrupt-parent = <&mpic>;
138 interrupts = <2 1>; 135 interrupts = <2 1>;
139 reg = <3>; 136 reg = <0x3>;
140 device_type = "ethernet-phy"; 137 device_type = "ethernet-phy";
141 }; 138 };
142 }; 139 };
@@ -146,9 +143,9 @@
146 device_type = "network"; 143 device_type = "network";
147 model = "eTSEC"; 144 model = "eTSEC";
148 compatible = "gianfar"; 145 compatible = "gianfar";
149 reg = <24000 1000>; 146 reg = <0x24000 0x1000>;
150 local-mac-address = [ 00 00 00 00 00 00 ]; 147 local-mac-address = [ 00 00 00 00 00 00 ];
151 interrupts = <1d 2 1e 2 22 2>; 148 interrupts = <29 2 30 2 34 2>;
152 interrupt-parent = <&mpic>; 149 interrupt-parent = <&mpic>;
153 phy-handle = <&phy2>; 150 phy-handle = <&phy2>;
154 }; 151 };
@@ -158,9 +155,9 @@
158 device_type = "network"; 155 device_type = "network";
159 model = "eTSEC"; 156 model = "eTSEC";
160 compatible = "gianfar"; 157 compatible = "gianfar";
161 reg = <25000 1000>; 158 reg = <0x25000 0x1000>;
162 local-mac-address = [ 00 00 00 00 00 00 ]; 159 local-mac-address = [ 00 00 00 00 00 00 ];
163 interrupts = <23 2 24 2 28 2>; 160 interrupts = <35 2 36 2 40 2>;
164 interrupt-parent = <&mpic>; 161 interrupt-parent = <&mpic>;
165 phy-handle = <&phy3>; 162 phy-handle = <&phy3>;
166 }; 163 };
@@ -169,15 +166,15 @@
169 cell-index = <0>; 166 cell-index = <0>;
170 device_type = "serial"; 167 device_type = "serial";
171 compatible = "ns16550"; 168 compatible = "ns16550";
172 reg = <4500 100>; 169 reg = <0x4500 0x100>;
173 clock-frequency = <0>; 170 clock-frequency = <0>;
174 interrupts = <2a 2>; 171 interrupts = <42 2>;
175 interrupt-parent = <&mpic>; 172 interrupt-parent = <&mpic>;
176 }; 173 };
177 174
178 global-utilities@e0000 { //global utilities block 175 global-utilities@e0000 { //global utilities block
179 compatible = "fsl,mpc8548-guts"; 176 compatible = "fsl,mpc8548-guts";
180 reg = <e0000 1000>; 177 reg = <0xe0000 0x1000>;
181 fsl,has-rstcr; 178 fsl,has-rstcr;
182 }; 179 };
183 180
@@ -185,9 +182,9 @@
185 cell-index = <1>; 182 cell-index = <1>;
186 device_type = "serial"; 183 device_type = "serial";
187 compatible = "ns16550"; 184 compatible = "ns16550";
188 reg = <4600 100>; 185 reg = <0x4600 0x100>;
189 clock-frequency = <0>; 186 clock-frequency = <0>;
190 interrupts = <2a 2>; 187 interrupts = <42 2>;
191 interrupt-parent = <&mpic>; 188 interrupt-parent = <&mpic>;
192 }; 189 };
193 190
@@ -195,13 +192,13 @@
195 device_type = "crypto"; 192 device_type = "crypto";
196 model = "SEC2"; 193 model = "SEC2";
197 compatible = "talitos"; 194 compatible = "talitos";
198 reg = <30000 f000>; 195 reg = <0x30000 0xf000>;
199 interrupts = <2d 2>; 196 interrupts = <45 2>;
200 interrupt-parent = <&mpic>; 197 interrupt-parent = <&mpic>;
201 num-channels = <4>; 198 num-channels = <4>;
202 channel-fifo-len = <18>; 199 channel-fifo-len = <24>;
203 exec-units-mask = <000000fe>; 200 exec-units-mask = <0xfe>;
204 descriptor-types-mask = <012b0ebf>; 201 descriptor-types-mask = <0x12b0ebf>;
205 }; 202 };
206 203
207 mpic: pic@40000 { 204 mpic: pic@40000 {
@@ -209,73 +206,73 @@
209 interrupt-controller; 206 interrupt-controller;
210 #address-cells = <0>; 207 #address-cells = <0>;
211 #interrupt-cells = <2>; 208 #interrupt-cells = <2>;
212 reg = <40000 40000>; 209 reg = <0x40000 0x40000>;
213 compatible = "chrp,open-pic"; 210 compatible = "chrp,open-pic";
214 device_type = "open-pic"; 211 device_type = "open-pic";
215 big-endian; 212 big-endian;
216 }; 213 };
217 214
218 par_io@e0100 { 215 par_io@e0100 {
219 reg = <e0100 100>; 216 reg = <0xe0100 0x100>;
220 device_type = "par_io"; 217 device_type = "par_io";
221 num-ports = <7>; 218 num-ports = <7>;
222 219
223 pio1: ucc_pin@01 { 220 pio1: ucc_pin@01 {
224 pio-map = < 221 pio-map = <
225 /* port pin dir open_drain assignment has_irq */ 222 /* port pin dir open_drain assignment has_irq */
226 4 0a 1 0 2 0 /* TxD0 */ 223 0x4 0xa 0x1 0x0 0x2 0x0 /* TxD0 */
227 4 09 1 0 2 0 /* TxD1 */ 224 0x4 0x9 0x1 0x0 0x2 0x0 /* TxD1 */
228 4 08 1 0 2 0 /* TxD2 */ 225 0x4 0x8 0x1 0x0 0x2 0x0 /* TxD2 */
229 4 07 1 0 2 0 /* TxD3 */ 226 0x4 0x7 0x1 0x0 0x2 0x0 /* TxD3 */
230 4 17 1 0 2 0 /* TxD4 */ 227 0x4 0x17 0x1 0x0 0x2 0x0 /* TxD4 */
231 4 16 1 0 2 0 /* TxD5 */ 228 0x4 0x16 0x1 0x0 0x2 0x0 /* TxD5 */
232 4 15 1 0 2 0 /* TxD6 */ 229 0x4 0x15 0x1 0x0 0x2 0x0 /* TxD6 */
233 4 14 1 0 2 0 /* TxD7 */ 230 0x4 0x14 0x1 0x0 0x2 0x0 /* TxD7 */
234 4 0f 2 0 2 0 /* RxD0 */ 231 0x4 0xf 0x2 0x0 0x2 0x0 /* RxD0 */
235 4 0e 2 0 2 0 /* RxD1 */ 232 0x4 0xe 0x2 0x0 0x2 0x0 /* RxD1 */
236 4 0d 2 0 2 0 /* RxD2 */ 233 0x4 0xd 0x2 0x0 0x2 0x0 /* RxD2 */
237 4 0c 2 0 2 0 /* RxD3 */ 234 0x4 0xc 0x2 0x0 0x2 0x0 /* RxD3 */
238 4 1d 2 0 2 0 /* RxD4 */ 235 0x4 0x1d 0x2 0x0 0x2 0x0 /* RxD4 */
239 4 1c 2 0 2 0 /* RxD5 */ 236 0x4 0x1c 0x2 0x0 0x2 0x0 /* RxD5 */
240 4 1b 2 0 2 0 /* RxD6 */ 237 0x4 0x1b 0x2 0x0 0x2 0x0 /* RxD6 */
241 4 1a 2 0 2 0 /* RxD7 */ 238 0x4 0x1a 0x2 0x0 0x2 0x0 /* RxD7 */
242 4 0b 1 0 2 0 /* TX_EN */ 239 0x4 0xb 0x1 0x0 0x2 0x0 /* TX_EN */
243 4 18 1 0 2 0 /* TX_ER */ 240 0x4 0x18 0x1 0x0 0x2 0x0 /* TX_ER */
244 4 10 2 0 2 0 /* RX_DV */ 241 0x4 0x10 0x2 0x0 0x2 0x0 /* RX_DV */
245 4 1e 2 0 2 0 /* RX_ER */ 242 0x4 0x1e 0x2 0x0 0x2 0x0 /* RX_ER */
246 4 11 2 0 2 0 /* RX_CLK */ 243 0x4 0x11 0x2 0x0 0x2 0x0 /* RX_CLK */
247 4 13 1 0 2 0 /* GTX_CLK */ 244 0x4 0x13 0x1 0x0 0x2 0x0 /* GTX_CLK */
248 1 1f 2 0 3 0>; /* GTX125 */ 245 0x1 0x1f 0x2 0x0 0x3 0x0>; /* GTX125 */
249 }; 246 };
250 247
251 pio2: ucc_pin@02 { 248 pio2: ucc_pin@02 {
252 pio-map = < 249 pio-map = <
253 /* port pin dir open_drain assignment has_irq */ 250 /* port pin dir open_drain assignment has_irq */
254 5 0a 1 0 2 0 /* TxD0 */ 251 0x5 0xa 0x1 0x0 0x2 0x0 /* TxD0 */
255 5 09 1 0 2 0 /* TxD1 */ 252 0x5 0x9 0x1 0x0 0x2 0x0 /* TxD1 */
256 5 08 1 0 2 0 /* TxD2 */ 253 0x5 0x8 0x1 0x0 0x2 0x0 /* TxD2 */
257 5 07 1 0 2 0 /* TxD3 */ 254 0x5 0x7 0x1 0x0 0x2 0x0 /* TxD3 */
258 5 17 1 0 2 0 /* TxD4 */ 255 0x5 0x17 0x1 0x0 0x2 0x0 /* TxD4 */
259 5 16 1 0 2 0 /* TxD5 */ 256 0x5 0x16 0x1 0x0 0x2 0x0 /* TxD5 */
260 5 15 1 0 2 0 /* TxD6 */ 257 0x5 0x15 0x1 0x0 0x2 0x0 /* TxD6 */
261 5 14 1 0 2 0 /* TxD7 */ 258 0x5 0x14 0x1 0x0 0x2 0x0 /* TxD7 */
262 5 0f 2 0 2 0 /* RxD0 */ 259 0x5 0xf 0x2 0x0 0x2 0x0 /* RxD0 */
263 5 0e 2 0 2 0 /* RxD1 */ 260 0x5 0xe 0x2 0x0 0x2 0x0 /* RxD1 */
264 5 0d 2 0 2 0 /* RxD2 */ 261 0x5 0xd 0x2 0x0 0x2 0x0 /* RxD2 */
265 5 0c 2 0 2 0 /* RxD3 */ 262 0x5 0xc 0x2 0x0 0x2 0x0 /* RxD3 */
266 5 1d 2 0 2 0 /* RxD4 */ 263 0x5 0x1d 0x2 0x0 0x2 0x0 /* RxD4 */
267 5 1c 2 0 2 0 /* RxD5 */ 264 0x5 0x1c 0x2 0x0 0x2 0x0 /* RxD5 */
268 5 1b 2 0 2 0 /* RxD6 */ 265 0x5 0x1b 0x2 0x0 0x2 0x0 /* RxD6 */
269 5 1a 2 0 2 0 /* RxD7 */ 266 0x5 0x1a 0x2 0x0 0x2 0x0 /* RxD7 */
270 5 0b 1 0 2 0 /* TX_EN */ 267 0x5 0xb 0x1 0x0 0x2 0x0 /* TX_EN */
271 5 18 1 0 2 0 /* TX_ER */ 268 0x5 0x18 0x1 0x0 0x2 0x0 /* TX_ER */
272 5 10 2 0 2 0 /* RX_DV */ 269 0x5 0x10 0x2 0x0 0x2 0x0 /* RX_DV */
273 5 1e 2 0 2 0 /* RX_ER */ 270 0x5 0x1e 0x2 0x0 0x2 0x0 /* RX_ER */
274 5 11 2 0 2 0 /* RX_CLK */ 271 0x5 0x11 0x2 0x0 0x2 0x0 /* RX_CLK */
275 5 13 1 0 2 0 /* GTX_CLK */ 272 0x5 0x13 0x1 0x0 0x2 0x0 /* GTX_CLK */
276 1 1f 2 0 3 0 /* GTX125 */ 273 0x1 0x1f 0x2 0x0 0x3 0x0 /* GTX125 */
277 4 06 3 0 2 0 /* MDIO */ 274 0x4 0x6 0x3 0x0 0x2 0x0 /* MDIO */
278 4 05 1 0 2 0>; /* MDC */ 275 0x4 0x5 0x1 0x0 0x2 0x0>; /* MDC */
279 }; 276 };
280 }; 277 };
281 }; 278 };
@@ -285,28 +282,28 @@
285 #size-cells = <1>; 282 #size-cells = <1>;
286 device_type = "qe"; 283 device_type = "qe";
287 compatible = "fsl,qe"; 284 compatible = "fsl,qe";
288 ranges = <0 e0080000 00040000>; 285 ranges = <0x0 0xe0080000 0x40000>;
289 reg = <e0080000 480>; 286 reg = <0xe0080000 0x480>;
290 brg-frequency = <0>; 287 brg-frequency = <0>;
291 bus-frequency = <179A7B00>; 288 bus-frequency = <396000000>;
292 289
293 muram@10000 { 290 muram@10000 {
294 #address-cells = <1>; 291 #address-cells = <1>;
295 #size-cells = <1>; 292 #size-cells = <1>;
296 compatible = "fsl,qe-muram", "fsl,cpm-muram"; 293 compatible = "fsl,qe-muram", "fsl,cpm-muram";
297 ranges = <0 00010000 0000c000>; 294 ranges = <0x0 0x10000 0x10000>;
298 295
299 data-only@0 { 296 data-only@0 {
300 compatible = "fsl,qe-muram-data", 297 compatible = "fsl,qe-muram-data",
301 "fsl,cpm-muram-data"; 298 "fsl,cpm-muram-data";
302 reg = <0 c000>; 299 reg = <0x0 0x10000>;
303 }; 300 };
304 }; 301 };
305 302
306 spi@4c0 { 303 spi@4c0 {
307 cell-index = <0>; 304 cell-index = <0>;
308 compatible = "fsl,spi"; 305 compatible = "fsl,spi";
309 reg = <4c0 40>; 306 reg = <0x4c0 0x40>;
310 interrupts = <2>; 307 interrupts = <2>;
311 interrupt-parent = <&qeic>; 308 interrupt-parent = <&qeic>;
312 mode = "cpu"; 309 mode = "cpu";
@@ -315,7 +312,7 @@
315 spi@500 { 312 spi@500 {
316 cell-index = <1>; 313 cell-index = <1>;
317 compatible = "fsl,spi"; 314 compatible = "fsl,spi";
318 reg = <500 40>; 315 reg = <0x500 0x40>;
319 interrupts = <1>; 316 interrupts = <1>;
320 interrupt-parent = <&qeic>; 317 interrupt-parent = <&qeic>;
321 mode = "cpu"; 318 mode = "cpu";
@@ -324,11 +321,9 @@
324 enet2: ucc@2000 { 321 enet2: ucc@2000 {
325 device_type = "network"; 322 device_type = "network";
326 compatible = "ucc_geth"; 323 compatible = "ucc_geth";
327 model = "UCC";
328 cell-index = <1>; 324 cell-index = <1>;
329 device-id = <1>; 325 reg = <0x2000 0x200>;
330 reg = <2000 200>; 326 interrupts = <32>;
331 interrupts = <20>;
332 interrupt-parent = <&qeic>; 327 interrupt-parent = <&qeic>;
333 local-mac-address = [ 00 00 00 00 00 00 ]; 328 local-mac-address = [ 00 00 00 00 00 00 ];
334 rx-clock-name = "none"; 329 rx-clock-name = "none";
@@ -341,11 +336,9 @@
341 enet3: ucc@3000 { 336 enet3: ucc@3000 {
342 device_type = "network"; 337 device_type = "network";
343 compatible = "ucc_geth"; 338 compatible = "ucc_geth";
344 model = "UCC";
345 cell-index = <2>; 339 cell-index = <2>;
346 device-id = <2>; 340 reg = <0x3000 0x200>;
347 reg = <3000 200>; 341 interrupts = <33>;
348 interrupts = <21>;
349 interrupt-parent = <&qeic>; 342 interrupt-parent = <&qeic>;
350 local-mac-address = [ 00 00 00 00 00 00 ]; 343 local-mac-address = [ 00 00 00 00 00 00 ];
351 rx-clock-name = "none"; 344 rx-clock-name = "none";
@@ -358,7 +351,7 @@
358 mdio@2120 { 351 mdio@2120 {
359 #address-cells = <1>; 352 #address-cells = <1>;
360 #size-cells = <0>; 353 #size-cells = <0>;
361 reg = <2120 18>; 354 reg = <0x2120 0x18>;
362 compatible = "fsl,ucc-mdio"; 355 compatible = "fsl,ucc-mdio";
363 356
364 /* These are the same PHYs as on 357 /* These are the same PHYs as on
@@ -366,25 +359,25 @@
366 qe_phy0: ethernet-phy@07 { 359 qe_phy0: ethernet-phy@07 {
367 interrupt-parent = <&mpic>; 360 interrupt-parent = <&mpic>;
368 interrupts = <1 1>; 361 interrupts = <1 1>;
369 reg = <7>; 362 reg = <0x7>;
370 device_type = "ethernet-phy"; 363 device_type = "ethernet-phy";
371 }; 364 };
372 qe_phy1: ethernet-phy@01 { 365 qe_phy1: ethernet-phy@01 {
373 interrupt-parent = <&mpic>; 366 interrupt-parent = <&mpic>;
374 interrupts = <2 1>; 367 interrupts = <2 1>;
375 reg = <1>; 368 reg = <0x1>;
376 device_type = "ethernet-phy"; 369 device_type = "ethernet-phy";
377 }; 370 };
378 qe_phy2: ethernet-phy@02 { 371 qe_phy2: ethernet-phy@02 {
379 interrupt-parent = <&mpic>; 372 interrupt-parent = <&mpic>;
380 interrupts = <1 1>; 373 interrupts = <1 1>;
381 reg = <2>; 374 reg = <0x2>;
382 device_type = "ethernet-phy"; 375 device_type = "ethernet-phy";
383 }; 376 };
384 qe_phy3: ethernet-phy@03 { 377 qe_phy3: ethernet-phy@03 {
385 interrupt-parent = <&mpic>; 378 interrupt-parent = <&mpic>;
386 interrupts = <2 1>; 379 interrupts = <2 1>;
387 reg = <3>; 380 reg = <0x3>;
388 device_type = "ethernet-phy"; 381 device_type = "ethernet-phy";
389 }; 382 };
390 }; 383 };
@@ -394,9 +387,9 @@
394 compatible = "fsl,qe-ic"; 387 compatible = "fsl,qe-ic";
395 #address-cells = <0>; 388 #address-cells = <0>;
396 #interrupt-cells = <1>; 389 #interrupt-cells = <1>;
397 reg = <80 80>; 390 reg = <0x80 0x80>;
398 big-endian; 391 big-endian;
399 interrupts = <2e 2 2e 2>; //high:30 low:30 392 interrupts = <46 2 46 2>; //high:30 low:30
400 interrupt-parent = <&mpic>; 393 interrupt-parent = <&mpic>;
401 }; 394 };
402 395
@@ -404,30 +397,30 @@
404 397
405 pci0: pci@e0008000 { 398 pci0: pci@e0008000 {
406 cell-index = <0>; 399 cell-index = <0>;
407 interrupt-map-mask = <f800 0 0 7>; 400 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
408 interrupt-map = < 401 interrupt-map = <
409 /* IDSEL 0x12 AD18 */ 402 /* IDSEL 0x12 AD18 */
410 9000 0 0 1 &mpic 5 1 403 0x9000 0x0 0x0 0x1 &mpic 0x5 0x1
411 9000 0 0 2 &mpic 6 1 404 0x9000 0x0 0x0 0x2 &mpic 0x6 0x1
412 9000 0 0 3 &mpic 7 1 405 0x9000 0x0 0x0 0x3 &mpic 0x7 0x1
413 9000 0 0 4 &mpic 4 1 406 0x9000 0x0 0x0 0x4 &mpic 0x4 0x1
414 407
415 /* IDSEL 0x13 AD19 */ 408 /* IDSEL 0x13 AD19 */
416 9800 0 0 1 &mpic 6 1 409 0x9800 0x0 0x0 0x1 &mpic 0x6 0x1
417 9800 0 0 2 &mpic 7 1 410 0x9800 0x0 0x0 0x2 &mpic 0x7 0x1
418 9800 0 0 3 &mpic 4 1 411 0x9800 0x0 0x0 0x3 &mpic 0x4 0x1
419 9800 0 0 4 &mpic 5 1>; 412 0x9800 0x0 0x0 0x4 &mpic 0x5 0x1>;
420 413
421 interrupt-parent = <&mpic>; 414 interrupt-parent = <&mpic>;
422 interrupts = <18 2>; 415 interrupts = <24 2>;
423 bus-range = <0 ff>; 416 bus-range = <0 255>;
424 ranges = <02000000 0 80000000 80000000 0 20000000 417 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
425 01000000 0 00000000 e2000000 0 00800000>; 418 0x1000000 0x0 0x0 0xe2000000 0x0 0x800000>;
426 clock-frequency = <3f940aa>; 419 clock-frequency = <66666666>;
427 #interrupt-cells = <1>; 420 #interrupt-cells = <1>;
428 #size-cells = <2>; 421 #size-cells = <2>;
429 #address-cells = <3>; 422 #address-cells = <3>;
430 reg = <e0008000 1000>; 423 reg = <0xe0008000 0x1000>;
431 compatible = "fsl,mpc8540-pci"; 424 compatible = "fsl,mpc8540-pci";
432 device_type = "pci"; 425 device_type = "pci";
433 }; 426 };
@@ -435,39 +428,39 @@
435 /* PCI Express */ 428 /* PCI Express */
436 pci1: pcie@e000a000 { 429 pci1: pcie@e000a000 {
437 cell-index = <2>; 430 cell-index = <2>;
438 interrupt-map-mask = <f800 0 0 7>; 431 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
439 interrupt-map = < 432 interrupt-map = <
440 433
441 /* IDSEL 0x0 (PEX) */ 434 /* IDSEL 0x0 (PEX) */
442 00000 0 0 1 &mpic 0 1 435 00000 0x0 0x0 0x1 &mpic 0x0 0x1
443 00000 0 0 2 &mpic 1 1 436 00000 0x0 0x0 0x2 &mpic 0x1 0x1
444 00000 0 0 3 &mpic 2 1 437 00000 0x0 0x0 0x3 &mpic 0x2 0x1
445 00000 0 0 4 &mpic 3 1>; 438 00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
446 439
447 interrupt-parent = <&mpic>; 440 interrupt-parent = <&mpic>;
448 interrupts = <1a 2>; 441 interrupts = <26 2>;
449 bus-range = <0 ff>; 442 bus-range = <0 255>;
450 ranges = <02000000 0 a0000000 a0000000 0 10000000 443 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
451 01000000 0 00000000 e2800000 0 00800000>; 444 0x1000000 0x0 0x0 0xe2800000 0x0 0x800000>;
452 clock-frequency = <1fca055>; 445 clock-frequency = <33333333>;
453 #interrupt-cells = <1>; 446 #interrupt-cells = <1>;
454 #size-cells = <2>; 447 #size-cells = <2>;
455 #address-cells = <3>; 448 #address-cells = <3>;
456 reg = <e000a000 1000>; 449 reg = <0xe000a000 0x1000>;
457 compatible = "fsl,mpc8548-pcie"; 450 compatible = "fsl,mpc8548-pcie";
458 device_type = "pci"; 451 device_type = "pci";
459 pcie@0 { 452 pcie@0 {
460 reg = <0 0 0 0 0>; 453 reg = <0x0 0x0 0x0 0x0 0x0>;
461 #size-cells = <2>; 454 #size-cells = <2>;
462 #address-cells = <3>; 455 #address-cells = <3>;
463 device_type = "pci"; 456 device_type = "pci";
464 ranges = <02000000 0 a0000000 457 ranges = <0x2000000 0x0 0xa0000000
465 02000000 0 a0000000 458 0x2000000 0x0 0xa0000000
466 0 10000000 459 0x0 0x10000000
467 460
468 01000000 0 00000000 461 0x1000000 0x0 0x0
469 01000000 0 00000000 462 0x1000000 0x0 0x0
470 0 00800000>; 463 0x0 0x800000>;
471 }; 464 };
472 }; 465 };
473}; 466};
diff --git a/arch/powerpc/boot/dts/mpc8572ds.dts b/arch/powerpc/boot/dts/mpc8572ds.dts
index db37214aee37..66f27ab613a2 100644
--- a/arch/powerpc/boot/dts/mpc8572ds.dts
+++ b/arch/powerpc/boot/dts/mpc8572ds.dts
@@ -1,7 +1,7 @@
1/* 1/*
2 * MPC8572 DS Device Tree Source 2 * MPC8572 DS Device Tree Source
3 * 3 *
4 * Copyright 2007 Freescale Semiconductor Inc. 4 * Copyright 2007, 2008 Freescale Semiconductor Inc.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the 7 * under the terms of the GNU General Public License as published by the
@@ -9,6 +9,7 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/dts-v1/;
12/ { 13/ {
13 model = "fsl,MPC8572DS"; 14 model = "fsl,MPC8572DS";
14 compatible = "fsl,MPC8572DS"; 15 compatible = "fsl,MPC8572DS";
@@ -33,11 +34,11 @@
33 34
34 PowerPC,8572@0 { 35 PowerPC,8572@0 {
35 device_type = "cpu"; 36 device_type = "cpu";
36 reg = <0>; 37 reg = <0x0>;
37 d-cache-line-size = <20>; // 32 bytes 38 d-cache-line-size = <32>; // 32 bytes
38 i-cache-line-size = <20>; // 32 bytes 39 i-cache-line-size = <32>; // 32 bytes
39 d-cache-size = <8000>; // L1, 32K 40 d-cache-size = <0x8000>; // L1, 32K
40 i-cache-size = <8000>; // L1, 32K 41 i-cache-size = <0x8000>; // L1, 32K
41 timebase-frequency = <0>; 42 timebase-frequency = <0>;
42 bus-frequency = <0>; 43 bus-frequency = <0>;
43 clock-frequency = <0>; 44 clock-frequency = <0>;
@@ -45,11 +46,11 @@
45 46
46 PowerPC,8572@1 { 47 PowerPC,8572@1 {
47 device_type = "cpu"; 48 device_type = "cpu";
48 reg = <1>; 49 reg = <0x1>;
49 d-cache-line-size = <20>; // 32 bytes 50 d-cache-line-size = <32>; // 32 bytes
50 i-cache-line-size = <20>; // 32 bytes 51 i-cache-line-size = <32>; // 32 bytes
51 d-cache-size = <8000>; // L1, 32K 52 d-cache-size = <0x8000>; // L1, 32K
52 i-cache-size = <8000>; // L1, 32K 53 i-cache-size = <0x8000>; // L1, 32K
53 timebase-frequency = <0>; 54 timebase-frequency = <0>;
54 bus-frequency = <0>; 55 bus-frequency = <0>;
55 clock-frequency = <0>; 56 clock-frequency = <0>;
@@ -58,38 +59,38 @@
58 59
59 memory { 60 memory {
60 device_type = "memory"; 61 device_type = "memory";
61 reg = <00000000 00000000>; // Filled by U-Boot 62 reg = <0x0 0x0>; // Filled by U-Boot
62 }; 63 };
63 64
64 soc8572@ffe00000 { 65 soc8572@ffe00000 {
65 #address-cells = <1>; 66 #address-cells = <1>;
66 #size-cells = <1>; 67 #size-cells = <1>;
67 device_type = "soc"; 68 device_type = "soc";
68 ranges = <00000000 ffe00000 00100000>; 69 ranges = <0x0 0xffe00000 0x100000>;
69 reg = <ffe00000 00001000>; // CCSRBAR & soc regs, remove once parse code for immrbase fixed 70 reg = <0xffe00000 0x1000>; // CCSRBAR & soc regs, remove once parse code for immrbase fixed
70 bus-frequency = <0>; // Filled out by uboot. 71 bus-frequency = <0>; // Filled out by uboot.
71 72
72 memory-controller@2000 { 73 memory-controller@2000 {
73 compatible = "fsl,mpc8572-memory-controller"; 74 compatible = "fsl,mpc8572-memory-controller";
74 reg = <2000 1000>; 75 reg = <0x2000 0x1000>;
75 interrupt-parent = <&mpic>; 76 interrupt-parent = <&mpic>;
76 interrupts = <12 2>; 77 interrupts = <18 2>;
77 }; 78 };
78 79
79 memory-controller@6000 { 80 memory-controller@6000 {
80 compatible = "fsl,mpc8572-memory-controller"; 81 compatible = "fsl,mpc8572-memory-controller";
81 reg = <6000 1000>; 82 reg = <0x6000 0x1000>;
82 interrupt-parent = <&mpic>; 83 interrupt-parent = <&mpic>;
83 interrupts = <12 2>; 84 interrupts = <18 2>;
84 }; 85 };
85 86
86 l2-cache-controller@20000 { 87 l2-cache-controller@20000 {
87 compatible = "fsl,mpc8572-l2-cache-controller"; 88 compatible = "fsl,mpc8572-l2-cache-controller";
88 reg = <20000 1000>; 89 reg = <0x20000 0x1000>;
89 cache-line-size = <20>; // 32 bytes 90 cache-line-size = <32>; // 32 bytes
90 cache-size = <80000>; // L2, 512K 91 cache-size = <0x80000>; // L2, 512K
91 interrupt-parent = <&mpic>; 92 interrupt-parent = <&mpic>;
92 interrupts = <10 2>; 93 interrupts = <16 2>;
93 }; 94 };
94 95
95 i2c@3000 { 96 i2c@3000 {
@@ -97,8 +98,8 @@
97 #size-cells = <0>; 98 #size-cells = <0>;
98 cell-index = <0>; 99 cell-index = <0>;
99 compatible = "fsl-i2c"; 100 compatible = "fsl-i2c";
100 reg = <3000 100>; 101 reg = <0x3000 0x100>;
101 interrupts = <2b 2>; 102 interrupts = <43 2>;
102 interrupt-parent = <&mpic>; 103 interrupt-parent = <&mpic>;
103 dfsrr; 104 dfsrr;
104 }; 105 };
@@ -108,8 +109,8 @@
108 #size-cells = <0>; 109 #size-cells = <0>;
109 cell-index = <1>; 110 cell-index = <1>;
110 compatible = "fsl-i2c"; 111 compatible = "fsl-i2c";
111 reg = <3100 100>; 112 reg = <0x3100 0x100>;
112 interrupts = <2b 2>; 113 interrupts = <43 2>;
113 interrupt-parent = <&mpic>; 114 interrupt-parent = <&mpic>;
114 dfsrr; 115 dfsrr;
115 }; 116 };
@@ -118,27 +119,27 @@
118 #address-cells = <1>; 119 #address-cells = <1>;
119 #size-cells = <0>; 120 #size-cells = <0>;
120 compatible = "fsl,gianfar-mdio"; 121 compatible = "fsl,gianfar-mdio";
121 reg = <24520 20>; 122 reg = <0x24520 0x20>;
122 123
123 phy0: ethernet-phy@0 { 124 phy0: ethernet-phy@0 {
124 interrupt-parent = <&mpic>; 125 interrupt-parent = <&mpic>;
125 interrupts = <a 1>; 126 interrupts = <10 1>;
126 reg = <0>; 127 reg = <0x0>;
127 }; 128 };
128 phy1: ethernet-phy@1 { 129 phy1: ethernet-phy@1 {
129 interrupt-parent = <&mpic>; 130 interrupt-parent = <&mpic>;
130 interrupts = <a 1>; 131 interrupts = <10 1>;
131 reg = <1>; 132 reg = <0x1>;
132 }; 133 };
133 phy2: ethernet-phy@2 { 134 phy2: ethernet-phy@2 {
134 interrupt-parent = <&mpic>; 135 interrupt-parent = <&mpic>;
135 interrupts = <a 1>; 136 interrupts = <10 1>;
136 reg = <2>; 137 reg = <0x2>;
137 }; 138 };
138 phy3: ethernet-phy@3 { 139 phy3: ethernet-phy@3 {
139 interrupt-parent = <&mpic>; 140 interrupt-parent = <&mpic>;
140 interrupts = <a 1>; 141 interrupts = <10 1>;
141 reg = <3>; 142 reg = <0x3>;
142 }; 143 };
143 }; 144 };
144 145
@@ -147,9 +148,9 @@
147 device_type = "network"; 148 device_type = "network";
148 model = "eTSEC"; 149 model = "eTSEC";
149 compatible = "gianfar"; 150 compatible = "gianfar";
150 reg = <24000 1000>; 151 reg = <0x24000 0x1000>;
151 local-mac-address = [ 00 00 00 00 00 00 ]; 152 local-mac-address = [ 00 00 00 00 00 00 ];
152 interrupts = <1d 2 1e 2 22 2>; 153 interrupts = <29 2 30 2 34 2>;
153 interrupt-parent = <&mpic>; 154 interrupt-parent = <&mpic>;
154 phy-handle = <&phy0>; 155 phy-handle = <&phy0>;
155 phy-connection-type = "rgmii-id"; 156 phy-connection-type = "rgmii-id";
@@ -160,9 +161,9 @@
160 device_type = "network"; 161 device_type = "network";
161 model = "eTSEC"; 162 model = "eTSEC";
162 compatible = "gianfar"; 163 compatible = "gianfar";
163 reg = <25000 1000>; 164 reg = <0x25000 0x1000>;
164 local-mac-address = [ 00 00 00 00 00 00 ]; 165 local-mac-address = [ 00 00 00 00 00 00 ];
165 interrupts = <23 2 24 2 28 2>; 166 interrupts = <35 2 36 2 40 2>;
166 interrupt-parent = <&mpic>; 167 interrupt-parent = <&mpic>;
167 phy-handle = <&phy1>; 168 phy-handle = <&phy1>;
168 phy-connection-type = "rgmii-id"; 169 phy-connection-type = "rgmii-id";
@@ -173,9 +174,9 @@
173 device_type = "network"; 174 device_type = "network";
174 model = "eTSEC"; 175 model = "eTSEC";
175 compatible = "gianfar"; 176 compatible = "gianfar";
176 reg = <26000 1000>; 177 reg = <0x26000 0x1000>;
177 local-mac-address = [ 00 00 00 00 00 00 ]; 178 local-mac-address = [ 00 00 00 00 00 00 ];
178 interrupts = <1f 2 20 2 21 2>; 179 interrupts = <31 2 32 2 33 2>;
179 interrupt-parent = <&mpic>; 180 interrupt-parent = <&mpic>;
180 phy-handle = <&phy2>; 181 phy-handle = <&phy2>;
181 phy-connection-type = "rgmii-id"; 182 phy-connection-type = "rgmii-id";
@@ -186,9 +187,9 @@
186 device_type = "network"; 187 device_type = "network";
187 model = "eTSEC"; 188 model = "eTSEC";
188 compatible = "gianfar"; 189 compatible = "gianfar";
189 reg = <27000 1000>; 190 reg = <0x27000 0x1000>;
190 local-mac-address = [ 00 00 00 00 00 00 ]; 191 local-mac-address = [ 00 00 00 00 00 00 ];
191 interrupts = <25 2 26 2 27 2>; 192 interrupts = <37 2 38 2 39 2>;
192 interrupt-parent = <&mpic>; 193 interrupt-parent = <&mpic>;
193 phy-handle = <&phy3>; 194 phy-handle = <&phy3>;
194 phy-connection-type = "rgmii-id"; 195 phy-connection-type = "rgmii-id";
@@ -198,9 +199,9 @@
198 cell-index = <0>; 199 cell-index = <0>;
199 device_type = "serial"; 200 device_type = "serial";
200 compatible = "ns16550"; 201 compatible = "ns16550";
201 reg = <4500 100>; 202 reg = <0x4500 0x100>;
202 clock-frequency = <0>; 203 clock-frequency = <0>;
203 interrupts = <2a 2>; 204 interrupts = <42 2>;
204 interrupt-parent = <&mpic>; 205 interrupt-parent = <&mpic>;
205 }; 206 };
206 207
@@ -208,15 +209,15 @@
208 cell-index = <1>; 209 cell-index = <1>;
209 device_type = "serial"; 210 device_type = "serial";
210 compatible = "ns16550"; 211 compatible = "ns16550";
211 reg = <4600 100>; 212 reg = <0x4600 0x100>;
212 clock-frequency = <0>; 213 clock-frequency = <0>;
213 interrupts = <2a 2>; 214 interrupts = <42 2>;
214 interrupt-parent = <&mpic>; 215 interrupt-parent = <&mpic>;
215 }; 216 };
216 217
217 global-utilities@e0000 { //global utilities block 218 global-utilities@e0000 { //global utilities block
218 compatible = "fsl,mpc8572-guts"; 219 compatible = "fsl,mpc8572-guts";
219 reg = <e0000 1000>; 220 reg = <0xe0000 0x1000>;
220 fsl,has-rstcr; 221 fsl,has-rstcr;
221 }; 222 };
222 223
@@ -225,7 +226,7 @@
225 interrupt-controller; 226 interrupt-controller;
226 #address-cells = <0>; 227 #address-cells = <0>;
227 #interrupt-cells = <2>; 228 #interrupt-cells = <2>;
228 reg = <40000 40000>; 229 reg = <0x40000 0x40000>;
229 compatible = "chrp,open-pic"; 230 compatible = "chrp,open-pic";
230 device_type = "open-pic"; 231 device_type = "open-pic";
231 big-endian; 232 big-endian;
@@ -239,167 +240,167 @@
239 #interrupt-cells = <1>; 240 #interrupt-cells = <1>;
240 #size-cells = <2>; 241 #size-cells = <2>;
241 #address-cells = <3>; 242 #address-cells = <3>;
242 reg = <ffe08000 1000>; 243 reg = <0xffe08000 0x1000>;
243 bus-range = <0 ff>; 244 bus-range = <0 255>;
244 ranges = <02000000 0 80000000 80000000 0 20000000 245 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
245 01000000 0 00000000 ffc00000 0 00010000>; 246 0x1000000 0x0 0x0 0xffc00000 0x0 0x10000>;
246 clock-frequency = <1fca055>; 247 clock-frequency = <33333333>;
247 interrupt-parent = <&mpic>; 248 interrupt-parent = <&mpic>;
248 interrupts = <18 2>; 249 interrupts = <24 2>;
249 interrupt-map-mask = <ff00 0 0 7>; 250 interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
250 interrupt-map = < 251 interrupt-map = <
251 /* IDSEL 0x11 func 0 - PCI slot 1 */ 252 /* IDSEL 0x11 func 0 - PCI slot 1 */
252 8800 0 0 1 &mpic 2 1 253 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
253 8800 0 0 2 &mpic 3 1 254 0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
254 8800 0 0 3 &mpic 4 1 255 0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
255 8800 0 0 4 &mpic 1 1 256 0x8800 0x0 0x0 0x4 &mpic 0x1 0x1
256 257
257 /* IDSEL 0x11 func 1 - PCI slot 1 */ 258 /* IDSEL 0x11 func 1 - PCI slot 1 */
258 8900 0 0 1 &mpic 2 1 259 0x8900 0x0 0x0 0x1 &mpic 0x2 0x1
259 8900 0 0 2 &mpic 3 1 260 0x8900 0x0 0x0 0x2 &mpic 0x3 0x1
260 8900 0 0 3 &mpic 4 1 261 0x8900 0x0 0x0 0x3 &mpic 0x4 0x1
261 8900 0 0 4 &mpic 1 1 262 0x8900 0x0 0x0 0x4 &mpic 0x1 0x1
262 263
263 /* IDSEL 0x11 func 2 - PCI slot 1 */ 264 /* IDSEL 0x11 func 2 - PCI slot 1 */
264 8a00 0 0 1 &mpic 2 1 265 0x8a00 0x0 0x0 0x1 &mpic 0x2 0x1
265 8a00 0 0 2 &mpic 3 1 266 0x8a00 0x0 0x0 0x2 &mpic 0x3 0x1
266 8a00 0 0 3 &mpic 4 1 267 0x8a00 0x0 0x0 0x3 &mpic 0x4 0x1
267 8a00 0 0 4 &mpic 1 1 268 0x8a00 0x0 0x0 0x4 &mpic 0x1 0x1
268 269
269 /* IDSEL 0x11 func 3 - PCI slot 1 */ 270 /* IDSEL 0x11 func 3 - PCI slot 1 */
270 8b00 0 0 1 &mpic 2 1 271 0x8b00 0x0 0x0 0x1 &mpic 0x2 0x1
271 8b00 0 0 2 &mpic 3 1 272 0x8b00 0x0 0x0 0x2 &mpic 0x3 0x1
272 8b00 0 0 3 &mpic 4 1 273 0x8b00 0x0 0x0 0x3 &mpic 0x4 0x1
273 8b00 0 0 4 &mpic 1 1 274 0x8b00 0x0 0x0 0x4 &mpic 0x1 0x1
274 275
275 /* IDSEL 0x11 func 4 - PCI slot 1 */ 276 /* IDSEL 0x11 func 4 - PCI slot 1 */
276 8c00 0 0 1 &mpic 2 1 277 0x8c00 0x0 0x0 0x1 &mpic 0x2 0x1
277 8c00 0 0 2 &mpic 3 1 278 0x8c00 0x0 0x0 0x2 &mpic 0x3 0x1
278 8c00 0 0 3 &mpic 4 1 279 0x8c00 0x0 0x0 0x3 &mpic 0x4 0x1
279 8c00 0 0 4 &mpic 1 1 280 0x8c00 0x0 0x0 0x4 &mpic 0x1 0x1
280 281
281 /* IDSEL 0x11 func 5 - PCI slot 1 */ 282 /* IDSEL 0x11 func 5 - PCI slot 1 */
282 8d00 0 0 1 &mpic 2 1 283 0x8d00 0x0 0x0 0x1 &mpic 0x2 0x1
283 8d00 0 0 2 &mpic 3 1 284 0x8d00 0x0 0x0 0x2 &mpic 0x3 0x1
284 8d00 0 0 3 &mpic 4 1 285 0x8d00 0x0 0x0 0x3 &mpic 0x4 0x1
285 8d00 0 0 4 &mpic 1 1 286 0x8d00 0x0 0x0 0x4 &mpic 0x1 0x1
286 287
287 /* IDSEL 0x11 func 6 - PCI slot 1 */ 288 /* IDSEL 0x11 func 6 - PCI slot 1 */
288 8e00 0 0 1 &mpic 2 1 289 0x8e00 0x0 0x0 0x1 &mpic 0x2 0x1
289 8e00 0 0 2 &mpic 3 1 290 0x8e00 0x0 0x0 0x2 &mpic 0x3 0x1
290 8e00 0 0 3 &mpic 4 1 291 0x8e00 0x0 0x0 0x3 &mpic 0x4 0x1
291 8e00 0 0 4 &mpic 1 1 292 0x8e00 0x0 0x0 0x4 &mpic 0x1 0x1
292 293
293 /* IDSEL 0x11 func 7 - PCI slot 1 */ 294 /* IDSEL 0x11 func 7 - PCI slot 1 */
294 8f00 0 0 1 &mpic 2 1 295 0x8f00 0x0 0x0 0x1 &mpic 0x2 0x1
295 8f00 0 0 2 &mpic 3 1 296 0x8f00 0x0 0x0 0x2 &mpic 0x3 0x1
296 8f00 0 0 3 &mpic 4 1 297 0x8f00 0x0 0x0 0x3 &mpic 0x4 0x1
297 8f00 0 0 4 &mpic 1 1 298 0x8f00 0x0 0x0 0x4 &mpic 0x1 0x1
298 299
299 /* IDSEL 0x12 func 0 - PCI slot 2 */ 300 /* IDSEL 0x12 func 0 - PCI slot 2 */
300 9000 0 0 1 &mpic 3 1 301 0x9000 0x0 0x0 0x1 &mpic 0x3 0x1
301 9000 0 0 2 &mpic 4 1 302 0x9000 0x0 0x0 0x2 &mpic 0x4 0x1
302 9000 0 0 3 &mpic 1 1 303 0x9000 0x0 0x0 0x3 &mpic 0x1 0x1
303 9000 0 0 4 &mpic 2 1 304 0x9000 0x0 0x0 0x4 &mpic 0x2 0x1
304 305
305 /* IDSEL 0x12 func 1 - PCI slot 2 */ 306 /* IDSEL 0x12 func 1 - PCI slot 2 */
306 9100 0 0 1 &mpic 3 1 307 0x9100 0x0 0x0 0x1 &mpic 0x3 0x1
307 9100 0 0 2 &mpic 4 1 308 0x9100 0x0 0x0 0x2 &mpic 0x4 0x1
308 9100 0 0 3 &mpic 1 1 309 0x9100 0x0 0x0 0x3 &mpic 0x1 0x1
309 9100 0 0 4 &mpic 2 1 310 0x9100 0x0 0x0 0x4 &mpic 0x2 0x1
310 311
311 /* IDSEL 0x12 func 2 - PCI slot 2 */ 312 /* IDSEL 0x12 func 2 - PCI slot 2 */
312 9200 0 0 1 &mpic 3 1 313 0x9200 0x0 0x0 0x1 &mpic 0x3 0x1
313 9200 0 0 2 &mpic 4 1 314 0x9200 0x0 0x0 0x2 &mpic 0x4 0x1
314 9200 0 0 3 &mpic 1 1 315 0x9200 0x0 0x0 0x3 &mpic 0x1 0x1
315 9200 0 0 4 &mpic 2 1 316 0x9200 0x0 0x0 0x4 &mpic 0x2 0x1
316 317
317 /* IDSEL 0x12 func 3 - PCI slot 2 */ 318 /* IDSEL 0x12 func 3 - PCI slot 2 */
318 9300 0 0 1 &mpic 3 1 319 0x9300 0x0 0x0 0x1 &mpic 0x3 0x1
319 9300 0 0 2 &mpic 4 1 320 0x9300 0x0 0x0 0x2 &mpic 0x4 0x1
320 9300 0 0 3 &mpic 1 1 321 0x9300 0x0 0x0 0x3 &mpic 0x1 0x1
321 9300 0 0 4 &mpic 2 1 322 0x9300 0x0 0x0 0x4 &mpic 0x2 0x1
322 323
323 /* IDSEL 0x12 func 4 - PCI slot 2 */ 324 /* IDSEL 0x12 func 4 - PCI slot 2 */
324 9400 0 0 1 &mpic 3 1 325 0x9400 0x0 0x0 0x1 &mpic 0x3 0x1
325 9400 0 0 2 &mpic 4 1 326 0x9400 0x0 0x0 0x2 &mpic 0x4 0x1
326 9400 0 0 3 &mpic 1 1 327 0x9400 0x0 0x0 0x3 &mpic 0x1 0x1
327 9400 0 0 4 &mpic 2 1 328 0x9400 0x0 0x0 0x4 &mpic 0x2 0x1
328 329
329 /* IDSEL 0x12 func 5 - PCI slot 2 */ 330 /* IDSEL 0x12 func 5 - PCI slot 2 */
330 9500 0 0 1 &mpic 3 1 331 0x9500 0x0 0x0 0x1 &mpic 0x3 0x1
331 9500 0 0 2 &mpic 4 1 332 0x9500 0x0 0x0 0x2 &mpic 0x4 0x1
332 9500 0 0 3 &mpic 1 1 333 0x9500 0x0 0x0 0x3 &mpic 0x1 0x1
333 9500 0 0 4 &mpic 2 1 334 0x9500 0x0 0x0 0x4 &mpic 0x2 0x1
334 335
335 /* IDSEL 0x12 func 6 - PCI slot 2 */ 336 /* IDSEL 0x12 func 6 - PCI slot 2 */
336 9600 0 0 1 &mpic 3 1 337 0x9600 0x0 0x0 0x1 &mpic 0x3 0x1
337 9600 0 0 2 &mpic 4 1 338 0x9600 0x0 0x0 0x2 &mpic 0x4 0x1
338 9600 0 0 3 &mpic 1 1 339 0x9600 0x0 0x0 0x3 &mpic 0x1 0x1
339 9600 0 0 4 &mpic 2 1 340 0x9600 0x0 0x0 0x4 &mpic 0x2 0x1
340 341
341 /* IDSEL 0x12 func 7 - PCI slot 2 */ 342 /* IDSEL 0x12 func 7 - PCI slot 2 */
342 9700 0 0 1 &mpic 3 1 343 0x9700 0x0 0x0 0x1 &mpic 0x3 0x1
343 9700 0 0 2 &mpic 4 1 344 0x9700 0x0 0x0 0x2 &mpic 0x4 0x1
344 9700 0 0 3 &mpic 1 1 345 0x9700 0x0 0x0 0x3 &mpic 0x1 0x1
345 9700 0 0 4 &mpic 2 1 346 0x9700 0x0 0x0 0x4 &mpic 0x2 0x1
346 347
347 // IDSEL 0x1c USB 348 // IDSEL 0x1c USB
348 e000 0 0 1 &i8259 c 2 349 0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
349 e100 0 0 2 &i8259 9 2 350 0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
350 e200 0 0 3 &i8259 a 2 351 0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
351 e300 0 0 4 &i8259 b 2 352 0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
352 353
353 // IDSEL 0x1d Audio 354 // IDSEL 0x1d Audio
354 e800 0 0 1 &i8259 6 2 355 0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
355 356
356 // IDSEL 0x1e Legacy 357 // IDSEL 0x1e Legacy
357 f000 0 0 1 &i8259 7 2 358 0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
358 f100 0 0 1 &i8259 7 2 359 0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
359 360
360 // IDSEL 0x1f IDE/SATA 361 // IDSEL 0x1f IDE/SATA
361 f800 0 0 1 &i8259 e 2 362 0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
362 f900 0 0 1 &i8259 5 2 363 0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
363 364
364 >; 365 >;
365 366
366 pcie@0 { 367 pcie@0 {
367 reg = <0 0 0 0 0>; 368 reg = <0x0 0x0 0x0 0x0 0x0>;
368 #size-cells = <2>; 369 #size-cells = <2>;
369 #address-cells = <3>; 370 #address-cells = <3>;
370 device_type = "pci"; 371 device_type = "pci";
371 ranges = <02000000 0 80000000 372 ranges = <0x2000000 0x0 0x80000000
372 02000000 0 80000000 373 0x2000000 0x0 0x80000000
373 0 20000000 374 0x0 0x20000000
374 375
375 01000000 0 00000000 376 0x1000000 0x0 0x0
376 01000000 0 00000000 377 0x1000000 0x0 0x0
377 0 00100000>; 378 0x0 0x100000>;
378 uli1575@0 { 379 uli1575@0 {
379 reg = <0 0 0 0 0>; 380 reg = <0x0 0x0 0x0 0x0 0x0>;
380 #size-cells = <2>; 381 #size-cells = <2>;
381 #address-cells = <3>; 382 #address-cells = <3>;
382 ranges = <02000000 0 80000000 383 ranges = <0x2000000 0x0 0x80000000
383 02000000 0 80000000 384 0x2000000 0x0 0x80000000
384 0 20000000 385 0x0 0x20000000
385 386
386 01000000 0 00000000 387 0x1000000 0x0 0x0
387 01000000 0 00000000 388 0x1000000 0x0 0x0
388 0 00100000>; 389 0x0 0x100000>;
389 isa@1e { 390 isa@1e {
390 device_type = "isa"; 391 device_type = "isa";
391 #interrupt-cells = <2>; 392 #interrupt-cells = <2>;
392 #size-cells = <1>; 393 #size-cells = <1>;
393 #address-cells = <2>; 394 #address-cells = <2>;
394 reg = <f000 0 0 0 0>; 395 reg = <0xf000 0x0 0x0 0x0 0x0>;
395 ranges = <1 0 01000000 0 0 396 ranges = <0x1 0x0 0x1000000 0x0 0x0
396 00001000>; 397 0x1000>;
397 interrupt-parent = <&i8259>; 398 interrupt-parent = <&i8259>;
398 399
399 i8259: interrupt-controller@20 { 400 i8259: interrupt-controller@20 {
400 reg = <1 20 2 401 reg = <0x1 0x20 0x2
401 1 a0 2 402 0x1 0xa0 0x2
402 1 4d0 2>; 403 0x1 0x4d0 0x2>;
403 interrupt-controller; 404 interrupt-controller;
404 device_type = "interrupt-controller"; 405 device_type = "interrupt-controller";
405 #address-cells = <0>; 406 #address-cells = <0>;
@@ -412,29 +413,29 @@
412 i8042@60 { 413 i8042@60 {
413 #size-cells = <0>; 414 #size-cells = <0>;
414 #address-cells = <1>; 415 #address-cells = <1>;
415 reg = <1 60 1 1 64 1>; 416 reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
416 interrupts = <1 3 c 3>; 417 interrupts = <1 3 12 3>;
417 interrupt-parent = 418 interrupt-parent =
418 <&i8259>; 419 <&i8259>;
419 420
420 keyboard@0 { 421 keyboard@0 {
421 reg = <0>; 422 reg = <0x0>;
422 compatible = "pnpPNP,303"; 423 compatible = "pnpPNP,303";
423 }; 424 };
424 425
425 mouse@1 { 426 mouse@1 {
426 reg = <1>; 427 reg = <0x1>;
427 compatible = "pnpPNP,f03"; 428 compatible = "pnpPNP,f03";
428 }; 429 };
429 }; 430 };
430 431
431 rtc@70 { 432 rtc@70 {
432 compatible = "pnpPNP,b00"; 433 compatible = "pnpPNP,b00";
433 reg = <1 70 2>; 434 reg = <0x1 0x70 0x2>;
434 }; 435 };
435 436
436 gpio@400 { 437 gpio@400 {
437 reg = <1 400 80>; 438 reg = <0x1 0x400 0x80>;
438 }; 439 };
439 }; 440 };
440 }; 441 };
@@ -449,33 +450,33 @@
449 #interrupt-cells = <1>; 450 #interrupt-cells = <1>;
450 #size-cells = <2>; 451 #size-cells = <2>;
451 #address-cells = <3>; 452 #address-cells = <3>;
452 reg = <ffe09000 1000>; 453 reg = <0xffe09000 0x1000>;
453 bus-range = <0 ff>; 454 bus-range = <0 255>;
454 ranges = <02000000 0 a0000000 a0000000 0 20000000 455 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
455 01000000 0 00000000 ffc10000 0 00010000>; 456 0x1000000 0x0 0x0 0xffc10000 0x0 0x10000>;
456 clock-frequency = <1fca055>; 457 clock-frequency = <33333333>;
457 interrupt-parent = <&mpic>; 458 interrupt-parent = <&mpic>;
458 interrupts = <1a 2>; 459 interrupts = <26 2>;
459 interrupt-map-mask = <f800 0 0 7>; 460 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
460 interrupt-map = < 461 interrupt-map = <
461 /* IDSEL 0x0 */ 462 /* IDSEL 0x0 */
462 0000 0 0 1 &mpic 4 1 463 0000 0x0 0x0 0x1 &mpic 0x4 0x1
463 0000 0 0 2 &mpic 5 1 464 0000 0x0 0x0 0x2 &mpic 0x5 0x1
464 0000 0 0 3 &mpic 6 1 465 0000 0x0 0x0 0x3 &mpic 0x6 0x1
465 0000 0 0 4 &mpic 7 1 466 0000 0x0 0x0 0x4 &mpic 0x7 0x1
466 >; 467 >;
467 pcie@0 { 468 pcie@0 {
468 reg = <0 0 0 0 0>; 469 reg = <0x0 0x0 0x0 0x0 0x0>;
469 #size-cells = <2>; 470 #size-cells = <2>;
470 #address-cells = <3>; 471 #address-cells = <3>;
471 device_type = "pci"; 472 device_type = "pci";
472 ranges = <02000000 0 a0000000 473 ranges = <0x2000000 0x0 0xa0000000
473 02000000 0 a0000000 474 0x2000000 0x0 0xa0000000
474 0 20000000 475 0x0 0x20000000
475 476
476 01000000 0 00000000 477 0x1000000 0x0 0x0
477 01000000 0 00000000 478 0x1000000 0x0 0x0
478 0 00100000>; 479 0x0 0x100000>;
479 }; 480 };
480 }; 481 };
481 482
@@ -486,33 +487,33 @@
486 #interrupt-cells = <1>; 487 #interrupt-cells = <1>;
487 #size-cells = <2>; 488 #size-cells = <2>;
488 #address-cells = <3>; 489 #address-cells = <3>;
489 reg = <ffe0a000 1000>; 490 reg = <0xffe0a000 0x1000>;
490 bus-range = <0 ff>; 491 bus-range = <0 255>;
491 ranges = <02000000 0 c0000000 c0000000 0 20000000 492 ranges = <0x2000000 0x0 0xc0000000 0xc0000000 0x0 0x20000000
492 01000000 0 00000000 ffc20000 0 00010000>; 493 0x1000000 0x0 0x0 0xffc20000 0x0 0x10000>;
493 clock-frequency = <1fca055>; 494 clock-frequency = <33333333>;
494 interrupt-parent = <&mpic>; 495 interrupt-parent = <&mpic>;
495 interrupts = <1b 2>; 496 interrupts = <27 2>;
496 interrupt-map-mask = <f800 0 0 7>; 497 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
497 interrupt-map = < 498 interrupt-map = <
498 /* IDSEL 0x0 */ 499 /* IDSEL 0x0 */
499 0000 0 0 1 &mpic 0 1 500 0000 0x0 0x0 0x1 &mpic 0x0 0x1
500 0000 0 0 2 &mpic 1 1 501 0000 0x0 0x0 0x2 &mpic 0x1 0x1
501 0000 0 0 3 &mpic 2 1 502 0000 0x0 0x0 0x3 &mpic 0x2 0x1
502 0000 0 0 4 &mpic 3 1 503 0000 0x0 0x0 0x4 &mpic 0x3 0x1
503 >; 504 >;
504 pcie@0 { 505 pcie@0 {
505 reg = <0 0 0 0 0>; 506 reg = <0x0 0x0 0x0 0x0 0x0>;
506 #size-cells = <2>; 507 #size-cells = <2>;
507 #address-cells = <3>; 508 #address-cells = <3>;
508 device_type = "pci"; 509 device_type = "pci";
509 ranges = <02000000 0 c0000000 510 ranges = <0x2000000 0x0 0xc0000000
510 02000000 0 c0000000 511 0x2000000 0x0 0xc0000000
511 0 20000000 512 0x0 0x20000000
512 513
513 01000000 0 00000000 514 0x1000000 0x0 0x0
514 01000000 0 00000000 515 0x1000000 0x0 0x0
515 0 00100000>; 516 0x0 0x100000>;
516 }; 517 };
517 }; 518 };
518}; 519};
diff --git a/arch/powerpc/boot/dts/mpc8641_hpcn.dts b/arch/powerpc/boot/dts/mpc8641_hpcn.dts
index 79385bcd5c5f..7f9b999843ce 100644
--- a/arch/powerpc/boot/dts/mpc8641_hpcn.dts
+++ b/arch/powerpc/boot/dts/mpc8641_hpcn.dts
@@ -13,7 +13,7 @@
13 13
14/ { 14/ {
15 model = "MPC8641HPCN"; 15 model = "MPC8641HPCN";
16 compatible = "mpc86xx"; 16 compatible = "fsl,mpc8641hpcn";
17 #address-cells = <1>; 17 #address-cells = <1>;
18 #size-cells = <1>; 18 #size-cells = <1>;
19 19
diff --git a/arch/powerpc/boot/dts/mpc866ads.dts b/arch/powerpc/boot/dts/mpc866ads.dts
index daf9433e906b..765e43c997da 100644
--- a/arch/powerpc/boot/dts/mpc866ads.dts
+++ b/arch/powerpc/boot/dts/mpc866ads.dts
@@ -2,6 +2,7 @@
2 * MPC866 ADS Device Tree Source 2 * MPC866 ADS Device Tree Source
3 * 3 *
4 * Copyright 2006 MontaVista Software, Inc. 4 * Copyright 2006 MontaVista Software, Inc.
5 * Copyright 2008 Freescale Semiconductor, Inc.
5 * 6 *
6 * This program is free software; you can redistribute it and/or modify it 7 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the 8 * under the terms of the GNU General Public License as published by the
@@ -9,6 +10,7 @@
9 * option) any later version. 10 * option) any later version.
10 */ 11 */
11 12
13/dts-v1/;
12 14
13/ { 15/ {
14 model = "MPC866ADS"; 16 model = "MPC866ADS";
@@ -22,37 +24,37 @@
22 24
23 PowerPC,866@0 { 25 PowerPC,866@0 {
24 device_type = "cpu"; 26 device_type = "cpu";
25 reg = <0>; 27 reg = <0x0>;
26 d-cache-line-size = <10>; // 16 bytes 28 d-cache-line-size = <16>; // 16 bytes
27 i-cache-line-size = <10>; // 16 bytes 29 i-cache-line-size = <16>; // 16 bytes
28 d-cache-size = <2000>; // L1, 8K 30 d-cache-size = <0x2000>; // L1, 8K
29 i-cache-size = <4000>; // L1, 16K 31 i-cache-size = <0x4000>; // L1, 16K
30 timebase-frequency = <0>; 32 timebase-frequency = <0>;
31 bus-frequency = <0>; 33 bus-frequency = <0>;
32 clock-frequency = <0>; 34 clock-frequency = <0>;
33 interrupts = <f 2>; // decrementer interrupt 35 interrupts = <15 2>; // decrementer interrupt
34 interrupt-parent = <&PIC>; 36 interrupt-parent = <&PIC>;
35 }; 37 };
36 }; 38 };
37 39
38 memory { 40 memory {
39 device_type = "memory"; 41 device_type = "memory";
40 reg = <00000000 800000>; 42 reg = <0x0 0x800000>;
41 }; 43 };
42 44
43 localbus@ff000100 { 45 localbus@ff000100 {
44 compatible = "fsl,mpc866-localbus", "fsl,pq1-localbus"; 46 compatible = "fsl,mpc866-localbus", "fsl,pq1-localbus";
45 #address-cells = <2>; 47 #address-cells = <2>;
46 #size-cells = <1>; 48 #size-cells = <1>;
47 reg = <ff000100 40>; 49 reg = <0xff000100 0x40>;
48 50
49 ranges = < 51 ranges = <
50 1 0 ff080000 00008000 52 0x1 0x0 0xff080000 0x8000
51 5 0 ff0a0000 00008000 53 0x5 0x0 0xff0a0000 0x8000
52 >; 54 >;
53 55
54 board-control@1,0 { 56 board-control@1,0 {
55 reg = <1 0 20 5 300 4>; 57 reg = <0x1 0x0 0x20 0x5 0x300 0x4>;
56 compatible = "fsl,mpc866ads-bcsr"; 58 compatible = "fsl,mpc866ads-bcsr";
57 }; 59 };
58 }; 60 };
@@ -61,17 +63,17 @@
61 #address-cells = <1>; 63 #address-cells = <1>;
62 #size-cells = <1>; 64 #size-cells = <1>;
63 device_type = "soc"; 65 device_type = "soc";
64 ranges = <0 ff000000 00100000>; 66 ranges = <0x0 0xff000000 0x100000>;
65 reg = <ff000000 00000200>; 67 reg = <0xff000000 0x200>;
66 bus-frequency = <0>; 68 bus-frequency = <0>;
67 69
68 mdio@e00 { 70 mdio@e00 {
69 compatible = "fsl,mpc866-fec-mdio", "fsl,pq1-fec-mdio"; 71 compatible = "fsl,mpc866-fec-mdio", "fsl,pq1-fec-mdio";
70 reg = <e00 188>; 72 reg = <0xe00 0x188>;
71 #address-cells = <1>; 73 #address-cells = <1>;
72 #size-cells = <0>; 74 #size-cells = <0>;
73 PHY: ethernet-phy@f { 75 PHY: ethernet-phy@f {
74 reg = <f>; 76 reg = <0xf>;
75 device_type = "ethernet-phy"; 77 device_type = "ethernet-phy";
76 }; 78 };
77 }; 79 };
@@ -80,7 +82,7 @@
80 device_type = "network"; 82 device_type = "network";
81 compatible = "fsl,mpc866-fec-enet", 83 compatible = "fsl,mpc866-fec-enet",
82 "fsl,pq1-fec-enet"; 84 "fsl,pq1-fec-enet";
83 reg = <e00 188>; 85 reg = <0xe00 0x188>;
84 local-mac-address = [ 00 00 00 00 00 00 ]; 86 local-mac-address = [ 00 00 00 00 00 00 ];
85 interrupts = <3 1>; 87 interrupts = <3 1>;
86 interrupt-parent = <&PIC>; 88 interrupt-parent = <&PIC>;
@@ -91,7 +93,7 @@
91 PIC: pic@0 { 93 PIC: pic@0 {
92 interrupt-controller; 94 interrupt-controller;
93 #interrupt-cells = <2>; 95 #interrupt-cells = <2>;
94 reg = <0 24>; 96 reg = <0x0 0x24>;
95 compatible = "fsl,mpc866-pic", "fsl,pq1-pic"; 97 compatible = "fsl,mpc866-pic", "fsl,pq1-pic";
96 }; 98 };
97 99
@@ -100,7 +102,7 @@
100 #size-cells = <1>; 102 #size-cells = <1>;
101 compatible = "fsl,mpc866-cpm", "fsl,cpm1"; 103 compatible = "fsl,mpc866-cpm", "fsl,cpm1";
102 ranges; 104 ranges;
103 reg = <9c0 40>; 105 reg = <0x9c0 0x40>;
104 brg-frequency = <0>; 106 brg-frequency = <0>;
105 interrupts = <0 2>; // cpm error interrupt 107 interrupts = <0 2>; // cpm error interrupt
106 interrupt-parent = <&CPM_PIC>; 108 interrupt-parent = <&CPM_PIC>;
@@ -108,11 +110,11 @@
108 muram@2000 { 110 muram@2000 {
109 #address-cells = <1>; 111 #address-cells = <1>;
110 #size-cells = <1>; 112 #size-cells = <1>;
111 ranges = <0 2000 2000>; 113 ranges = <0x0 0x2000 0x2000>;
112 114
113 data@0 { 115 data@0 {
114 compatible = "fsl,cpm-muram-data"; 116 compatible = "fsl,cpm-muram-data";
115 reg = <0 1c00>; 117 reg = <0x0 0x1c00>;
116 }; 118 };
117 }; 119 };
118 120
@@ -120,7 +122,7 @@
120 compatible = "fsl,mpc866-brg", 122 compatible = "fsl,mpc866-brg",
121 "fsl,cpm1-brg", 123 "fsl,cpm1-brg",
122 "fsl,cpm-brg"; 124 "fsl,cpm-brg";
123 reg = <9f0 10>; 125 reg = <0x9f0 0x10>;
124 clock-frequency = <0>; 126 clock-frequency = <0>;
125 }; 127 };
126 128
@@ -130,7 +132,7 @@
130 #interrupt-cells = <1>; 132 #interrupt-cells = <1>;
131 interrupts = <5 2 0 2>; 133 interrupts = <5 2 0 2>;
132 interrupt-parent = <&PIC>; 134 interrupt-parent = <&PIC>;
133 reg = <930 20>; 135 reg = <0x930 0x20>;
134 compatible = "fsl,mpc866-cpm-pic", 136 compatible = "fsl,mpc866-cpm-pic",
135 "fsl,cpm1-pic"; 137 "fsl,cpm1-pic";
136 }; 138 };
@@ -140,31 +142,31 @@
140 device_type = "serial"; 142 device_type = "serial";
141 compatible = "fsl,mpc866-smc-uart", 143 compatible = "fsl,mpc866-smc-uart",
142 "fsl,cpm1-smc-uart"; 144 "fsl,cpm1-smc-uart";
143 reg = <a80 10 3e80 40>; 145 reg = <0xa80 0x10 0x3e80 0x40>;
144 interrupts = <4>; 146 interrupts = <4>;
145 interrupt-parent = <&CPM_PIC>; 147 interrupt-parent = <&CPM_PIC>;
146 fsl,cpm-brg = <1>; 148 fsl,cpm-brg = <1>;
147 fsl,cpm-command = <0090>; 149 fsl,cpm-command = <0x90>;
148 }; 150 };
149 151
150 serial@a90 { 152 serial@a90 {
151 device_type = "serial"; 153 device_type = "serial";
152 compatible = "fsl,mpc866-smc-uart", 154 compatible = "fsl,mpc866-smc-uart",
153 "fsl,cpm1-smc-uart"; 155 "fsl,cpm1-smc-uart";
154 reg = <a90 10 3f80 40>; 156 reg = <0xa90 0x10 0x3f80 0x40>;
155 interrupts = <3>; 157 interrupts = <3>;
156 interrupt-parent = <&CPM_PIC>; 158 interrupt-parent = <&CPM_PIC>;
157 fsl,cpm-brg = <2>; 159 fsl,cpm-brg = <2>;
158 fsl,cpm-command = <00d0>; 160 fsl,cpm-command = <0xd0>;
159 }; 161 };
160 162
161 ethernet@a00 { 163 ethernet@a00 {
162 device_type = "network"; 164 device_type = "network";
163 compatible = "fsl,mpc866-scc-enet", 165 compatible = "fsl,mpc866-scc-enet",
164 "fsl,cpm1-scc-enet"; 166 "fsl,cpm1-scc-enet";
165 reg = <a00 18 3c00 100>; 167 reg = <0xa00 0x18 0x3c00 0x100>;
166 local-mac-address = [ 00 00 00 00 00 00 ]; 168 local-mac-address = [ 00 00 00 00 00 00 ];
167 interrupts = <1e>; 169 interrupts = <30>;
168 interrupt-parent = <&CPM_PIC>; 170 interrupt-parent = <&CPM_PIC>;
169 fsl,cpm-command = <0000>; 171 fsl,cpm-command = <0000>;
170 linux,network-index = <1>; 172 linux,network-index = <1>;
diff --git a/arch/powerpc/boot/dts/mpc885ads.dts b/arch/powerpc/boot/dts/mpc885ads.dts
index d84a012c2aaf..9895043722b9 100644
--- a/arch/powerpc/boot/dts/mpc885ads.dts
+++ b/arch/powerpc/boot/dts/mpc885ads.dts
@@ -2,7 +2,7 @@
2 * MPC885 ADS Device Tree Source 2 * MPC885 ADS Device Tree Source
3 * 3 *
4 * Copyright 2006 MontaVista Software, Inc. 4 * Copyright 2006 MontaVista Software, Inc.
5 * Copyright 2007 Freescale Semiconductor, Inc. 5 * Copyright 2007,2008 Freescale Semiconductor, Inc.
6 * 6 *
7 * This program is free software; you can redistribute it and/or modify it 7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the 8 * under the terms of the GNU General Public License as published by the
@@ -10,6 +10,7 @@
10 * option) any later version. 10 * option) any later version.
11 */ 11 */
12 12
13/dts-v1/;
13 14
14/ { 15/ {
15 model = "MPC885ADS"; 16 model = "MPC885ADS";
@@ -23,45 +24,45 @@
23 24
24 PowerPC,885@0 { 25 PowerPC,885@0 {
25 device_type = "cpu"; 26 device_type = "cpu";
26 reg = <0>; 27 reg = <0x0>;
27 d-cache-line-size = <d#16>; 28 d-cache-line-size = <16>;
28 i-cache-line-size = <d#16>; 29 i-cache-line-size = <16>;
29 d-cache-size = <d#8192>; 30 d-cache-size = <8192>;
30 i-cache-size = <d#8192>; 31 i-cache-size = <8192>;
31 timebase-frequency = <0>; 32 timebase-frequency = <0>;
32 bus-frequency = <0>; 33 bus-frequency = <0>;
33 clock-frequency = <0>; 34 clock-frequency = <0>;
34 interrupts = <f 2>; // decrementer interrupt 35 interrupts = <15 2>; // decrementer interrupt
35 interrupt-parent = <&PIC>; 36 interrupt-parent = <&PIC>;
36 }; 37 };
37 }; 38 };
38 39
39 memory { 40 memory {
40 device_type = "memory"; 41 device_type = "memory";
41 reg = <0 0>; 42 reg = <0x0 0x0>;
42 }; 43 };
43 44
44 localbus@ff000100 { 45 localbus@ff000100 {
45 compatible = "fsl,mpc885-localbus", "fsl,pq1-localbus"; 46 compatible = "fsl,mpc885-localbus", "fsl,pq1-localbus";
46 #address-cells = <2>; 47 #address-cells = <2>;
47 #size-cells = <1>; 48 #size-cells = <1>;
48 reg = <ff000100 40>; 49 reg = <0xff000100 0x40>;
49 50
50 ranges = < 51 ranges = <
51 0 0 fe000000 00800000 52 0x0 0x0 0xfe000000 0x800000
52 1 0 ff080000 00008000 53 0x1 0x0 0xff080000 0x8000
53 5 0 ff0a0000 00008000 54 0x5 0x0 0xff0a0000 0x8000
54 >; 55 >;
55 56
56 flash@0,0 { 57 flash@0,0 {
57 compatible = "jedec-flash"; 58 compatible = "jedec-flash";
58 reg = <0 0 800000>; 59 reg = <0x0 0x0 0x800000>;
59 bank-width = <4>; 60 bank-width = <4>;
60 device-width = <1>; 61 device-width = <1>;
61 }; 62 };
62 63
63 board-control@1,0 { 64 board-control@1,0 {
64 reg = <1 0 20 5 300 4>; 65 reg = <0x1 0x0 0x20 0x5 0x300 0x4>;
65 compatible = "fsl,mpc885ads-bcsr"; 66 compatible = "fsl,mpc885ads-bcsr";
66 }; 67 };
67 }; 68 };
@@ -71,30 +72,30 @@
71 #address-cells = <1>; 72 #address-cells = <1>;
72 #size-cells = <1>; 73 #size-cells = <1>;
73 device_type = "soc"; 74 device_type = "soc";
74 ranges = <0 ff000000 00004000>; 75 ranges = <0x0 0xff000000 0x4000>;
75 bus-frequency = <0>; 76 bus-frequency = <0>;
76 77
77 // Temporary -- will go away once kernel uses ranges for get_immrbase(). 78 // Temporary -- will go away once kernel uses ranges for get_immrbase().
78 reg = <ff000000 4000>; 79 reg = <0xff000000 0x4000>;
79 80
80 mdio@e00 { 81 mdio@e00 {
81 compatible = "fsl,mpc885-fec-mdio", "fsl,pq1-fec-mdio"; 82 compatible = "fsl,mpc885-fec-mdio", "fsl,pq1-fec-mdio";
82 reg = <e00 188>; 83 reg = <0xe00 0x188>;
83 #address-cells = <1>; 84 #address-cells = <1>;
84 #size-cells = <0>; 85 #size-cells = <0>;
85 86
86 PHY0: ethernet-phy@0 { 87 PHY0: ethernet-phy@0 {
87 reg = <0>; 88 reg = <0x0>;
88 device_type = "ethernet-phy"; 89 device_type = "ethernet-phy";
89 }; 90 };
90 91
91 PHY1: ethernet-phy@1 { 92 PHY1: ethernet-phy@1 {
92 reg = <1>; 93 reg = <0x1>;
93 device_type = "ethernet-phy"; 94 device_type = "ethernet-phy";
94 }; 95 };
95 96
96 PHY2: ethernet-phy@2 { 97 PHY2: ethernet-phy@2 {
97 reg = <2>; 98 reg = <0x2>;
98 device_type = "ethernet-phy"; 99 device_type = "ethernet-phy";
99 }; 100 };
100 }; 101 };
@@ -103,7 +104,7 @@
103 device_type = "network"; 104 device_type = "network";
104 compatible = "fsl,mpc885-fec-enet", 105 compatible = "fsl,mpc885-fec-enet",
105 "fsl,pq1-fec-enet"; 106 "fsl,pq1-fec-enet";
106 reg = <e00 188>; 107 reg = <0xe00 0x188>;
107 local-mac-address = [ 00 00 00 00 00 00 ]; 108 local-mac-address = [ 00 00 00 00 00 00 ];
108 interrupts = <3 1>; 109 interrupts = <3 1>;
109 interrupt-parent = <&PIC>; 110 interrupt-parent = <&PIC>;
@@ -115,7 +116,7 @@
115 device_type = "network"; 116 device_type = "network";
116 compatible = "fsl,mpc885-fec-enet", 117 compatible = "fsl,mpc885-fec-enet",
117 "fsl,pq1-fec-enet"; 118 "fsl,pq1-fec-enet";
118 reg = <1e00 188>; 119 reg = <0x1e00 0x188>;
119 local-mac-address = [ 00 00 00 00 00 00 ]; 120 local-mac-address = [ 00 00 00 00 00 00 ];
120 interrupts = <7 1>; 121 interrupts = <7 1>;
121 interrupt-parent = <&PIC>; 122 interrupt-parent = <&PIC>;
@@ -126,7 +127,7 @@
126 PIC: interrupt-controller@0 { 127 PIC: interrupt-controller@0 {
127 interrupt-controller; 128 interrupt-controller;
128 #interrupt-cells = <2>; 129 #interrupt-cells = <2>;
129 reg = <0 24>; 130 reg = <0x0 0x24>;
130 compatible = "fsl,mpc885-pic", "fsl,pq1-pic"; 131 compatible = "fsl,mpc885-pic", "fsl,pq1-pic";
131 }; 132 };
132 133
@@ -136,29 +137,29 @@
136 #size-cells = <2>; 137 #size-cells = <2>;
137 compatible = "fsl,pq-pcmcia"; 138 compatible = "fsl,pq-pcmcia";
138 device_type = "pcmcia"; 139 device_type = "pcmcia";
139 reg = <80 80>; 140 reg = <0x80 0x80>;
140 interrupt-parent = <&PIC>; 141 interrupt-parent = <&PIC>;
141 interrupts = <d 1>; 142 interrupts = <13 1>;
142 }; 143 };
143 144
144 cpm@9c0 { 145 cpm@9c0 {
145 #address-cells = <1>; 146 #address-cells = <1>;
146 #size-cells = <1>; 147 #size-cells = <1>;
147 compatible = "fsl,mpc885-cpm", "fsl,cpm1"; 148 compatible = "fsl,mpc885-cpm", "fsl,cpm1";
148 command-proc = <9c0>; 149 command-proc = <0x9c0>;
149 interrupts = <0>; // cpm error interrupt 150 interrupts = <0>; // cpm error interrupt
150 interrupt-parent = <&CPM_PIC>; 151 interrupt-parent = <&CPM_PIC>;
151 reg = <9c0 40>; 152 reg = <0x9c0 0x40>;
152 ranges; 153 ranges;
153 154
154 muram@2000 { 155 muram@2000 {
155 #address-cells = <1>; 156 #address-cells = <1>;
156 #size-cells = <1>; 157 #size-cells = <1>;
157 ranges = <0 2000 2000>; 158 ranges = <0x0 0x2000 0x2000>;
158 159
159 data@0 { 160 data@0 {
160 compatible = "fsl,cpm-muram-data"; 161 compatible = "fsl,cpm-muram-data";
161 reg = <0 1c00>; 162 reg = <0x0 0x1c00>;
162 }; 163 };
163 }; 164 };
164 165
@@ -167,7 +168,7 @@
167 "fsl,cpm1-brg", 168 "fsl,cpm1-brg",
168 "fsl,cpm-brg"; 169 "fsl,cpm-brg";
169 clock-frequency = <0>; 170 clock-frequency = <0>;
170 reg = <9f0 10>; 171 reg = <0x9f0 0x10>;
171 }; 172 };
172 173
173 CPM_PIC: interrupt-controller@930 { 174 CPM_PIC: interrupt-controller@930 {
@@ -175,7 +176,7 @@
175 #interrupt-cells = <1>; 176 #interrupt-cells = <1>;
176 interrupts = <5 2 0 2>; 177 interrupts = <5 2 0 2>;
177 interrupt-parent = <&PIC>; 178 interrupt-parent = <&PIC>;
178 reg = <930 20>; 179 reg = <0x930 0x20>;
179 compatible = "fsl,mpc885-cpm-pic", 180 compatible = "fsl,mpc885-cpm-pic",
180 "fsl,cpm1-pic"; 181 "fsl,cpm1-pic";
181 }; 182 };
@@ -184,34 +185,34 @@
184 device_type = "serial"; 185 device_type = "serial";
185 compatible = "fsl,mpc885-smc-uart", 186 compatible = "fsl,mpc885-smc-uart",
186 "fsl,cpm1-smc-uart"; 187 "fsl,cpm1-smc-uart";
187 reg = <a80 10 3e80 40>; 188 reg = <0xa80 0x10 0x3e80 0x40>;
188 interrupts = <4>; 189 interrupts = <4>;
189 interrupt-parent = <&CPM_PIC>; 190 interrupt-parent = <&CPM_PIC>;
190 fsl,cpm-brg = <1>; 191 fsl,cpm-brg = <1>;
191 fsl,cpm-command = <0090>; 192 fsl,cpm-command = <0x90>;
192 }; 193 };
193 194
194 serial@a90 { 195 serial@a90 {
195 device_type = "serial"; 196 device_type = "serial";
196 compatible = "fsl,mpc885-smc-uart", 197 compatible = "fsl,mpc885-smc-uart",
197 "fsl,cpm1-smc-uart"; 198 "fsl,cpm1-smc-uart";
198 reg = <a90 10 3f80 40>; 199 reg = <0xa90 0x10 0x3f80 0x40>;
199 interrupts = <3>; 200 interrupts = <3>;
200 interrupt-parent = <&CPM_PIC>; 201 interrupt-parent = <&CPM_PIC>;
201 fsl,cpm-brg = <2>; 202 fsl,cpm-brg = <2>;
202 fsl,cpm-command = <00d0>; 203 fsl,cpm-command = <0xd0>;
203 }; 204 };
204 205
205 ethernet@a40 { 206 ethernet@a40 {
206 device_type = "network"; 207 device_type = "network";
207 compatible = "fsl,mpc885-scc-enet", 208 compatible = "fsl,mpc885-scc-enet",
208 "fsl,cpm1-scc-enet"; 209 "fsl,cpm1-scc-enet";
209 reg = <a40 18 3e00 100>; 210 reg = <0xa40 0x18 0x3e00 0x100>;
210 local-mac-address = [ 00 00 00 00 00 00 ]; 211 local-mac-address = [ 00 00 00 00 00 00 ];
211 interrupts = <1c>; 212 interrupts = <28>;
212 interrupt-parent = <&CPM_PIC>; 213 interrupt-parent = <&CPM_PIC>;
213 phy-handle = <&PHY2>; 214 phy-handle = <&PHY2>;
214 fsl,cpm-command = <0080>; 215 fsl,cpm-command = <0x80>;
215 linux,network-index = <2>; 216 linux,network-index = <2>;
216 }; 217 };
217 }; 218 };
diff --git a/arch/powerpc/boot/dts/pq2fads.dts b/arch/powerpc/boot/dts/pq2fads.dts
index 2d564921897a..b2d61091b36d 100644
--- a/arch/powerpc/boot/dts/pq2fads.dts
+++ b/arch/powerpc/boot/dts/pq2fads.dts
@@ -1,7 +1,7 @@
1/* 1/*
2 * Device Tree for the PQ2FADS-ZU board with an MPC8280 chip. 2 * Device Tree for the PQ2FADS-ZU board with an MPC8280 chip.
3 * 3 *
4 * Copyright 2007 Freescale Semiconductor Inc. 4 * Copyright 2007,2008 Freescale Semiconductor Inc.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the 7 * under the terms of the GNU General Public License as published by the
@@ -9,6 +9,8 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/dts-v1/;
13
12/ { 14/ {
13 model = "pq2fads"; 15 model = "pq2fads";
14 compatible = "fsl,pq2fads"; 16 compatible = "fsl,pq2fads";
@@ -21,11 +23,11 @@
21 23
22 cpu@0 { 24 cpu@0 {
23 device_type = "cpu"; 25 device_type = "cpu";
24 reg = <0>; 26 reg = <0x0>;
25 d-cache-line-size = <d#32>; 27 d-cache-line-size = <32>;
26 i-cache-line-size = <d#32>; 28 i-cache-line-size = <32>;
27 d-cache-size = <d#16384>; 29 d-cache-size = <16384>;
28 i-cache-size = <d#16384>; 30 i-cache-size = <16384>;
29 timebase-frequency = <0>; 31 timebase-frequency = <0>;
30 clock-frequency = <0>; 32 clock-frequency = <0>;
31 }; 33 };
@@ -33,7 +35,7 @@
33 35
34 memory { 36 memory {
35 device_type = "memory"; 37 device_type = "memory";
36 reg = <0 0>; 38 reg = <0x0 0x0>;
37 }; 39 };
38 40
39 localbus@f0010100 { 41 localbus@f0010100 {
@@ -41,67 +43,67 @@
41 "fsl,pq2-localbus"; 43 "fsl,pq2-localbus";
42 #address-cells = <2>; 44 #address-cells = <2>;
43 #size-cells = <1>; 45 #size-cells = <1>;
44 reg = <f0010100 60>; 46 reg = <0xf0010100 0x60>;
45 47
46 ranges = <0 0 fe000000 00800000 48 ranges = <0x0 0x0 0xfe000000 0x800000
47 1 0 f4500000 00008000 49 0x1 0x0 0xf4500000 0x8000
48 8 0 f8200000 00008000>; 50 0x8 0x0 0xf8200000 0x8000>;
49 51
50 flash@0,0 { 52 flash@0,0 {
51 compatible = "jedec-flash"; 53 compatible = "jedec-flash";
52 reg = <0 0 800000>; 54 reg = <0x0 0x0 0x800000>;
53 bank-width = <4>; 55 bank-width = <4>;
54 device-width = <1>; 56 device-width = <1>;
55 }; 57 };
56 58
57 bcsr@1,0 { 59 bcsr@1,0 {
58 reg = <1 0 20>; 60 reg = <0x1 0x0 0x20>;
59 compatible = "fsl,pq2fads-bcsr"; 61 compatible = "fsl,pq2fads-bcsr";
60 }; 62 };
61 63
62 PCI_PIC: pic@8,0 { 64 PCI_PIC: pic@8,0 {
63 #interrupt-cells = <1>; 65 #interrupt-cells = <1>;
64 interrupt-controller; 66 interrupt-controller;
65 reg = <8 0 8>; 67 reg = <0x8 0x0 0x8>;
66 compatible = "fsl,pq2ads-pci-pic"; 68 compatible = "fsl,pq2ads-pci-pic";
67 interrupt-parent = <&PIC>; 69 interrupt-parent = <&PIC>;
68 interrupts = <18 8>; 70 interrupts = <24 8>;
69 }; 71 };
70 }; 72 };
71 73
72 pci@f0010800 { 74 pci@f0010800 {
73 device_type = "pci"; 75 device_type = "pci";
74 reg = <f0010800 10c f00101ac 8 f00101c4 8>; 76 reg = <0xf0010800 0x10c 0xf00101ac 0x8 0xf00101c4 0x8>;
75 compatible = "fsl,mpc8280-pci", "fsl,pq2-pci"; 77 compatible = "fsl,mpc8280-pci", "fsl,pq2-pci";
76 #interrupt-cells = <1>; 78 #interrupt-cells = <1>;
77 #size-cells = <2>; 79 #size-cells = <2>;
78 #address-cells = <3>; 80 #address-cells = <3>;
79 clock-frequency = <d#66000000>; 81 clock-frequency = <66000000>;
80 interrupt-map-mask = <f800 0 0 7>; 82 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
81 interrupt-map = < 83 interrupt-map = <
82 /* IDSEL 0x16 */ 84 /* IDSEL 0x16 */
83 b000 0 0 1 &PCI_PIC 0 85 0xb000 0x0 0x0 0x1 &PCI_PIC 0
84 b000 0 0 2 &PCI_PIC 1 86 0xb000 0x0 0x0 0x2 &PCI_PIC 1
85 b000 0 0 3 &PCI_PIC 2 87 0xb000 0x0 0x0 0x3 &PCI_PIC 2
86 b000 0 0 4 &PCI_PIC 3 88 0xb000 0x0 0x0 0x4 &PCI_PIC 3
87 89
88 /* IDSEL 0x17 */ 90 /* IDSEL 0x17 */
89 b800 0 0 1 &PCI_PIC 4 91 0xb800 0x0 0x0 0x1 &PCI_PIC 4
90 b800 0 0 2 &PCI_PIC 5 92 0xb800 0x0 0x0 0x2 &PCI_PIC 5
91 b800 0 0 3 &PCI_PIC 6 93 0xb800 0x0 0x0 0x3 &PCI_PIC 6
92 b800 0 0 4 &PCI_PIC 7 94 0xb800 0x0 0x0 0x4 &PCI_PIC 7
93 95
94 /* IDSEL 0x18 */ 96 /* IDSEL 0x18 */
95 c000 0 0 1 &PCI_PIC 8 97 0xc000 0x0 0x0 0x1 &PCI_PIC 8
96 c000 0 0 2 &PCI_PIC 9 98 0xc000 0x0 0x0 0x2 &PCI_PIC 9
97 c000 0 0 3 &PCI_PIC a 99 0xc000 0x0 0x0 0x3 &PCI_PIC 10
98 c000 0 0 4 &PCI_PIC b>; 100 0xc000 0x0 0x0 0x4 &PCI_PIC 11>;
99 101
100 interrupt-parent = <&PIC>; 102 interrupt-parent = <&PIC>;
101 interrupts = <12 8>; 103 interrupts = <18 8>;
102 ranges = <42000000 0 80000000 80000000 0 20000000 104 ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x20000000
103 02000000 0 a0000000 a0000000 0 20000000 105 0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
104 01000000 0 00000000 f6000000 0 02000000>; 106 0x1000000 0x0 0x0 0xf6000000 0x0 0x2000000>;
105 }; 107 };
106 108
107 soc@f0000000 { 109 soc@f0000000 {
@@ -109,27 +111,27 @@
109 #size-cells = <1>; 111 #size-cells = <1>;
110 device_type = "soc"; 112 device_type = "soc";
111 compatible = "fsl,mpc8280", "fsl,pq2-soc"; 113 compatible = "fsl,mpc8280", "fsl,pq2-soc";
112 ranges = <00000000 f0000000 00053000>; 114 ranges = <0x0 0xf0000000 0x53000>;
113 115
114 // Temporary -- will go away once kernel uses ranges for get_immrbase(). 116 // Temporary -- will go away once kernel uses ranges for get_immrbase().
115 reg = <f0000000 00053000>; 117 reg = <0xf0000000 0x53000>;
116 118
117 cpm@119c0 { 119 cpm@119c0 {
118 #address-cells = <1>; 120 #address-cells = <1>;
119 #size-cells = <1>; 121 #size-cells = <1>;
120 #interrupt-cells = <2>; 122 #interrupt-cells = <2>;
121 compatible = "fsl,mpc8280-cpm", "fsl,cpm2"; 123 compatible = "fsl,mpc8280-cpm", "fsl,cpm2";
122 reg = <119c0 30>; 124 reg = <0x119c0 0x30>;
123 ranges; 125 ranges;
124 126
125 muram@0 { 127 muram@0 {
126 #address-cells = <1>; 128 #address-cells = <1>;
127 #size-cells = <1>; 129 #size-cells = <1>;
128 ranges = <0 0 10000>; 130 ranges = <0x0 0x0 0x10000>;
129 131
130 data@0 { 132 data@0 {
131 compatible = "fsl,cpm-muram-data"; 133 compatible = "fsl,cpm-muram-data";
132 reg = <0 2000 9800 800>; 134 reg = <0x0 0x2000 0x9800 0x800>;
133 }; 135 };
134 }; 136 };
135 137
@@ -137,53 +139,53 @@
137 compatible = "fsl,mpc8280-brg", 139 compatible = "fsl,mpc8280-brg",
138 "fsl,cpm2-brg", 140 "fsl,cpm2-brg",
139 "fsl,cpm-brg"; 141 "fsl,cpm-brg";
140 reg = <119f0 10 115f0 10>; 142 reg = <0x119f0 0x10 0x115f0 0x10>;
141 }; 143 };
142 144
143 serial@11a00 { 145 serial@11a00 {
144 device_type = "serial"; 146 device_type = "serial";
145 compatible = "fsl,mpc8280-scc-uart", 147 compatible = "fsl,mpc8280-scc-uart",
146 "fsl,cpm2-scc-uart"; 148 "fsl,cpm2-scc-uart";
147 reg = <11a00 20 8000 100>; 149 reg = <0x11a00 0x20 0x8000 0x100>;
148 interrupts = <28 8>; 150 interrupts = <40 8>;
149 interrupt-parent = <&PIC>; 151 interrupt-parent = <&PIC>;
150 fsl,cpm-brg = <1>; 152 fsl,cpm-brg = <1>;
151 fsl,cpm-command = <00800000>; 153 fsl,cpm-command = <0x800000>;
152 }; 154 };
153 155
154 serial@11a20 { 156 serial@11a20 {
155 device_type = "serial"; 157 device_type = "serial";
156 compatible = "fsl,mpc8280-scc-uart", 158 compatible = "fsl,mpc8280-scc-uart",
157 "fsl,cpm2-scc-uart"; 159 "fsl,cpm2-scc-uart";
158 reg = <11a20 20 8100 100>; 160 reg = <0x11a20 0x20 0x8100 0x100>;
159 interrupts = <29 8>; 161 interrupts = <41 8>;
160 interrupt-parent = <&PIC>; 162 interrupt-parent = <&PIC>;
161 fsl,cpm-brg = <2>; 163 fsl,cpm-brg = <2>;
162 fsl,cpm-command = <04a00000>; 164 fsl,cpm-command = <0x4a00000>;
163 }; 165 };
164 166
165 ethernet@11320 { 167 ethernet@11320 {
166 device_type = "network"; 168 device_type = "network";
167 compatible = "fsl,mpc8280-fcc-enet", 169 compatible = "fsl,mpc8280-fcc-enet",
168 "fsl,cpm2-fcc-enet"; 170 "fsl,cpm2-fcc-enet";
169 reg = <11320 20 8500 100 113b0 1>; 171 reg = <0x11320 0x20 0x8500 0x100 0x113b0 0x1>;
170 interrupts = <21 8>; 172 interrupts = <33 8>;
171 interrupt-parent = <&PIC>; 173 interrupt-parent = <&PIC>;
172 phy-handle = <&PHY0>; 174 phy-handle = <&PHY0>;
173 linux,network-index = <0>; 175 linux,network-index = <0>;
174 fsl,cpm-command = <16200300>; 176 fsl,cpm-command = <0x16200300>;
175 }; 177 };
176 178
177 ethernet@11340 { 179 ethernet@11340 {
178 device_type = "network"; 180 device_type = "network";
179 compatible = "fsl,mpc8280-fcc-enet", 181 compatible = "fsl,mpc8280-fcc-enet",
180 "fsl,cpm2-fcc-enet"; 182 "fsl,cpm2-fcc-enet";
181 reg = <11340 20 8600 100 113d0 1>; 183 reg = <0x11340 0x20 0x8600 0x100 0x113d0 0x1>;
182 interrupts = <22 8>; 184 interrupts = <34 8>;
183 interrupt-parent = <&PIC>; 185 interrupt-parent = <&PIC>;
184 phy-handle = <&PHY1>; 186 phy-handle = <&PHY1>;
185 linux,network-index = <1>; 187 linux,network-index = <1>;
186 fsl,cpm-command = <1a400300>; 188 fsl,cpm-command = <0x1a400300>;
187 local-mac-address = [00 e0 0c 00 79 01]; 189 local-mac-address = [00 e0 0c 00 79 01];
188 }; 190 };
189 191
@@ -194,21 +196,21 @@
194 "fsl,cpm2-mdio-bitbang"; 196 "fsl,cpm2-mdio-bitbang";
195 #address-cells = <1>; 197 #address-cells = <1>;
196 #size-cells = <0>; 198 #size-cells = <0>;
197 reg = <10d40 14>; 199 reg = <0x10d40 0x14>;
198 fsl,mdio-pin = <9>; 200 fsl,mdio-pin = <9>;
199 fsl,mdc-pin = <a>; 201 fsl,mdc-pin = <10>;
200 202
201 PHY0: ethernet-phy@0 { 203 PHY0: ethernet-phy@0 {
202 interrupt-parent = <&PIC>; 204 interrupt-parent = <&PIC>;
203 interrupts = <19 2>; 205 interrupts = <25 2>;
204 reg = <0>; 206 reg = <0x0>;
205 device_type = "ethernet-phy"; 207 device_type = "ethernet-phy";
206 }; 208 };
207 209
208 PHY1: ethernet-phy@1 { 210 PHY1: ethernet-phy@1 {
209 interrupt-parent = <&PIC>; 211 interrupt-parent = <&PIC>;
210 interrupts = <19 2>; 212 interrupts = <25 2>;
211 reg = <3>; 213 reg = <0x3>;
212 device_type = "ethernet-phy"; 214 device_type = "ethernet-phy";
213 }; 215 };
214 }; 216 };
@@ -218,17 +220,17 @@
218 #size-cells = <0>; 220 #size-cells = <0>;
219 compatible = "fsl,mpc8280-usb", 221 compatible = "fsl,mpc8280-usb",
220 "fsl,cpm2-usb"; 222 "fsl,cpm2-usb";
221 reg = <11b60 18 8b00 100>; 223 reg = <0x11b60 0x18 0x8b00 0x100>;
222 interrupt-parent = <&PIC>; 224 interrupt-parent = <&PIC>;
223 interrupts = <b 8>; 225 interrupts = <11 8>;
224 fsl,cpm-command = <2e600000>; 226 fsl,cpm-command = <0x2e600000>;
225 }; 227 };
226 }; 228 };
227 229
228 PIC: interrupt-controller@10c00 { 230 PIC: interrupt-controller@10c00 {
229 #interrupt-cells = <2>; 231 #interrupt-cells = <2>;
230 interrupt-controller; 232 interrupt-controller;
231 reg = <10c00 80>; 233 reg = <0x10c00 0x80>;
232 compatible = "fsl,mpc8280-pic", "fsl,cpm2-pic"; 234 compatible = "fsl,mpc8280-pic", "fsl,cpm2-pic";
233 }; 235 };
234 236
diff --git a/arch/powerpc/boot/dts/prpmc2800.dts b/arch/powerpc/boot/dts/prpmc2800.dts
index 297dfa53fe9e..1ee6ff43dd57 100644
--- a/arch/powerpc/boot/dts/prpmc2800.dts
+++ b/arch/powerpc/boot/dts/prpmc2800.dts
@@ -11,6 +11,8 @@
11 * if it can determine the exact PrPMC type. 11 * if it can determine the exact PrPMC type.
12 */ 12 */
13 13
14/dts-v1/;
15
14/ { 16/ {
15 #address-cells = <1>; 17 #address-cells = <1>;
16 #size-cells = <1>; 18 #size-cells = <1>;
@@ -25,46 +27,46 @@
25 PowerPC,7447 { 27 PowerPC,7447 {
26 device_type = "cpu"; 28 device_type = "cpu";
27 reg = <0>; 29 reg = <0>;
28 clock-frequency = <2bb0b140>; /* Default (733 MHz) */ 30 clock-frequency = <733333333>; /* Default */
29 bus-frequency = <7f28155>; /* 133.333333 MHz */ 31 bus-frequency = <133333333>;
30 timebase-frequency = <1fca055>; /* 33.333333 MHz */ 32 timebase-frequency = <33333333>;
31 i-cache-line-size = <20>; 33 i-cache-line-size = <32>;
32 d-cache-line-size = <20>; 34 d-cache-line-size = <32>;
33 i-cache-size = <8000>; 35 i-cache-size = <32768>;
34 d-cache-size = <8000>; 36 d-cache-size = <32768>;
35 }; 37 };
36 }; 38 };
37 39
38 memory { 40 memory {
39 device_type = "memory"; 41 device_type = "memory";
40 reg = <00000000 20000000>; /* Default (512MB) */ 42 reg = <0x0 0x20000000>; /* Default (512MB) */
41 }; 43 };
42 44
43 mv64x60@f1000000 { /* Marvell Discovery */ 45 system-controller@f1000000 { /* Marvell Discovery mv64360 */
44 #address-cells = <1>; 46 #address-cells = <1>;
45 #size-cells = <1>; 47 #size-cells = <1>;
46 model = "mv64360"; /* Default */ 48 model = "mv64360"; /* Default */
47 compatible = "marvell,mv64x60"; 49 compatible = "marvell,mv64360";
48 clock-frequency = <7f28155>; /* 133.333333 MHz */ 50 clock-frequency = <133333333>;
49 reg = <f1000000 00010000>; 51 reg = <0xf1000000 0x10000>;
50 virtual-reg = <f1000000>; 52 virtual-reg = <0xf1000000>;
51 ranges = <88000000 88000000 01000000 /* PCI 0 I/O Space */ 53 ranges = <0x88000000 0x88000000 0x1000000 /* PCI 0 I/O Space */
52 80000000 80000000 08000000 /* PCI 0 MEM Space */ 54 0x80000000 0x80000000 0x8000000 /* PCI 0 MEM Space */
53 a0000000 a0000000 04000000 /* User FLASH */ 55 0xa0000000 0xa0000000 0x4000000 /* User FLASH */
54 00000000 f1000000 00010000 /* Bridge's regs */ 56 0x00000000 0xf1000000 0x0010000 /* Bridge's regs */
55 f2000000 f2000000 00040000>; /* Integrated SRAM */ 57 0xf2000000 0xf2000000 0x0040000>;/* Integrated SRAM */
56 58
57 flash@a0000000 { 59 flash@a0000000 {
58 device_type = "rom"; 60 device_type = "rom";
59 compatible = "direct-mapped"; 61 compatible = "direct-mapped";
60 reg = <a0000000 4000000>; /* Default (64MB) */ 62 reg = <0xa0000000 0x4000000>; /* Default (64MB) */
61 probe-type = "CFI"; 63 probe-type = "CFI";
62 bank-width = <4>; 64 bank-width = <4>;
63 partitions = <00000000 00100000 /* RO */ 65 partitions = <0x00000000 0x00100000 /* RO */
64 00100000 00040001 /* RW */ 66 0x00100000 0x00040001 /* RW */
65 00140000 00400000 /* RO */ 67 0x00140000 0x00400000 /* RO */
66 00540000 039c0000 /* RO */ 68 0x00540000 0x039c0000 /* RO */
67 03f00000 00100000>; /* RO */ 69 0x03f00000 0x00100000>; /* RO */
68 partition-names = "FW Image A", "FW Config Data", "Kernel Image", "Filesystem", "FW Image B"; 70 partition-names = "FW Image A", "FW Config Data", "Kernel Image", "Filesystem", "FW Image B";
69 }; 71 };
70 72
@@ -72,171 +74,153 @@
72 #address-cells = <1>; 74 #address-cells = <1>;
73 #size-cells = <0>; 75 #size-cells = <0>;
74 device_type = "mdio"; 76 device_type = "mdio";
75 compatible = "marvell,mv64x60-mdio"; 77 compatible = "marvell,mv64360-mdio";
76 ethernet-phy@1 { 78 PHY0: ethernet-phy@1 {
77 device_type = "ethernet-phy"; 79 device_type = "ethernet-phy";
78 compatible = "broadcom,bcm5421"; 80 compatible = "broadcom,bcm5421";
79 interrupts = <4c>; /* GPP 12 */ 81 interrupts = <76>; /* GPP 12 */
80 interrupt-parent = <&/mv64x60/pic>; 82 interrupt-parent = <&PIC>;
81 reg = <1>; 83 reg = <1>;
82 }; 84 };
83 ethernet-phy@3 { 85 PHY1: ethernet-phy@3 {
84 device_type = "ethernet-phy"; 86 device_type = "ethernet-phy";
85 compatible = "broadcom,bcm5421"; 87 compatible = "broadcom,bcm5421";
86 interrupts = <4c>; /* GPP 12 */ 88 interrupts = <76>; /* GPP 12 */
87 interrupt-parent = <&/mv64x60/pic>; 89 interrupt-parent = <&PIC>;
88 reg = <3>; 90 reg = <3>;
89 }; 91 };
90 }; 92 };
91 93
92 ethernet@2000 { 94 ethernet-group@2000 {
93 reg = <2000 2000>; 95 #address-cells = <1>;
94 eth0 { 96 #size-cells = <0>;
97 compatible = "marvell,mv64360-eth-group";
98 reg = <0x2000 0x2000>;
99 ethernet@0 {
95 device_type = "network"; 100 device_type = "network";
96 compatible = "marvell,mv64x60-eth"; 101 compatible = "marvell,mv64360-eth";
97 block-index = <0>; 102 reg = <0>;
98 interrupts = <20>; 103 interrupts = <32>;
99 interrupt-parent = <&/mv64x60/pic>; 104 interrupt-parent = <&PIC>;
100 phy = <&/mv64x60/mdio/ethernet-phy@1>; 105 phy = <&PHY0>;
101 local-mac-address = [ 00 00 00 00 00 00 ]; 106 local-mac-address = [ 00 00 00 00 00 00 ];
102 }; 107 };
103 eth1 { 108 ethernet@1 {
104 device_type = "network"; 109 device_type = "network";
105 compatible = "marvell,mv64x60-eth"; 110 compatible = "marvell,mv64360-eth";
106 block-index = <1>; 111 reg = <1>;
107 interrupts = <21>; 112 interrupts = <33>;
108 interrupt-parent = <&/mv64x60/pic>; 113 interrupt-parent = <&PIC>;
109 phy = <&/mv64x60/mdio/ethernet-phy@3>; 114 phy = <&PHY1>;
110 local-mac-address = [ 00 00 00 00 00 00 ]; 115 local-mac-address = [ 00 00 00 00 00 00 ];
111 }; 116 };
112 }; 117 };
113 118
114 sdma@4000 { 119 SDMA0: sdma@4000 {
115 device_type = "dma"; 120 compatible = "marvell,mv64360-sdma";
116 compatible = "marvell,mv64x60-sdma"; 121 reg = <0x4000 0xc18>;
117 reg = <4000 c18>; 122 virtual-reg = <0xf1004000>;
118 virtual-reg = <f1004000>; 123 interrupts = <36>;
119 interrupt-base = <0>; 124 interrupt-parent = <&PIC>;
120 interrupts = <24>;
121 interrupt-parent = <&/mv64x60/pic>;
122 }; 125 };
123 126
124 sdma@6000 { 127 SDMA1: sdma@6000 {
125 device_type = "dma"; 128 compatible = "marvell,mv64360-sdma";
126 compatible = "marvell,mv64x60-sdma"; 129 reg = <0x6000 0xc18>;
127 reg = <6000 c18>; 130 virtual-reg = <0xf1006000>;
128 virtual-reg = <f1006000>; 131 interrupts = <38>;
129 interrupt-base = <0>; 132 interrupt-parent = <&PIC>;
130 interrupts = <26>;
131 interrupt-parent = <&/mv64x60/pic>;
132 }; 133 };
133 134
134 brg@b200 { 135 BRG0: brg@b200 {
135 compatible = "marvell,mv64x60-brg"; 136 compatible = "marvell,mv64360-brg";
136 reg = <b200 8>; 137 reg = <0xb200 0x8>;
137 clock-src = <8>; 138 clock-src = <8>;
138 clock-frequency = <7ed6b40>; 139 clock-frequency = <133333333>;
139 current-speed = <2580>; 140 current-speed = <9600>;
140 bcr = <0>;
141 }; 141 };
142 142
143 brg@b208 { 143 BRG1: brg@b208 {
144 compatible = "marvell,mv64x60-brg"; 144 compatible = "marvell,mv64360-brg";
145 reg = <b208 8>; 145 reg = <0xb208 0x8>;
146 clock-src = <8>; 146 clock-src = <8>;
147 clock-frequency = <7ed6b40>; 147 clock-frequency = <133333333>;
148 current-speed = <2580>; 148 current-speed = <9600>;
149 bcr = <0>;
150 }; 149 };
151 150
152 cunit@f200 { 151 CUNIT: cunit@f200 {
153 reg = <f200 200>; 152 reg = <0xf200 0x200>;
154 }; 153 };
155 154
156 mpscrouting@b400 { 155 MPSCROUTING: mpscrouting@b400 {
157 reg = <b400 c>; 156 reg = <0xb400 0xc>;
158 }; 157 };
159 158
160 mpscintr@b800 { 159 MPSCINTR: mpscintr@b800 {
161 reg = <b800 100>; 160 reg = <0xb800 0x100>;
162 virtual-reg = <f100b800>; 161 virtual-reg = <0xf100b800>;
163 }; 162 };
164 163
165 mpsc@8000 { 164 MPSC0: mpsc@8000 {
166 device_type = "serial"; 165 device_type = "serial";
167 compatible = "marvell,mpsc"; 166 compatible = "marvell,mv64360-mpsc";
168 reg = <8000 38>; 167 reg = <0x8000 0x38>;
169 virtual-reg = <f1008000>; 168 virtual-reg = <0xf1008000>;
170 sdma = <&/mv64x60/sdma@4000>; 169 sdma = <&SDMA0>;
171 brg = <&/mv64x60/brg@b200>; 170 brg = <&BRG0>;
172 cunit = <&/mv64x60/cunit@f200>; 171 cunit = <&CUNIT>;
173 mpscrouting = <&/mv64x60/mpscrouting@b400>; 172 mpscrouting = <&MPSCROUTING>;
174 mpscintr = <&/mv64x60/mpscintr@b800>; 173 mpscintr = <&MPSCINTR>;
175 block-index = <0>; 174 cell-index = <0>;
176 max_idle = <28>; 175 interrupts = <40>;
177 chr_1 = <0>; 176 interrupt-parent = <&PIC>;
178 chr_2 = <0>;
179 chr_10 = <3>;
180 mpcr = <0>;
181 interrupts = <28>;
182 interrupt-parent = <&/mv64x60/pic>;
183 }; 177 };
184 178
185 mpsc@9000 { 179 MPSC1: mpsc@9000 {
186 device_type = "serial"; 180 device_type = "serial";
187 compatible = "marvell,mpsc"; 181 compatible = "marvell,mv64360-mpsc";
188 reg = <9000 38>; 182 reg = <0x9000 0x38>;
189 virtual-reg = <f1009000>; 183 virtual-reg = <0xf1009000>;
190 sdma = <&/mv64x60/sdma@6000>; 184 sdma = <&SDMA1>;
191 brg = <&/mv64x60/brg@b208>; 185 brg = <&BRG1>;
192 cunit = <&/mv64x60/cunit@f200>; 186 cunit = <&CUNIT>;
193 mpscrouting = <&/mv64x60/mpscrouting@b400>; 187 mpscrouting = <&MPSCROUTING>;
194 mpscintr = <&/mv64x60/mpscintr@b800>; 188 mpscintr = <&MPSCINTR>;
195 block-index = <1>; 189 cell-index = <1>;
196 max_idle = <28>; 190 interrupts = <42>;
197 chr_1 = <0>; 191 interrupt-parent = <&PIC>;
198 chr_2 = <0>;
199 chr_10 = <3>;
200 mpcr = <0>;
201 interrupts = <2a>;
202 interrupt-parent = <&/mv64x60/pic>;
203 }; 192 };
204 193
205 wdt@b410 { /* watchdog timer */ 194 wdt@b410 { /* watchdog timer */
206 compatible = "marvell,mv64x60-wdt"; 195 compatible = "marvell,mv64360-wdt";
207 reg = <b410 8>; 196 reg = <0xb410 0x8>;
208 timeout = <a>; /* wdt timeout in seconds */
209 }; 197 };
210 198
211 i2c@c000 { 199 i2c@c000 {
212 device_type = "i2c"; 200 device_type = "i2c";
213 compatible = "marvell,mv64x60-i2c"; 201 compatible = "marvell,mv64360-i2c";
214 reg = <c000 20>; 202 reg = <0xc000 0x20>;
215 virtual-reg = <f100c000>; 203 virtual-reg = <0xf100c000>;
216 freq_m = <8>; 204 interrupts = <37>;
217 freq_n = <3>; 205 interrupt-parent = <&PIC>;
218 timeout = <3e8>; /* 1000 = 1 second */
219 retries = <1>;
220 interrupts = <25>;
221 interrupt-parent = <&/mv64x60/pic>;
222 }; 206 };
223 207
224 pic { 208 PIC: pic {
225 #interrupt-cells = <1>; 209 #interrupt-cells = <1>;
226 #address-cells = <0>; 210 #address-cells = <0>;
227 compatible = "marvell,mv64x60-pic"; 211 compatible = "marvell,mv64360-pic";
228 reg = <0000 88>; 212 reg = <0x0 0x88>;
229 interrupt-controller; 213 interrupt-controller;
230 }; 214 };
231 215
232 mpp@f000 { 216 mpp@f000 {
233 compatible = "marvell,mv64x60-mpp"; 217 compatible = "marvell,mv64360-mpp";
234 reg = <f000 10>; 218 reg = <0xf000 0x10>;
235 }; 219 };
236 220
237 gpp@f100 { 221 gpp@f100 {
238 compatible = "marvell,mv64x60-gpp"; 222 compatible = "marvell,mv64360-gpp";
239 reg = <f100 20>; 223 reg = <0xf100 0x20>;
240 }; 224 };
241 225
242 pci@80000000 { 226 pci@80000000 {
@@ -244,73 +228,75 @@
244 #size-cells = <2>; 228 #size-cells = <2>;
245 #interrupt-cells = <1>; 229 #interrupt-cells = <1>;
246 device_type = "pci"; 230 device_type = "pci";
247 compatible = "marvell,mv64x60-pci"; 231 compatible = "marvell,mv64360-pci";
248 reg = <0cf8 8>; 232 reg = <0xcf8 0x8>;
249 ranges = <01000000 0 0 88000000 0 01000000 233 ranges = <0x01000000 0x0 0x0
250 02000000 0 80000000 80000000 0 08000000>; 234 0x88000000 0x0 0x01000000
251 bus-range = <0 ff>; 235 0x02000000 0x0 0x80000000
252 clock-frequency = <3EF1480>; 236 0x80000000 0x0 0x08000000>;
253 interrupt-pci-iack = <0c34>; 237 bus-range = <0 255>;
254 interrupt-parent = <&/mv64x60/pic>; 238 clock-frequency = <66000000>;
255 interrupt-map-mask = <f800 0 0 7>; 239 interrupt-pci-iack = <0xc34>;
240 interrupt-parent = <&PIC>;
241 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
256 interrupt-map = < 242 interrupt-map = <
257 /* IDSEL 0x0a */ 243 /* IDSEL 0x0a */
258 5000 0 0 1 &/mv64x60/pic 50 244 0x5000 0 0 1 &PIC 80
259 5000 0 0 2 &/mv64x60/pic 51 245 0x5000 0 0 2 &PIC 81
260 5000 0 0 3 &/mv64x60/pic 5b 246 0x5000 0 0 3 &PIC 91
261 5000 0 0 4 &/mv64x60/pic 5d 247 0x5000 0 0 4 &PIC 93
262 248
263 /* IDSEL 0x0b */ 249 /* IDSEL 0x0b */
264 5800 0 0 1 &/mv64x60/pic 5b 250 0x5800 0 0 1 &PIC 91
265 5800 0 0 2 &/mv64x60/pic 5d 251 0x5800 0 0 2 &PIC 93
266 5800 0 0 3 &/mv64x60/pic 50 252 0x5800 0 0 3 &PIC 80
267 5800 0 0 4 &/mv64x60/pic 51 253 0x5800 0 0 4 &PIC 81
268 254
269 /* IDSEL 0x0c */ 255 /* IDSEL 0x0c */
270 6000 0 0 1 &/mv64x60/pic 5b 256 0x6000 0 0 1 &PIC 91
271 6000 0 0 2 &/mv64x60/pic 5d 257 0x6000 0 0 2 &PIC 93
272 6000 0 0 3 &/mv64x60/pic 50 258 0x6000 0 0 3 &PIC 80
273 6000 0 0 4 &/mv64x60/pic 51 259 0x6000 0 0 4 &PIC 81
274 260
275 /* IDSEL 0x0d */ 261 /* IDSEL 0x0d */
276 6800 0 0 1 &/mv64x60/pic 5d 262 0x6800 0 0 1 &PIC 93
277 6800 0 0 2 &/mv64x60/pic 50 263 0x6800 0 0 2 &PIC 80
278 6800 0 0 3 &/mv64x60/pic 51 264 0x6800 0 0 3 &PIC 81
279 6800 0 0 4 &/mv64x60/pic 5b 265 0x6800 0 0 4 &PIC 91
280 >; 266 >;
281 }; 267 };
282 268
283 cpu-error@0070 { 269 cpu-error@0070 {
284 compatible = "marvell,mv64x60-cpu-error"; 270 compatible = "marvell,mv64360-cpu-error";
285 reg = <0070 10 0128 28>; 271 reg = <0x70 0x10 0x128 0x28>;
286 interrupts = <03>; 272 interrupts = <3>;
287 interrupt-parent = <&/mv64x60/pic>; 273 interrupt-parent = <&PIC>;
288 }; 274 };
289 275
290 sram-ctrl@0380 { 276 sram-ctrl@0380 {
291 compatible = "marvell,mv64x60-sram-ctrl"; 277 compatible = "marvell,mv64360-sram-ctrl";
292 reg = <0380 80>; 278 reg = <0x380 0x80>;
293 interrupts = <0d>; 279 interrupts = <13>;
294 interrupt-parent = <&/mv64x60/pic>; 280 interrupt-parent = <&PIC>;
295 }; 281 };
296 282
297 pci-error@1d40 { 283 pci-error@1d40 {
298 compatible = "marvell,mv64x60-pci-error"; 284 compatible = "marvell,mv64360-pci-error";
299 reg = <1d40 40 0c28 4>; 285 reg = <0x1d40 0x40 0xc28 0x4>;
300 interrupts = <0c>; 286 interrupts = <12>;
301 interrupt-parent = <&/mv64x60/pic>; 287 interrupt-parent = <&PIC>;
302 }; 288 };
303 289
304 mem-ctrl@1400 { 290 mem-ctrl@1400 {
305 compatible = "marvell,mv64x60-mem-ctrl"; 291 compatible = "marvell,mv64360-mem-ctrl";
306 reg = <1400 60>; 292 reg = <0x1400 0x60>;
307 interrupts = <11>; 293 interrupts = <17>;
308 interrupt-parent = <&/mv64x60/pic>; 294 interrupt-parent = <&PIC>;
309 }; 295 };
310 }; 296 };
311 297
312 chosen { 298 chosen {
313 bootargs = "ip=on"; 299 bootargs = "ip=on";
314 linux,stdout-path = "/mv64x60@f1000000/mpsc@8000"; 300 linux,stdout-path = &MPSC0;
315 }; 301 };
316}; 302};
diff --git a/arch/powerpc/boot/dts/rainier.dts b/arch/powerpc/boot/dts/rainier.dts
index f947c75a2e94..6a8fa7089ea2 100644
--- a/arch/powerpc/boot/dts/rainier.dts
+++ b/arch/powerpc/boot/dts/rainier.dts
@@ -254,7 +254,6 @@
254 }; 254 };
255 255
256 EMAC0: ethernet@ef600e00 { 256 EMAC0: ethernet@ef600e00 {
257 linux,network-index = <0>;
258 device_type = "network"; 257 device_type = "network";
259 compatible = "ibm,emac-440grx", "ibm,emac-440epx", "ibm,emac4"; 258 compatible = "ibm,emac-440grx", "ibm,emac-440epx", "ibm,emac4";
260 interrupt-parent = <&EMAC0>; 259 interrupt-parent = <&EMAC0>;
@@ -270,7 +269,7 @@
270 mal-tx-channel = <0>; 269 mal-tx-channel = <0>;
271 mal-rx-channel = <0>; 270 mal-rx-channel = <0>;
272 cell-index = <0>; 271 cell-index = <0>;
273 max-frame-size = <5dc>; 272 max-frame-size = <2328>;
274 rx-fifo-size = <1000>; 273 rx-fifo-size = <1000>;
275 tx-fifo-size = <800>; 274 tx-fifo-size = <800>;
276 phy-mode = "rgmii"; 275 phy-mode = "rgmii";
@@ -284,7 +283,6 @@
284 }; 283 };
285 284
286 EMAC1: ethernet@ef600f00 { 285 EMAC1: ethernet@ef600f00 {
287 linux,network-index = <1>;
288 device_type = "network"; 286 device_type = "network";
289 compatible = "ibm,emac-440grx", "ibm,emac-440epx", "ibm,emac4"; 287 compatible = "ibm,emac-440grx", "ibm,emac-440epx", "ibm,emac4";
290 interrupt-parent = <&EMAC1>; 288 interrupt-parent = <&EMAC1>;
@@ -300,7 +298,7 @@
300 mal-tx-channel = <1>; 298 mal-tx-channel = <1>;
301 mal-rx-channel = <1>; 299 mal-rx-channel = <1>;
302 cell-index = <1>; 300 cell-index = <1>;
303 max-frame-size = <5dc>; 301 max-frame-size = <2328>;
304 rx-fifo-size = <1000>; 302 rx-fifo-size = <1000>;
305 tx-fifo-size = <800>; 303 tx-fifo-size = <800>;
306 phy-mode = "rgmii"; 304 phy-mode = "rgmii";
diff --git a/arch/powerpc/boot/dts/sbc8641d.dts b/arch/powerpc/boot/dts/sbc8641d.dts
new file mode 100644
index 000000000000..3eebeec157b3
--- /dev/null
+++ b/arch/powerpc/boot/dts/sbc8641d.dts
@@ -0,0 +1,352 @@
1/*
2 * SBC8641D Device Tree Source
3 *
4 * Copyright 2008 Wind River Systems Inc.
5 *
6 * Paul Gortmaker (see MAINTAINERS for contact information)
7 *
8 * Based largely on the mpc8641_hpcn.dts by Freescale Semiconductor Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16/dts-v1/;
17
18/ {
19 model = "SBC8641D";
20 compatible = "wind,sbc8641";
21 #address-cells = <1>;
22 #size-cells = <1>;
23
24 aliases {
25 ethernet0 = &enet0;
26 ethernet1 = &enet1;
27 ethernet2 = &enet2;
28 ethernet3 = &enet3;
29 serial0 = &serial0;
30 serial1 = &serial1;
31 pci0 = &pci0;
32 pci1 = &pci1;
33 };
34
35 cpus {
36 #address-cells = <1>;
37 #size-cells = <0>;
38
39 PowerPC,8641@0 {
40 device_type = "cpu";
41 reg = <0>;
42 d-cache-line-size = <32>;
43 i-cache-line-size = <32>;
44 d-cache-size = <32768>; // L1
45 i-cache-size = <32768>; // L1
46 timebase-frequency = <0>; // From uboot
47 bus-frequency = <0>; // From uboot
48 clock-frequency = <0>; // From uboot
49 };
50 PowerPC,8641@1 {
51 device_type = "cpu";
52 reg = <1>;
53 d-cache-line-size = <32>;
54 i-cache-line-size = <32>;
55 d-cache-size = <32768>;
56 i-cache-size = <32768>;
57 timebase-frequency = <0>; // From uboot
58 bus-frequency = <0>; // From uboot
59 clock-frequency = <0>; // From uboot
60 };
61 };
62
63 memory {
64 device_type = "memory";
65 reg = <0x00000000 0x20000000>; // 512M at 0x0
66 };
67
68 localbus@f8005000 {
69 #address-cells = <2>;
70 #size-cells = <1>;
71 compatible = "fsl,mpc8641-localbus", "simple-bus";
72 reg = <0xf8005000 0x1000>;
73 interrupts = <19 2>;
74 interrupt-parent = <&mpic>;
75
76 ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash
77 1 0 0xf0000000 0x00010000 // 64KB EEPROM
78 2 0 0xf1000000 0x00100000 // EPLD (1MB)
79 3 0 0xe0000000 0x04000000 // 64MB LB SDRAM (CS3)
80 4 0 0xe4000000 0x04000000 // 64MB LB SDRAM (CS4)
81 6 0 0xf4000000 0x00100000 // LCD display (1MB)
82 7 0 0xe8000000 0x04000000>; // 64MB OneNAND
83
84 flash@0,0 {
85 compatible = "cfi-flash";
86 reg = <0 0 0x01000000>;
87 bank-width = <2>;
88 device-width = <2>;
89 #address-cells = <1>;
90 #size-cells = <1>;
91 partition@0 {
92 label = "dtb";
93 reg = <0x00000000 0x00100000>;
94 read-only;
95 };
96 partition@300000 {
97 label = "kernel";
98 reg = <0x00100000 0x00400000>;
99 read-only;
100 };
101 partition@400000 {
102 label = "fs";
103 reg = <0x00500000 0x00a00000>;
104 };
105 partition@700000 {
106 label = "firmware";
107 reg = <0x00f00000 0x00100000>;
108 read-only;
109 };
110 };
111
112 epld@2,0 {
113 compatible = "wrs,epld-localbus";
114 #address-cells = <2>;
115 #size-cells = <1>;
116 reg = <2 0 0x100000>;
117 ranges = <0 0 5 0 1 // User switches
118 1 0 5 1 1 // Board ID/Rev
119 3 0 5 3 1>; // LEDs
120 };
121 };
122
123 soc@f8000000 {
124 #address-cells = <1>;
125 #size-cells = <1>;
126 device_type = "soc";
127 compatible = "simple-bus";
128 ranges = <0x00000000 0xf8000000 0x00100000>;
129 reg = <0xf8000000 0x00001000>; // CCSRBAR
130 bus-frequency = <0>;
131
132 i2c@3000 {
133 #address-cells = <1>;
134 #size-cells = <0>;
135 cell-index = <0>;
136 compatible = "fsl-i2c";
137 reg = <0x3000 0x100>;
138 interrupts = <43 2>;
139 interrupt-parent = <&mpic>;
140 dfsrr;
141 };
142
143 i2c@3100 {
144 #address-cells = <1>;
145 #size-cells = <0>;
146 cell-index = <1>;
147 compatible = "fsl-i2c";
148 reg = <0x3100 0x100>;
149 interrupts = <43 2>;
150 interrupt-parent = <&mpic>;
151 dfsrr;
152 };
153
154 mdio@24520 {
155 #address-cells = <1>;
156 #size-cells = <0>;
157 compatible = "fsl,gianfar-mdio";
158 reg = <0x24520 0x20>;
159
160 phy0: ethernet-phy@1f {
161 interrupt-parent = <&mpic>;
162 interrupts = <10 1>;
163 reg = <0x1f>;
164 device_type = "ethernet-phy";
165 };
166 phy1: ethernet-phy@0 {
167 interrupt-parent = <&mpic>;
168 interrupts = <10 1>;
169 reg = <0>;
170 device_type = "ethernet-phy";
171 };
172 phy2: ethernet-phy@1 {
173 interrupt-parent = <&mpic>;
174 interrupts = <10 1>;
175 reg = <1>;
176 device_type = "ethernet-phy";
177 };
178 phy3: ethernet-phy@2 {
179 interrupt-parent = <&mpic>;
180 interrupts = <10 1>;
181 reg = <2>;
182 device_type = "ethernet-phy";
183 };
184 };
185
186 enet0: ethernet@24000 {
187 cell-index = <0>;
188 device_type = "network";
189 model = "TSEC";
190 compatible = "gianfar";
191 reg = <0x24000 0x1000>;
192 local-mac-address = [ 00 00 00 00 00 00 ];
193 interrupts = <29 2 30 2 34 2>;
194 interrupt-parent = <&mpic>;
195 phy-handle = <&phy0>;
196 phy-connection-type = "rgmii-id";
197 };
198
199 enet1: ethernet@25000 {
200 cell-index = <1>;
201 device_type = "network";
202 model = "TSEC";
203 compatible = "gianfar";
204 reg = <0x25000 0x1000>;
205 local-mac-address = [ 00 00 00 00 00 00 ];
206 interrupts = <35 2 36 2 40 2>;
207 interrupt-parent = <&mpic>;
208 phy-handle = <&phy1>;
209 phy-connection-type = "rgmii-id";
210 };
211
212 enet2: ethernet@26000 {
213 cell-index = <2>;
214 device_type = "network";
215 model = "TSEC";
216 compatible = "gianfar";
217 reg = <0x26000 0x1000>;
218 local-mac-address = [ 00 00 00 00 00 00 ];
219 interrupts = <31 2 32 2 33 2>;
220 interrupt-parent = <&mpic>;
221 phy-handle = <&phy2>;
222 phy-connection-type = "rgmii-id";
223 };
224
225 enet3: ethernet@27000 {
226 cell-index = <3>;
227 device_type = "network";
228 model = "TSEC";
229 compatible = "gianfar";
230 reg = <0x27000 0x1000>;
231 local-mac-address = [ 00 00 00 00 00 00 ];
232 interrupts = <37 2 38 2 39 2>;
233 interrupt-parent = <&mpic>;
234 phy-handle = <&phy3>;
235 phy-connection-type = "rgmii-id";
236 };
237
238 serial0: serial@4500 {
239 cell-index = <0>;
240 device_type = "serial";
241 compatible = "ns16550";
242 reg = <0x4500 0x100>;
243 clock-frequency = <0>;
244 interrupts = <42 2>;
245 interrupt-parent = <&mpic>;
246 };
247
248 serial1: serial@4600 {
249 cell-index = <1>;
250 device_type = "serial";
251 compatible = "ns16550";
252 reg = <0x4600 0x100>;
253 clock-frequency = <0>;
254 interrupts = <28 2>;
255 interrupt-parent = <&mpic>;
256 };
257
258 mpic: pic@40000 {
259 clock-frequency = <0>;
260 interrupt-controller;
261 #address-cells = <0>;
262 #interrupt-cells = <2>;
263 reg = <0x40000 0x40000>;
264 compatible = "chrp,open-pic";
265 device_type = "open-pic";
266 big-endian;
267 };
268
269 global-utilities@e0000 {
270 compatible = "fsl,mpc8641-guts";
271 reg = <0xe0000 0x1000>;
272 fsl,has-rstcr;
273 };
274 };
275
276 pci0: pcie@f8008000 {
277 cell-index = <0>;
278 compatible = "fsl,mpc8641-pcie";
279 device_type = "pci";
280 #interrupt-cells = <1>;
281 #size-cells = <2>;
282 #address-cells = <3>;
283 reg = <0xf8008000 0x1000>;
284 bus-range = <0x0 0xff>;
285 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000
286 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
287 clock-frequency = <33333333>;
288 interrupt-parent = <&mpic>;
289 interrupts = <24 2>;
290 interrupt-map-mask = <0xff00 0 0 7>;
291 interrupt-map = <
292 /* IDSEL 0x0 */
293 0x0000 0 0 1 &mpic 0 1
294 0x0000 0 0 2 &mpic 1 1
295 0x0000 0 0 3 &mpic 2 1
296 0x0000 0 0 4 &mpic 3 1
297 >;
298
299 pcie@0 {
300 reg = <0 0 0 0 0>;
301 #size-cells = <2>;
302 #address-cells = <3>;
303 device_type = "pci";
304 ranges = <0x02000000 0x0 0x80000000
305 0x02000000 0x0 0x80000000
306 0x0 0x20000000
307
308 0x01000000 0x0 0x00000000
309 0x01000000 0x0 0x00000000
310 0x0 0x00100000>;
311 };
312
313 };
314
315 pci1: pcie@f8009000 {
316 cell-index = <1>;
317 compatible = "fsl,mpc8641-pcie";
318 device_type = "pci";
319 #interrupt-cells = <1>;
320 #size-cells = <2>;
321 #address-cells = <3>;
322 reg = <0xf8009000 0x1000>;
323 bus-range = <0 0xff>;
324 ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
325 0x01000000 0x0 0x00000000 0xe3000000 0x0 0x00100000>;
326 clock-frequency = <33333333>;
327 interrupt-parent = <&mpic>;
328 interrupts = <25 2>;
329 interrupt-map-mask = <0xf800 0 0 7>;
330 interrupt-map = <
331 /* IDSEL 0x0 */
332 0x0000 0 0 1 &mpic 4 1
333 0x0000 0 0 2 &mpic 5 1
334 0x0000 0 0 3 &mpic 6 1
335 0x0000 0 0 4 &mpic 7 1
336 >;
337
338 pcie@0 {
339 reg = <0 0 0 0 0>;
340 #size-cells = <2>;
341 #address-cells = <3>;
342 device_type = "pci";
343 ranges = <0x02000000 0x0 0xa0000000
344 0x02000000 0x0 0xa0000000
345 0x0 0x20000000
346
347 0x01000000 0x0 0x00000000
348 0x01000000 0x0 0x00000000
349 0x0 0x00100000>;
350 };
351 };
352};
diff --git a/arch/powerpc/boot/dts/sequoia.dts b/arch/powerpc/boot/dts/sequoia.dts
index 8db9515d7dc3..a1ae4d6ec990 100644
--- a/arch/powerpc/boot/dts/sequoia.dts
+++ b/arch/powerpc/boot/dts/sequoia.dts
@@ -269,7 +269,6 @@
269 }; 269 };
270 270
271 EMAC0: ethernet@ef600e00 { 271 EMAC0: ethernet@ef600e00 {
272 linux,network-index = <0>;
273 device_type = "network"; 272 device_type = "network";
274 compatible = "ibm,emac-440epx", "ibm,emac4"; 273 compatible = "ibm,emac-440epx", "ibm,emac4";
275 interrupt-parent = <&EMAC0>; 274 interrupt-parent = <&EMAC0>;
@@ -285,7 +284,7 @@
285 mal-tx-channel = <0>; 284 mal-tx-channel = <0>;
286 mal-rx-channel = <0>; 285 mal-rx-channel = <0>;
287 cell-index = <0>; 286 cell-index = <0>;
288 max-frame-size = <5dc>; 287 max-frame-size = <2328>;
289 rx-fifo-size = <1000>; 288 rx-fifo-size = <1000>;
290 tx-fifo-size = <800>; 289 tx-fifo-size = <800>;
291 phy-mode = "rgmii"; 290 phy-mode = "rgmii";
@@ -299,7 +298,6 @@
299 }; 298 };
300 299
301 EMAC1: ethernet@ef600f00 { 300 EMAC1: ethernet@ef600f00 {
302 linux,network-index = <1>;
303 device_type = "network"; 301 device_type = "network";
304 compatible = "ibm,emac-440epx", "ibm,emac4"; 302 compatible = "ibm,emac-440epx", "ibm,emac4";
305 interrupt-parent = <&EMAC1>; 303 interrupt-parent = <&EMAC1>;
@@ -315,7 +313,7 @@
315 mal-tx-channel = <1>; 313 mal-tx-channel = <1>;
316 mal-rx-channel = <1>; 314 mal-rx-channel = <1>;
317 cell-index = <1>; 315 cell-index = <1>;
318 max-frame-size = <5dc>; 316 max-frame-size = <2328>;
319 rx-fifo-size = <1000>; 317 rx-fifo-size = <1000>;
320 tx-fifo-size = <800>; 318 tx-fifo-size = <800>;
321 phy-mode = "rgmii"; 319 phy-mode = "rgmii";
diff --git a/arch/powerpc/boot/dts/taishan.dts b/arch/powerpc/boot/dts/taishan.dts
index 8278068c802c..e808e1c5593a 100644
--- a/arch/powerpc/boot/dts/taishan.dts
+++ b/arch/powerpc/boot/dts/taishan.dts
@@ -104,6 +104,16 @@
104 // FIXME: anything else? 104 // FIXME: anything else?
105 }; 105 };
106 106
107 L2C0: l2c {
108 compatible = "ibm,l2-cache-440gx", "ibm,l2-cache";
109 dcr-reg = <20 8 /* Internal SRAM DCR's */
110 30 8>; /* L2 cache DCR's */
111 cache-line-size = <20>; /* 32 bytes */
112 cache-size = <40000>; /* L2, 256K */
113 interrupt-parent = <&UIC2>;
114 interrupts = <17 1>;
115 };
116
107 plb { 117 plb {
108 compatible = "ibm,plb-440gx", "ibm,plb4"; 118 compatible = "ibm,plb-440gx", "ibm,plb4";
109 #address-cells = <2>; 119 #address-cells = <2>;
@@ -232,10 +242,18 @@
232 reg = <40000790 8>; 242 reg = <40000790 8>;
233 }; 243 };
234 244
245 TAH0: emac-tah@40000b50 {
246 compatible = "ibm,tah-440gx", "ibm,tah";
247 reg = <40000b50 30>;
248 };
249
250 TAH1: emac-tah@40000d50 {
251 compatible = "ibm,tah-440gx", "ibm,tah";
252 reg = <40000d50 30>;
253 };
235 254
236 EMAC0: ethernet@40000800 { 255 EMAC0: ethernet@40000800 {
237 unused = <1>; 256 unused = <1>;
238 linux,network-index = <2>;
239 device_type = "network"; 257 device_type = "network";
240 compatible = "ibm,emac-440gx", "ibm,emac4"; 258 compatible = "ibm,emac-440gx", "ibm,emac4";
241 interrupt-parent = <&UIC1>; 259 interrupt-parent = <&UIC1>;
@@ -256,7 +274,6 @@
256 }; 274 };
257 EMAC1: ethernet@40000900 { 275 EMAC1: ethernet@40000900 {
258 unused = <1>; 276 unused = <1>;
259 linux,network-index = <3>;
260 device_type = "network"; 277 device_type = "network";
261 compatible = "ibm,emac-440gx", "ibm,emac4"; 278 compatible = "ibm,emac-440gx", "ibm,emac4";
262 interrupt-parent = <&UIC1>; 279 interrupt-parent = <&UIC1>;
@@ -277,7 +294,6 @@
277 }; 294 };
278 295
279 EMAC2: ethernet@40000c00 { 296 EMAC2: ethernet@40000c00 {
280 linux,network-index = <0>;
281 device_type = "network"; 297 device_type = "network";
282 compatible = "ibm,emac-440gx", "ibm,emac4"; 298 compatible = "ibm,emac-440gx", "ibm,emac4";
283 interrupt-parent = <&UIC2>; 299 interrupt-parent = <&UIC2>;
@@ -288,7 +304,7 @@
288 mal-tx-channel = <2>; 304 mal-tx-channel = <2>;
289 mal-rx-channel = <2>; 305 mal-rx-channel = <2>;
290 cell-index = <2>; 306 cell-index = <2>;
291 max-frame-size = <5dc>; 307 max-frame-size = <2328>;
292 rx-fifo-size = <1000>; 308 rx-fifo-size = <1000>;
293 tx-fifo-size = <800>; 309 tx-fifo-size = <800>;
294 phy-mode = "rgmii"; 310 phy-mode = "rgmii";
@@ -297,10 +313,11 @@
297 rgmii-channel = <0>; 313 rgmii-channel = <0>;
298 zmii-device = <&ZMII0>; 314 zmii-device = <&ZMII0>;
299 zmii-channel = <2>; 315 zmii-channel = <2>;
316 tah-device = <&TAH0>;
317 tah-channel = <0>;
300 }; 318 };
301 319
302 EMAC3: ethernet@40000e00 { 320 EMAC3: ethernet@40000e00 {
303 linux,network-index = <1>;
304 device_type = "network"; 321 device_type = "network";
305 compatible = "ibm,emac-440gx", "ibm,emac4"; 322 compatible = "ibm,emac-440gx", "ibm,emac4";
306 interrupt-parent = <&UIC2>; 323 interrupt-parent = <&UIC2>;
@@ -311,7 +328,7 @@
311 mal-tx-channel = <3>; 328 mal-tx-channel = <3>;
312 mal-rx-channel = <3>; 329 mal-rx-channel = <3>;
313 cell-index = <3>; 330 cell-index = <3>;
314 max-frame-size = <5dc>; 331 max-frame-size = <2328>;
315 rx-fifo-size = <1000>; 332 rx-fifo-size = <1000>;
316 tx-fifo-size = <800>; 333 tx-fifo-size = <800>;
317 phy-mode = "rgmii"; 334 phy-mode = "rgmii";
@@ -320,6 +337,8 @@
320 rgmii-channel = <1>; 337 rgmii-channel = <1>;
321 zmii-device = <&ZMII0>; 338 zmii-device = <&ZMII0>;
322 zmii-channel = <3>; 339 zmii-channel = <3>;
340 tah-device = <&TAH1>;
341 tah-channel = <0>;
323 }; 342 };
324 343
325 344
diff --git a/arch/powerpc/boot/dts/walnut.dts b/arch/powerpc/boot/dts/walnut.dts
index dcc21b0438e5..a328607c8f84 100644
--- a/arch/powerpc/boot/dts/walnut.dts
+++ b/arch/powerpc/boot/dts/walnut.dts
@@ -125,7 +125,6 @@
125 }; 125 };
126 126
127 EMAC: ethernet@ef600800 { 127 EMAC: ethernet@ef600800 {
128 linux,network-index = <0>;
129 device_type = "network"; 128 device_type = "network";
130 compatible = "ibm,emac-405gp", "ibm,emac"; 129 compatible = "ibm,emac-405gp", "ibm,emac";
131 interrupt-parent = <&UIC0>; 130 interrupt-parent = <&UIC0>;
diff --git a/arch/powerpc/boot/dts/warp.dts b/arch/powerpc/boot/dts/warp.dts
index dc1499d30f43..b04a52e22bf5 100644
--- a/arch/powerpc/boot/dts/warp.dts
+++ b/arch/powerpc/boot/dts/warp.dts
@@ -204,7 +204,6 @@
204 }; 204 };
205 205
206 EMAC0: ethernet@ef600e00 { 206 EMAC0: ethernet@ef600e00 {
207 linux,network-index = <0>;
208 device_type = "network"; 207 device_type = "network";
209 compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac"; 208 compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac";
210 interrupt-parent = <&UIC1>; 209 interrupt-parent = <&UIC1>;
diff --git a/arch/powerpc/boot/dts/yosemite.dts b/arch/powerpc/boot/dts/yosemite.dts
new file mode 100644
index 000000000000..0d6d332814e0
--- /dev/null
+++ b/arch/powerpc/boot/dts/yosemite.dts
@@ -0,0 +1,304 @@
1/*
2 * Device Tree Source for AMCC Yosemite
3 *
4 * Copyright 2008 IBM Corp.
5 * Josh Boyer <jwboyer@linux.vnet.ibm.com>
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without
9 * any warranty of any kind, whether express or implied.
10 */
11
12/ {
13 #address-cells = <2>;
14 #size-cells = <1>;
15 model = "amcc,yosemite";
16 compatible = "amcc,yosemite","amcc,bamboo";
17 dcr-parent = <&/cpus/cpu@0>;
18
19 aliases {
20 ethernet0 = &EMAC0;
21 ethernet1 = &EMAC1;
22 serial0 = &UART0;
23 serial1 = &UART1;
24 serial2 = &UART2;
25 serial3 = &UART3;
26 };
27
28 cpus {
29 #address-cells = <1>;
30 #size-cells = <0>;
31
32 cpu@0 {
33 device_type = "cpu";
34 model = "PowerPC,440EP";
35 reg = <0>;
36 clock-frequency = <0>; /* Filled in by zImage */
37 timebase-frequency = <0>; /* Filled in by zImage */
38 i-cache-line-size = <20>;
39 d-cache-line-size = <20>;
40 i-cache-size = <8000>;
41 d-cache-size = <8000>;
42 dcr-controller;
43 dcr-access-method = "native";
44 };
45 };
46
47 memory {
48 device_type = "memory";
49 reg = <0 0 0>; /* Filled in by zImage */
50 };
51
52 UIC0: interrupt-controller0 {
53 compatible = "ibm,uic-440ep","ibm,uic";
54 interrupt-controller;
55 cell-index = <0>;
56 dcr-reg = <0c0 009>;
57 #address-cells = <0>;
58 #size-cells = <0>;
59 #interrupt-cells = <2>;
60 };
61
62 UIC1: interrupt-controller1 {
63 compatible = "ibm,uic-440ep","ibm,uic";
64 interrupt-controller;
65 cell-index = <1>;
66 dcr-reg = <0d0 009>;
67 #address-cells = <0>;
68 #size-cells = <0>;
69 #interrupt-cells = <2>;
70 interrupts = <1e 4 1f 4>; /* cascade */
71 interrupt-parent = <&UIC0>;
72 };
73
74 SDR0: sdr {
75 compatible = "ibm,sdr-440ep";
76 dcr-reg = <00e 002>;
77 };
78
79 CPR0: cpr {
80 compatible = "ibm,cpr-440ep";
81 dcr-reg = <00c 002>;
82 };
83
84 plb {
85 compatible = "ibm,plb-440ep", "ibm,plb-440gp", "ibm,plb4";
86 #address-cells = <2>;
87 #size-cells = <1>;
88 ranges;
89 clock-frequency = <0>; /* Filled in by zImage */
90
91 SDRAM0: sdram {
92 compatible = "ibm,sdram-440ep", "ibm,sdram-405gp";
93 dcr-reg = <010 2>;
94 };
95
96 DMA0: dma {
97 compatible = "ibm,dma-440ep", "ibm,dma-440gp";
98 dcr-reg = <100 027>;
99 };
100
101 MAL0: mcmal {
102 compatible = "ibm,mcmal-440ep", "ibm,mcmal-440gp", "ibm,mcmal";
103 dcr-reg = <180 62>;
104 num-tx-chans = <4>;
105 num-rx-chans = <2>;
106 interrupt-parent = <&MAL0>;
107 interrupts = <0 1 2 3 4>;
108 #interrupt-cells = <1>;
109 #address-cells = <0>;
110 #size-cells = <0>;
111 interrupt-map = </*TXEOB*/ 0 &UIC0 a 4
112 /*RXEOB*/ 1 &UIC0 b 4
113 /*SERR*/ 2 &UIC1 0 4
114 /*TXDE*/ 3 &UIC1 1 4
115 /*RXDE*/ 4 &UIC1 2 4>;
116 };
117
118 POB0: opb {
119 compatible = "ibm,opb-440ep", "ibm,opb-440gp", "ibm,opb";
120 #address-cells = <1>;
121 #size-cells = <1>;
122 /* Bamboo is oddball in the 44x world and doesn't use the ERPN
123 * bits.
124 */
125 ranges = <00000000 0 00000000 80000000
126 80000000 0 80000000 80000000>;
127 interrupt-parent = <&UIC1>;
128 interrupts = <7 4>;
129 clock-frequency = <0>; /* Filled in by zImage */
130
131 EBC0: ebc {
132 compatible = "ibm,ebc-440ep", "ibm,ebc-440gp", "ibm,ebc";
133 dcr-reg = <012 2>;
134 #address-cells = <2>;
135 #size-cells = <1>;
136 clock-frequency = <0>; /* Filled in by zImage */
137 interrupts = <5 1>;
138 interrupt-parent = <&UIC1>;
139 };
140
141 UART0: serial@ef600300 {
142 device_type = "serial";
143 compatible = "ns16550";
144 reg = <ef600300 8>;
145 virtual-reg = <ef600300>;
146 clock-frequency = <0>; /* Filled in by zImage */
147 current-speed = <1c200>;
148 interrupt-parent = <&UIC0>;
149 interrupts = <0 4>;
150 };
151
152 UART1: serial@ef600400 {
153 device_type = "serial";
154 compatible = "ns16550";
155 reg = <ef600400 8>;
156 virtual-reg = <ef600400>;
157 clock-frequency = <0>;
158 current-speed = <0>;
159 interrupt-parent = <&UIC0>;
160 interrupts = <1 4>;
161 };
162
163 UART2: serial@ef600500 {
164 device_type = "serial";
165 compatible = "ns16550";
166 reg = <ef600500 8>;
167 virtual-reg = <ef600500>;
168 clock-frequency = <0>;
169 current-speed = <0>;
170 interrupt-parent = <&UIC0>;
171 interrupts = <3 4>;
172 status = "disabled";
173 };
174
175 UART3: serial@ef600600 {
176 device_type = "serial";
177 compatible = "ns16550";
178 reg = <ef600600 8>;
179 virtual-reg = <ef600600>;
180 clock-frequency = <0>;
181 current-speed = <0>;
182 interrupt-parent = <&UIC0>;
183 interrupts = <4 4>;
184 status = "disabled";
185 };
186
187 IIC0: i2c@ef600700 {
188 compatible = "ibm,iic-440ep", "ibm,iic-440gp", "ibm,iic";
189 reg = <ef600700 14>;
190 interrupt-parent = <&UIC0>;
191 interrupts = <2 4>;
192 };
193
194 IIC1: i2c@ef600800 {
195 compatible = "ibm,iic-440ep", "ibm,iic-440gp", "ibm,iic";
196 reg = <ef600800 14>;
197 interrupt-parent = <&UIC0>;
198 interrupts = <7 4>;
199 };
200
201 spi@ef600900 {
202 compatible = "amcc,spi-440ep";
203 reg = <ef600900 6>;
204 interrupts = <8 4>;
205 interrupt-parent = <&UIC0>;
206 };
207
208 ZMII0: emac-zmii@ef600d00 {
209 compatible = "ibm,zmii-440ep", "ibm,zmii-440gp", "ibm,zmii";
210 reg = <ef600d00 c>;
211 };
212
213 EMAC0: ethernet@ef600e00 {
214 device_type = "network";
215 compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac";
216 interrupt-parent = <&UIC1>;
217 interrupts = <1c 4 1d 4>;
218 reg = <ef600e00 70>;
219 local-mac-address = [000000000000];
220 mal-device = <&MAL0>;
221 mal-tx-channel = <0 1>;
222 mal-rx-channel = <0>;
223 cell-index = <0>;
224 max-frame-size = <5dc>;
225 rx-fifo-size = <1000>;
226 tx-fifo-size = <800>;
227 phy-mode = "rmii";
228 phy-map = <00000000>;
229 zmii-device = <&ZMII0>;
230 zmii-channel = <0>;
231 };
232
233 EMAC1: ethernet@ef600f00 {
234 device_type = "network";
235 compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac";
236 interrupt-parent = <&UIC1>;
237 interrupts = <1e 4 1f 4>;
238 reg = <ef600f00 70>;
239 local-mac-address = [000000000000];
240 mal-device = <&MAL0>;
241 mal-tx-channel = <2 3>;
242 mal-rx-channel = <1>;
243 cell-index = <1>;
244 max-frame-size = <5dc>;
245 rx-fifo-size = <1000>;
246 tx-fifo-size = <800>;
247 phy-mode = "rmii";
248 phy-map = <00000000>;
249 zmii-device = <&ZMII0>;
250 zmii-channel = <1>;
251 };
252
253 usb@ef601000 {
254 compatible = "ohci-be";
255 reg = <ef601000 80>;
256 interrupts = <8 4 9 4>;
257 interrupt-parent = < &UIC1 >;
258 };
259 };
260
261 PCI0: pci@ec000000 {
262 device_type = "pci";
263 #interrupt-cells = <1>;
264 #size-cells = <2>;
265 #address-cells = <3>;
266 compatible = "ibm,plb440ep-pci", "ibm,plb-pci";
267 primary;
268 reg = <0 eec00000 8 /* Config space access */
269 0 eed00000 4 /* IACK */
270 0 eed00000 4 /* Special cycle */
271 0 ef400000 40>; /* Internal registers */
272
273 /* Outbound ranges, one memory and one IO,
274 * later cannot be changed. Chip supports a second
275 * IO range but we don't use it for now
276 */
277 ranges = <02000000 0 a0000000 0 a0000000 0 20000000
278 01000000 0 00000000 0 e8000000 0 00010000>;
279
280 /* Inbound 2GB range starting at 0 */
281 dma-ranges = <42000000 0 0 0 0 0 80000000>;
282
283 /* Bamboo has all 4 IRQ pins tied together per slot */
284 interrupt-map-mask = <f800 0 0 0>;
285 interrupt-map = <
286 /* IDSEL 1 */
287 0800 0 0 0 &UIC0 1c 8
288
289 /* IDSEL 2 */
290 1000 0 0 0 &UIC0 1b 8
291
292 /* IDSEL 3 */
293 1800 0 0 0 &UIC0 1a 8
294
295 /* IDSEL 4 */
296 2000 0 0 0 &UIC0 19 8
297 >;
298 };
299 };
300
301 chosen {
302 linux,stdout-path = "/plb/opb/serial@ef600300";
303 };
304};
diff --git a/arch/powerpc/boot/ebony.c b/arch/powerpc/boot/ebony.c
index f61364c47a76..5532ab3221dd 100644
--- a/arch/powerpc/boot/ebony.c
+++ b/arch/powerpc/boot/ebony.c
@@ -75,7 +75,8 @@ static void ebony_fixups(void)
75 75
76 ibm440gp_fixup_clocks(sysclk, 6 * 1843200); 76 ibm440gp_fixup_clocks(sysclk, 6 * 1843200);
77 ibm4xx_sdram_fixup_memsize(); 77 ibm4xx_sdram_fixup_memsize();
78 dt_fixup_mac_addresses(ebony_mac0, ebony_mac1); 78 dt_fixup_mac_address_by_alias("ethernet0", ebony_mac0);
79 dt_fixup_mac_address_by_alias("ethernet1", ebony_mac1);
79 ibm4xx_fixup_ebc_ranges("/plb/opb/ebc"); 80 ibm4xx_fixup_ebc_ranges("/plb/opb/ebc");
80 ebony_flashsel_fixup(); 81 ebony_flashsel_fixup();
81} 82}
diff --git a/arch/powerpc/boot/libfdt-wrapper.c b/arch/powerpc/boot/libfdt-wrapper.c
index 59016bef1391..c541fd8a95d4 100644
--- a/arch/powerpc/boot/libfdt-wrapper.c
+++ b/arch/powerpc/boot/libfdt-wrapper.c
@@ -35,7 +35,7 @@
35#define check_err(err) \ 35#define check_err(err) \
36 ({ \ 36 ({ \
37 if (BAD_ERROR(err) || ((err < 0) && DEBUG)) \ 37 if (BAD_ERROR(err) || ((err < 0) && DEBUG)) \
38 printf("%s():%d %s\n\r", __FUNCTION__, __LINE__, \ 38 printf("%s():%d %s\n\r", __func__, __LINE__, \
39 fdt_strerror(err)); \ 39 fdt_strerror(err)); \
40 if (BAD_ERROR(err)) \ 40 if (BAD_ERROR(err)) \
41 exit(); \ 41 exit(); \
diff --git a/arch/powerpc/boot/mpc52xx-psc.c b/arch/powerpc/boot/mpc52xx-psc.c
index 1074626e6a37..d4cb4e4e0938 100644
--- a/arch/powerpc/boot/mpc52xx-psc.c
+++ b/arch/powerpc/boot/mpc52xx-psc.c
@@ -51,14 +51,9 @@ static unsigned char psc_getc(void)
51 51
52int mpc5200_psc_console_init(void *devp, struct serial_console_data *scdp) 52int mpc5200_psc_console_init(void *devp, struct serial_console_data *scdp)
53{ 53{
54 int n;
55
56 /* Get the base address of the psc registers */ 54 /* Get the base address of the psc registers */
57 n = getprop(devp, "virtual-reg", &psc, sizeof(psc)); 55 if (dt_get_virtual_reg(devp, &psc, 1) < 1)
58 if (n != sizeof(psc)) { 56 return -1;
59 if (!dt_xlate_reg(devp, 0, (void *)&psc, NULL))
60 return -1;
61 }
62 57
63 scdp->open = psc_open; 58 scdp->open = psc_open;
64 scdp->putc = psc_putc; 59 scdp->putc = psc_putc;
diff --git a/arch/powerpc/boot/mpsc.c b/arch/powerpc/boot/mpsc.c
index 802ea53790d8..425ad88cce8d 100644
--- a/arch/powerpc/boot/mpsc.c
+++ b/arch/powerpc/boot/mpsc.c
@@ -141,7 +141,7 @@ int mpsc_console_init(void *devp, struct serial_console_data *scdp)
141 if (mpscintr_base == NULL) 141 if (mpscintr_base == NULL)
142 goto err_out; 142 goto err_out;
143 143
144 n = getprop(devp, "block-index", &v, sizeof(v)); 144 n = getprop(devp, "cell-index", &v, sizeof(v));
145 if (n != sizeof(v)) 145 if (n != sizeof(v))
146 goto err_out; 146 goto err_out;
147 reg_set = (int)v; 147 reg_set = (int)v;
diff --git a/arch/powerpc/boot/mv64x60.c b/arch/powerpc/boot/mv64x60.c
index b43259455d4b..d9bb302b91d2 100644
--- a/arch/powerpc/boot/mv64x60.c
+++ b/arch/powerpc/boot/mv64x60.c
@@ -535,7 +535,7 @@ u8 *mv64x60_get_bridge_pbase(void)
535 u32 v[2]; 535 u32 v[2];
536 void *devp; 536 void *devp;
537 537
538 devp = finddevice("/mv64x60"); 538 devp = find_node_by_compatible(NULL, "marvell,mv64360");
539 if (devp == NULL) 539 if (devp == NULL)
540 goto err_out; 540 goto err_out;
541 if (getprop(devp, "reg", v, sizeof(v)) != sizeof(v)) 541 if (getprop(devp, "reg", v, sizeof(v)) != sizeof(v))
@@ -553,7 +553,7 @@ u8 *mv64x60_get_bridge_base(void)
553 u32 v; 553 u32 v;
554 void *devp; 554 void *devp;
555 555
556 devp = finddevice("/mv64x60"); 556 devp = find_node_by_compatible(NULL, "marvell,mv64360");
557 if (devp == NULL) 557 if (devp == NULL)
558 goto err_out; 558 goto err_out;
559 if (getprop(devp, "virtual-reg", &v, sizeof(v)) != sizeof(v)) 559 if (getprop(devp, "virtual-reg", &v, sizeof(v)) != sizeof(v))
diff --git a/arch/powerpc/boot/mv64x60_i2c.c b/arch/powerpc/boot/mv64x60_i2c.c
index d085377be3bc..52a3212b6638 100644
--- a/arch/powerpc/boot/mv64x60_i2c.c
+++ b/arch/powerpc/boot/mv64x60_i2c.c
@@ -185,7 +185,7 @@ int mv64x60_i2c_open(void)
185 u32 v; 185 u32 v;
186 void *devp; 186 void *devp;
187 187
188 devp = finddevice("/mv64x60/i2c"); 188 devp = find_node_by_compatible(NULL, "marvell,mv64360-i2c");
189 if (devp == NULL) 189 if (devp == NULL)
190 goto err_out; 190 goto err_out;
191 if (getprop(devp, "virtual-reg", &v, sizeof(v)) != sizeof(v)) 191 if (getprop(devp, "virtual-reg", &v, sizeof(v)) != sizeof(v))
diff --git a/arch/powerpc/boot/ns16550.c b/arch/powerpc/boot/ns16550.c
index f8f1b2f31412..aef3bdc89160 100644
--- a/arch/powerpc/boot/ns16550.c
+++ b/arch/powerpc/boot/ns16550.c
@@ -55,15 +55,9 @@ static u8 ns16550_tstc(void)
55int ns16550_console_init(void *devp, struct serial_console_data *scdp) 55int ns16550_console_init(void *devp, struct serial_console_data *scdp)
56{ 56{
57 int n; 57 int n;
58 unsigned long reg_phys;
59 58
60 n = getprop(devp, "virtual-reg", &reg_base, sizeof(reg_base)); 59 if (dt_get_virtual_reg(devp, (void **)&reg_base, 1) < 1)
61 if (n != sizeof(reg_base)) { 60 return -1;
62 if (!dt_xlate_reg(devp, 0, &reg_phys, NULL))
63 return -1;
64
65 reg_base = (void *)reg_phys;
66 }
67 61
68 n = getprop(devp, "reg-shift", &reg_shift, sizeof(reg_shift)); 62 n = getprop(devp, "reg-shift", &reg_shift, sizeof(reg_shift));
69 if (n != sizeof(reg_shift)) 63 if (n != sizeof(reg_shift))
diff --git a/arch/powerpc/boot/ops.h b/arch/powerpc/boot/ops.h
index 4b0544b03c64..321e2f5afe71 100644
--- a/arch/powerpc/boot/ops.h
+++ b/arch/powerpc/boot/ops.h
@@ -95,6 +95,7 @@ int dt_xlate_reg(void *node, int res, unsigned long *addr, unsigned long *size);
95int dt_xlate_addr(void *node, u32 *buf, int buflen, unsigned long *xlated_addr); 95int dt_xlate_addr(void *node, u32 *buf, int buflen, unsigned long *xlated_addr);
96int dt_is_compatible(void *node, const char *compat); 96int dt_is_compatible(void *node, const char *compat);
97void dt_get_reg_format(void *node, u32 *naddr, u32 *nsize); 97void dt_get_reg_format(void *node, u32 *naddr, u32 *nsize);
98int dt_get_virtual_reg(void *node, void **addr, int nres);
98 99
99static inline void *finddevice(const char *name) 100static inline void *finddevice(const char *name)
100{ 101{
diff --git a/arch/powerpc/boot/prpmc2800.c b/arch/powerpc/boot/prpmc2800.c
index 05c3245b30d7..da31d6030482 100644
--- a/arch/powerpc/boot/prpmc2800.c
+++ b/arch/powerpc/boot/prpmc2800.c
@@ -344,20 +344,20 @@ static void prpmc2800_bridge_setup(u32 mem_size)
344 acc_bits); 344 acc_bits);
345 345
346 /* Get the cpu -> pci i/o & mem mappings from the device tree */ 346 /* Get the cpu -> pci i/o & mem mappings from the device tree */
347 devp = finddevice("/mv64x60/pci@80000000"); 347 devp = find_node_by_compatible(NULL, "marvell,mv64360-pci");
348 if (devp == NULL) 348 if (devp == NULL)
349 fatal("Error: Missing /mv64x60/pci@80000000" 349 fatal("Error: Missing marvell,mv64360-pci"
350 " device tree node\n\r"); 350 " device tree node\n\r");
351 351
352 rc = getprop(devp, "ranges", v, sizeof(v)); 352 rc = getprop(devp, "ranges", v, sizeof(v));
353 if (rc != sizeof(v)) 353 if (rc != sizeof(v))
354 fatal("Error: Can't find /mv64x60/pci@80000000/ranges" 354 fatal("Error: Can't find marvell,mv64360-pci ranges"
355 " property\n\r"); 355 " property\n\r");
356 356
357 /* Get the cpu -> pci i/o & mem mappings from the device tree */ 357 /* Get the cpu -> pci i/o & mem mappings from the device tree */
358 devp = finddevice("/mv64x60"); 358 devp = find_node_by_compatible(NULL, "marvell,mv64360");
359 if (devp == NULL) 359 if (devp == NULL)
360 fatal("Error: Missing /mv64x60 device tree node\n\r"); 360 fatal("Error: Missing marvell,mv64360 device tree node\n\r");
361 361
362 enables = in_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE)); 362 enables = in_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE));
363 enables |= 0x0007fe00; /* Disable all cpu->pci windows */ 363 enables |= 0x0007fe00; /* Disable all cpu->pci windows */
@@ -429,9 +429,9 @@ static void prpmc2800_fixups(void)
429 setprop(devp, "model", model, l); 429 setprop(devp, "model", model, l);
430 430
431 /* Set /cpus/PowerPC,7447/clock-frequency */ 431 /* Set /cpus/PowerPC,7447/clock-frequency */
432 devp = finddevice("/cpus/PowerPC,7447"); 432 devp = find_node_by_prop_value_str(NULL, "device_type", "cpu");
433 if (devp == NULL) 433 if (devp == NULL)
434 fatal("Error: Missing proper /cpus device tree node\n\r"); 434 fatal("Error: Missing proper cpu device tree node\n\r");
435 v[0] = bip->core_speed; 435 v[0] = bip->core_speed;
436 setprop(devp, "clock-frequency", &v[0], sizeof(v[0])); 436 setprop(devp, "clock-frequency", &v[0], sizeof(v[0]));
437 437
@@ -443,16 +443,17 @@ static void prpmc2800_fixups(void)
443 v[1] = bip->mem_size; 443 v[1] = bip->mem_size;
444 setprop(devp, "reg", v, sizeof(v)); 444 setprop(devp, "reg", v, sizeof(v));
445 445
446 /* Update /mv64x60/model, if this is a mv64362 */ 446 /* Update model, if this is a mv64362 */
447 if (bip->bridge_type == BRIDGE_TYPE_MV64362) { 447 if (bip->bridge_type == BRIDGE_TYPE_MV64362) {
448 devp = finddevice("/mv64x60"); 448 devp = find_node_by_compatible(NULL, "marvell,mv64360");
449 if (devp == NULL) 449 if (devp == NULL)
450 fatal("Error: Missing /mv64x60 device tree node\n\r"); 450 fatal("Error: Missing marvell,mv64360"
451 " device tree node\n\r");
451 setprop(devp, "model", "mv64362", strlen("mv64362") + 1); 452 setprop(devp, "model", "mv64362", strlen("mv64362") + 1);
452 } 453 }
453 454
454 /* Set User FLASH size */ 455 /* Set User FLASH size */
455 devp = finddevice("/mv64x60/flash@a0000000"); 456 devp = find_node_by_compatible(NULL, "direct-mapped");
456 if (devp == NULL) 457 if (devp == NULL)
457 fatal("Error: Missing User FLASH device tree node\n\r"); 458 fatal("Error: Missing User FLASH device tree node\n\r");
458 rc = getprop(devp, "reg", v, sizeof(v)); 459 rc = getprop(devp, "reg", v, sizeof(v));
diff --git a/arch/powerpc/boot/ps3-head.S b/arch/powerpc/boot/ps3-head.S
index a55c2735f759..b6fcbaf5027b 100644
--- a/arch/powerpc/boot/ps3-head.S
+++ b/arch/powerpc/boot/ps3-head.S
@@ -27,8 +27,9 @@
27/* 27/*
28 * __system_reset_overlay - The PS3 first stage entry. 28 * __system_reset_overlay - The PS3 first stage entry.
29 * 29 *
30 * The bootwraper build script copies the 0x100 bytes at symbol 30 * The bootwraper build script copies the 512 bytes at symbol
31 * __system_reset_overlay to offset 0x100 of the rom image. 31 * __system_reset_overlay to offset 0x100 of the rom image. This symbol
32 * must occupy 512 or less bytes.
32 * 33 *
33 * The PS3 has a single processor with two threads. 34 * The PS3 has a single processor with two threads.
34 */ 35 */
@@ -47,8 +48,6 @@ __system_reset_overlay:
47 48
48 mfspr r3, 0x88 49 mfspr r3, 0x88
49 cntlzw. r3, r3 50 cntlzw. r3, r3
50 li r4, 0
51 li r5, 0
52 beq 1f 51 beq 1f
53 52
54 /* Secondary goes to __secondary_hold in kernel. */ 53 /* Secondary goes to __secondary_hold in kernel. */
@@ -57,8 +56,14 @@ __system_reset_overlay:
57 mtctr r4 56 mtctr r4
58 bctr 57 bctr
59 58
60 /* Primary delays then goes to _zimage_start in wrapper. */
611: 591:
60 /* Save the value at addr zero for a null pointer write check later. */
61
62 li r4, 0
63 lwz r3, 0(r4)
64
65 /* Primary delays then goes to _zimage_start in wrapper. */
66
62 or 31, 31, 31 /* db16cyc */ 67 or 31, 31, 31 /* db16cyc */
63 or 31, 31, 31 /* db16cyc */ 68 or 31, 31, 31 /* db16cyc */
64 69
@@ -67,16 +72,18 @@ __system_reset_overlay:
67 mtctr r4 72 mtctr r4
68 bctr 73 bctr
69 74
75 . = __system_reset_overlay + 512
76
70/* 77/*
71 * __system_reset_kernel - Place holder for the kernel reset vector. 78 * __system_reset_kernel - Place holder for the kernel reset vector.
72 * 79 *
73 * The bootwrapper build script copies 0x100 bytes from offset 0x100 80 * The bootwrapper build script copies 512 bytes from offset 0x100
74 * of the rom image to the symbol __system_reset_kernel. At runtime 81 * of the rom image to the symbol __system_reset_kernel. At runtime
75 * the bootwrapper program copies the 0x100 bytes at __system_reset_kernel 82 * the bootwrapper program copies the 512 bytes at __system_reset_kernel
76 * to ram address 0x100. This symbol must occupy 0x100 bytes. 83 * to ram address 0x100. This symbol must occupy 512 bytes.
77 */ 84 */
78 85
79 .globl __system_reset_kernel 86 .globl __system_reset_kernel
80__system_reset_kernel: 87__system_reset_kernel:
81 88
82 . = __system_reset_kernel + 0x100 89 . = __system_reset_kernel + 512
diff --git a/arch/powerpc/boot/ps3.c b/arch/powerpc/boot/ps3.c
index 3b0ac4d006ec..9954d98871d0 100644
--- a/arch/powerpc/boot/ps3.c
+++ b/arch/powerpc/boot/ps3.c
@@ -27,10 +27,10 @@
27#include "page.h" 27#include "page.h"
28#include "ops.h" 28#include "ops.h"
29 29
30extern s64 lv1_panic(u64 in_1); 30extern int lv1_panic(u64 in_1);
31extern s64 lv1_get_logical_partition_id(u64 *out_1); 31extern int lv1_get_logical_partition_id(u64 *out_1);
32extern s64 lv1_get_logical_ppe_id(u64 *out_1); 32extern int lv1_get_logical_ppe_id(u64 *out_1);
33extern s64 lv1_get_repository_node_value(u64 in_1, u64 in_2, u64 in_3, 33extern int lv1_get_repository_node_value(u64 in_1, u64 in_2, u64 in_3,
34 u64 in_4, u64 in_5, u64 *out_1, u64 *out_2); 34 u64 in_4, u64 in_5, u64 *out_1, u64 *out_2);
35 35
36#ifdef DEBUG 36#ifdef DEBUG
@@ -46,6 +46,7 @@ BSS_STACK(4096);
46 * edit the command line passed to vmlinux (by setting /chosen/bootargs). 46 * edit the command line passed to vmlinux (by setting /chosen/bootargs).
47 * The buffer is put in it's own section so that tools may locate it easier. 47 * The buffer is put in it's own section so that tools may locate it easier.
48 */ 48 */
49
49static char cmdline[COMMAND_LINE_SIZE] 50static char cmdline[COMMAND_LINE_SIZE]
50 __attribute__((__section__("__builtin_cmdline"))); 51 __attribute__((__section__("__builtin_cmdline")));
51 52
@@ -75,7 +76,7 @@ static void ps3_exit(void)
75 76
76static int ps3_repository_read_rm_size(u64 *rm_size) 77static int ps3_repository_read_rm_size(u64 *rm_size)
77{ 78{
78 s64 result; 79 int result;
79 u64 lpar_id; 80 u64 lpar_id;
80 u64 ppe_id; 81 u64 ppe_id;
81 u64 v2; 82 u64 v2;
@@ -114,16 +115,17 @@ void ps3_copy_vectors(void)
114{ 115{
115 extern char __system_reset_kernel[]; 116 extern char __system_reset_kernel[];
116 117
117 memcpy((void *)0x100, __system_reset_kernel, 0x100); 118 memcpy((void *)0x100, __system_reset_kernel, 512);
118 flush_cache((void *)0x100, 0x100); 119 flush_cache((void *)0x100, 512);
119} 120}
120 121
121void platform_init(void) 122void platform_init(unsigned long null_check)
122{ 123{
123 const u32 heapsize = 0x1000000 - (u32)_end; /* 16MiB */ 124 const u32 heapsize = 0x1000000 - (u32)_end; /* 16MiB */
124 void *chosen; 125 void *chosen;
125 unsigned long ft_addr; 126 unsigned long ft_addr;
126 u64 rm_size; 127 u64 rm_size;
128 unsigned long val;
127 129
128 console_ops.write = ps3_console_write; 130 console_ops.write = ps3_console_write;
129 platform_ops.exit = ps3_exit; 131 platform_ops.exit = ps3_exit;
@@ -151,6 +153,11 @@ void platform_init(void)
151 153
152 printf(" flat tree at 0x%lx\n\r", ft_addr); 154 printf(" flat tree at 0x%lx\n\r", ft_addr);
153 155
156 val = *(unsigned long *)0;
157
158 if (val != null_check)
159 printf("null check failed: %lx != %lx\n\r", val, null_check);
160
154 ((kernel_entry_t)0)(ft_addr, 0, NULL); 161 ((kernel_entry_t)0)(ft_addr, 0, NULL);
155 162
156 ps3_exit(); 163 ps3_exit();
diff --git a/arch/powerpc/boot/serial.c b/arch/powerpc/boot/serial.c
index 9960421eb6b9..8b3607cb53fb 100644
--- a/arch/powerpc/boot/serial.c
+++ b/arch/powerpc/boot/serial.c
@@ -119,7 +119,7 @@ int serial_console_init(void)
119 119
120 if (dt_is_compatible(devp, "ns16550")) 120 if (dt_is_compatible(devp, "ns16550"))
121 rc = ns16550_console_init(devp, &serial_cd); 121 rc = ns16550_console_init(devp, &serial_cd);
122 else if (dt_is_compatible(devp, "marvell,mpsc")) 122 else if (dt_is_compatible(devp, "marvell,mv64360-mpsc"))
123 rc = mpsc_console_init(devp, &serial_cd); 123 rc = mpsc_console_init(devp, &serial_cd);
124 else if (dt_is_compatible(devp, "fsl,cpm1-scc-uart") || 124 else if (dt_is_compatible(devp, "fsl,cpm1-scc-uart") ||
125 dt_is_compatible(devp, "fsl,cpm1-smc-uart") || 125 dt_is_compatible(devp, "fsl,cpm1-smc-uart") ||
diff --git a/arch/powerpc/boot/simpleboot.c b/arch/powerpc/boot/simpleboot.c
new file mode 100644
index 000000000000..86cd285bccc6
--- /dev/null
+++ b/arch/powerpc/boot/simpleboot.c
@@ -0,0 +1,84 @@
1/*
2 * The simple platform -- for booting when firmware doesn't supply a device
3 * tree or any platform configuration information.
4 * All data is extracted from an embedded device tree
5 * blob.
6 *
7 * Authors: Scott Wood <scottwood@freescale.com>
8 * Grant Likely <grant.likely@secretlab.ca>
9 *
10 * Copyright (c) 2007 Freescale Semiconductor, Inc.
11 * Copyright (c) 2008 Secret Lab Technologies Ltd.
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License version 2 as published
15 * by the Free Software Foundation.
16 */
17
18#include "ops.h"
19#include "types.h"
20#include "io.h"
21#include "stdio.h"
22#include "libfdt/libfdt.h"
23
24BSS_STACK(4*1024);
25
26void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
27 unsigned long r6, unsigned long r7)
28{
29 const u32 *na, *ns, *reg, *timebase;
30 u64 memsize64;
31 int node, size, i;
32
33 /* Make sure FDT blob is sane */
34 if (fdt_check_header(_dtb_start) != 0)
35 fatal("Invalid device tree blob\n");
36
37 /* Find the #address-cells and #size-cells properties */
38 node = fdt_path_offset(_dtb_start, "/");
39 if (node < 0)
40 fatal("Cannot find root node\n");
41 na = fdt_getprop(_dtb_start, node, "#address-cells", &size);
42 if (!na || (size != 4))
43 fatal("Cannot find #address-cells property");
44 ns = fdt_getprop(_dtb_start, node, "#size-cells", &size);
45 if (!ns || (size != 4))
46 fatal("Cannot find #size-cells property");
47
48 /* Find the memory range */
49 node = fdt_node_offset_by_prop_value(_dtb_start, -1, "device_type",
50 "memory", sizeof("memory"));
51 if (node < 0)
52 fatal("Cannot find memory node\n");
53 reg = fdt_getprop(_dtb_start, node, "reg", &size);
54 if (size < (*na+*ns) * sizeof(u32))
55 fatal("cannot get memory range\n");
56
57 /* Only interested in memory based at 0 */
58 for (i = 0; i < *na; i++)
59 if (*reg++ != 0)
60 fatal("Memory range is not based at address 0\n");
61
62 /* get the memsize and trucate it to under 4G on 32 bit machines */
63 memsize64 = 0;
64 for (i = 0; i < *ns; i++)
65 memsize64 = (memsize64 << 32) | *reg++;
66 if (sizeof(void *) == 4 && memsize64 >= 0x100000000ULL)
67 memsize64 = 0xffffffff;
68
69 /* finally, setup the timebase */
70 node = fdt_node_offset_by_prop_value(_dtb_start, -1, "device_type",
71 "cpu", sizeof("cpu"));
72 if (!node)
73 fatal("Cannot find cpu node\n");
74 timebase = fdt_getprop(_dtb_start, node, "timebase-frequency", &size);
75 if (timebase && (size == 4))
76 timebase_period_ns = 1000000000 / *timebase;
77
78 /* Now we have the memory size; initialize the heap */
79 simple_alloc_init(_end, memsize64 - (unsigned long)_end, 32, 64);
80
81 /* prepare the device tree and find the console */
82 fdt_init(_dtb_start);
83 serial_console_init();
84}
diff --git a/arch/powerpc/boot/treeboot-walnut.c b/arch/powerpc/boot/treeboot-walnut.c
index 472e36605a52..097974e59fac 100644
--- a/arch/powerpc/boot/treeboot-walnut.c
+++ b/arch/powerpc/boot/treeboot-walnut.c
@@ -68,7 +68,7 @@ static void walnut_fixups(void)
68 ibm4xx_quiesce_eth((u32 *)0xef600800, NULL); 68 ibm4xx_quiesce_eth((u32 *)0xef600800, NULL);
69 ibm4xx_fixup_ebc_ranges("/plb/ebc"); 69 ibm4xx_fixup_ebc_ranges("/plb/ebc");
70 walnut_flashsel_fixup(); 70 walnut_flashsel_fixup();
71 dt_fixup_mac_addresses((u8 *) WALNUT_OPENBIOS_MAC_OFF); 71 dt_fixup_mac_address_by_alias("ethernet0", (u8 *) WALNUT_OPENBIOS_MAC_OFF);
72} 72}
73 73
74void platform_init(void) 74void platform_init(void)
diff --git a/arch/powerpc/boot/virtex405-head.S b/arch/powerpc/boot/virtex405-head.S
new file mode 100644
index 000000000000..3edb13f94669
--- /dev/null
+++ b/arch/powerpc/boot/virtex405-head.S
@@ -0,0 +1,30 @@
1#include "ppc_asm.h"
2
3 .text
4 .global _zimage_start
5_zimage_start:
6
7 /* PPC errata 213: needed by Virtex-4 FX */
8 mfccr0 0
9 oris 0,0,0x50000000@h
10 mtccr0 0
11
12 /*
13 * Invalidate the data cache if the data cache is turned off.
14 * - The 405 core does not invalidate the data cache on power-up
15 * or reset but does turn off the data cache. We cannot assume
16 * that the cache contents are valid.
17 * - If the data cache is turned on this must have been done by
18 * a bootloader and we assume that the cache contents are
19 * valid.
20 */
21 mfdccr r9
22 cmplwi r9,0
23 bne 2f
24 lis r9,0
25 li r8,256
26 mtctr r8
271: dccci r0,r9
28 addi r9,r9,0x20
29 bdnz 1b
302: b _zimage_start_lib
diff --git a/arch/powerpc/boot/wrapper b/arch/powerpc/boot/wrapper
index 8f8b8494d62f..d6c96d9ab291 100755
--- a/arch/powerpc/boot/wrapper
+++ b/arch/powerpc/boot/wrapper
@@ -174,7 +174,7 @@ cuboot*)
174 *-mpc83*) 174 *-mpc83*)
175 platformo=$object/cuboot-83xx.o 175 platformo=$object/cuboot-83xx.o
176 ;; 176 ;;
177 *-tqm8541|*-mpc8560*|*-tqm8560|*-tqm8555) 177 *-tqm8541|*-mpc8560*|*-tqm8560|*-tqm8555|*-ksi8560*)
178 platformo=$object/cuboot-85xx-cpm2.o 178 platformo=$object/cuboot-85xx-cpm2.o
179 ;; 179 ;;
180 *-mpc85*|*-tqm8540|*-sbc85*) 180 *-mpc85*|*-tqm8540|*-sbc85*)
@@ -199,6 +199,10 @@ adder875-redboot)
199 platformo="$object/fixed-head.o $object/redboot-8xx.o" 199 platformo="$object/fixed-head.o $object/redboot-8xx.o"
200 binary=y 200 binary=y
201 ;; 201 ;;
202simpleboot-virtex405-*)
203 platformo="$object/virtex405-head.o $object/simpleboot.o"
204 binary=y
205 ;;
202esac 206esac
203 207
204vmz="$tmpdir/`basename \"$kernel\"`.$ext" 208vmz="$tmpdir/`basename \"$kernel\"`.$ext"
@@ -226,10 +230,13 @@ if [ -n "$version" ]; then
226 uboot_version="-n Linux-$version" 230 uboot_version="-n Linux-$version"
227fi 231fi
228 232
233# physical offset of kernel image
234membase=`${CROSS}objdump -p "$kernel" | grep -m 1 LOAD | awk '{print $7}'`
235
229case "$platform" in 236case "$platform" in
230uboot) 237uboot)
231 rm -f "$ofile" 238 rm -f "$ofile"
232 mkimage -A ppc -O linux -T kernel -C gzip -a 00000000 -e 00000000 \ 239 mkimage -A ppc -O linux -T kernel -C gzip -a $membase -e $membase \
233 $uboot_version -d "$vmz" "$ofile" 240 $uboot_version -d "$vmz" "$ofile"
234 if [ -z "$cacheit" ]; then 241 if [ -z "$cacheit" ]; then
235 rm -f "$vmz" 242 rm -f "$vmz"
@@ -298,15 +305,16 @@ treeboot*)
298 exit 0 305 exit 0
299 ;; 306 ;;
300ps3) 307ps3)
301 # The ps3's loader supports loading gzipped binary images from flash 308 # The ps3's loader supports loading a gzipped binary image from flash
302 # rom to addr zero. The loader enters the image at addr 0x100. A 309 # rom to ram addr zero. The loader then enters the system reset
303 # bootwrapper overlay is use to arrange for the kernel to be loaded 310 # vector at addr 0x100. A bootwrapper overlay is used to arrange for
304 # to addr zero and to have a suitable bootwrapper entry at 0x100. 311 # a binary image of the kernel to be at addr zero, and yet have a
305 # To construct the rom image, 0x100 bytes from offset 0x100 in the 312 # suitable bootwrapper entry at 0x100. To construct the final rom
306 # kernel is copied to the bootwrapper symbol __system_reset_kernel. 313 # image 512 bytes from offset 0x100 is copied to the bootwrapper
307 # The 0x100 bytes at the bootwrapper symbol __system_reset_overlay is 314 # place holder at symbol __system_reset_kernel. The 512 bytes of the
308 # then copied to offset 0x100. At runtime the bootwrapper program 315 # bootwrapper entry code at symbol __system_reset_overlay is then
309 # copies the 0x100 bytes at __system_reset_kernel to addr 0x100. 316 # copied to offset 0x100. At runtime the bootwrapper program copies
317 # the data at __system_reset_kernel back to addr 0x100.
310 318
311 system_reset_overlay=0x`${CROSS}nm "$ofile" \ 319 system_reset_overlay=0x`${CROSS}nm "$ofile" \
312 | grep ' __system_reset_overlay$' \ 320 | grep ' __system_reset_overlay$' \
@@ -317,7 +325,7 @@ ps3)
317 | cut -d' ' -f1` 325 | cut -d' ' -f1`
318 system_reset_kernel=`printf "%d" $system_reset_kernel` 326 system_reset_kernel=`printf "%d" $system_reset_kernel`
319 overlay_dest="256" 327 overlay_dest="256"
320 overlay_size="256" 328 overlay_size="512"
321 329
322 ${CROSS}objcopy -O binary "$ofile" "$ofile.bin" 330 ${CROSS}objcopy -O binary "$ofile" "$ofile.bin"
323 331
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-17 08:54:27 -0500