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-rw-r--r--arch/powerpc/boot/44x.c40
-rw-r--r--arch/powerpc/boot/44x.h16
-rw-r--r--arch/powerpc/boot/Makefile49
-rw-r--r--arch/powerpc/boot/cuboot-ebony.c42
-rw-r--r--arch/powerpc/boot/dcr.h87
-rw-r--r--arch/powerpc/boot/dts/ebony.dts307
-rw-r--r--arch/powerpc/boot/dts/holly.dts198
-rw-r--r--arch/powerpc/boot/dts/lite5200.dts11
-rw-r--r--arch/powerpc/boot/dts/lite5200b.dts11
-rw-r--r--arch/powerpc/boot/dts/mpc832x_mds.dts2
-rw-r--r--arch/powerpc/boot/dts/mpc832x_rdb.dts2
-rw-r--r--arch/powerpc/boot/dts/mpc836x_mds.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc8568mds.dts6
-rw-r--r--arch/powerpc/boot/ebony.c129
-rw-r--r--arch/powerpc/boot/holly.c38
-rw-r--r--arch/powerpc/boot/mktree.c10
-rw-r--r--arch/powerpc/boot/treeboot-ebony.c34
-rwxr-xr-xarch/powerpc/boot/wrapper36
18 files changed, 968 insertions, 54 deletions
diff --git a/arch/powerpc/boot/44x.c b/arch/powerpc/boot/44x.c
new file mode 100644
index 000000000000..d51377d9024f
--- /dev/null
+++ b/arch/powerpc/boot/44x.c
@@ -0,0 +1,40 @@
1/*
2 * Copyright 2007 David Gibson, IBM Corporation.
3 *
4 * Based on earlier code:
5 * Matt Porter <mporter@kernel.crashing.org>
6 * Copyright 2002-2005 MontaVista Software Inc.
7 *
8 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
9 * Copyright (c) 2003, 2004 Zultys Technologies
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version
14 * 2 of the License, or (at your option) any later version.
15 */
16#include <stddef.h>
17#include "types.h"
18#include "string.h"
19#include "stdio.h"
20#include "ops.h"
21#include "reg.h"
22#include "dcr.h"
23
24/* Read the 44x memory controller to get size of system memory. */
25void ibm44x_fixup_memsize(void)
26{
27 int i;
28 unsigned long memsize, bank_config;
29
30 memsize = 0;
31 for (i = 0; i < ARRAY_SIZE(sdram_bxcr); i++) {
32 mtdcr(DCRN_SDRAM0_CFGADDR, sdram_bxcr[i]);
33 bank_config = mfdcr(DCRN_SDRAM0_CFGDATA);
34
35 if (bank_config & SDRAM_CONFIG_BANK_ENABLE)
36 memsize += SDRAM_CONFIG_BANK_SIZE(bank_config);
37 }
38
39 dt_fixup_memory(0, memsize);
40}
diff --git a/arch/powerpc/boot/44x.h b/arch/powerpc/boot/44x.h
new file mode 100644
index 000000000000..7b129ad043e1
--- /dev/null
+++ b/arch/powerpc/boot/44x.h
@@ -0,0 +1,16 @@
1/*
2 * PowerPC 44x related functions
3 *
4 * Copyright 2007 David Gibson, IBM Corporation.
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10#ifndef _PPC_BOOT_44X_H_
11#define _PPC_BOOT_44X_H_
12
13void ibm44x_fixup_memsize(void);
14void ebony_init(void *mac0, void *mac1);
15
16#endif /* _PPC_BOOT_44X_H_ */
diff --git a/arch/powerpc/boot/Makefile b/arch/powerpc/boot/Makefile
index 3716594ea33e..5c384aad1184 100644
--- a/arch/powerpc/boot/Makefile
+++ b/arch/powerpc/boot/Makefile
@@ -37,13 +37,15 @@ zlib := inffast.c inflate.c inftrees.c
37zlibheader := inffast.h inffixed.h inflate.h inftrees.h infutil.h 37zlibheader := inffast.h inffixed.h inflate.h inftrees.h infutil.h
38zliblinuxheader := zlib.h zconf.h zutil.h 38zliblinuxheader := zlib.h zconf.h zutil.h
39 39
40$(addprefix $(obj)/,$(zlib) main.o): $(addprefix $(obj)/,$(zliblinuxheader)) \ 40$(addprefix $(obj)/,$(zlib) gunzip_util.o main.o): \
41 $(addprefix $(obj)/,$(zlibheader)) 41 $(addprefix $(obj)/,$(zliblinuxheader)) $(addprefix $(obj)/,$(zlibheader))
42 42
43src-wlib := string.S crt0.S stdio.c main.c flatdevtree.c flatdevtree_misc.c \ 43src-wlib := string.S crt0.S stdio.c main.c flatdevtree.c flatdevtree_misc.c \
44 ns16550.c serial.c simple_alloc.c div64.S util.S \ 44 ns16550.c serial.c simple_alloc.c div64.S util.S \
45 gunzip_util.c elf_util.c $(zlib) devtree.c 45 gunzip_util.c elf_util.c $(zlib) devtree.c \
46src-plat := of.c cuboot-83xx.c cuboot-85xx.c 46 44x.c ebony.c
47src-plat := of.c cuboot-83xx.c cuboot-85xx.c holly.c \
48 cuboot-ebony.c treeboot-ebony.c
47src-boot := $(src-wlib) $(src-plat) empty.c 49src-boot := $(src-wlib) $(src-plat) empty.c
48 50
49src-boot := $(addprefix $(obj)/, $(src-boot)) 51src-boot := $(addprefix $(obj)/, $(src-boot))
@@ -129,7 +131,14 @@ image-$(CONFIG_PPC_CELLEB) += zImage.pseries
129image-$(CONFIG_PPC_CHRP) += zImage.chrp 131image-$(CONFIG_PPC_CHRP) += zImage.chrp
130image-$(CONFIG_PPC_EFIKA) += zImage.chrp 132image-$(CONFIG_PPC_EFIKA) += zImage.chrp
131image-$(CONFIG_PPC_PMAC) += zImage.pmac 133image-$(CONFIG_PPC_PMAC) += zImage.pmac
132image-$(CONFIG_DEFAULT_UIMAGE) += uImage cuImage 134image-$(CONFIG_PPC_HOLLY) += zImage.holly-elf
135image-$(CONFIG_DEFAULT_UIMAGE) += uImage
136
137ifneq ($(CONFIG_DEVICE_TREE),"")
138image-$(CONFIG_PPC_83xx) += cuImage.83xx
139image-$(CONFIG_PPC_85xx) += cuImage.85xx
140image-$(CONFIG_EBONY) += treeImage.ebony cuImage.ebony
141endif
133 142
134# For 32-bit powermacs, build the COFF and miboot images 143# For 32-bit powermacs, build the COFF and miboot images
135# as well as the ELF images. 144# as well as the ELF images.
@@ -138,7 +147,8 @@ image-$(CONFIG_PPC_PMAC) += zImage.coff zImage.miboot
138endif 147endif
139 148
140initrd- := $(patsubst zImage%, zImage.initrd%, $(image-n) $(image-)) 149initrd- := $(patsubst zImage%, zImage.initrd%, $(image-n) $(image-))
141initrd-y := $(patsubst zImage%, zImage.initrd%, $(image-y)) 150initrd-y := $(patsubst zImage%, zImage.initrd%, \
151 $(patsubst treeImage%, treeImage.initrd%, $(image-y)))
142initrd-y := $(filter-out $(image-y), $(initrd-y)) 152initrd-y := $(filter-out $(image-y), $(initrd-y))
143targets += $(image-y) $(initrd-y) 153targets += $(image-y) $(initrd-y)
144 154
@@ -159,18 +169,27 @@ $(obj)/zImage.ps3: vmlinux
159$(obj)/zImage.initrd.ps3: vmlinux 169$(obj)/zImage.initrd.ps3: vmlinux
160 @echo " WARNING zImage.initrd.ps3 not supported (yet)" 170 @echo " WARNING zImage.initrd.ps3 not supported (yet)"
161 171
172$(obj)/zImage.holly-elf: vmlinux $(wrapperbits)
173 $(call if_changed,wrap,holly,$(obj)/dts/holly.dts,,)
174
175$(obj)/zImage.initrd.holly-elf: vmlinux $(wrapperbits) $(obj)/ramdisk.image.gz
176 $(call if_changed,wrap,holly,$(obj)/dts/holly.dts,,$(obj)/ramdisk.image.gz)
177
162$(obj)/uImage: vmlinux $(wrapperbits) 178$(obj)/uImage: vmlinux $(wrapperbits)
163 $(call if_changed,wrap,uboot) 179 $(call if_changed,wrap,uboot)
164 180
165cuboot-plat-$(CONFIG_83xx) += 83xx 181# CONFIG_DEVICE_TREE will have "" around it, make sure to strip them
166cuboot-plat-$(CONFIG_85xx) += 85xx
167cuboot-plat-y += unknown-platform
168
169dts = $(if $(shell echo $(CONFIG_DEVICE_TREE) | grep '^/'),\ 182dts = $(if $(shell echo $(CONFIG_DEVICE_TREE) | grep '^/'),\
170 ,$(srctree)/$(src)/dts/)$(CONFIG_DEVICE_TREE) 183 ,$(srctree)/$(src)/dts/)$(CONFIG_DEVICE_TREE:"%"=%)
184
185$(obj)/cuImage.%: vmlinux $(dts) $(wrapperbits)
186 $(call if_changed,wrap,cuboot-$*,$(dts))
187
188$(obj)/treeImage.%: vmlinux $(dts) $(wrapperbits)
189 $(call if_changed,wrap,treeboot-$*,$(dts))
171 190
172$(obj)/cuImage: vmlinux $(wrapperbits) 191$(obj)/treeImage.initrd.%: vmlinux $(dts) $(wrapperbits)
173 $(call if_changed,wrap,cuboot-$(word 1,$(cuboot-plat-y)),$(dts)) 192 $(call if_changed,wrap,treeboot-$*,$(dts),,$(obj)/ramdisk.image.gz)
174 193
175$(obj)/zImage: $(addprefix $(obj)/, $(image-y)) 194$(obj)/zImage: $(addprefix $(obj)/, $(image-y))
176 @rm -f $@; ln $< $@ 195 @rm -f $@; ln $< $@
@@ -181,8 +200,8 @@ install: $(CONFIGURE) $(addprefix $(obj)/, $(image-y))
181 sh -x $(srctree)/$(src)/install.sh "$(KERNELRELEASE)" vmlinux System.map "$(INSTALL_PATH)" $< 200 sh -x $(srctree)/$(src)/install.sh "$(KERNELRELEASE)" vmlinux System.map "$(INSTALL_PATH)" $<
182 201
183# anything not in $(targets) 202# anything not in $(targets)
184clean-files += $(image-) $(initrd-) zImage zImage.initrd \ 203clean-files += $(image-) $(initrd-) zImage zImage.initrd cuImage.* \
185 cuImage.elf cuImage.bin.gz 204 treeImage.*
186 205
187# clean up files cached by wrapper 206# clean up files cached by wrapper
188clean-kernel := vmlinux.strip vmlinux.bin 207clean-kernel := vmlinux.strip vmlinux.bin
diff --git a/arch/powerpc/boot/cuboot-ebony.c b/arch/powerpc/boot/cuboot-ebony.c
new file mode 100644
index 000000000000..4464c5f67acb
--- /dev/null
+++ b/arch/powerpc/boot/cuboot-ebony.c
@@ -0,0 +1,42 @@
1/*
2 * Old U-boot compatibility for Ebony
3 *
4 * Author: David Gibson <david@gibson.dropbear.id.au>
5 *
6 * Copyright 2007 David Gibson, IBM Corporatio.
7 * Based on cuboot-83xx.c, which is:
8 * Copyright (c) 2007 Freescale Semiconductor, Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published
12 * by the Free Software Foundation.
13 */
14
15#include "ops.h"
16#include "stdio.h"
17#include "44x.h"
18
19#define TARGET_44x
20#include "ppcboot.h"
21
22static bd_t bd;
23extern char _end[];
24
25BSS_STACK(4096);
26
27void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
28 unsigned long r6, unsigned long r7)
29{
30 unsigned long end_of_ram = bd.bi_memstart + bd.bi_memsize;
31 unsigned long avail_ram = end_of_ram - (unsigned long)_end;
32
33 memcpy(&bd, (bd_t *)r3, sizeof(bd));
34 loader_info.initrd_addr = r4;
35 loader_info.initrd_size = r4 ? r5 : 0;
36 loader_info.cmdline = (char *)r6;
37 loader_info.cmdline_len = r7 - r6;
38
39 simple_alloc_init(_end, avail_ram, 32, 64);
40
41 ebony_init(&bd.bi_enetaddr, &bd.bi_enet1addr);
42}
diff --git a/arch/powerpc/boot/dcr.h b/arch/powerpc/boot/dcr.h
new file mode 100644
index 000000000000..877bc97b1e97
--- /dev/null
+++ b/arch/powerpc/boot/dcr.h
@@ -0,0 +1,87 @@
1#ifndef _PPC_BOOT_DCR_H_
2#define _PPC_BOOT_DCR_H_
3
4#define mfdcr(rn) \
5 ({ \
6 unsigned long rval; \
7 asm volatile("mfdcr %0,%1" : "=r"(rval) : "i"(rn)); \
8 rval; \
9 })
10#define mtdcr(rn, val) \
11 asm volatile("mtdcr %0,%1" : : "i"(rn), "r"(val))
12
13/* 440GP/440GX SDRAM controller DCRs */
14#define DCRN_SDRAM0_CFGADDR 0x010
15#define DCRN_SDRAM0_CFGDATA 0x011
16
17#define SDRAM0_B0CR 0x40
18#define SDRAM0_B1CR 0x44
19#define SDRAM0_B2CR 0x48
20#define SDRAM0_B3CR 0x4c
21
22static const unsigned long sdram_bxcr[] = { SDRAM0_B0CR, SDRAM0_B1CR, SDRAM0_B2CR, SDRAM0_B3CR };
23
24#define SDRAM_CONFIG_BANK_ENABLE 0x00000001
25#define SDRAM_CONFIG_SIZE_MASK 0x000e0000
26#define SDRAM_CONFIG_BANK_SIZE(reg) \
27 (0x00400000 << ((reg & SDRAM_CONFIG_SIZE_MASK) >> 17))
28
29/* 440GP Clock, PM, chip control */
30#define DCRN_CPC0_SR 0x0b0
31#define DCRN_CPC0_ER 0x0b1
32#define DCRN_CPC0_FR 0x0b2
33#define DCRN_CPC0_SYS0 0x0e0
34#define CPC0_SYS0_TUNE 0xffc00000
35#define CPC0_SYS0_FBDV_MASK 0x003c0000
36#define CPC0_SYS0_FWDVA_MASK 0x00038000
37#define CPC0_SYS0_FWDVB_MASK 0x00007000
38#define CPC0_SYS0_OPDV_MASK 0x00000c00
39#define CPC0_SYS0_EPDV_MASK 0x00000300
40/* Helper macros to compute the actual clock divider values from the
41 * encodings in the CPC0 register */
42#define CPC0_SYS0_FBDV(reg) \
43 ((((((reg) & CPC0_SYS0_FBDV_MASK) >> 18) - 1) & 0xf) + 1)
44#define CPC0_SYS0_FWDVA(reg) \
45 (8 - (((reg) & CPC0_SYS0_FWDVA_MASK) >> 15))
46#define CPC0_SYS0_FWDVB(reg) \
47 (8 - (((reg) & CPC0_SYS0_FWDVB_MASK) >> 12))
48#define CPC0_SYS0_OPDV(reg) \
49 ((((reg) & CPC0_SYS0_OPDV_MASK) >> 10) + 1)
50#define CPC0_SYS0_EPDV(reg) \
51 ((((reg) & CPC0_SYS0_EPDV_MASK) >> 8) + 1)
52#define CPC0_SYS0_EXTSL 0x00000080
53#define CPC0_SYS0_RW_MASK 0x00000060
54#define CPC0_SYS0_RL 0x00000010
55#define CPC0_SYS0_ZMIISL_MASK 0x0000000c
56#define CPC0_SYS0_BYPASS 0x00000002
57#define CPC0_SYS0_NTO1 0x00000001
58#define DCRN_CPC0_SYS1 0x0e1
59#define DCRN_CPC0_CUST0 0x0e2
60#define DCRN_CPC0_CUST1 0x0e3
61#define DCRN_CPC0_STRP0 0x0e4
62#define DCRN_CPC0_STRP1 0x0e5
63#define DCRN_CPC0_STRP2 0x0e6
64#define DCRN_CPC0_STRP3 0x0e7
65#define DCRN_CPC0_GPIO 0x0e8
66#define DCRN_CPC0_PLB 0x0e9
67#define DCRN_CPC0_CR1 0x0ea
68#define DCRN_CPC0_CR0 0x0eb
69#define CPC0_CR0_SWE 0x80000000
70#define CPC0_CR0_CETE 0x40000000
71#define CPC0_CR0_U1FCS 0x20000000
72#define CPC0_CR0_U0DTE 0x10000000
73#define CPC0_CR0_U0DRE 0x08000000
74#define CPC0_CR0_U0DC 0x04000000
75#define CPC0_CR0_U1DTE 0x02000000
76#define CPC0_CR0_U1DRE 0x01000000
77#define CPC0_CR0_U1DC 0x00800000
78#define CPC0_CR0_U0EC 0x00400000
79#define CPC0_CR0_U1EC 0x00200000
80#define CPC0_CR0_UDIV_MASK 0x001f0000
81#define CPC0_CR0_UDIV(reg) \
82 ((((reg) & CPC0_CR0_UDIV_MASK) >> 16) + 1)
83#define DCRN_CPC0_MIRQ0 0x0ec
84#define DCRN_CPC0_MIRQ1 0x0ed
85#define DCRN_CPC0_JTAGID 0x0ef
86
87#endif /* _PPC_BOOT_DCR_H_ */
diff --git a/arch/powerpc/boot/dts/ebony.dts b/arch/powerpc/boot/dts/ebony.dts
new file mode 100644
index 000000000000..b67918651c48
--- /dev/null
+++ b/arch/powerpc/boot/dts/ebony.dts
@@ -0,0 +1,307 @@
1/*
2 * Device Tree Source for IBM Ebony
3 *
4 * Copyright (c) 2006, 2007 IBM Corp.
5 * Josh Boyer <jwboyer@linux.vnet.ibm.com>, David Gibson <dwg@au1.ibm.com>
6 *
7 * FIXME: Draft only!
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without
11 * any warranty of any kind, whether express or implied.
12 *
13 * To build:
14 * dtc -I dts -O asm -o ebony.S -b 0 ebony.dts
15 * dtc -I dts -O dtb -o ebony.dtb -b 0 ebony.dts
16 */
17
18/ {
19 #address-cells = <2>;
20 #size-cells = <1>;
21 model = "ibm,ebony";
22 compatible = "ibm,ebony";
23 dcr-parent = <&/cpus/PowerPC,440GP@0>;
24
25 cpus {
26 #address-cells = <1>;
27 #size-cells = <0>;
28
29 PowerPC,440GP@0 {
30 device_type = "cpu";
31 reg = <0>;
32 clock-frequency = <0>; // Filled in by zImage
33 timebase-frequency = <0>; // Filled in by zImage
34 i-cache-line-size = <32>;
35 d-cache-line-size = <32>;
36 i-cache-size = <0>;
37 d-cache-size = <0>;
38 dcr-controller;
39 dcr-access-method = "native";
40 };
41 };
42
43 memory {
44 device_type = "memory";
45 reg = <0 0 0>; // Filled in by zImage
46 };
47
48 UIC0: interrupt-controller0 {
49 device_type = "ibm,uic";
50 compatible = "ibm,uic-440gp", "ibm,uic";
51 interrupt-controller;
52 cell-index = <0>;
53 dcr-reg = <0c0 009>;
54 #address-cells = <0>;
55 #size-cells = <0>;
56 #interrupt-cells = <2>;
57
58 };
59
60 UIC1: interrupt-controller1 {
61 device_type = "ibm,uic";
62 compatible = "ibm,uic-440gp", "ibm,uic";
63 interrupt-controller;
64 cell-index = <1>;
65 dcr-reg = <0d0 009>;
66 #address-cells = <0>;
67 #size-cells = <0>;
68 #interrupt-cells = <2>;
69 interrupts = <1e 4 1f 4>; /* cascade */
70 interrupt-parent = <&UIC0>;
71 };
72
73 CPC0: cpc {
74 device_type = "ibm,cpc";
75 compatible = "ibm,cpc-440gp";
76 dcr-reg = <0b0 003 0e0 010>;
77 // FIXME: anything else?
78 };
79
80 plb {
81 device_type = "ibm,plb";
82 compatible = "ibm,plb-440gp", "ibm,plb4";
83 #address-cells = <2>;
84 #size-cells = <1>;
85 ranges;
86 clock-frequency = <0>; // Filled in by zImage
87
88 SDRAM0: sdram {
89 device_type = "memory-controller";
90 compatible = "ibm,sdram-440gp", "ibm,sdram";
91 dcr-reg = <010 2>;
92 // FIXME: anything else?
93 };
94
95 DMA0: dma {
96 // FIXME: ???
97 device_type = "ibm,dma-4xx";
98 compatible = "ibm,dma-440gp", "ibm,dma-4xx";
99 dcr-reg = <100 027>;
100 };
101
102 MAL0: mcmal {
103 device_type = "mcmal-dma";
104 compatible = "ibm,mcmal-440gp", "ibm,mcmal";
105 dcr-reg = <180 62>;
106 num-tx-chans = <4>;
107 num-rx-chans = <4>;
108 interrupt-parent = <&MAL0>;
109 interrupts = <0 1 2 3 4>;
110 #interrupt-cells = <1>;
111 #address-cells = <0>;
112 #size-cells = <0>;
113 interrupt-map = </*TXEOB*/ 0 &UIC0 a 4
114 /*RXEOB*/ 1 &UIC0 b 4
115 /*SERR*/ 2 &UIC1 0 4
116 /*TXDE*/ 3 &UIC1 1 4
117 /*RXDE*/ 4 &UIC1 2 4>;
118 interrupt-map-mask = <ffffffff>;
119 };
120
121 POB0: opb {
122 device_type = "ibm,opb";
123 compatible = "ibm,opb-440gp", "ibm,opb";
124 #address-cells = <1>;
125 #size-cells = <1>;
126 /* Wish there was a nicer way of specifying a full 32-bit
127 range */
128 ranges = <00000000 1 00000000 80000000
129 80000000 1 80000000 80000000>;
130 dcr-reg = <090 00b>;
131 interrupt-parent = <&UIC1>;
132 interrupts = <7 4>;
133 clock-frequency = <0>; // Filled in by zImage
134
135 EBC0: ebc {
136 device_type = "ibm,ebc";
137 compatible = "ibm,ebc-440gp";
138 dcr-reg = <012 2>;
139 #address-cells = <2>;
140 #size-cells = <1>;
141 clock-frequency = <0>; // Filled in by zImage
142 ranges = <0 00000000 fff00000 100000
143 1 00000000 48000000 100000
144 2 00000000 ff800000 400000
145 3 00000000 48200000 100000
146 7 00000000 48300000 100000>;
147 interrupts = <5 4>;
148 interrupt-parent = <&UIC1>;
149
150 small-flash@0,0 {
151 device_type = "rom";
152 compatible = "direct-mapped";
153 probe-type = "JEDEC";
154 bank-width = <1>;
155 partitions = <0 80000>;
156 partition-names = "OpenBIOS";
157 reg = <0 80000 80000>;
158 };
159
160 ds1743@1,0 {
161 /* NVRAM & RTC */
162 device_type = "nvram";
163 compatible = "ds1743";
164 reg = <1 0 2000>;
165 };
166
167 large-flash@2,0 {
168 device_type = "rom";
169 compatible = "direct-mapped";
170 probe-type = "JEDEC";
171 bank-width = <1>;
172 partitions = <0 380000
173 280000 80000>;
174 partition-names = "fs", "firmware";
175 reg = <2 0 400000>;
176 };
177
178 ir@3,0 {
179 reg = <3 0 10>;
180 };
181
182 fpga@7,0 {
183 compatible = "Ebony-FPGA";
184 reg = <7 0 10>;
185 };
186 };
187
188 UART0: serial@40000200 {
189 device_type = "serial";
190 compatible = "ns16550";
191 reg = <40000200 8>;
192 virtual-reg = <e0000200>;
193 clock-frequency = <A8C000>;
194 current-speed = <2580>;
195 interrupt-parent = <&UIC0>;
196 interrupts = <0 4>;
197 };
198
199 UART1: serial@40000300 {
200 device_type = "serial";
201 compatible = "ns16550";
202 reg = <40000300 8>;
203 virtual-reg = <e0000300>;
204 clock-frequency = <A8C000>;
205 current-speed = <2580>;
206 interrupt-parent = <&UIC0>;
207 interrupts = <1 4>;
208 };
209
210 IIC0: i2c@40000400 {
211 /* FIXME */
212 device_type = "i2c";
213 compatible = "ibm,iic-440gp", "ibm,iic";
214 reg = <40000400 14>;
215 interrupt-parent = <&UIC0>;
216 interrupts = <2 4>;
217 };
218 IIC1: i2c@40000500 {
219 /* FIXME */
220 device_type = "i2c";
221 compatible = "ibm,iic-440gp", "ibm,iic";
222 reg = <40000500 14>;
223 interrupt-parent = <&UIC0>;
224 interrupts = <3 4>;
225 };
226
227 GPIO0: gpio@40000700 {
228 /* FIXME */
229 device_type = "gpio";
230 compatible = "ibm,gpio-440gp";
231 reg = <40000700 20>;
232 };
233
234 ZMII0: emac-zmii@40000780 {
235 device_type = "emac-zmii";
236 compatible = "ibm,zmii-440gp", "ibm,zmii";
237 reg = <40000780 c>;
238 };
239
240 EMAC0: ethernet@40000800 {
241 linux,network-index = <0>;
242 device_type = "network";
243 compatible = "ibm,emac-440gp", "ibm,emac";
244 interrupt-parent = <&UIC1>;
245 interrupts = <1c 4 1d 4>;
246 reg = <40000800 70>;
247 local-mac-address = [000000000000]; // Filled in by zImage
248 mal-device = <&MAL0>;
249 mal-tx-channel = <0 1>;
250 mal-rx-channel = <0>;
251 cell-index = <0>;
252 max-frame-size = <5dc>;
253 rx-fifo-size = <1000>;
254 tx-fifo-size = <800>;
255 phy-mode = "rmii";
256 phy-map = <00000001>;
257 zmii-device = <&ZMII0>;
258 zmii-channel = <0>;
259 };
260 EMAC1: ethernet@40000900 {
261 linux,network-index = <1>;
262 device_type = "network";
263 compatible = "ibm,emac-440gp", "ibm,emac";
264 interrupt-parent = <&UIC1>;
265 interrupts = <1e 4 1f 4>;
266 reg = <40000900 70>;
267 local-mac-address = [000000000000]; // Filled in by zImage
268 mal-device = <&MAL0>;
269 mal-tx-channel = <2 3>;
270 mal-rx-channel = <1>;
271 cell-index = <1>;
272 max-frame-size = <5dc>;
273 rx-fifo-size = <1000>;
274 tx-fifo-size = <800>;
275 phy-mode = "rmii";
276 phy-map = <00000001>;
277 zmii-device = <&ZMII0>;
278 zmii-channel = <1>;
279 };
280
281
282 GPT0: gpt@40000a00 {
283 /* FIXME */
284 reg = <40000a00 d4>;
285 interrupt-parent = <&UIC0>;
286 interrupts = <12 4 13 4 14 4 15 4 16 4>;
287 };
288
289 };
290
291 PCIX0: pci@1234 {
292 device_type = "pci";
293 /* FIXME */
294 reg = <2 0ec00000 8
295 2 0ec80000 f0
296 2 0ec80100 fc>;
297 };
298 };
299
300 chosen {
301 linux,stdout-path = "/plb/opb/serial@40000200";
302// linux,initrd-start = <0>; /* FIXME */
303// linux,initrd-end = <0>;
304// bootargs = "";
305 };
306};
307
diff --git a/arch/powerpc/boot/dts/holly.dts b/arch/powerpc/boot/dts/holly.dts
new file mode 100644
index 000000000000..254499b107f4
--- /dev/null
+++ b/arch/powerpc/boot/dts/holly.dts
@@ -0,0 +1,198 @@
1/*
2 * Device Tree Source for IBM Holly (PPC 750CL with TSI controller)
3 * Copyright 2007, IBM Corporation
4 *
5 * Stephen Winiecki <stevewin@us.ibm.com>
6 * Josh Boyer <jwboyer@linux.vnet.ibm.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without
10 * any warranty of any kind, whether express or implied.
11 *
12 * To build:
13 * dtc -I dts -O asm -o holly.S -b 0 holly.dts
14 * dtc -I dts -O dtb -o holly.dtb -b 0 holly.dts
15 */
16
17/ {
18 model = "41K7339";
19 compatible = "ibm,holly";
20 #address-cells = <1>;
21 #size-cells = <1>;
22
23 cpus {
24 #address-cells = <1>;
25 #size-cells =<0>;
26 PowerPC,750CL@0 {
27 device_type = "cpu";
28 reg = <0>;
29 d-cache-line-size = <20>;
30 i-cache-line-size = <20>;
31 d-cache-size = <8000>;
32 i-cache-size = <8000>;
33 d-cache-sets = <80>;
34 i-cache-sets = <80>;
35 timebase-frequency = <2faf080>;
36 clock-frequency = <23c34600>;
37 bus-frequency = <bebc200>;
38 32-bit;
39 };
40 };
41
42 memory@0 {
43 device_type = "memory";
44 reg = <00000000 20000000>;
45 };
46
47 tsi109@c0000000 {
48 device_type = "tsi-bridge";
49 compatible = "tsi-bridge";
50 #address-cells = <1>;
51 #size-cells = <1>;
52 ranges = <00000000 c0000000 00010000>;
53 reg = <c0000000 00010000>;
54
55 i2c@7000 {
56 device_type = "i2c";
57 compatible = "tsi-i2c";
58 interrupt-parent = < &/tsi109@c0000000/pic@7400 >;
59 interrupts = <e 2>;
60 reg = <7000 400>;
61 };
62
63 mdio@6000 {
64 device_type = "mdio";
65 compatible = "tsi-ethernet";
66
67 PHY1: ethernet-phy@6000 {
68 device_type = "ethernet-phy";
69 compatible = "bcm54xx";
70 reg = <6000 50>;
71 phy-id = <1>;
72 };
73
74 PHY2: ethernet-phy@6400 {
75 device_type = "ethernet-phy";
76 compatible = "bcm54xx";
77 reg = <6000 50>;
78 phy-id = <2>;
79 };
80 };
81
82 ethernet@6200 {
83 device_type = "network";
84 compatible = "tsi-ethernet";
85 #address-cells = <1>;
86 #size-cells = <0>;
87 reg = <6000 200>;
88 local-mac-address = [ 00 00 00 00 00 00 ];
89 interrupt-parent = < &/tsi109@c0000000/pic@7400 >;
90 interrupts = <10 2>;
91 phy-handle = <&PHY1>;
92 };
93
94 ethernet@6600 {
95 device_type = "network";
96 compatible = "tsi-ethernet";
97 #address-cells = <1>;
98 #size-cells = <0>;
99 reg = <6400 200>;
100 local-mac-address = [ 00 00 00 00 00 00 ];
101 interrupt-parent = < &/tsi109@c0000000/pic@7400 >;
102 interrupts = <11 2>;
103 phy-handle = <&PHY2>;
104 };
105
106 serial@7808 {
107 device_type = "serial";
108 compatible = "ns16550";
109 reg = <7808 200>;
110 virtual-reg = <c0007808>;
111 clock-frequency = <3F9C6000>;
112 current-speed = <1c200>;
113 interrupt-parent = < &/tsi109@c0000000/pic@7400 >;
114 interrupts = <c 2>;
115 };
116
117 serial@7c08 {
118 device_type = "serial";
119 compatible = "ns16550";
120 reg = <7c08 200>;
121 virtual-reg = <c0007c08>;
122 clock-frequency = <3F9C6000>;
123 current-speed = <1c200>;
124 interrupt-parent = < &/tsi109@c0000000/pic@7400 >;
125 interrupts = <d 2>;
126 };
127
128 MPIC: pic@7400 {
129 device_type = "open-pic";
130 compatible = "chrp,open-pic";
131 interrupt-controller;
132 #interrupt-cells = <2>;
133 reg = <7400 400>;
134 big-endian;
135 };
136
137 pci@1000 {
138 device_type = "pci";
139 compatible = "tsi109";
140 #interrupt-cells = <1>;
141 #size-cells = <2>;
142 #address-cells = <3>;
143 reg = <1000 1000>;
144 bus-range = <0 0>;
145 /*----------------------------------------------------+
146 | PCI memory range.
147 | 01 denotes I/O space
148 | 02 denotes 32-bit memory space
149 +----------------------------------------------------*/
150 ranges = <02000000 0 40000000 40000000 0 10000000
151 01000000 0 00000000 7e000000 0 00010000>;
152 clock-frequency = <7f28154>;
153 interrupt-parent = < &/tsi109@c0000000/pic@7400 >;
154 interrupts = <17 2>;
155 interrupt-map-mask = <f800 0 0 7>;
156 /*----------------------------------------------------+
157 | The INTA, INTB, INTC, INTD are shared.
158 +----------------------------------------------------*/
159 interrupt-map = <
160 0800 0 0 1 &RT0 24 0
161 0800 0 0 2 &RT0 25 0
162 0800 0 0 3 &RT0 26 0
163 0800 0 0 4 &RT0 27 0
164
165 1000 0 0 1 &RT0 25 0
166 1000 0 0 2 &RT0 26 0
167 1000 0 0 3 &RT0 27 0
168 1000 0 0 4 &RT0 24 0
169
170 1800 0 0 1 &RT0 26 0
171 1800 0 0 2 &RT0 27 0
172 1800 0 0 3 &RT0 24 0
173 1800 0 0 4 &RT0 25 0
174
175 2000 0 0 1 &RT0 27 0
176 2000 0 0 2 &RT0 24 0
177 2000 0 0 3 &RT0 25 0
178 2000 0 0 4 &RT0 26 0
179 >;
180
181 RT0: router@1180 {
182 device_type = "pic-router";
183 interrupt-controller;
184 big-endian;
185 clock-frequency = <0>;
186 #address-cells = <0>;
187 #interrupt-cells = <2>;
188 interrupts = <17 2>;
189 interrupt-parent = < &/tsi109@c0000000/pic@7400 >;
190 };
191 };
192 };
193
194 chosen {
195 linux,stdout-path = "/tsi109@c0000000/serial@7808";
196 bootargs = "console=ttyS0,115200";
197 };
198};
diff --git a/arch/powerpc/boot/dts/lite5200.dts b/arch/powerpc/boot/dts/lite5200.dts
index ba54c6b40a09..e13ac6ef05a9 100644
--- a/arch/powerpc/boot/dts/lite5200.dts
+++ b/arch/powerpc/boot/dts/lite5200.dts
@@ -48,6 +48,7 @@
48 48
49 soc5200@f0000000 { 49 soc5200@f0000000 {
50 model = "fsl,mpc5200"; 50 model = "fsl,mpc5200";
51 compatible = "mpc5200";
51 revision = "" // from bootloader 52 revision = "" // from bootloader
52 #interrupt-cells = <3>; 53 #interrupt-cells = <3>;
53 device_type = "soc"; 54 device_type = "soc";
@@ -166,7 +167,7 @@
166 device_type = "mscan"; 167 device_type = "mscan";
167 compatible = "mpc5200-mscan"; 168 compatible = "mpc5200-mscan";
168 cell-index = <1>; 169 cell-index = <1>;
169 interrupts = <1 12 0>; 170 interrupts = <2 12 0>;
170 interrupt-parent = <500>; 171 interrupt-parent = <500>;
171 reg = <980 80>; 172 reg = <980 80>;
172 }; 173 };
@@ -178,7 +179,7 @@
178 interrupt-parent = <500>; 179 interrupt-parent = <500>;
179 }; 180 };
180 181
181 gpio-wkup@b00 { 182 gpio-wkup@c00 {
182 compatible = "mpc5200-gpio-wkup"; 183 compatible = "mpc5200-gpio-wkup";
183 reg = <c00 40>; 184 reg = <c00 40>;
184 interrupts = <1 8 0 0 3 0>; 185 interrupts = <1 8 0 0 3 0>;
@@ -317,20 +318,22 @@
317 318
318 i2c@3d00 { 319 i2c@3d00 {
319 device_type = "i2c"; 320 device_type = "i2c";
320 compatible = "mpc5200-i2c"; 321 compatible = "mpc5200-i2c\0fsl-i2c";
321 cell-index = <0>; 322 cell-index = <0>;
322 reg = <3d00 40>; 323 reg = <3d00 40>;
323 interrupts = <2 f 0>; 324 interrupts = <2 f 0>;
324 interrupt-parent = <500>; 325 interrupt-parent = <500>;
326 fsl5200-clocking;
325 }; 327 };
326 328
327 i2c@3d40 { 329 i2c@3d40 {
328 device_type = "i2c"; 330 device_type = "i2c";
329 compatible = "mpc5200-i2c"; 331 compatible = "mpc5200-i2c\0fsl-i2c";
330 cell-index = <1>; 332 cell-index = <1>;
331 reg = <3d40 40>; 333 reg = <3d40 40>;
332 interrupts = <2 10 0>; 334 interrupts = <2 10 0>;
333 interrupt-parent = <500>; 335 interrupt-parent = <500>;
336 fsl5200-clocking;
334 }; 337 };
335 sram@8000 { 338 sram@8000 {
336 device_type = "sram"; 339 device_type = "sram";
diff --git a/arch/powerpc/boot/dts/lite5200b.dts b/arch/powerpc/boot/dts/lite5200b.dts
index 2e003081b0d3..00211b39a342 100644
--- a/arch/powerpc/boot/dts/lite5200b.dts
+++ b/arch/powerpc/boot/dts/lite5200b.dts
@@ -48,6 +48,7 @@
48 48
49 soc5200@f0000000 { 49 soc5200@f0000000 {
50 model = "fsl,mpc5200b"; 50 model = "fsl,mpc5200b";
51 compatible = "mpc5200";
51 revision = ""; // from bootloader 52 revision = ""; // from bootloader
52 #interrupt-cells = <3>; 53 #interrupt-cells = <3>;
53 device_type = "soc"; 54 device_type = "soc";
@@ -166,7 +167,7 @@
166 device_type = "mscan"; 167 device_type = "mscan";
167 compatible = "mpc5200b-mscan\0mpc5200-mscan"; 168 compatible = "mpc5200b-mscan\0mpc5200-mscan";
168 cell-index = <1>; 169 cell-index = <1>;
169 interrupts = <1 12 0>; 170 interrupts = <2 12 0>;
170 interrupt-parent = <500>; 171 interrupt-parent = <500>;
171 reg = <980 80>; 172 reg = <980 80>;
172 }; 173 };
@@ -178,7 +179,7 @@
178 interrupt-parent = <500>; 179 interrupt-parent = <500>;
179 }; 180 };
180 181
181 gpio-wkup@b00 { 182 gpio-wkup@c00 {
182 compatible = "mpc5200b-gpio-wkup\0mpc5200-gpio-wkup"; 183 compatible = "mpc5200b-gpio-wkup\0mpc5200-gpio-wkup";
183 reg = <c00 40>; 184 reg = <c00 40>;
184 interrupts = <1 8 0 0 3 0>; 185 interrupts = <1 8 0 0 3 0>;
@@ -322,20 +323,22 @@
322 323
323 i2c@3d00 { 324 i2c@3d00 {
324 device_type = "i2c"; 325 device_type = "i2c";
325 compatible = "mpc5200b-i2c\0mpc5200-i2c"; 326 compatible = "mpc5200b-i2c\0mpc5200-i2c\0fsl-i2c";
326 cell-index = <0>; 327 cell-index = <0>;
327 reg = <3d00 40>; 328 reg = <3d00 40>;
328 interrupts = <2 f 0>; 329 interrupts = <2 f 0>;
329 interrupt-parent = <500>; 330 interrupt-parent = <500>;
331 fsl5200-clocking;
330 }; 332 };
331 333
332 i2c@3d40 { 334 i2c@3d40 {
333 device_type = "i2c"; 335 device_type = "i2c";
334 compatible = "mpc5200b-i2c\0mpc5200-i2c"; 336 compatible = "mpc5200b-i2c\0mpc5200-i2c\0fsl-i2c";
335 cell-index = <1>; 337 cell-index = <1>;
336 reg = <3d40 40>; 338 reg = <3d40 40>;
337 interrupts = <2 10 0>; 339 interrupts = <2 10 0>;
338 interrupt-parent = <500>; 340 interrupt-parent = <500>;
341 fsl5200-clocking;
339 }; 342 };
340 sram@8000 { 343 sram@8000 {
341 device_type = "sram"; 344 device_type = "sram";
diff --git a/arch/powerpc/boot/dts/mpc832x_mds.dts b/arch/powerpc/boot/dts/mpc832x_mds.dts
index c798491f4cd0..93b760696010 100644
--- a/arch/powerpc/boot/dts/mpc832x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc832x_mds.dts
@@ -306,14 +306,12 @@
306 interrupts = <11 8>; 306 interrupts = <11 8>;
307 reg = <3>; 307 reg = <3>;
308 device_type = "ethernet-phy"; 308 device_type = "ethernet-phy";
309 interface = <3>; //ENET_100_MII
310 }; 309 };
311 phy4: ethernet-phy@04 { 310 phy4: ethernet-phy@04 {
312 interrupt-parent = < &ipic >; 311 interrupt-parent = < &ipic >;
313 interrupts = <12 8>; 312 interrupts = <12 8>;
314 reg = <4>; 313 reg = <4>;
315 device_type = "ethernet-phy"; 314 device_type = "ethernet-phy";
316 interface = <3>;
317 }; 315 };
318 }; 316 };
319 317
diff --git a/arch/powerpc/boot/dts/mpc832x_rdb.dts b/arch/powerpc/boot/dts/mpc832x_rdb.dts
index b55bced1593d..be4c35784e49 100644
--- a/arch/powerpc/boot/dts/mpc832x_rdb.dts
+++ b/arch/powerpc/boot/dts/mpc832x_rdb.dts
@@ -265,14 +265,12 @@
265 interrupts = <0>; 265 interrupts = <0>;
266 reg = <0>; 266 reg = <0>;
267 device_type = "ethernet-phy"; 267 device_type = "ethernet-phy";
268 interface = <3>; //ENET_100_MII
269 }; 268 };
270 phy04:ethernet-phy@04 { 269 phy04:ethernet-phy@04 {
271 interrupt-parent = <&pic>; 270 interrupt-parent = <&pic>;
272 interrupts = <0>; 271 interrupts = <0>;
273 reg = <4>; 272 reg = <4>;
274 device_type = "ethernet-phy"; 273 device_type = "ethernet-phy";
275 interface = <3>;
276 }; 274 };
277 }; 275 };
278 276
diff --git a/arch/powerpc/boot/dts/mpc836x_mds.dts b/arch/powerpc/boot/dts/mpc836x_mds.dts
index 7f578eb57082..38c8594df3a4 100644
--- a/arch/powerpc/boot/dts/mpc836x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc836x_mds.dts
@@ -305,6 +305,7 @@
305 rx-clock = <0>; 305 rx-clock = <0>;
306 tx-clock = <19>; 306 tx-clock = <19>;
307 phy-handle = < &phy0 >; 307 phy-handle = < &phy0 >;
308 phy-connection-type = "rgmii-id";
308 pio-handle = < &pio1 >; 309 pio-handle = < &pio1 >;
309 }; 310 };
310 311
@@ -320,6 +321,7 @@
320 rx-clock = <0>; 321 rx-clock = <0>;
321 tx-clock = <14>; 322 tx-clock = <14>;
322 phy-handle = < &phy1 >; 323 phy-handle = < &phy1 >;
324 phy-connection-type = "rgmii-id";
323 pio-handle = < &pio2 >; 325 pio-handle = < &pio2 >;
324 }; 326 };
325 327
@@ -335,14 +337,12 @@
335 interrupts = <11 8>; 337 interrupts = <11 8>;
336 reg = <0>; 338 reg = <0>;
337 device_type = "ethernet-phy"; 339 device_type = "ethernet-phy";
338 interface = <6>; //ENET_1000_GMII
339 }; 340 };
340 phy1: ethernet-phy@01 { 341 phy1: ethernet-phy@01 {
341 interrupt-parent = < &ipic >; 342 interrupt-parent = < &ipic >;
342 interrupts = <12 8>; 343 interrupts = <12 8>;
343 reg = <1>; 344 reg = <1>;
344 device_type = "ethernet-phy"; 345 device_type = "ethernet-phy";
345 interface = <6>;
346 }; 346 };
347 }; 347 };
348 348
diff --git a/arch/powerpc/boot/dts/mpc8568mds.dts b/arch/powerpc/boot/dts/mpc8568mds.dts
index 7361b36749cb..948a3b61bd4a 100644
--- a/arch/powerpc/boot/dts/mpc8568mds.dts
+++ b/arch/powerpc/boot/dts/mpc8568mds.dts
@@ -288,6 +288,7 @@
288 rx-clock = <0>; 288 rx-clock = <0>;
289 tx-clock = <19>; 289 tx-clock = <19>;
290 phy-handle = <&qe_phy0>; 290 phy-handle = <&qe_phy0>;
291 phy-connection-type = "gmii";
291 pio-handle = <&pio1>; 292 pio-handle = <&pio1>;
292 }; 293 };
293 294
@@ -303,6 +304,7 @@
303 rx-clock = <0>; 304 rx-clock = <0>;
304 tx-clock = <14>; 305 tx-clock = <14>;
305 phy-handle = <&qe_phy1>; 306 phy-handle = <&qe_phy1>;
307 phy-connection-type = "gmii";
306 pio-handle = <&pio2>; 308 pio-handle = <&pio2>;
307 }; 309 };
308 310
@@ -320,28 +322,24 @@
320 interrupts = <31 1>; 322 interrupts = <31 1>;
321 reg = <0>; 323 reg = <0>;
322 device_type = "ethernet-phy"; 324 device_type = "ethernet-phy";
323 interface = <6>; //ENET_1000_GMII
324 }; 325 };
325 qe_phy1: ethernet-phy@01 { 326 qe_phy1: ethernet-phy@01 {
326 interrupt-parent = <&mpic>; 327 interrupt-parent = <&mpic>;
327 interrupts = <32 1>; 328 interrupts = <32 1>;
328 reg = <1>; 329 reg = <1>;
329 device_type = "ethernet-phy"; 330 device_type = "ethernet-phy";
330 interface = <6>;
331 }; 331 };
332 qe_phy2: ethernet-phy@02 { 332 qe_phy2: ethernet-phy@02 {
333 interrupt-parent = <&mpic>; 333 interrupt-parent = <&mpic>;
334 interrupts = <31 1>; 334 interrupts = <31 1>;
335 reg = <2>; 335 reg = <2>;
336 device_type = "ethernet-phy"; 336 device_type = "ethernet-phy";
337 interface = <6>; //ENET_1000_GMII
338 }; 337 };
339 qe_phy3: ethernet-phy@03 { 338 qe_phy3: ethernet-phy@03 {
340 interrupt-parent = <&mpic>; 339 interrupt-parent = <&mpic>;
341 interrupts = <32 1>; 340 interrupts = <32 1>;
342 reg = <3>; 341 reg = <3>;
343 device_type = "ethernet-phy"; 342 device_type = "ethernet-phy";
344 interface = <6>; //ENET_1000_GMII
345 }; 343 };
346 }; 344 };
347 345
diff --git a/arch/powerpc/boot/ebony.c b/arch/powerpc/boot/ebony.c
new file mode 100644
index 000000000000..b1251ee7a102
--- /dev/null
+++ b/arch/powerpc/boot/ebony.c
@@ -0,0 +1,129 @@
1/*
2 * Copyright 2007 David Gibson, IBM Corporation.
3 *
4 * Based on earlier code:
5 * Copyright (C) Paul Mackerras 1997.
6 *
7 * Matt Porter <mporter@kernel.crashing.org>
8 * Copyright 2002-2005 MontaVista Software Inc.
9 *
10 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
11 * Copyright (c) 2003, 2004 Zultys Technologies
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version
16 * 2 of the License, or (at your option) any later version.
17 */
18#include <stdarg.h>
19#include <stddef.h>
20#include "types.h"
21#include "elf.h"
22#include "string.h"
23#include "stdio.h"
24#include "page.h"
25#include "ops.h"
26#include "reg.h"
27#include "dcr.h"
28#include "44x.h"
29
30extern char _dtb_start[];
31extern char _dtb_end[];
32
33static u8 *ebony_mac0, *ebony_mac1;
34
35/* Calculate 440GP clocks */
36void ibm440gp_fixup_clocks(unsigned int sysclk, unsigned int ser_clk)
37{
38 u32 sys0 = mfdcr(DCRN_CPC0_SYS0);
39 u32 cr0 = mfdcr(DCRN_CPC0_CR0);
40 u32 cpu, plb, opb, ebc, tb, uart0, uart1, m;
41 u32 opdv = CPC0_SYS0_OPDV(sys0);
42 u32 epdv = CPC0_SYS0_EPDV(sys0);
43
44 if (sys0 & CPC0_SYS0_BYPASS) {
45 /* Bypass system PLL */
46 cpu = plb = sysclk;
47 } else {
48 if (sys0 & CPC0_SYS0_EXTSL)
49 /* PerClk */
50 m = CPC0_SYS0_FWDVB(sys0) * opdv * epdv;
51 else
52 /* CPU clock */
53 m = CPC0_SYS0_FBDV(sys0) * CPC0_SYS0_FWDVA(sys0);
54 cpu = sysclk * m / CPC0_SYS0_FWDVA(sys0);
55 plb = sysclk * m / CPC0_SYS0_FWDVB(sys0);
56 }
57
58 opb = plb / opdv;
59 ebc = opb / epdv;
60
61 /* FIXME: Check if this is for all 440GP, or just Ebony */
62 if ((mfpvr() & 0xf0000fff) == 0x40000440)
63 /* Rev. B 440GP, use external system clock */
64 tb = sysclk;
65 else
66 /* Rev. C 440GP, errata force us to use internal clock */
67 tb = cpu;
68
69 if (cr0 & CPC0_CR0_U0EC)
70 /* External UART clock */
71 uart0 = ser_clk;
72 else
73 /* Internal UART clock */
74 uart0 = plb / CPC0_CR0_UDIV(cr0);
75
76 if (cr0 & CPC0_CR0_U1EC)
77 /* External UART clock */
78 uart1 = ser_clk;
79 else
80 /* Internal UART clock */
81 uart1 = plb / CPC0_CR0_UDIV(cr0);
82
83 printf("PPC440GP: SysClk = %dMHz (%x)\n\r",
84 (sysclk + 500000) / 1000000, sysclk);
85
86 dt_fixup_cpu_clocks(cpu, tb, 0);
87
88 dt_fixup_clock("/plb", plb);
89 dt_fixup_clock("/plb/opb", opb);
90 dt_fixup_clock("/plb/opb/ebc", ebc);
91 dt_fixup_clock("/plb/opb/serial@40000200", uart0);
92 dt_fixup_clock("/plb/opb/serial@40000300", uart1);
93}
94
95static void ebony_fixups(void)
96{
97 // FIXME: sysclk should be derived by reading the FPGA registers
98 unsigned long sysclk = 33000000;
99
100 ibm440gp_fixup_clocks(sysclk, 6 * 1843200);
101 ibm44x_fixup_memsize();
102 dt_fixup_mac_addresses(ebony_mac0, ebony_mac1);
103}
104
105#define SPRN_DBCR0 0x134
106#define DBCR0_RST_SYSTEM 0x30000000
107
108static void ebony_exit(void)
109{
110 unsigned long tmp;
111
112 asm volatile (
113 "mfspr %0,%1\n"
114 "oris %0,%0,%2@h\n"
115 "mtspr %1,%0"
116 : "=&r"(tmp) : "i"(SPRN_DBCR0), "i"(DBCR0_RST_SYSTEM)
117 );
118
119}
120
121void ebony_init(void *mac0, void *mac1)
122{
123 platform_ops.fixups = ebony_fixups;
124 platform_ops.exit = ebony_exit;
125 ebony_mac0 = mac0;
126 ebony_mac1 = mac1;
127 ft_init(_dtb_start, _dtb_end - _dtb_start, 32);
128 serial_console_init();
129}
diff --git a/arch/powerpc/boot/holly.c b/arch/powerpc/boot/holly.c
new file mode 100644
index 000000000000..7d6539f5e22c
--- /dev/null
+++ b/arch/powerpc/boot/holly.c
@@ -0,0 +1,38 @@
1/*
2 * Copyright 2007 IBM Corporation
3 *
4 * Stephen Winiecki <stevewin@us.ibm.com>
5 * Josh Boyer <jwboyer@linux.vnet.ibm.com>
6 *
7 * Based on earlier code:
8 * Copyright (C) Paul Mackerras 1997.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * version 2 as published by the Free Software Foundation.
13 */
14#include <stdarg.h>
15#include <stddef.h>
16#include "types.h"
17#include "elf.h"
18#include "string.h"
19#include "stdio.h"
20#include "page.h"
21#include "ops.h"
22#include "io.h"
23
24extern char _start[];
25extern char _end[];
26extern char _dtb_start[];
27extern char _dtb_end[];
28
29BSS_STACK(4096);
30
31void platform_init(unsigned long r3, unsigned long r4, unsigned long r5)
32{
33 u32 heapsize = 0x8000000 - (u32)_end; /* 128M */
34
35 simple_alloc_init(_end, heapsize, 32, 64);
36 ft_init(_dtb_start, 0, 4);
37 serial_console_init();
38}
diff --git a/arch/powerpc/boot/mktree.c b/arch/powerpc/boot/mktree.c
index 4cb892993651..45d06a8c7cd1 100644
--- a/arch/powerpc/boot/mktree.c
+++ b/arch/powerpc/boot/mktree.c
@@ -46,8 +46,8 @@ int main(int argc, char *argv[])
46 struct stat st; 46 struct stat st;
47 boot_block_t bt; 47 boot_block_t bt;
48 48
49 if (argc < 3) { 49 if (argc < 5) {
50 fprintf(stderr, "usage: %s <zImage-file> <boot-image> [entry-point]\n",argv[0]); 50 fprintf(stderr, "usage: %s <zImage-file> <boot-image> <load address> <entry point>\n",argv[0]);
51 exit(1); 51 exit(1);
52 } 52 }
53 53
@@ -61,10 +61,8 @@ int main(int argc, char *argv[])
61 bt.bb_magic = htonl(0x0052504F); 61 bt.bb_magic = htonl(0x0052504F);
62 62
63 /* If we have the optional entry point parameter, use it */ 63 /* If we have the optional entry point parameter, use it */
64 if (argc == 4) 64 bt.bb_dest = htonl(strtoul(argv[3], NULL, 0));
65 bt.bb_dest = bt.bb_entry_point = htonl(strtoul(argv[3], NULL, 0)); 65 bt.bb_entry_point = htonl(strtoul(argv[4], NULL, 0));
66 else
67 bt.bb_dest = bt.bb_entry_point = htonl(0x500000);
68 66
69 /* We know these from the linker command. 67 /* We know these from the linker command.
70 * ...and then move it up into memory a little more so the 68 * ...and then move it up into memory a little more so the
diff --git a/arch/powerpc/boot/treeboot-ebony.c b/arch/powerpc/boot/treeboot-ebony.c
new file mode 100644
index 000000000000..8436a9c55192
--- /dev/null
+++ b/arch/powerpc/boot/treeboot-ebony.c
@@ -0,0 +1,34 @@
1/*
2 * Old U-boot compatibility for Ebony
3 *
4 * Author: David Gibson <david@gibson.dropbear.id.au>
5 *
6 * Copyright 2007 David Gibson, IBM Corporatio.
7 * Based on cuboot-83xx.c, which is:
8 * Copyright (c) 2007 Freescale Semiconductor, Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published
12 * by the Free Software Foundation.
13 */
14
15#include "ops.h"
16#include "stdio.h"
17#include "44x.h"
18
19extern char _end[];
20
21BSS_STACK(4096);
22
23#define OPENBIOS_MAC_BASE 0xfffffe0c
24#define OPENBIOS_MAC_OFFSET 0xc
25
26void platform_init(void)
27{
28 unsigned long end_of_ram = 0x8000000;
29 unsigned long avail_ram = end_of_ram - (unsigned long)_end;
30
31 simple_alloc_init(_end, avail_ram, 32, 64);
32 ebony_init((u8 *)OPENBIOS_MAC_BASE,
33 (u8 *)(OPENBIOS_MAC_BASE + OPENBIOS_MAC_OFFSET));
34}
diff --git a/arch/powerpc/boot/wrapper b/arch/powerpc/boot/wrapper
index 5cedd901201f..2ed8b8b3f0ec 100755
--- a/arch/powerpc/boot/wrapper
+++ b/arch/powerpc/boot/wrapper
@@ -163,20 +163,19 @@ fi
163 163
164vmz="$vmz$gzip" 164vmz="$vmz$gzip"
165 165
166case "$platform" in 166# Extract kernel version information, some platforms want to include
167uboot|cuboot*) 167# it in the image header
168 version=`${CROSS}strings "$kernel" | grep '^Linux version [-0-9.]' | \ 168version=`${CROSS}strings "$kernel" | grep '^Linux version [-0-9.]' | \
169 cut -d' ' -f3` 169 cut -d' ' -f3`
170 if [ -n "$version" ]; then 170if [ -n "$version" ]; then
171 version="-n Linux-$version" 171 uboot_version="-n Linux-$version"
172 fi 172fi
173esac
174 173
175case "$platform" in 174case "$platform" in
176uboot) 175uboot)
177 rm -f "$ofile" 176 rm -f "$ofile"
178 mkimage -A ppc -O linux -T kernel -C gzip -a 00000000 -e 00000000 \ 177 mkimage -A ppc -O linux -T kernel -C gzip -a 00000000 -e 00000000 \
179 $version -d "$vmz" "$ofile" 178 $uboot_version -d "$vmz" "$ofile"
180 if [ -z "$cacheit" ]; then 179 if [ -z "$cacheit" ]; then
181 rm -f "$vmz" 180 rm -f "$vmz"
182 fi 181 fi
@@ -212,25 +211,32 @@ if [ "$platform" != "miboot" ]; then
212 rm $tmp 211 rm $tmp
213fi 212fi
214 213
214# Some platforms need the zImage's entry point and base address
215base=0x`${CROSS}nm "$ofile" | grep ' _start$' | cut -d' ' -f1`
216entry=`${CROSS}objdump -f "$ofile" | grep '^start address ' | cut -d' ' -f3`
217
215# post-processing needed for some platforms 218# post-processing needed for some platforms
216case "$platform" in 219case "$platform" in
217pseries|chrp) 220pseries|chrp)
218 $object/addnote "$ofile" 221 $object/addnote "$ofile"
219 ;; 222 ;;
220pmaccoff) 223pmaccoff)
221 entry=`objdump -f "$ofile" | grep '^start address ' | \
222 cut -d' ' -f3`
223 ${CROSS}objcopy -O aixcoff-rs6000 --set-start "$entry" "$ofile" 224 ${CROSS}objcopy -O aixcoff-rs6000 --set-start "$entry" "$ofile"
224 $object/hack-coff "$ofile" 225 $object/hack-coff "$ofile"
225 ;; 226 ;;
226cuboot*) 227cuboot*)
227 base=`${CROSS}nm "$ofile" | grep ' _start$' | cut -d' ' -f1`
228 entry=`${CROSS}objdump -f "$ofile" | grep '^start address ' | \
229 cut -d' ' -f3`
230 mv "$ofile" "$ofile".elf 228 mv "$ofile" "$ofile".elf
231 ${CROSS}objcopy -O binary "$ofile".elf "$ofile".bin 229 ${CROSS}objcopy -O binary "$ofile".elf "$ofile".bin
232 gzip -f -9 "$ofile".bin 230 gzip -f -9 "$ofile".bin
233 mkimage -A ppc -O linux -T kernel -C gzip -a "$base" -e "$entry" \ 231 mkimage -A ppc -O linux -T kernel -C gzip -a "$base" -e "$entry" \
234 $version -d "$ofile".bin.gz "$ofile" 232 $uboot_version -d "$ofile".bin.gz "$ofile"
233 ;;
234treeboot*)
235 mv "$ofile" "$ofile.elf"
236 $object/mktree "$ofile.elf" "$ofile" "$base" "$entry"
237 if [ -z "$cacheit" ]; then
238 rm -f "$ofile.elf"
239 fi
240 exit 0
235 ;; 241 ;;
236esac 242esac
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-10 22:14:39 -0500