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-rw-r--r--arch/powerpc/boot/addRamDisk.c6
-rw-r--r--arch/powerpc/boot/dts/cm5200.dts1
-rw-r--r--arch/powerpc/boot/dts/digsy_mtc.dts1
-rw-r--r--arch/powerpc/boot/dts/lite5200.dts2
-rw-r--r--arch/powerpc/boot/dts/lite5200b.dts2
-rw-r--r--arch/powerpc/boot/dts/media5200.dts2
-rw-r--r--arch/powerpc/boot/dts/motionpro.dts1
-rw-r--r--arch/powerpc/boot/dts/mpc5121ads.dts3
-rw-r--r--arch/powerpc/boot/dts/mpc8377_wlan.dts2
-rw-r--r--arch/powerpc/boot/dts/mpc8569mds.dts4
-rw-r--r--arch/powerpc/boot/dts/mucmc52.dts332
-rw-r--r--arch/powerpc/boot/dts/pcm030.dts2
-rw-r--r--arch/powerpc/boot/dts/pcm032.dts2
-rw-r--r--arch/powerpc/boot/dts/sbc8548.dts17
-rw-r--r--arch/powerpc/boot/dts/tqm5200.dts1
-rw-r--r--arch/powerpc/boot/dts/uc101.dts284
16 files changed, 630 insertions, 32 deletions
diff --git a/arch/powerpc/boot/addRamDisk.c b/arch/powerpc/boot/addRamDisk.c
index c02a99952be7..893f446cbd22 100644
--- a/arch/powerpc/boot/addRamDisk.c
+++ b/arch/powerpc/boot/addRamDisk.c
@@ -58,7 +58,7 @@ static int check_elf64(void *p, int size, struct addr_range *r)
58 58
59 return 64; 59 return 64;
60} 60}
61void get4k(FILE *file, char *buf ) 61static void get4k(FILE *file, char *buf )
62{ 62{
63 unsigned j; 63 unsigned j;
64 unsigned num = fread(buf, 1, 4096, file); 64 unsigned num = fread(buf, 1, 4096, file);
@@ -66,12 +66,12 @@ void get4k(FILE *file, char *buf )
66 buf[j] = 0; 66 buf[j] = 0;
67} 67}
68 68
69void put4k(FILE *file, char *buf ) 69static void put4k(FILE *file, char *buf )
70{ 70{
71 fwrite(buf, 1, 4096, file); 71 fwrite(buf, 1, 4096, file);
72} 72}
73 73
74void death(const char *msg, FILE *fdesc, const char *fname) 74static void death(const char *msg, FILE *fdesc, const char *fname)
75{ 75{
76 fprintf(stderr, msg); 76 fprintf(stderr, msg);
77 fclose(fdesc); 77 fclose(fdesc);
diff --git a/arch/powerpc/boot/dts/cm5200.dts b/arch/powerpc/boot/dts/cm5200.dts
index cee8080aa245..dd3860846f15 100644
--- a/arch/powerpc/boot/dts/cm5200.dts
+++ b/arch/powerpc/boot/dts/cm5200.dts
@@ -210,7 +210,6 @@
210 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; 210 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
211 reg = <0x3d40 0x40>; 211 reg = <0x3d40 0x40>;
212 interrupts = <2 16 0>; 212 interrupts = <2 16 0>;
213 fsl5200-clocking;
214 }; 213 };
215 214
216 sram@8000 { 215 sram@8000 {
diff --git a/arch/powerpc/boot/dts/digsy_mtc.dts b/arch/powerpc/boot/dts/digsy_mtc.dts
index 4c36186ef946..8e9be6bfe23e 100644
--- a/arch/powerpc/boot/dts/digsy_mtc.dts
+++ b/arch/powerpc/boot/dts/digsy_mtc.dts
@@ -199,7 +199,6 @@
199 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; 199 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
200 reg = <0x3d00 0x40>; 200 reg = <0x3d00 0x40>;
201 interrupts = <2 15 0>; 201 interrupts = <2 15 0>;
202 fsl5200-clocking;
203 202
204 rtc@50 { 203 rtc@50 {
205 compatible = "at,24c08"; 204 compatible = "at,24c08";
diff --git a/arch/powerpc/boot/dts/lite5200.dts b/arch/powerpc/boot/dts/lite5200.dts
index de30b3f9eb26..82ff2b13bc37 100644
--- a/arch/powerpc/boot/dts/lite5200.dts
+++ b/arch/powerpc/boot/dts/lite5200.dts
@@ -247,7 +247,6 @@
247 compatible = "fsl,mpc5200-i2c","fsl-i2c"; 247 compatible = "fsl,mpc5200-i2c","fsl-i2c";
248 reg = <0x3d00 0x40>; 248 reg = <0x3d00 0x40>;
249 interrupts = <2 15 0>; 249 interrupts = <2 15 0>;
250 fsl5200-clocking;
251 }; 250 };
252 251
253 i2c@3d40 { 252 i2c@3d40 {
@@ -256,7 +255,6 @@
256 compatible = "fsl,mpc5200-i2c","fsl-i2c"; 255 compatible = "fsl,mpc5200-i2c","fsl-i2c";
257 reg = <0x3d40 0x40>; 256 reg = <0x3d40 0x40>;
258 interrupts = <2 16 0>; 257 interrupts = <2 16 0>;
259 fsl5200-clocking;
260 }; 258 };
261 sram@8000 { 259 sram@8000 {
262 compatible = "fsl,mpc5200-sram"; 260 compatible = "fsl,mpc5200-sram";
diff --git a/arch/powerpc/boot/dts/lite5200b.dts b/arch/powerpc/boot/dts/lite5200b.dts
index d13cb11ce623..e45a63be3a86 100644
--- a/arch/powerpc/boot/dts/lite5200b.dts
+++ b/arch/powerpc/boot/dts/lite5200b.dts
@@ -251,7 +251,6 @@
251 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; 251 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
252 reg = <0x3d00 0x40>; 252 reg = <0x3d00 0x40>;
253 interrupts = <2 15 0>; 253 interrupts = <2 15 0>;
254 fsl5200-clocking;
255 }; 254 };
256 255
257 i2c@3d40 { 256 i2c@3d40 {
@@ -260,7 +259,6 @@
260 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; 259 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
261 reg = <0x3d40 0x40>; 260 reg = <0x3d40 0x40>;
262 interrupts = <2 16 0>; 261 interrupts = <2 16 0>;
263 fsl5200-clocking;
264 }; 262 };
265 263
266 sram@8000 { 264 sram@8000 {
diff --git a/arch/powerpc/boot/dts/media5200.dts b/arch/powerpc/boot/dts/media5200.dts
index e297d8b41875..0c3902bc5b6a 100644
--- a/arch/powerpc/boot/dts/media5200.dts
+++ b/arch/powerpc/boot/dts/media5200.dts
@@ -223,7 +223,6 @@
223 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; 223 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
224 reg = <0x3d00 0x40>; 224 reg = <0x3d00 0x40>;
225 interrupts = <2 15 0>; 225 interrupts = <2 15 0>;
226 fsl5200-clocking;
227 }; 226 };
228 227
229 i2c@3d40 { 228 i2c@3d40 {
@@ -232,7 +231,6 @@
232 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; 231 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
233 reg = <0x3d40 0x40>; 232 reg = <0x3d40 0x40>;
234 interrupts = <2 16 0>; 233 interrupts = <2 16 0>;
235 fsl5200-clocking;
236 }; 234 };
237 235
238 sram@8000 { 236 sram@8000 {
diff --git a/arch/powerpc/boot/dts/motionpro.dts b/arch/powerpc/boot/dts/motionpro.dts
index 7be8ca038676..6ca4fc144a33 100644
--- a/arch/powerpc/boot/dts/motionpro.dts
+++ b/arch/powerpc/boot/dts/motionpro.dts
@@ -222,7 +222,6 @@
222 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; 222 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
223 reg = <0x3d40 0x40>; 223 reg = <0x3d40 0x40>;
224 interrupts = <2 16 0>; 224 interrupts = <2 16 0>;
225 fsl5200-clocking;
226 225
227 rtc@68 { 226 rtc@68 {
228 compatible = "dallas,ds1339"; 227 compatible = "dallas,ds1339";
diff --git a/arch/powerpc/boot/dts/mpc5121ads.dts b/arch/powerpc/boot/dts/mpc5121ads.dts
index c2b8dbfab79e..c353dac33416 100644
--- a/arch/powerpc/boot/dts/mpc5121ads.dts
+++ b/arch/powerpc/boot/dts/mpc5121ads.dts
@@ -209,7 +209,6 @@
209 reg = <0x1700 0x20>; 209 reg = <0x1700 0x20>;
210 interrupts = <9 0x8>; 210 interrupts = <9 0x8>;
211 interrupt-parent = < &ipic >; 211 interrupt-parent = < &ipic >;
212 fsl5200-clocking;
213 }; 212 };
214 213
215 i2c@1720 { 214 i2c@1720 {
@@ -220,7 +219,6 @@
220 reg = <0x1720 0x20>; 219 reg = <0x1720 0x20>;
221 interrupts = <10 0x8>; 220 interrupts = <10 0x8>;
222 interrupt-parent = < &ipic >; 221 interrupt-parent = < &ipic >;
223 fsl5200-clocking;
224 }; 222 };
225 223
226 i2c@1740 { 224 i2c@1740 {
@@ -231,7 +229,6 @@
231 reg = <0x1740 0x20>; 229 reg = <0x1740 0x20>;
232 interrupts = <11 0x8>; 230 interrupts = <11 0x8>;
233 interrupt-parent = < &ipic >; 231 interrupt-parent = < &ipic >;
234 fsl5200-clocking;
235 }; 232 };
236 233
237 i2ccontrol@1760 { 234 i2ccontrol@1760 {
diff --git a/arch/powerpc/boot/dts/mpc8377_wlan.dts b/arch/powerpc/boot/dts/mpc8377_wlan.dts
index 9a603695723b..9ea783056969 100644
--- a/arch/powerpc/boot/dts/mpc8377_wlan.dts
+++ b/arch/powerpc/boot/dts/mpc8377_wlan.dts
@@ -67,7 +67,7 @@
67 device-width = <1>; 67 device-width = <1>;
68 68
69 partition@0 { 69 partition@0 {
70 reg = <0 0x8000>; 70 reg = <0 0x80000>;
71 label = "u-boot"; 71 label = "u-boot";
72 read-only; 72 read-only;
73 }; 73 };
diff --git a/arch/powerpc/boot/dts/mpc8569mds.dts b/arch/powerpc/boot/dts/mpc8569mds.dts
index 06332d61830a..1e3ec8f059bf 100644
--- a/arch/powerpc/boot/dts/mpc8569mds.dts
+++ b/arch/powerpc/boot/dts/mpc8569mds.dts
@@ -487,8 +487,8 @@
487 &qe_pio_f 5 0 /* USBTN */ 487 &qe_pio_f 5 0 /* USBTN */
488 &qe_pio_f 6 0 /* USBRP */ 488 &qe_pio_f 6 0 /* USBRP */
489 &qe_pio_f 8 0 /* USBRN */ 489 &qe_pio_f 8 0 /* USBRN */
490 &bcsr17 6 0 /* SPEED */ 490 &bcsr17 1 0 /* SPEED */
491 &bcsr17 5 1>; /* POWER */ 491 &bcsr17 2 0>; /* POWER */
492 }; 492 };
493 493
494 enet0: ucc@2000 { 494 enet0: ucc@2000 {
diff --git a/arch/powerpc/boot/dts/mucmc52.dts b/arch/powerpc/boot/dts/mucmc52.dts
new file mode 100644
index 000000000000..b72a7581d798
--- /dev/null
+++ b/arch/powerpc/boot/dts/mucmc52.dts
@@ -0,0 +1,332 @@
1/*
2 * Manroland mucmc52 board Device Tree Source
3 *
4 * Copyright (C) 2009 DENX Software Engineering GmbH
5 * Heiko Schocher <hs@denx.de>
6 * Copyright 2006-2007 Secret Lab Technologies Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14/dts-v1/;
15
16/ {
17 model = "manroland,mucmc52";
18 compatible = "manroland,mucmc52";
19 #address-cells = <1>;
20 #size-cells = <1>;
21 interrupt-parent = <&mpc5200_pic>;
22
23 cpus {
24 #address-cells = <1>;
25 #size-cells = <0>;
26
27 PowerPC,5200@0 {
28 device_type = "cpu";
29 reg = <0>;
30 d-cache-line-size = <32>;
31 i-cache-line-size = <32>;
32 d-cache-size = <0x4000>; // L1, 16K
33 i-cache-size = <0x4000>; // L1, 16K
34 timebase-frequency = <0>; // from bootloader
35 bus-frequency = <0>; // from bootloader
36 clock-frequency = <0>; // from bootloader
37 };
38 };
39
40 memory {
41 device_type = "memory";
42 reg = <0x00000000 0x04000000>; // 64MB
43 };
44
45 soc5200@f0000000 {
46 #address-cells = <1>;
47 #size-cells = <1>;
48 compatible = "fsl,mpc5200b-immr";
49 ranges = <0 0xf0000000 0x0000c000>;
50 reg = <0xf0000000 0x00000100>;
51 bus-frequency = <0>; // from bootloader
52 system-frequency = <0>; // from bootloader
53
54 cdm@200 {
55 compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
56 reg = <0x200 0x38>;
57 };
58
59 mpc5200_pic: interrupt-controller@500 {
60 // 5200 interrupts are encoded into two levels;
61 interrupt-controller;
62 #interrupt-cells = <3>;
63 compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
64 reg = <0x500 0x80>;
65 };
66
67 gpt0: timer@600 { // GPT 0 in GPIO mode
68 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
69 reg = <0x600 0x10>;
70 interrupts = <1 9 0>;
71 gpio-controller;
72 #gpio-cells = <2>;
73 };
74
75 gpt1: timer@610 { // General Purpose Timer in GPIO mode
76 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
77 reg = <0x610 0x10>;
78 interrupts = <1 10 0>;
79 gpio-controller;
80 #gpio-cells = <2>;
81 };
82
83 gpt2: timer@620 { // General Purpose Timer in GPIO mode
84 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
85 reg = <0x620 0x10>;
86 interrupts = <1 11 0>;
87 gpio-controller;
88 #gpio-cells = <2>;
89 };
90
91 gpt3: timer@630 { // General Purpose Timer in GPIO mode
92 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
93 reg = <0x630 0x10>;
94 interrupts = <1 12 0>;
95 gpio-controller;
96 #gpio-cells = <2>;
97 };
98
99 gpio_simple: gpio@b00 {
100 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
101 reg = <0xb00 0x40>;
102 interrupts = <1 7 0>;
103 gpio-controller;
104 #gpio-cells = <2>;
105 };
106
107 gpio_wkup: gpio@c00 {
108 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
109 reg = <0xc00 0x40>;
110 interrupts = <1 8 0 0 3 0>;
111 gpio-controller;
112 #gpio-cells = <2>;
113 };
114
115 dma-controller@1200 {
116 compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
117 reg = <0x1200 0x80>;
118 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
119 3 4 0 3 5 0 3 6 0 3 7 0
120 3 8 0 3 9 0 3 10 0 3 11 0
121 3 12 0 3 13 0 3 14 0 3 15 0>;
122 };
123
124 xlb@1f00 {
125 compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
126 reg = <0x1f00 0x100>;
127 };
128
129 serial@2000 { /* PSC1 in UART mode */
130 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
131 reg = <0x2000 0x100>;
132 interrupts = <2 1 0>;
133 };
134
135 serial@2200 { /* PSC2 in UART mode */
136 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
137 reg = <0x2200 0x100>;
138 interrupts = <2 2 0>;
139 };
140
141 serial@2c00 { /* PSC6 in UART mode */
142 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
143 reg = <0x2c00 0x100>;
144 interrupts = <2 4 0>;
145 };
146
147 ethernet@3000 {
148 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
149 reg = <0x3000 0x400>;
150 local-mac-address = [ 00 00 00 00 00 00 ];
151 interrupts = <2 5 0>;
152 phy-handle = <&phy0>;
153 };
154
155 mdio@3000 {
156 #address-cells = <1>;
157 #size-cells = <0>;
158 compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
159 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
160 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
161
162 phy0: ethernet-phy@0 {
163 compatible = "intel,lxt971";
164 reg = <0>;
165 };
166 };
167
168 ata@3a00 {
169 compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
170 reg = <0x3a00 0x100>;
171 interrupts = <2 7 0>;
172 };
173
174 i2c@3d40 {
175 #address-cells = <1>;
176 #size-cells = <0>;
177 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
178 reg = <0x3d40 0x40>;
179 interrupts = <2 16 0>;
180 hwmon@2c {
181 compatible = "ad,adm9240";
182 reg = <0x2c>;
183 };
184 rtc@51 {
185 compatible = "nxp,pcf8563";
186 reg = <0x51>;
187 };
188 };
189
190 sram@8000 {
191 compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
192 reg = <0x8000 0x4000>;
193 };
194 };
195
196 pci@f0000d00 {
197 #interrupt-cells = <1>;
198 #size-cells = <2>;
199 #address-cells = <3>;
200 device_type = "pci";
201 compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci";
202 reg = <0xf0000d00 0x100>;
203 interrupt-map-mask = <0xf800 0 0 7>;
204 interrupt-map = <
205 /* IDSEL 0x10 */
206 0x8000 0 0 1 &mpc5200_pic 0 3 3
207 0x8000 0 0 2 &mpc5200_pic 0 3 3
208 0x8000 0 0 3 &mpc5200_pic 0 2 3
209 0x8000 0 0 4 &mpc5200_pic 0 1 3
210 >;
211 clock-frequency = <0>; // From boot loader
212 interrupts = <2 8 0 2 9 0 2 10 0>;
213 bus-range = <0 0>;
214 ranges = <0x42000000 0 0x60000000 0x60000000 0 0x10000000
215 0x02000000 0 0x90000000 0x90000000 0 0x10000000
216 0x01000000 0 0x00000000 0xa0000000 0 0x01000000>;
217 };
218
219 localbus {
220 compatible = "fsl,mpc5200b-lpb","fsl,mpc5200-lpb","simple-bus";
221
222 #address-cells = <2>;
223 #size-cells = <1>;
224
225 ranges = <0 0 0xff800000 0x00800000
226 1 0 0x80000000 0x00800000
227 3 0 0x80000000 0x00800000>;
228
229 flash@0,0 {
230 compatible = "cfi-flash";
231 reg = <0 0 0x00800000>;
232 bank-width = <4>;
233 device-width = <2>;
234 #size-cells = <1>;
235 #address-cells = <1>;
236 partition@0 {
237 label = "DTS";
238 reg = <0x0 0x00100000>;
239 };
240 partition@100000 {
241 label = "Kernel";
242 reg = <0x100000 0x00200000>;
243 };
244 partition@300000 {
245 label = "RootFS";
246 reg = <0x00300000 0x00200000>;
247 };
248 partition@500000 {
249 label = "user";
250 reg = <0x00500000 0x00200000>;
251 };
252 partition@700000 {
253 label = "U-Boot";
254 reg = <0x00700000 0x00040000>;
255 };
256 partition@740000 {
257 label = "Env";
258 reg = <0x00740000 0x00020000>;
259 };
260 partition@760000 {
261 label = "red. Env";
262 reg = <0x00760000 0x00020000>;
263 };
264 partition@780000 {
265 label = "reserve";
266 reg = <0x00780000 0x00080000>;
267 };
268 };
269
270 simple100: gpio-controller-100@3,600100 {
271 compatible = "manroland,mucmc52-aux-gpio";
272 reg = <3 0x00600100 0x1>;
273 gpio-controller;
274 #gpio-cells = <2>;
275 };
276 simple104: gpio-controller-104@3,600104 {
277 compatible = "manroland,mucmc52-aux-gpio";
278 reg = <3 0x00600104 0x1>;
279 gpio-controller;
280 #gpio-cells = <2>;
281 };
282 simple200: gpio-controller-200@3,600200 {
283 compatible = "manroland,mucmc52-aux-gpio";
284 reg = <3 0x00600200 0x1>;
285 gpio-controller;
286 #gpio-cells = <2>;
287 };
288 simple201: gpio-controller-201@3,600201 {
289 compatible = "manroland,mucmc52-aux-gpio";
290 reg = <3 0x00600201 0x1>;
291 gpio-controller;
292 #gpio-cells = <2>;
293 };
294 simple202: gpio-controller-202@3,600202 {
295 compatible = "manroland,mucmc52-aux-gpio";
296 reg = <3 0x00600202 0x1>;
297 gpio-controller;
298 #gpio-cells = <2>;
299 };
300 simple203: gpio-controller-203@3,600203 {
301 compatible = "manroland,mucmc52-aux-gpio";
302 reg = <3 0x00600203 0x1>;
303 gpio-controller;
304 #gpio-cells = <2>;
305 };
306 simple204: gpio-controller-204@3,600204 {
307 compatible = "manroland,mucmc52-aux-gpio";
308 reg = <3 0x00600204 0x1>;
309 gpio-controller;
310 #gpio-cells = <2>;
311 };
312 simple206: gpio-controller-206@3,600206 {
313 compatible = "manroland,mucmc52-aux-gpio";
314 reg = <3 0x00600206 0x1>;
315 gpio-controller;
316 #gpio-cells = <2>;
317 };
318 simple207: gpio-controller-207@3,600207 {
319 compatible = "manroland,mucmc52-aux-gpio";
320 reg = <3 0x00600207 0x1>;
321 gpio-controller;
322 #gpio-cells = <2>;
323 };
324 simple20f: gpio-controller-20f@3,60020f {
325 compatible = "manroland,mucmc52-aux-gpio";
326 reg = <3 0x0060020f 0x1>;
327 gpio-controller;
328 #gpio-cells = <2>;
329 };
330
331 };
332};
diff --git a/arch/powerpc/boot/dts/pcm030.dts b/arch/powerpc/boot/dts/pcm030.dts
index 30bfdc04c6df..8a4ec30b21ae 100644
--- a/arch/powerpc/boot/dts/pcm030.dts
+++ b/arch/powerpc/boot/dts/pcm030.dts
@@ -244,7 +244,6 @@
244 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; 244 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
245 reg = <0x3d00 0x40>; 245 reg = <0x3d00 0x40>;
246 interrupts = <2 15 0>; 246 interrupts = <2 15 0>;
247 fsl5200-clocking;
248 }; 247 };
249 248
250 i2c@3d40 { 249 i2c@3d40 {
@@ -253,7 +252,6 @@
253 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; 252 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
254 reg = <0x3d40 0x40>; 253 reg = <0x3d40 0x40>;
255 interrupts = <2 16 0>; 254 interrupts = <2 16 0>;
256 fsl5200-clocking;
257 rtc@51 { 255 rtc@51 {
258 compatible = "nxp,pcf8563"; 256 compatible = "nxp,pcf8563";
259 reg = <0x51>; 257 reg = <0x51>;
diff --git a/arch/powerpc/boot/dts/pcm032.dts b/arch/powerpc/boot/dts/pcm032.dts
index 030042678392..85d857a5d46e 100644
--- a/arch/powerpc/boot/dts/pcm032.dts
+++ b/arch/powerpc/boot/dts/pcm032.dts
@@ -244,7 +244,6 @@
244 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; 244 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
245 reg = <0x3d00 0x40>; 245 reg = <0x3d00 0x40>;
246 interrupts = <2 15 0>; 246 interrupts = <2 15 0>;
247 fsl5200-clocking;
248 }; 247 };
249 248
250 i2c@3d40 { 249 i2c@3d40 {
@@ -253,7 +252,6 @@
253 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; 252 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
254 reg = <0x3d40 0x40>; 253 reg = <0x3d40 0x40>;
255 interrupts = <2 16 0>; 254 interrupts = <2 16 0>;
256 fsl5200-clocking;
257 rtc@51 { 255 rtc@51 {
258 compatible = "nxp,pcf8563"; 256 compatible = "nxp,pcf8563";
259 reg = <0x51>; 257 reg = <0x51>;
diff --git a/arch/powerpc/boot/dts/sbc8548.dts b/arch/powerpc/boot/dts/sbc8548.dts
index 9eefe00ed253..94a332251710 100644
--- a/arch/powerpc/boot/dts/sbc8548.dts
+++ b/arch/powerpc/boot/dts/sbc8548.dts
@@ -26,8 +26,7 @@
26 serial0 = &serial0; 26 serial0 = &serial0;
27 serial1 = &serial1; 27 serial1 = &serial1;
28 pci0 = &pci0; 28 pci0 = &pci0;
29 /* pci1 doesn't have a corresponding physical connector */ 29 pci1 = &pci1;
30 pci2 = &pci2;
31 }; 30 };
32 31
33 cpus { 32 cpus {
@@ -381,7 +380,7 @@
381 bus-range = <0 0>; 380 bus-range = <0 0>;
382 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x10000000 381 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x10000000
383 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00800000>; 382 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00800000>;
384 clock-frequency = <66666666>; 383 clock-frequency = <66000000>;
385 #interrupt-cells = <1>; 384 #interrupt-cells = <1>;
386 #size-cells = <2>; 385 #size-cells = <2>;
387 #address-cells = <3>; 386 #address-cells = <3>;
@@ -390,7 +389,7 @@
390 device_type = "pci"; 389 device_type = "pci";
391 }; 390 };
392 391
393 pci2: pcie@e000a000 { 392 pci1: pcie@e000a000 {
394 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 393 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
395 interrupt-map = < 394 interrupt-map = <
396 395
@@ -403,9 +402,9 @@
403 interrupt-parent = <&mpic>; 402 interrupt-parent = <&mpic>;
404 interrupts = <0x1a 0x2>; 403 interrupts = <0x1a 0x2>;
405 bus-range = <0x0 0xff>; 404 bus-range = <0x0 0xff>;
406 ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000 405 ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
407 0x01000000 0x0 0x00000000 0xe3000000 0x0 0x08000000>; 406 0x01000000 0x0 0x00000000 0xe2800000 0x0 0x08000000>;
408 clock-frequency = <33333333>; 407 clock-frequency = <33000000>;
409 #interrupt-cells = <1>; 408 #interrupt-cells = <1>;
410 #size-cells = <2>; 409 #size-cells = <2>;
411 #address-cells = <3>; 410 #address-cells = <3>;
@@ -419,11 +418,11 @@
419 device_type = "pci"; 418 device_type = "pci";
420 ranges = <0x02000000 0x0 0xa0000000 419 ranges = <0x02000000 0x0 0xa0000000
421 0x02000000 0x0 0xa0000000 420 0x02000000 0x0 0xa0000000
422 0x0 0x20000000 421 0x0 0x10000000
423 422
424 0x01000000 0x0 0x00000000 423 0x01000000 0x0 0x00000000
425 0x01000000 0x0 0x00000000 424 0x01000000 0x0 0x00000000
426 0x0 0x08000000>; 425 0x0 0x00800000>;
427 }; 426 };
428 }; 427 };
429}; 428};
diff --git a/arch/powerpc/boot/dts/tqm5200.dts b/arch/powerpc/boot/dts/tqm5200.dts
index c9590b58b7b0..1db07f6cf133 100644
--- a/arch/powerpc/boot/dts/tqm5200.dts
+++ b/arch/powerpc/boot/dts/tqm5200.dts
@@ -160,7 +160,6 @@
160 compatible = "fsl,mpc5200-i2c","fsl-i2c"; 160 compatible = "fsl,mpc5200-i2c","fsl-i2c";
161 reg = <0x3d40 0x40>; 161 reg = <0x3d40 0x40>;
162 interrupts = <2 16 0>; 162 interrupts = <2 16 0>;
163 fsl5200-clocking;
164 163
165 rtc@68 { 164 rtc@68 {
166 compatible = "dallas,ds1307"; 165 compatible = "dallas,ds1307";
diff --git a/arch/powerpc/boot/dts/uc101.dts b/arch/powerpc/boot/dts/uc101.dts
new file mode 100644
index 000000000000..019264c62904
--- /dev/null
+++ b/arch/powerpc/boot/dts/uc101.dts
@@ -0,0 +1,284 @@
1/*
2 * Manroland uc101 board Device Tree Source
3 *
4 * Copyright (C) 2009 DENX Software Engineering GmbH
5 * Heiko Schocher <hs@denx.de>
6 * Copyright 2006-2007 Secret Lab Technologies Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14/dts-v1/;
15
16/ {
17 model = "manroland,uc101";
18 compatible = "manroland,uc101";
19 #address-cells = <1>;
20 #size-cells = <1>;
21 interrupt-parent = <&mpc5200_pic>;
22
23 cpus {
24 #address-cells = <1>;
25 #size-cells = <0>;
26
27 PowerPC,5200@0 {
28 device_type = "cpu";
29 reg = <0>;
30 d-cache-line-size = <32>;
31 i-cache-line-size = <32>;
32 d-cache-size = <0x4000>; // L1, 16K
33 i-cache-size = <0x4000>; // L1, 16K
34 timebase-frequency = <0>; // from bootloader
35 bus-frequency = <0>; // from bootloader
36 clock-frequency = <0>; // from bootloader
37 };
38 };
39
40 memory {
41 device_type = "memory";
42 reg = <0x00000000 0x04000000>; // 64MB
43 };
44
45 soc5200@f0000000 {
46 #address-cells = <1>;
47 #size-cells = <1>;
48 compatible = "fsl,mpc5200b-immr";
49 ranges = <0 0xf0000000 0x0000c000>;
50 reg = <0xf0000000 0x00000100>;
51 bus-frequency = <0>; // from bootloader
52 system-frequency = <0>; // from bootloader
53
54 cdm@200 {
55 compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
56 reg = <0x200 0x38>;
57 };
58
59 mpc5200_pic: interrupt-controller@500 {
60 // 5200 interrupts are encoded into two levels;
61 interrupt-controller;
62 #interrupt-cells = <3>;
63 compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
64 reg = <0x500 0x80>;
65 };
66
67 gpt0: timer@600 { // General Purpose Timer in GPIO mode
68 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
69 reg = <0x600 0x10>;
70 interrupts = <1 9 0>;
71 gpio-controller;
72 #gpio-cells = <2>;
73 };
74
75 gpt1: timer@610 { // General Purpose Timer in GPIO mode
76 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
77 reg = <0x610 0x10>;
78 interrupts = <1 10 0>;
79 gpio-controller;
80 #gpio-cells = <2>;
81 };
82
83 gpt2: timer@620 { // General Purpose Timer in GPIO mode
84 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
85 reg = <0x620 0x10>;
86 interrupts = <1 11 0>;
87 gpio-controller;
88 #gpio-cells = <2>;
89 };
90
91 gpt3: timer@630 { // General Purpose Timer in GPIO mode
92 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
93 reg = <0x630 0x10>;
94 interrupts = <1 12 0>;
95 gpio-controller;
96 #gpio-cells = <2>;
97 };
98
99 gpt4: timer@640 { // General Purpose Timer in GPIO mode
100 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
101 reg = <0x640 0x10>;
102 interrupts = <1 13 0>;
103 gpio-controller;
104 #gpio-cells = <2>;
105 };
106
107 gpt5: timer@650 { // General Purpose Timer in GPIO mode
108 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
109 reg = <0x650 0x10>;
110 interrupts = <1 14 0>;
111 gpio-controller;
112 #gpio-cells = <2>;
113 };
114
115 gpt6: timer@660 { // General Purpose Timer in GPIO mode
116 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
117 reg = <0x660 0x10>;
118 interrupts = <1 15 0>;
119 gpio-controller;
120 #gpio-cells = <2>;
121 };
122
123 gpt7: timer@670 { // General Purpose Timer in GPIO mode
124 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
125 reg = <0x670 0x10>;
126 interrupts = <1 16 0>;
127 gpio-controller;
128 #gpio-cells = <2>;
129 };
130
131 gpio_simple: gpio@b00 {
132 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
133 reg = <0xb00 0x40>;
134 interrupts = <1 7 0>;
135 gpio-controller;
136 #gpio-cells = <2>;
137 };
138
139 gpio_wkup: gpio@c00 {
140 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
141 reg = <0xc00 0x40>;
142 interrupts = <1 8 0 0 3 0>;
143 gpio-controller;
144 #gpio-cells = <2>;
145 };
146
147 dma-controller@1200 {
148 compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
149 reg = <0x1200 0x80>;
150 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
151 3 4 0 3 5 0 3 6 0 3 7 0
152 3 8 0 3 9 0 3 10 0 3 11 0
153 3 12 0 3 13 0 3 14 0 3 15 0>;
154 };
155
156 xlb@1f00 {
157 compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
158 reg = <0x1f00 0x100>;
159 };
160
161 serial@2000 { /* PSC1 in UART mode */
162 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
163 reg = <0x2000 0x100>;
164 interrupts = <2 1 0>;
165 };
166
167 serial@2200 { /* PSC2 in UART mode */
168 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
169 reg = <0x2200 0x100>;
170 interrupts = <2 2 0>;
171 };
172
173 serial@2c00 { /* PSC6 in UART mode */
174 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
175 reg = <0x2c00 0x100>;
176 interrupts = <2 4 0>;
177 };
178
179 ethernet@3000 {
180 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
181 reg = <0x3000 0x400>;
182 local-mac-address = [ 00 00 00 00 00 00 ];
183 interrupts = <2 5 0>;
184 phy-handle = <&phy0>;
185 };
186
187 mdio@3000 {
188 #address-cells = <1>;
189 #size-cells = <0>;
190 compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
191 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
192 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
193
194 phy0: ethernet-phy@0 {
195 compatible = "intel,lxt971";
196 reg = <0>;
197 };
198 };
199
200 ata@3a00 {
201 compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
202 reg = <0x3a00 0x100>;
203 interrupts = <2 7 0>;
204 };
205
206 i2c@3d40 {
207 #address-cells = <1>;
208 #size-cells = <0>;
209 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
210 reg = <0x3d40 0x40>;
211 interrupts = <2 16 0>;
212 fsl,preserve-clocking;
213 clock-frequency = <400000>;
214
215 hwmon@2c {
216 compatible = "ad,adm9240";
217 reg = <0x2c>;
218 };
219 rtc@51 {
220 compatible = "nxp,pcf8563";
221 reg = <0x51>;
222 };
223 };
224
225 sram@8000 {
226 compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
227 reg = <0x8000 0x4000>;
228 };
229 };
230
231 localbus {
232 compatible = "fsl,mpc5200b-lpb","fsl,mpc5200-lpb","simple-bus";
233
234 #address-cells = <2>;
235 #size-cells = <1>;
236
237 ranges = <0 0 0xff800000 0x00800000
238 1 0 0x80000000 0x00800000
239 3 0 0x80000000 0x00800000>;
240
241 flash@0,0 {
242 compatible = "cfi-flash";
243 reg = <0 0 0x00800000>;
244 bank-width = <2>;
245 device-width = <2>;
246 #size-cells = <1>;
247 #address-cells = <1>;
248
249 partition@0 {
250 label = "DTS";
251 reg = <0x0 0x00100000>;
252 };
253 partition@100000 {
254 label = "Kernel";
255 reg = <0x100000 0x00200000>;
256 };
257 partition@300000 {
258 label = "RootFS";
259 reg = <0x00300000 0x00200000>;
260 };
261 partition@500000 {
262 label = "user";
263 reg = <0x00500000 0x00200000>;
264 };
265 partition@700000 {
266 label = "U-Boot";
267 reg = <0x00700000 0x00040000>;
268 };
269 partition@740000 {
270 label = "Env";
271 reg = <0x00740000 0x00010000>;
272 };
273 partition@750000 {
274 label = "red. Env";
275 reg = <0x00750000 0x00010000>;
276 };
277 partition@760000 {
278 label = "reserve";
279 reg = <0x00760000 0x000a0000>;
280 };
281 };
282
283 };
284};
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-18 07:43:00 -0500