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-rw-r--r--arch/powerpc/boot/Makefile4
-rw-r--r--arch/powerpc/boot/cuboot-hotfoot.c142
-rw-r--r--arch/powerpc/boot/dts/hotfoot.dts294
-rw-r--r--arch/powerpc/boot/ppcboot-hotfoot.h133
4 files changed, 572 insertions, 1 deletions
diff --git a/arch/powerpc/boot/Makefile b/arch/powerpc/boot/Makefile
index 9ae7b7e2ba71..5a109a93753a 100644
--- a/arch/powerpc/boot/Makefile
+++ b/arch/powerpc/boot/Makefile
@@ -39,6 +39,7 @@ DTS_FLAGS ?= -p 1024
39 39
40$(obj)/4xx.o: BOOTCFLAGS += -mcpu=405 40$(obj)/4xx.o: BOOTCFLAGS += -mcpu=405
41$(obj)/ebony.o: BOOTCFLAGS += -mcpu=405 41$(obj)/ebony.o: BOOTCFLAGS += -mcpu=405
42$(obj)/cuboot-hotfoot.o: BOOTCFLAGS += -mcpu=405
42$(obj)/cuboot-taishan.o: BOOTCFLAGS += -mcpu=405 43$(obj)/cuboot-taishan.o: BOOTCFLAGS += -mcpu=405
43$(obj)/cuboot-katmai.o: BOOTCFLAGS += -mcpu=405 44$(obj)/cuboot-katmai.o: BOOTCFLAGS += -mcpu=405
44$(obj)/cuboot-acadia.o: BOOTCFLAGS += -mcpu=405 45$(obj)/cuboot-acadia.o: BOOTCFLAGS += -mcpu=405
@@ -67,7 +68,7 @@ src-wlib := string.S crt0.S crtsavres.S stdio.c main.c \
67 cpm-serial.c stdlib.c mpc52xx-psc.c planetcore.c uartlite.c \ 68 cpm-serial.c stdlib.c mpc52xx-psc.c planetcore.c uartlite.c \
68 fsl-soc.c mpc8xx.c pq2.c 69 fsl-soc.c mpc8xx.c pq2.c
69src-plat := of.c cuboot-52xx.c cuboot-824x.c cuboot-83xx.c cuboot-85xx.c holly.c \ 70src-plat := of.c cuboot-52xx.c cuboot-824x.c cuboot-83xx.c cuboot-85xx.c holly.c \
70 cuboot-ebony.c treeboot-ebony.c prpmc2800.c \ 71 cuboot-ebony.c cuboot-hotfoot.c treeboot-ebony.c prpmc2800.c \
71 ps3-head.S ps3-hvcall.S ps3.c treeboot-bamboo.c cuboot-8xx.c \ 72 ps3-head.S ps3-hvcall.S ps3.c treeboot-bamboo.c cuboot-8xx.c \
72 cuboot-pq2.c cuboot-sequoia.c treeboot-walnut.c \ 73 cuboot-pq2.c cuboot-sequoia.c treeboot-walnut.c \
73 cuboot-bamboo.c cuboot-mpc7448hpc2.c cuboot-taishan.c \ 74 cuboot-bamboo.c cuboot-mpc7448hpc2.c cuboot-taishan.c \
@@ -190,6 +191,7 @@ image-$(CONFIG_DEFAULT_UIMAGE) += uImage
190 191
191# Board ports in arch/powerpc/platform/40x/Kconfig 192# Board ports in arch/powerpc/platform/40x/Kconfig
192image-$(CONFIG_EP405) += dtbImage.ep405 193image-$(CONFIG_EP405) += dtbImage.ep405
194image-$(CONFIG_HOTFOOT) += cuImage.hotfoot
193image-$(CONFIG_WALNUT) += treeImage.walnut 195image-$(CONFIG_WALNUT) += treeImage.walnut
194image-$(CONFIG_ACADIA) += cuImage.acadia 196image-$(CONFIG_ACADIA) += cuImage.acadia
195 197
diff --git a/arch/powerpc/boot/cuboot-hotfoot.c b/arch/powerpc/boot/cuboot-hotfoot.c
new file mode 100644
index 000000000000..8f697b958e45
--- /dev/null
+++ b/arch/powerpc/boot/cuboot-hotfoot.c
@@ -0,0 +1,142 @@
1/*
2 * Old U-boot compatibility for Esteem 195E Hotfoot CPU Board
3 *
4 * Author: Solomon Peachy <solomon@linux-wlan.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 */
10
11#include "ops.h"
12#include "stdio.h"
13#include "reg.h"
14#include "dcr.h"
15#include "4xx.h"
16#include "cuboot.h"
17
18#define TARGET_4xx
19#define TARGET_HOTFOOT
20
21#include "ppcboot-hotfoot.h"
22
23static bd_t bd;
24
25#define NUM_REGS 3
26
27static void hotfoot_fixups(void)
28{
29 u32 uart = mfdcr(DCRN_CPC0_UCR) & 0x7f;
30
31 dt_fixup_memory(bd.bi_memstart, bd.bi_memsize);
32
33 dt_fixup_cpu_clocks(bd.bi_procfreq, bd.bi_procfreq, 0);
34 dt_fixup_clock("/plb", bd.bi_plb_busfreq);
35 dt_fixup_clock("/plb/opb", bd.bi_opbfreq);
36 dt_fixup_clock("/plb/ebc", bd.bi_pci_busfreq);
37 dt_fixup_clock("/plb/opb/serial@ef600300", bd.bi_procfreq / uart);
38 dt_fixup_clock("/plb/opb/serial@ef600400", bd.bi_procfreq / uart);
39
40 dt_fixup_mac_address_by_alias("ethernet0", bd.bi_enetaddr);
41 dt_fixup_mac_address_by_alias("ethernet1", bd.bi_enet1addr);
42
43 /* Is this a single eth/serial board? */
44 if ((bd.bi_enet1addr[0] == 0) &&
45 (bd.bi_enet1addr[1] == 0) &&
46 (bd.bi_enet1addr[2] == 0) &&
47 (bd.bi_enet1addr[3] == 0) &&
48 (bd.bi_enet1addr[4] == 0) &&
49 (bd.bi_enet1addr[5] == 0)) {
50 void *devp;
51
52 printf("Trimming devtree for single serial/eth board\n");
53
54 devp = finddevice("/plb/opb/serial@ef600300");
55 if (!devp)
56 fatal("Can't find node for /plb/opb/serial@ef600300");
57 del_node(devp);
58
59 devp = finddevice("/plb/opb/ethernet@ef600900");
60 if (!devp)
61 fatal("Can't find node for /plb/opb/ethernet@ef600900");
62 del_node(devp);
63 }
64
65 ibm4xx_quiesce_eth((u32 *)0xef600800, (u32 *)0xef600900);
66
67 /* Fix up flash size in fdt for 4M boards. */
68 if (bd.bi_flashsize < 0x800000) {
69 u32 regs[NUM_REGS];
70 void *devp = finddevice("/plb/ebc/nor_flash@0");
71 if (!devp)
72 fatal("Can't find FDT node for nor_flash!??");
73
74 printf("Fixing devtree for 4M Flash\n");
75
76 /* First fix up the base addresse */
77 getprop(devp, "reg", regs, sizeof(regs));
78 regs[0] = 0;
79 regs[1] = 0xffc00000;
80 regs[2] = 0x00400000;
81 setprop(devp, "reg", regs, sizeof(regs));
82
83 /* Then the offsets */
84 devp = finddevice("/plb/ebc/nor_flash@0/partition@0");
85 if (!devp)
86 fatal("Can't find FDT node for partition@0");
87 getprop(devp, "reg", regs, 2*sizeof(u32));
88 regs[0] -= 0x400000;
89 setprop(devp, "reg", regs, 2*sizeof(u32));
90
91 devp = finddevice("/plb/ebc/nor_flash@0/partition@1");
92 if (!devp)
93 fatal("Can't find FDT node for partition@1");
94 getprop(devp, "reg", regs, 2*sizeof(u32));
95 regs[0] -= 0x400000;
96 setprop(devp, "reg", regs, 2*sizeof(u32));
97
98 devp = finddevice("/plb/ebc/nor_flash@0/partition@2");
99 if (!devp)
100 fatal("Can't find FDT node for partition@2");
101 getprop(devp, "reg", regs, 2*sizeof(u32));
102 regs[0] -= 0x400000;
103 setprop(devp, "reg", regs, 2*sizeof(u32));
104
105 devp = finddevice("/plb/ebc/nor_flash@0/partition@3");
106 if (!devp)
107 fatal("Can't find FDT node for partition@3");
108 getprop(devp, "reg", regs, 2*sizeof(u32));
109 regs[0] -= 0x400000;
110 setprop(devp, "reg", regs, 2*sizeof(u32));
111
112 devp = finddevice("/plb/ebc/nor_flash@0/partition@4");
113 if (!devp)
114 fatal("Can't find FDT node for partition@4");
115 getprop(devp, "reg", regs, 2*sizeof(u32));
116 regs[0] -= 0x400000;
117 setprop(devp, "reg", regs, 2*sizeof(u32));
118
119 devp = finddevice("/plb/ebc/nor_flash@0/partition@6");
120 if (!devp)
121 fatal("Can't find FDT node for partition@6");
122 getprop(devp, "reg", regs, 2*sizeof(u32));
123 regs[0] -= 0x400000;
124 setprop(devp, "reg", regs, 2*sizeof(u32));
125
126 /* Delete the FeatFS node */
127 devp = finddevice("/plb/ebc/nor_flash@0/partition@5");
128 if (!devp)
129 fatal("Can't find FDT node for partition@5");
130 del_node(devp);
131 }
132}
133
134void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
135 unsigned long r6, unsigned long r7)
136{
137 CUBOOT_INIT();
138 platform_ops.fixups = hotfoot_fixups;
139 platform_ops.exit = ibm40x_dbcr_reset;
140 fdt_init(_dtb_start);
141 serial_console_init();
142}
diff --git a/arch/powerpc/boot/dts/hotfoot.dts b/arch/powerpc/boot/dts/hotfoot.dts
new file mode 100644
index 000000000000..cad9c3840afc
--- /dev/null
+++ b/arch/powerpc/boot/dts/hotfoot.dts
@@ -0,0 +1,294 @@
1/*
2 * Device Tree Source for ESTeem 195E Hotfoot
3 *
4 * Copyright 2009 AbsoluteValue Systems <solomon@linux-wlan.com>
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without
8 * any warranty of any kind, whether express or implied.
9 */
10
11/dts-v1/;
12
13/ {
14 #address-cells = <1>;
15 #size-cells = <1>;
16 model = "est,hotfoot";
17 compatible = "est,hotfoot";
18 dcr-parent = <&{/cpus/cpu@0}>;
19
20 aliases {
21 ethernet0 = &EMAC0;
22 ethernet1 = &EMAC1;
23 serial0 = &UART0;
24 serial1 = &UART1;
25 };
26
27 cpus {
28 #address-cells = <1>;
29 #size-cells = <0>;
30
31 cpu@0 {
32 device_type = "cpu";
33 model = "PowerPC,405EP";
34 reg = <0x00000000>;
35 clock-frequency = <0>; /* Filled in by zImage */
36 timebase-frequency = <0>; /* Filled in by zImage */
37 i-cache-line-size = <0x20>;
38 d-cache-line-size = <0x20>;
39 i-cache-size = <0x4000>;
40 d-cache-size = <0x4000>;
41 dcr-controller;
42 dcr-access-method = "native";
43 };
44 };
45
46 memory {
47 device_type = "memory";
48 reg = <0x00000000 0x00000000>; /* Filled in by zImage */
49 };
50
51 UIC0: interrupt-controller {
52 compatible = "ibm,uic";
53 interrupt-controller;
54 cell-index = <0>;
55 dcr-reg = <0x0c0 0x009>;
56 #address-cells = <0>;
57 #size-cells = <0>;
58 #interrupt-cells = <2>;
59 };
60
61 plb {
62 compatible = "ibm,plb3";
63 #address-cells = <1>;
64 #size-cells = <1>;
65 ranges;
66 clock-frequency = <0>; /* Filled in by zImage */
67
68 SDRAM0: memory-controller {
69 compatible = "ibm,sdram-405ep";
70 dcr-reg = <0x010 0x002>;
71 };
72
73 MAL: mcmal {
74 compatible = "ibm,mcmal-405ep", "ibm,mcmal";
75 dcr-reg = <0x180 0x062>;
76 num-tx-chans = <4>;
77 num-rx-chans = <2>;
78 interrupt-parent = <&UIC0>;
79 interrupts = <
80 0xb 0x4 /* TXEOB */
81 0xc 0x4 /* RXEOB */
82 0xa 0x4 /* SERR */
83 0xd 0x4 /* TXDE */
84 0xe 0x4 /* RXDE */>;
85 };
86
87 POB0: opb {
88 compatible = "ibm,opb-405ep", "ibm,opb";
89 #address-cells = <1>;
90 #size-cells = <1>;
91 ranges = <0xef600000 0xef600000 0x00a00000>;
92 dcr-reg = <0x0a0 0x005>;
93 clock-frequency = <0>; /* Filled in by zImage */
94
95 /* Hotfoot has UART0/UART1 swapped */
96
97 UART0: serial@ef600400 {
98 device_type = "serial";
99 compatible = "ns16550";
100 reg = <0xef600400 0x00000008>;
101 virtual-reg = <0xef600400>;
102 clock-frequency = <0>; /* Filled in by zImage */
103 current-speed = <0x9600>;
104 interrupt-parent = <&UIC0>;
105 interrupts = <0x1 0x4>;
106 };
107
108 UART1: serial@ef600300 {
109 device_type = "serial";
110 compatible = "ns16550";
111 reg = <0xef600300 0x00000008>;
112 virtual-reg = <0xef600300>;
113 clock-frequency = <0>; /* Filled in by zImage */
114 current-speed = <0x9600>;
115 interrupt-parent = <&UIC0>;
116 interrupts = <0x0 0x4>;
117 };
118
119 IIC: i2c@ef600500 {
120 compatible = "ibm,iic-405ep", "ibm,iic";
121 reg = <0xef600500 0x00000011>;
122 interrupt-parent = <&UIC0>;
123 interrupts = <0x2 0x4>;
124
125 rtc@68 {
126 /* Actually a DS1339 */
127 compatible = "dallas,ds1307";
128 reg = <0x68>;
129 };
130
131 temp@4a {
132 /* Not present on all boards */
133 compatible = "national,lm75";
134 reg = <0x4a>;
135 };
136 };
137
138 GPIO: gpio@ef600700 {
139 #gpio-cells = <2>;
140 compatible = "ibm,ppc4xx-gpio";
141 reg = <0xef600700 0x00000020>;
142 gpio-controller;
143 };
144
145 gpio-leds {
146 compatible = "gpio-leds";
147 status {
148 label = "Status";
149 gpios = <&GPIO 1 0>;
150 };
151 radiorx {
152 label = "Rx";
153 gpios = <&GPIO 0xe 0>;
154 };
155 };
156
157 EMAC0: ethernet@ef600800 {
158 linux,network-index = <0x0>;
159 device_type = "network";
160 compatible = "ibm,emac-405ep", "ibm,emac";
161 interrupt-parent = <&UIC0>;
162 interrupts = <
163 0xf 0x4 /* Ethernet */
164 0x9 0x4 /* Ethernet Wake Up */>;
165 local-mac-address = [000000000000]; /* Filled in by zImage */
166 reg = <0xef600800 0x00000070>;
167 mal-device = <&MAL>;
168 mal-tx-channel = <0>;
169 mal-rx-channel = <0>;
170 cell-index = <0>;
171 max-frame-size = <0x5dc>;
172 rx-fifo-size = <0x1000>;
173 tx-fifo-size = <0x800>;
174 phy-mode = "mii";
175 phy-map = <0x00000000>;
176 };
177
178 EMAC1: ethernet@ef600900 {
179 linux,network-index = <0x1>;
180 device_type = "network";
181 compatible = "ibm,emac-405ep", "ibm,emac";
182 interrupt-parent = <&UIC0>;
183 interrupts = <
184 0x11 0x4 /* Ethernet */
185 0x9 0x4 /* Ethernet Wake Up */>;
186 local-mac-address = [000000000000]; /* Filled in by zImage */
187 reg = <0xef600900 0x00000070>;
188 mal-device = <&MAL>;
189 mal-tx-channel = <2>;
190 mal-rx-channel = <1>;
191 cell-index = <1>;
192 max-frame-size = <0x5dc>;
193 rx-fifo-size = <0x1000>;
194 tx-fifo-size = <0x800>;
195 mdio-device = <&EMAC0>;
196 phy-mode = "mii";
197 phy-map = <0x0000001>;
198 };
199 };
200
201 EBC0: ebc {
202 compatible = "ibm,ebc-405ep", "ibm,ebc";
203 dcr-reg = <0x012 0x002>;
204 #address-cells = <2>;
205 #size-cells = <1>;
206
207 /* The ranges property is supplied by the bootwrapper
208 * and is based on the firmware's configuration of the
209 * EBC bridge
210 */
211 clock-frequency = <0>; /* Filled in by zImage */
212
213 nor_flash@0 {
214 compatible = "cfi-flash";
215 bank-width = <2>;
216 reg = <0x0 0xff800000 0x00800000>;
217 #address-cells = <1>;
218 #size-cells = <1>;
219
220 /* This mapping is for the 8M flash
221 4M flash has all ofssets -= 4M,
222 and FeatFS partition is not present */
223 partition@0 {
224 label = "Bootloader";
225 reg = <0x7c0000 0x40000>;
226 /* read-only; */
227 };
228 partition@1 {
229 label = "Env_and_Config_Primary";
230 reg = <0x400000 0x10000>;
231 };
232 partition@2 {
233 label = "Kernel";
234 reg = <0x420000 0x100000>;
235 };
236 partition@3 {
237 label = "Filesystem";
238 reg = <0x520000 0x2a0000>;
239 };
240 partition@4 {
241 label = "Env_and_Config_Secondary";
242 reg = <0x410000 0x10000>;
243 };
244 partition@5 {
245 label = "FeatFS";
246 reg = <0x000000 0x400000>;
247 };
248 partition@6 {
249 label = "Bootloader_Env";
250 reg = <0x7d0000 0x10000>;
251 };
252 };
253 };
254
255 PCI0: pci@ec000000 {
256 device_type = "pci";
257 #interrupt-cells = <1>;
258 #size-cells = <2>;
259 #address-cells = <3>;
260 compatible = "ibm,plb405ep-pci", "ibm,plb-pci";
261 primary;
262 reg = <0xeec00000 0x00000008 /* Config space access */
263 0xeed80000 0x00000004 /* IACK */
264 0xeed80000 0x00000004 /* Special cycle */
265 0xef480000 0x00000040>; /* Internal registers */
266
267 /* Outbound ranges, one memory and one IO,
268 * later cannot be changed. Chip supports a second
269 * IO range but we don't use it for now
270 */
271 ranges = <0x02000000 0x00000000 0x80000000 0x80000000 0x00000000 0x20000000
272 0x01000000 0x00000000 0x00000000 0xe8000000 0x00000000 0x00010000>;
273
274 /* Inbound 2GB range starting at 0 */
275 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>;
276
277 interrupt-parent = <&UIC0>;
278 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
279 interrupt-map = <
280 /* IDSEL 3 -- slot1 (optional) 27/29 A/B IRQ2/4 */
281 0x1800 0x0 0x0 0x1 &UIC0 0x1b 0x8
282 0x1800 0x0 0x0 0x2 &UIC0 0x1d 0x8
283
284 /* IDSEL 4 -- slot0, 26/28 A/B IRQ1/3 */
285 0x2000 0x0 0x0 0x1 &UIC0 0x1a 0x8
286 0x2000 0x0 0x0 0x2 &UIC0 0x1c 0x8
287 >;
288 };
289 };
290
291 chosen {
292 linux,stdout-path = &UART0;
293 };
294};
diff --git a/arch/powerpc/boot/ppcboot-hotfoot.h b/arch/powerpc/boot/ppcboot-hotfoot.h
new file mode 100644
index 000000000000..1a3e80b533da
--- /dev/null
+++ b/arch/powerpc/boot/ppcboot-hotfoot.h
@@ -0,0 +1,133 @@
1/*
2 * This interface is used for compatibility with old U-boots *ONLY*.
3 * Please do not imitate or extend this.
4 */
5
6/*
7 * Unfortunately, the ESTeem Hotfoot board uses a mangled version of
8 * ppcboot.h for historical reasons, and in the interest of having a
9 * mainline kernel boot on the production board+bootloader, this was the
10 * least-offensive solution. Please direct all flames to:
11 *
12 * Solomon Peachy <solomon@linux-wlan.com>
13 *
14 * (This header is identical to ppcboot.h except for the
15 * TARGET_HOTFOOT bits)
16 */
17
18/*
19 * (C) Copyright 2000, 2001
20 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
21 *
22 * This program is free software; you can redistribute it and/or
23 * modify it under the terms of the GNU General Public License as
24 * published by the Free Software Foundation; either version 2 of
25 * the License, or (at your option) any later version.
26 *
27 * This program is distributed in the hope that it will be useful,
28 * but WITHOUT ANY WARRANTY; without even the implied warranty of
29 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
30 * GNU General Public License for more details.
31 *
32 * You should have received a copy of the GNU General Public License
33 * along with this program; if not, write to the Free Software
34 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
35 * MA 02111-1307 USA
36 */
37
38#ifndef __PPCBOOT_H__
39#define __PPCBOOT_H__
40
41/*
42 * Board information passed to kernel from PPCBoot
43 *
44 * include/asm-ppc/ppcboot.h
45 */
46
47#include "types.h"
48
49typedef struct bd_info {
50 unsigned long bi_memstart; /* start of DRAM memory */
51 unsigned long bi_memsize; /* size of DRAM memory in bytes */
52 unsigned long bi_flashstart; /* start of FLASH memory */
53 unsigned long bi_flashsize; /* size of FLASH memory */
54 unsigned long bi_flashoffset; /* reserved area for startup monitor */
55 unsigned long bi_sramstart; /* start of SRAM memory */
56 unsigned long bi_sramsize; /* size of SRAM memory */
57#if defined(TARGET_8xx) || defined(TARGET_CPM2) || defined(TARGET_85xx) ||\
58 defined(TARGET_83xx)
59 unsigned long bi_immr_base; /* base of IMMR register */
60#endif
61#if defined(TARGET_PPC_MPC52xx)
62 unsigned long bi_mbar_base; /* base of internal registers */
63#endif
64 unsigned long bi_bootflags; /* boot / reboot flag (for LynxOS) */
65 unsigned long bi_ip_addr; /* IP Address */
66 unsigned char bi_enetaddr[6]; /* Ethernet address */
67#if defined(TARGET_HOTFOOT)
68 /* second onboard ethernet port */
69 unsigned char bi_enet1addr[6];
70#define HAVE_ENET1ADDR
71#endif /* TARGET_HOOTFOOT */
72 unsigned short bi_ethspeed; /* Ethernet speed in Mbps */
73 unsigned long bi_intfreq; /* Internal Freq, in MHz */
74 unsigned long bi_busfreq; /* Bus Freq, in MHz */
75#if defined(TARGET_CPM2)
76 unsigned long bi_cpmfreq; /* CPM_CLK Freq, in MHz */
77 unsigned long bi_brgfreq; /* BRG_CLK Freq, in MHz */
78 unsigned long bi_sccfreq; /* SCC_CLK Freq, in MHz */
79 unsigned long bi_vco; /* VCO Out from PLL, in MHz */
80#endif
81#if defined(TARGET_PPC_MPC52xx)
82 unsigned long bi_ipbfreq; /* IPB Bus Freq, in MHz */
83 unsigned long bi_pcifreq; /* PCI Bus Freq, in MHz */
84#endif
85 unsigned long bi_baudrate; /* Console Baudrate */
86#if defined(TARGET_4xx)
87 unsigned char bi_s_version[4]; /* Version of this structure */
88 unsigned char bi_r_version[32]; /* Version of the ROM (IBM) */
89 unsigned int bi_procfreq; /* CPU (Internal) Freq, in Hz */
90 unsigned int bi_plb_busfreq; /* PLB Bus speed, in Hz */
91 unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */
92 unsigned char bi_pci_enetaddr[6]; /* PCI Ethernet MAC address */
93#endif
94#if defined(TARGET_HOTFOOT)
95 unsigned int bi_pllouta_freq; /* PLL OUTA speed, in Hz */
96#endif
97#if defined(TARGET_HYMOD)
98 hymod_conf_t bi_hymod_conf; /* hymod configuration information */
99#endif
100#if defined(TARGET_EVB64260) || defined(TARGET_405EP) || defined(TARGET_44x) || \
101 defined(TARGET_85xx) || defined(TARGET_83xx) || defined(TARGET_HAS_ETH1)
102 /* second onboard ethernet port */
103 unsigned char bi_enet1addr[6];
104#define HAVE_ENET1ADDR
105#endif
106#if defined(TARGET_EVB64260) || defined(TARGET_440GX) || \
107 defined(TARGET_85xx) || defined(TARGET_HAS_ETH2)
108 /* third onboard ethernet ports */
109 unsigned char bi_enet2addr[6];
110#define HAVE_ENET2ADDR
111#endif
112#if defined(TARGET_440GX) || defined(TARGET_HAS_ETH3)
113 /* fourth onboard ethernet ports */
114 unsigned char bi_enet3addr[6];
115#define HAVE_ENET3ADDR
116#endif
117#if defined(TARGET_HOTFOOT)
118 int bi_phynum[2]; /* Determines phy mapping */
119 int bi_phymode[2]; /* Determines phy mode */
120#endif
121#if defined(TARGET_4xx)
122 unsigned int bi_opbfreq; /* OB clock in Hz */
123 int bi_iic_fast[2]; /* Use fast i2c mode */
124#endif
125#if defined(TARGET_440GX)
126 int bi_phynum[4]; /* phy mapping */
127 int bi_phymode[4]; /* phy mode */
128#endif
129} bd_t;
130
131#define bi_tbfreq bi_intfreq
132
133#endif /* __PPCBOOT_H__ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-05 05:36:50 -0500