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-rw-r--r--arch/powerpc/boot/dts/gef_ppc9a.dts14
-rw-r--r--arch/powerpc/boot/dts/gef_sbc310.dts14
-rw-r--r--arch/powerpc/boot/dts/gef_sbc610.dts14
-rw-r--r--arch/powerpc/boot/dts/ksi8560.dts13
-rw-r--r--arch/powerpc/boot/dts/mpc832x_mds.dts3
-rw-r--r--arch/powerpc/boot/dts/mpc832x_rdb.dts3
-rw-r--r--arch/powerpc/boot/dts/mpc8349emitx.dts2
-rw-r--r--arch/powerpc/boot/dts/mpc8349emitxgp.dts1
-rw-r--r--arch/powerpc/boot/dts/mpc834x_mds.dts2
-rw-r--r--arch/powerpc/boot/dts/mpc836x_mds.dts3
-rw-r--r--arch/powerpc/boot/dts/mpc836x_rdk.dts2
-rw-r--r--arch/powerpc/boot/dts/mpc8377_mds.dts1
-rw-r--r--arch/powerpc/boot/dts/mpc8378_mds.dts1
-rw-r--r--arch/powerpc/boot/dts/mpc8379_mds.dts1
-rw-r--r--arch/powerpc/boot/dts/mpc8536ds.dts18
-rw-r--r--arch/powerpc/boot/dts/mpc8540ads.dts15
-rw-r--r--arch/powerpc/boot/dts/mpc8541cds.dts16
-rw-r--r--arch/powerpc/boot/dts/mpc8544ds.dts18
-rw-r--r--arch/powerpc/boot/dts/mpc8548cds.dts17
-rw-r--r--arch/powerpc/boot/dts/mpc8555cds.dts16
-rw-r--r--arch/powerpc/boot/dts/mpc8560ads.dts15
-rw-r--r--arch/powerpc/boot/dts/mpc8568mds.dts51
-rw-r--r--arch/powerpc/boot/dts/mpc8569mds.dts583
-rw-r--r--arch/powerpc/boot/dts/mpc8572ds.dts17
-rw-r--r--arch/powerpc/boot/dts/mpc8572ds_36b.dts39
-rw-r--r--arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts16
-rw-r--r--arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts2
-rw-r--r--arch/powerpc/boot/dts/mpc8610_hpcd.dts16
-rw-r--r--arch/powerpc/boot/dts/mpc8641_hpcn.dts16
-rw-r--r--arch/powerpc/boot/dts/mpc8641_hpcn_36b.dts609
-rw-r--r--arch/powerpc/boot/dts/p2020ds.dts704
-rw-r--r--arch/powerpc/boot/dts/sbc8349.dts1
-rw-r--r--arch/powerpc/boot/dts/sbc8548.dts16
-rw-r--r--arch/powerpc/boot/dts/sbc8560.dts15
-rw-r--r--arch/powerpc/boot/dts/sbc8641d.dts16
-rw-r--r--arch/powerpc/boot/dts/sequoia.dts22
-rw-r--r--arch/powerpc/boot/dts/socrates.dts15
-rw-r--r--arch/powerpc/boot/dts/stx_gp3_8560.dts15
-rw-r--r--arch/powerpc/boot/dts/tqm8540.dts15
-rw-r--r--arch/powerpc/boot/dts/tqm8541.dts15
-rw-r--r--arch/powerpc/boot/dts/tqm8548-bigflash.dts16
-rw-r--r--arch/powerpc/boot/dts/tqm8548.dts16
-rw-r--r--arch/powerpc/boot/dts/tqm8555.dts15
-rw-r--r--arch/powerpc/boot/dts/tqm8560.dts15
-rw-r--r--arch/powerpc/boot/dts/virtex440-ml510.dts465
-rw-r--r--arch/powerpc/boot/dts/warp.dts27
46 files changed, 2814 insertions, 112 deletions
diff --git a/arch/powerpc/boot/dts/gef_ppc9a.dts b/arch/powerpc/boot/dts/gef_ppc9a.dts
index 53a7a6255909..910944edd886 100644
--- a/arch/powerpc/boot/dts/gef_ppc9a.dts
+++ b/arch/powerpc/boot/dts/gef_ppc9a.dts
@@ -164,9 +164,21 @@
164 device_type = "soc"; 164 device_type = "soc";
165 compatible = "fsl,mpc8641-soc", "simple-bus"; 165 compatible = "fsl,mpc8641-soc", "simple-bus";
166 ranges = <0x0 0xfef00000 0x00100000>; 166 ranges = <0x0 0xfef00000 0x00100000>;
167 reg = <0xfef00000 0x100000>; // CCSRBAR 1M
168 bus-frequency = <33333333>; 167 bus-frequency = <33333333>;
169 168
169 mcm-law@0 {
170 compatible = "fsl,mcm-law";
171 reg = <0x0 0x1000>;
172 fsl,num-laws = <10>;
173 };
174
175 mcm@1000 {
176 compatible = "fsl,mpc8641-mcm", "fsl,mcm";
177 reg = <0x1000 0x1000>;
178 interrupts = <17 2>;
179 interrupt-parent = <&mpic>;
180 };
181
170 i2c1: i2c@3000 { 182 i2c1: i2c@3000 {
171 #address-cells = <1>; 183 #address-cells = <1>;
172 #size-cells = <0>; 184 #size-cells = <0>;
diff --git a/arch/powerpc/boot/dts/gef_sbc310.dts b/arch/powerpc/boot/dts/gef_sbc310.dts
index 1569117e5ddc..0f4c9ec2c3a6 100644
--- a/arch/powerpc/boot/dts/gef_sbc310.dts
+++ b/arch/powerpc/boot/dts/gef_sbc310.dts
@@ -163,9 +163,21 @@
163 device_type = "soc"; 163 device_type = "soc";
164 compatible = "simple-bus"; 164 compatible = "simple-bus";
165 ranges = <0x0 0xfef00000 0x00100000>; 165 ranges = <0x0 0xfef00000 0x00100000>;
166 reg = <0xfef00000 0x100000>; // CCSRBAR 1M
167 bus-frequency = <33333333>; 166 bus-frequency = <33333333>;
168 167
168 mcm-law@0 {
169 compatible = "fsl,mcm-law";
170 reg = <0x0 0x1000>;
171 fsl,num-laws = <10>;
172 };
173
174 mcm@1000 {
175 compatible = "fsl,mpc8641-mcm", "fsl,mcm";
176 reg = <0x1000 0x1000>;
177 interrupts = <17 2>;
178 interrupt-parent = <&mpic>;
179 };
180
169 i2c1: i2c@3000 { 181 i2c1: i2c@3000 {
170 #address-cells = <1>; 182 #address-cells = <1>;
171 #size-cells = <0>; 183 #size-cells = <0>;
diff --git a/arch/powerpc/boot/dts/gef_sbc610.dts b/arch/powerpc/boot/dts/gef_sbc610.dts
index 6582dbd36da7..217f8aa66725 100644
--- a/arch/powerpc/boot/dts/gef_sbc610.dts
+++ b/arch/powerpc/boot/dts/gef_sbc610.dts
@@ -128,9 +128,21 @@
128 device_type = "soc"; 128 device_type = "soc";
129 compatible = "simple-bus"; 129 compatible = "simple-bus";
130 ranges = <0x0 0xfef00000 0x00100000>; 130 ranges = <0x0 0xfef00000 0x00100000>;
131 reg = <0xfef00000 0x100000>; // CCSRBAR 1M
132 bus-frequency = <33333333>; 131 bus-frequency = <33333333>;
133 132
133 mcm-law@0 {
134 compatible = "fsl,mcm-law";
135 reg = <0x0 0x1000>;
136 fsl,num-laws = <10>;
137 };
138
139 mcm@1000 {
140 compatible = "fsl,mpc8641-mcm", "fsl,mcm";
141 reg = <0x1000 0x1000>;
142 interrupts = <17 2>;
143 interrupt-parent = <&mpic>;
144 };
145
134 i2c1: i2c@3000 { 146 i2c1: i2c@3000 {
135 #address-cells = <1>; 147 #address-cells = <1>;
136 #size-cells = <0>; 148 #size-cells = <0>;
diff --git a/arch/powerpc/boot/dts/ksi8560.dts b/arch/powerpc/boot/dts/ksi8560.dts
index c9cfd374bffb..bdb7fc0fa332 100644
--- a/arch/powerpc/boot/dts/ksi8560.dts
+++ b/arch/powerpc/boot/dts/ksi8560.dts
@@ -56,6 +56,19 @@
56 ranges = <0x00000000 0xfdf00000 0x00100000>; 56 ranges = <0x00000000 0xfdf00000 0x00100000>;
57 bus-frequency = <0>; /* Fixed by bootwrapper */ 57 bus-frequency = <0>; /* Fixed by bootwrapper */
58 58
59 ecm-law@0 {
60 compatible = "fsl,ecm-law";
61 reg = <0x0 0x1000>;
62 fsl,num-laws = <8>;
63 };
64
65 ecm@1000 {
66 compatible = "fsl,mpc8560-ecm", "fsl,ecm";
67 reg = <0x1000 0x1000>;
68 interrupts = <17 2>;
69 interrupt-parent = <&mpic>;
70 };
71
59 memory-controller@2000 { 72 memory-controller@2000 {
60 compatible = "fsl,mpc8540-memory-controller"; 73 compatible = "fsl,mpc8540-memory-controller";
61 reg = <0x2000 0x1000>; 74 reg = <0x2000 0x1000>;
diff --git a/arch/powerpc/boot/dts/mpc832x_mds.dts b/arch/powerpc/boot/dts/mpc832x_mds.dts
index 57c595bf1071..436c9c671dd9 100644
--- a/arch/powerpc/boot/dts/mpc832x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc832x_mds.dts
@@ -249,6 +249,8 @@
249 reg = <0xe0100000 0x480>; 249 reg = <0xe0100000 0x480>;
250 brg-frequency = <0>; 250 brg-frequency = <0>;
251 bus-frequency = <198000000>; 251 bus-frequency = <198000000>;
252 fsl,qe-num-riscs = <1>;
253 fsl,qe-num-snums = <28>;
252 254
253 muram@10000 { 255 muram@10000 {
254 #address-cells = <1>; 256 #address-cells = <1>;
@@ -369,7 +371,6 @@
369 }; 371 };
370 372
371 pci0: pci@e0008500 { 373 pci0: pci@e0008500 {
372 cell-index = <1>;
373 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 374 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
374 interrupt-map = < 375 interrupt-map = <
375 /* IDSEL 0x11 AD17 */ 376 /* IDSEL 0x11 AD17 */
diff --git a/arch/powerpc/boot/dts/mpc832x_rdb.dts b/arch/powerpc/boot/dts/mpc832x_rdb.dts
index 4319bd70a580..9a0952f74b81 100644
--- a/arch/powerpc/boot/dts/mpc832x_rdb.dts
+++ b/arch/powerpc/boot/dts/mpc832x_rdb.dts
@@ -221,6 +221,8 @@
221 reg = <0xe0100000 0x480>; 221 reg = <0xe0100000 0x480>;
222 brg-frequency = <0>; 222 brg-frequency = <0>;
223 bus-frequency = <198000000>; 223 bus-frequency = <198000000>;
224 fsl,qe-num-riscs = <1>;
225 fsl,qe-num-snums = <28>;
224 226
225 muram@10000 { 227 muram@10000 {
226 #address-cells = <1>; 228 #address-cells = <1>;
@@ -327,7 +329,6 @@
327 }; 329 };
328 330
329 pci0: pci@e0008500 { 331 pci0: pci@e0008500 {
330 cell-index = <1>;
331 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 332 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
332 interrupt-map = < 333 interrupt-map = <
333 /* IDSEL 0x10 AD16 (USB) */ 334 /* IDSEL 0x10 AD16 (USB) */
diff --git a/arch/powerpc/boot/dts/mpc8349emitx.dts b/arch/powerpc/boot/dts/mpc8349emitx.dts
index 1ae38f0ddef8..e3eeaeda9187 100644
--- a/arch/powerpc/boot/dts/mpc8349emitx.dts
+++ b/arch/powerpc/boot/dts/mpc8349emitx.dts
@@ -278,7 +278,6 @@
278 }; 278 };
279 279
280 pci0: pci@e0008500 { 280 pci0: pci@e0008500 {
281 cell-index = <1>;
282 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 281 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
283 interrupt-map = < 282 interrupt-map = <
284 /* IDSEL 0x10 - SATA */ 283 /* IDSEL 0x10 - SATA */
@@ -301,7 +300,6 @@
301 }; 300 };
302 301
303 pci1: pci@e0008600 { 302 pci1: pci@e0008600 {
304 cell-index = <2>;
305 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 303 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
306 interrupt-map = < 304 interrupt-map = <
307 /* IDSEL 0x0E - MiniPCI Slot */ 305 /* IDSEL 0x0E - MiniPCI Slot */
diff --git a/arch/powerpc/boot/dts/mpc8349emitxgp.dts b/arch/powerpc/boot/dts/mpc8349emitxgp.dts
index 662abe1fb804..eb732115f016 100644
--- a/arch/powerpc/boot/dts/mpc8349emitxgp.dts
+++ b/arch/powerpc/boot/dts/mpc8349emitxgp.dts
@@ -227,7 +227,6 @@
227 }; 227 };
228 228
229 pci0: pci@e0008600 { 229 pci0: pci@e0008600 {
230 cell-index = <2>;
231 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 230 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
232 interrupt-map = < 231 interrupt-map = <
233 /* IDSEL 0x0F - PCI Slot */ 232 /* IDSEL 0x0F - PCI Slot */
diff --git a/arch/powerpc/boot/dts/mpc834x_mds.dts b/arch/powerpc/boot/dts/mpc834x_mds.dts
index d9f0a2325fa4..a2553a6f9009 100644
--- a/arch/powerpc/boot/dts/mpc834x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc834x_mds.dts
@@ -286,7 +286,6 @@
286 }; 286 };
287 287
288 pci0: pci@e0008500 { 288 pci0: pci@e0008500 {
289 cell-index = <1>;
290 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 289 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
291 interrupt-map = < 290 interrupt-map = <
292 291
@@ -348,7 +347,6 @@
348 }; 347 };
349 348
350 pci1: pci@e0008600 { 349 pci1: pci@e0008600 {
351 cell-index = <2>;
352 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 350 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
353 interrupt-map = < 351 interrupt-map = <
354 352
diff --git a/arch/powerpc/boot/dts/mpc836x_mds.dts b/arch/powerpc/boot/dts/mpc836x_mds.dts
index 6e34f170fa62..39ff4c829caf 100644
--- a/arch/powerpc/boot/dts/mpc836x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc836x_mds.dts
@@ -289,6 +289,8 @@
289 reg = <0xe0100000 0x480>; 289 reg = <0xe0100000 0x480>;
290 brg-frequency = <0>; 290 brg-frequency = <0>;
291 bus-frequency = <396000000>; 291 bus-frequency = <396000000>;
292 fsl,qe-num-riscs = <2>;
293 fsl,qe-num-snums = <28>;
292 294
293 muram@10000 { 295 muram@10000 {
294 #address-cells = <1>; 296 #address-cells = <1>;
@@ -410,7 +412,6 @@
410 }; 412 };
411 413
412 pci0: pci@e0008500 { 414 pci0: pci@e0008500 {
413 cell-index = <1>;
414 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 415 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
415 interrupt-map = < 416 interrupt-map = <
416 417
diff --git a/arch/powerpc/boot/dts/mpc836x_rdk.dts b/arch/powerpc/boot/dts/mpc836x_rdk.dts
index 37b789510d68..6315d6fcc58a 100644
--- a/arch/powerpc/boot/dts/mpc836x_rdk.dts
+++ b/arch/powerpc/boot/dts/mpc836x_rdk.dts
@@ -198,6 +198,8 @@
198 clock-frequency = <0>; 198 clock-frequency = <0>;
199 bus-frequency = <0>; 199 bus-frequency = <0>;
200 brg-frequency = <0>; 200 brg-frequency = <0>;
201 fsl,qe-num-riscs = <2>;
202 fsl,qe-num-snums = <28>;
201 203
202 muram@10000 { 204 muram@10000 {
203 #address-cells = <1>; 205 #address-cells = <1>;
diff --git a/arch/powerpc/boot/dts/mpc8377_mds.dts b/arch/powerpc/boot/dts/mpc8377_mds.dts
index 963708017e6c..67bb372c9451 100644
--- a/arch/powerpc/boot/dts/mpc8377_mds.dts
+++ b/arch/powerpc/boot/dts/mpc8377_mds.dts
@@ -383,7 +383,6 @@
383 }; 383 };
384 384
385 pci0: pci@e0008500 { 385 pci0: pci@e0008500 {
386 cell-index = <0>;
387 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 386 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
388 interrupt-map = < 387 interrupt-map = <
389 388
diff --git a/arch/powerpc/boot/dts/mpc8378_mds.dts b/arch/powerpc/boot/dts/mpc8378_mds.dts
index 651ff2f9db2d..a955a577db81 100644
--- a/arch/powerpc/boot/dts/mpc8378_mds.dts
+++ b/arch/powerpc/boot/dts/mpc8378_mds.dts
@@ -367,7 +367,6 @@
367 }; 367 };
368 368
369 pci0: pci@e0008500 { 369 pci0: pci@e0008500 {
370 cell-index = <0>;
371 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 370 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
372 interrupt-map = < 371 interrupt-map = <
373 372
diff --git a/arch/powerpc/boot/dts/mpc8379_mds.dts b/arch/powerpc/boot/dts/mpc8379_mds.dts
index d6f208b8297a..d266ddbfc28d 100644
--- a/arch/powerpc/boot/dts/mpc8379_mds.dts
+++ b/arch/powerpc/boot/dts/mpc8379_mds.dts
@@ -397,7 +397,6 @@
397 }; 397 };
398 398
399 pci0: pci@e0008500 { 399 pci0: pci@e0008500 {
400 cell-index = <0>;
401 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 400 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
402 interrupt-map = < 401 interrupt-map = <
403 402
diff --git a/arch/powerpc/boot/dts/mpc8536ds.dts b/arch/powerpc/boot/dts/mpc8536ds.dts
index b31c5041350b..e781ad2f1f8a 100644
--- a/arch/powerpc/boot/dts/mpc8536ds.dts
+++ b/arch/powerpc/boot/dts/mpc8536ds.dts
@@ -51,9 +51,21 @@
51 device_type = "soc"; 51 device_type = "soc";
52 compatible = "simple-bus"; 52 compatible = "simple-bus";
53 ranges = <0x0 0xffe00000 0x100000>; 53 ranges = <0x0 0xffe00000 0x100000>;
54 reg = <0xffe00000 0x1000>;
55 bus-frequency = <0>; // Filled out by uboot. 54 bus-frequency = <0>; // Filled out by uboot.
56 55
56 ecm-law@0 {
57 compatible = "fsl,ecm-law";
58 reg = <0x0 0x1000>;
59 fsl,num-laws = <12>;
60 };
61
62 ecm@1000 {
63 compatible = "fsl,mpc8536-ecm", "fsl,ecm";
64 reg = <0x1000 0x1000>;
65 interrupts = <17 2>;
66 interrupt-parent = <&mpic>;
67 };
68
57 memory-controller@2000 { 69 memory-controller@2000 {
58 compatible = "fsl,mpc8536-memory-controller"; 70 compatible = "fsl,mpc8536-memory-controller";
59 reg = <0x2000 0x1000>; 71 reg = <0x2000 0x1000>;
@@ -321,7 +333,6 @@
321 }; 333 };
322 334
323 pci0: pci@ffe08000 { 335 pci0: pci@ffe08000 {
324 cell-index = <0>;
325 compatible = "fsl,mpc8540-pci"; 336 compatible = "fsl,mpc8540-pci";
326 device_type = "pci"; 337 device_type = "pci";
327 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 338 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
@@ -346,7 +357,6 @@
346 }; 357 };
347 358
348 pci1: pcie@ffe09000 { 359 pci1: pcie@ffe09000 {
349 cell-index = <1>;
350 compatible = "fsl,mpc8548-pcie"; 360 compatible = "fsl,mpc8548-pcie";
351 device_type = "pci"; 361 device_type = "pci";
352 #interrupt-cells = <1>; 362 #interrupt-cells = <1>;
@@ -383,7 +393,6 @@
383 }; 393 };
384 394
385 pci2: pcie@ffe0a000 { 395 pci2: pcie@ffe0a000 {
386 cell-index = <2>;
387 compatible = "fsl,mpc8548-pcie"; 396 compatible = "fsl,mpc8548-pcie";
388 device_type = "pci"; 397 device_type = "pci";
389 #interrupt-cells = <1>; 398 #interrupt-cells = <1>;
@@ -420,7 +429,6 @@
420 }; 429 };
421 430
422 pci3: pcie@ffe0b000 { 431 pci3: pcie@ffe0b000 {
423 cell-index = <3>;
424 compatible = "fsl,mpc8548-pcie"; 432 compatible = "fsl,mpc8548-pcie";
425 device_type = "pci"; 433 device_type = "pci";
426 #interrupt-cells = <1>; 434 #interrupt-cells = <1>;
diff --git a/arch/powerpc/boot/dts/mpc8540ads.dts b/arch/powerpc/boot/dts/mpc8540ads.dts
index ddd67be10b03..9dc292962a9a 100644
--- a/arch/powerpc/boot/dts/mpc8540ads.dts
+++ b/arch/powerpc/boot/dts/mpc8540ads.dts
@@ -55,9 +55,21 @@
55 device_type = "soc"; 55 device_type = "soc";
56 compatible = "simple-bus"; 56 compatible = "simple-bus";
57 ranges = <0x0 0xe0000000 0x100000>; 57 ranges = <0x0 0xe0000000 0x100000>;
58 reg = <0xe0000000 0x100000>; // CCSRBAR 1M
59 bus-frequency = <0>; 58 bus-frequency = <0>;
60 59
60 ecm-law@0 {
61 compatible = "fsl,ecm-law";
62 reg = <0x0 0x1000>;
63 fsl,num-laws = <8>;
64 };
65
66 ecm@1000 {
67 compatible = "fsl,mpc8540-ecm", "fsl,ecm";
68 reg = <0x1000 0x1000>;
69 interrupts = <17 2>;
70 interrupt-parent = <&mpic>;
71 };
72
61 memory-controller@2000 { 73 memory-controller@2000 {
62 compatible = "fsl,8540-memory-controller"; 74 compatible = "fsl,8540-memory-controller";
63 reg = <0x2000 0x1000>; 75 reg = <0x2000 0x1000>;
@@ -258,7 +270,6 @@
258 }; 270 };
259 271
260 pci0: pci@e0008000 { 272 pci0: pci@e0008000 {
261 cell-index = <0>;
262 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 273 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
263 interrupt-map = < 274 interrupt-map = <
264 275
diff --git a/arch/powerpc/boot/dts/mpc8541cds.dts b/arch/powerpc/boot/dts/mpc8541cds.dts
index e45097f44fbd..9a3ad311aedf 100644
--- a/arch/powerpc/boot/dts/mpc8541cds.dts
+++ b/arch/powerpc/boot/dts/mpc8541cds.dts
@@ -55,9 +55,21 @@
55 device_type = "soc"; 55 device_type = "soc";
56 compatible = "simple-bus"; 56 compatible = "simple-bus";
57 ranges = <0x0 0xe0000000 0x100000>; 57 ranges = <0x0 0xe0000000 0x100000>;
58 reg = <0xe0000000 0x1000>; // CCSRBAR 1M
59 bus-frequency = <0>; 58 bus-frequency = <0>;
60 59
60 ecm-law@0 {
61 compatible = "fsl,ecm-law";
62 reg = <0x0 0x1000>;
63 fsl,num-laws = <8>;
64 };
65
66 ecm@1000 {
67 compatible = "fsl,mpc8541-ecm", "fsl,ecm";
68 reg = <0x1000 0x1000>;
69 interrupts = <17 2>;
70 interrupt-parent = <&mpic>;
71 };
72
61 memory-controller@2000 { 73 memory-controller@2000 {
62 compatible = "fsl,8541-memory-controller"; 74 compatible = "fsl,8541-memory-controller";
63 reg = <0x2000 0x1000>; 75 reg = <0x2000 0x1000>;
@@ -272,7 +284,6 @@
272 }; 284 };
273 285
274 pci0: pci@e0008000 { 286 pci0: pci@e0008000 {
275 cell-index = <0>;
276 interrupt-map-mask = <0x1f800 0x0 0x0 0x7>; 287 interrupt-map-mask = <0x1f800 0x0 0x0 0x7>;
277 interrupt-map = < 288 interrupt-map = <
278 289
@@ -344,7 +355,6 @@
344 }; 355 };
345 356
346 pci1: pci@e0009000 { 357 pci1: pci@e0009000 {
347 cell-index = <1>;
348 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 358 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
349 interrupt-map = < 359 interrupt-map = <
350 360
diff --git a/arch/powerpc/boot/dts/mpc8544ds.dts b/arch/powerpc/boot/dts/mpc8544ds.dts
index 7c6932be0197..98e94b465662 100644
--- a/arch/powerpc/boot/dts/mpc8544ds.dts
+++ b/arch/powerpc/boot/dts/mpc8544ds.dts
@@ -57,9 +57,21 @@
57 compatible = "simple-bus"; 57 compatible = "simple-bus";
58 58
59 ranges = <0x0 0xe0000000 0x100000>; 59 ranges = <0x0 0xe0000000 0x100000>;
60 reg = <0xe0000000 0x1000>; // CCSRBAR 1M
61 bus-frequency = <0>; // Filled out by uboot. 60 bus-frequency = <0>; // Filled out by uboot.
62 61
62 ecm-law@0 {
63 compatible = "fsl,ecm-law";
64 reg = <0x0 0x1000>;
65 fsl,num-laws = <10>;
66 };
67
68 ecm@1000 {
69 compatible = "fsl,mpc8544-ecm", "fsl,ecm";
70 reg = <0x1000 0x1000>;
71 interrupts = <17 2>;
72 interrupt-parent = <&mpic>;
73 };
74
63 memory-controller@2000 { 75 memory-controller@2000 {
64 compatible = "fsl,8544-memory-controller"; 76 compatible = "fsl,8544-memory-controller";
65 reg = <0x2000 0x1000>; 77 reg = <0x2000 0x1000>;
@@ -274,7 +286,6 @@
274 }; 286 };
275 287
276 pci0: pci@e0008000 { 288 pci0: pci@e0008000 {
277 cell-index = <0>;
278 compatible = "fsl,mpc8540-pci"; 289 compatible = "fsl,mpc8540-pci";
279 device_type = "pci"; 290 device_type = "pci";
280 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 291 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
@@ -306,7 +317,6 @@
306 }; 317 };
307 318
308 pci1: pcie@e0009000 { 319 pci1: pcie@e0009000 {
309 cell-index = <1>;
310 compatible = "fsl,mpc8548-pcie"; 320 compatible = "fsl,mpc8548-pcie";
311 device_type = "pci"; 321 device_type = "pci";
312 #interrupt-cells = <1>; 322 #interrupt-cells = <1>;
@@ -343,7 +353,6 @@
343 }; 353 };
344 354
345 pci2: pcie@e000a000 { 355 pci2: pcie@e000a000 {
346 cell-index = <2>;
347 compatible = "fsl,mpc8548-pcie"; 356 compatible = "fsl,mpc8548-pcie";
348 device_type = "pci"; 357 device_type = "pci";
349 #interrupt-cells = <1>; 358 #interrupt-cells = <1>;
@@ -380,7 +389,6 @@
380 }; 389 };
381 390
382 pci3: pcie@e000b000 { 391 pci3: pcie@e000b000 {
383 cell-index = <3>;
384 compatible = "fsl,mpc8548-pcie"; 392 compatible = "fsl,mpc8548-pcie";
385 device_type = "pci"; 393 device_type = "pci";
386 #interrupt-cells = <1>; 394 #interrupt-cells = <1>;
diff --git a/arch/powerpc/boot/dts/mpc8548cds.dts b/arch/powerpc/boot/dts/mpc8548cds.dts
index 804e90353293..475be1433fe1 100644
--- a/arch/powerpc/boot/dts/mpc8548cds.dts
+++ b/arch/powerpc/boot/dts/mpc8548cds.dts
@@ -60,9 +60,21 @@
60 device_type = "soc"; 60 device_type = "soc";
61 compatible = "simple-bus"; 61 compatible = "simple-bus";
62 ranges = <0x0 0xe0000000 0x100000>; 62 ranges = <0x0 0xe0000000 0x100000>;
63 reg = <0xe0000000 0x1000>; // CCSRBAR
64 bus-frequency = <0>; 63 bus-frequency = <0>;
65 64
65 ecm-law@0 {
66 compatible = "fsl,ecm-law";
67 reg = <0x0 0x1000>;
68 fsl,num-laws = <10>;
69 };
70
71 ecm@1000 {
72 compatible = "fsl,mpc8548-ecm", "fsl,ecm";
73 reg = <0x1000 0x1000>;
74 interrupts = <17 2>;
75 interrupt-parent = <&mpic>;
76 };
77
66 memory-controller@2000 { 78 memory-controller@2000 {
67 compatible = "fsl,8548-memory-controller"; 79 compatible = "fsl,8548-memory-controller";
68 reg = <0x2000 0x1000>; 80 reg = <0x2000 0x1000>;
@@ -328,7 +340,6 @@
328 }; 340 };
329 341
330 pci0: pci@e0008000 { 342 pci0: pci@e0008000 {
331 cell-index = <0>;
332 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 343 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
333 interrupt-map = < 344 interrupt-map = <
334 /* IDSEL 0x4 (PCIX Slot 2) */ 345 /* IDSEL 0x4 (PCIX Slot 2) */
@@ -478,7 +489,6 @@
478 }; 489 };
479 490
480 pci1: pci@e0009000 { 491 pci1: pci@e0009000 {
481 cell-index = <1>;
482 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 492 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
483 interrupt-map = < 493 interrupt-map = <
484 494
@@ -503,7 +513,6 @@
503 }; 513 };
504 514
505 pci2: pcie@e000a000 { 515 pci2: pcie@e000a000 {
506 cell-index = <2>;
507 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 516 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
508 interrupt-map = < 517 interrupt-map = <
509 518
diff --git a/arch/powerpc/boot/dts/mpc8555cds.dts b/arch/powerpc/boot/dts/mpc8555cds.dts
index 9484f0729b10..065b2f093de2 100644
--- a/arch/powerpc/boot/dts/mpc8555cds.dts
+++ b/arch/powerpc/boot/dts/mpc8555cds.dts
@@ -55,9 +55,21 @@
55 device_type = "soc"; 55 device_type = "soc";
56 compatible = "simple-bus"; 56 compatible = "simple-bus";
57 ranges = <0x0 0xe0000000 0x100000>; 57 ranges = <0x0 0xe0000000 0x100000>;
58 reg = <0xe0000000 0x1000>; // CCSRBAR 1M
59 bus-frequency = <0>; 58 bus-frequency = <0>;
60 59
60 ecm-law@0 {
61 compatible = "fsl,ecm-law";
62 reg = <0x0 0x1000>;
63 fsl,num-laws = <8>;
64 };
65
66 ecm@1000 {
67 compatible = "fsl,mpc8555-ecm", "fsl,ecm";
68 reg = <0x1000 0x1000>;
69 interrupts = <17 2>;
70 interrupt-parent = <&mpic>;
71 };
72
61 memory-controller@2000 { 73 memory-controller@2000 {
62 compatible = "fsl,8555-memory-controller"; 74 compatible = "fsl,8555-memory-controller";
63 reg = <0x2000 0x1000>; 75 reg = <0x2000 0x1000>;
@@ -272,7 +284,6 @@
272 }; 284 };
273 285
274 pci0: pci@e0008000 { 286 pci0: pci@e0008000 {
275 cell-index = <0>;
276 interrupt-map-mask = <0x1f800 0x0 0x0 0x7>; 287 interrupt-map-mask = <0x1f800 0x0 0x0 0x7>;
277 interrupt-map = < 288 interrupt-map = <
278 289
@@ -344,7 +355,6 @@
344 }; 355 };
345 356
346 pci1: pci@e0009000 { 357 pci1: pci@e0009000 {
347 cell-index = <1>;
348 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 358 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
349 interrupt-map = < 359 interrupt-map = <
350 360
diff --git a/arch/powerpc/boot/dts/mpc8560ads.dts b/arch/powerpc/boot/dts/mpc8560ads.dts
index cc2acf87d02f..a5bb1ec70a5a 100644
--- a/arch/powerpc/boot/dts/mpc8560ads.dts
+++ b/arch/powerpc/boot/dts/mpc8560ads.dts
@@ -55,9 +55,21 @@
55 device_type = "soc"; 55 device_type = "soc";
56 compatible = "simple-bus"; 56 compatible = "simple-bus";
57 ranges = <0x0 0xe0000000 0x100000>; 57 ranges = <0x0 0xe0000000 0x100000>;
58 reg = <0xe0000000 0x200>;
59 bus-frequency = <330000000>; 58 bus-frequency = <330000000>;
60 59
60 ecm-law@0 {
61 compatible = "fsl,ecm-law";
62 reg = <0x0 0x1000>;
63 fsl,num-laws = <8>;
64 };
65
66 ecm@1000 {
67 compatible = "fsl,mpc8560-ecm", "fsl,ecm";
68 reg = <0x1000 0x1000>;
69 interrupts = <17 2>;
70 interrupt-parent = <&mpic>;
71 };
72
61 memory-controller@2000 { 73 memory-controller@2000 {
62 compatible = "fsl,8540-memory-controller"; 74 compatible = "fsl,8540-memory-controller";
63 reg = <0x2000 0x1000>; 75 reg = <0x2000 0x1000>;
@@ -291,7 +303,6 @@
291 }; 303 };
292 304
293 pci0: pci@e0008000 { 305 pci0: pci@e0008000 {
294 cell-index = <0>;
295 #interrupt-cells = <1>; 306 #interrupt-cells = <1>;
296 #size-cells = <2>; 307 #size-cells = <2>;
297 #address-cells = <3>; 308 #address-cells = <3>;
diff --git a/arch/powerpc/boot/dts/mpc8568mds.dts b/arch/powerpc/boot/dts/mpc8568mds.dts
index 9d52e3b25047..00c2bbda7013 100644
--- a/arch/powerpc/boot/dts/mpc8568mds.dts
+++ b/arch/powerpc/boot/dts/mpc8568mds.dts
@@ -26,6 +26,7 @@
26 serial1 = &serial1; 26 serial1 = &serial1;
27 pci0 = &pci0; 27 pci0 = &pci0;
28 pci1 = &pci1; 28 pci1 = &pci1;
29 rapidio0 = &rio0;
29 }; 30 };
30 31
31 cpus { 32 cpus {
@@ -62,9 +63,21 @@
62 device_type = "soc"; 63 device_type = "soc";
63 compatible = "simple-bus"; 64 compatible = "simple-bus";
64 ranges = <0x0 0xe0000000 0x100000>; 65 ranges = <0x0 0xe0000000 0x100000>;
65 reg = <0xe0000000 0x1000>;
66 bus-frequency = <0>; 66 bus-frequency = <0>;
67 67
68 ecm-law@0 {
69 compatible = "fsl,ecm-law";
70 reg = <0x0 0x1000>;
71 fsl,num-laws = <10>;
72 };
73
74 ecm@1000 {
75 compatible = "fsl,mpc8568-ecm", "fsl,ecm";
76 reg = <0x1000 0x1000>;
77 interrupts = <17 2>;
78 interrupt-parent = <&mpic>;
79 };
80
68 memory-controller@2000 { 81 memory-controller@2000 {
69 compatible = "fsl,8568-memory-controller"; 82 compatible = "fsl,8568-memory-controller";
70 reg = <0x2000 0x1000>; 83 reg = <0x2000 0x1000>;
@@ -275,6 +288,22 @@
275 device_type = "open-pic"; 288 device_type = "open-pic";
276 }; 289 };
277 290
291 msi@41600 {
292 compatible = "fsl,mpc8568-msi", "fsl,mpic-msi";
293 reg = <0x41600 0x80>;
294 msi-available-ranges = <0 0x100>;
295 interrupts = <
296 0xe0 0
297 0xe1 0
298 0xe2 0
299 0xe3 0
300 0xe4 0
301 0xe5 0
302 0xe6 0
303 0xe7 0>;
304 interrupt-parent = <&mpic>;
305 };
306
278 par_io@e0100 { 307 par_io@e0100 {
279 reg = <0xe0100 0x100>; 308 reg = <0xe0100 0x100>;
280 device_type = "par_io"; 309 device_type = "par_io";
@@ -349,6 +378,8 @@
349 reg = <0xe0080000 0x480>; 378 reg = <0xe0080000 0x480>;
350 brg-frequency = <0>; 379 brg-frequency = <0>;
351 bus-frequency = <396000000>; 380 bus-frequency = <396000000>;
381 fsl,qe-num-riscs = <2>;
382 fsl,qe-num-snums = <28>;
352 383
353 muram@10000 { 384 muram@10000 {
354 #address-cells = <1>; 385 #address-cells = <1>;
@@ -459,7 +490,6 @@
459 }; 490 };
460 491
461 pci0: pci@e0008000 { 492 pci0: pci@e0008000 {
462 cell-index = <0>;
463 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 493 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
464 interrupt-map = < 494 interrupt-map = <
465 /* IDSEL 0x12 AD18 */ 495 /* IDSEL 0x12 AD18 */
@@ -490,7 +520,6 @@
490 520
491 /* PCI Express */ 521 /* PCI Express */
492 pci1: pcie@e000a000 { 522 pci1: pcie@e000a000 {
493 cell-index = <2>;
494 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 523 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
495 interrupt-map = < 524 interrupt-map = <
496 525
@@ -526,4 +555,20 @@
526 0x0 0x800000>; 555 0x0 0x800000>;
527 }; 556 };
528 }; 557 };
558
559 rio0: rapidio@e00c00000 {
560 #address-cells = <2>;
561 #size-cells = <2>;
562 compatible = "fsl,mpc8568-rapidio", "fsl,rapidio-delta";
563 reg = <0xe00c0000 0x20000>;
564 ranges = <0x0 0x0 0xc0000000 0x0 0x20000000>;
565 interrupts = <48 2 /* error */
566 49 2 /* bell_outb */
567 50 2 /* bell_inb */
568 53 2 /* msg1_tx */
569 54 2 /* msg1_rx */
570 55 2 /* msg2_tx */
571 56 2 /* msg2_rx */>;
572 interrupt-parent = <&mpic>;
573 };
529}; 574};
diff --git a/arch/powerpc/boot/dts/mpc8569mds.dts b/arch/powerpc/boot/dts/mpc8569mds.dts
new file mode 100644
index 000000000000..39c2927503cf
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc8569mds.dts
@@ -0,0 +1,583 @@
1/*
2 * MPC8569E MDS Device Tree Source
3 *
4 * Copyright (C) 2009 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/dts-v1/;
13
14/ {
15 model = "MPC8569EMDS";
16 compatible = "fsl,MPC8569EMDS";
17 #address-cells = <1>;
18 #size-cells = <1>;
19
20 aliases {
21 serial0 = &serial0;
22 serial1 = &serial1;
23 ethernet0 = &enet0;
24 ethernet1 = &enet1;
25 ethernet2 = &enet2;
26 ethernet3 = &enet3;
27 pci1 = &pci1;
28 rapidio0 = &rio0;
29 };
30
31 cpus {
32 #address-cells = <1>;
33 #size-cells = <0>;
34
35 PowerPC,8569@0 {
36 device_type = "cpu";
37 reg = <0x0>;
38 d-cache-line-size = <32>; // 32 bytes
39 i-cache-line-size = <32>; // 32 bytes
40 d-cache-size = <0x8000>; // L1, 32K
41 i-cache-size = <0x8000>; // L1, 32K
42 timebase-frequency = <0>;
43 bus-frequency = <0>;
44 clock-frequency = <0>;
45 next-level-cache = <&L2>;
46 };
47 };
48
49 memory {
50 device_type = "memory";
51 };
52
53 localbus@e0005000 {
54 #address-cells = <2>;
55 #size-cells = <1>;
56 compatible = "fsl,mpc8569-elbc", "fsl,elbc", "simple-bus";
57 reg = <0xe0005000 0x1000>;
58 interrupts = <19 2>;
59 interrupt-parent = <&mpic>;
60
61 ranges = <0x0 0x0 0xfe000000 0x02000000
62 0x1 0x0 0xf8000000 0x00008000
63 0x2 0x0 0xf0000000 0x04000000
64 0x3 0x0 0xfc000000 0x00008000
65 0x4 0x0 0xf8008000 0x00008000
66 0x5 0x0 0xf8010000 0x00008000>;
67
68 nor@0,0 {
69 #address-cells = <1>;
70 #size-cells = <1>;
71 compatible = "cfi-flash";
72 reg = <0x0 0x0 0x02000000>;
73 bank-width = <2>;
74 device-width = <1>;
75 };
76
77 bcsr@1,0 {
78 compatible = "fsl,mpc8569mds-bcsr";
79 reg = <1 0 0x8000>;
80 };
81
82 nand@3,0 {
83 compatible = "fsl,mpc8569-fcm-nand",
84 "fsl,elbc-fcm-nand";
85 reg = <3 0 0x8000>;
86 };
87
88 pib@4,0 {
89 compatible = "fsl,mpc8569mds-pib";
90 reg = <4 0 0x8000>;
91 };
92
93 pib@5,0 {
94 compatible = "fsl,mpc8569mds-pib";
95 reg = <5 0 0x8000>;
96 };
97 };
98
99 soc@e0000000 {
100 #address-cells = <1>;
101 #size-cells = <1>;
102 device_type = "soc";
103 compatible = "fsl,mpc8569-immr", "simple-bus";
104 ranges = <0x0 0xe0000000 0x100000>;
105 bus-frequency = <0>;
106
107 ecm-law@0 {
108 compatible = "fsl,ecm-law";
109 reg = <0x0 0x1000>;
110 fsl,num-laws = <10>;
111 };
112
113 ecm@1000 {
114 compatible = "fsl,mpc8569-ecm", "fsl,ecm";
115 reg = <0x1000 0x1000>;
116 interrupts = <17 2>;
117 interrupt-parent = <&mpic>;
118 };
119
120 memory-controller@2000 {
121 compatible = "fsl,mpc8569-memory-controller";
122 reg = <0x2000 0x1000>;
123 interrupt-parent = <&mpic>;
124 interrupts = <18 2>;
125 };
126
127 i2c@3000 {
128 #address-cells = <1>;
129 #size-cells = <0>;
130 cell-index = <0>;
131 compatible = "fsl-i2c";
132 reg = <0x3000 0x100>;
133 interrupts = <43 2>;
134 interrupt-parent = <&mpic>;
135 dfsrr;
136
137 rtc@68 {
138 compatible = "dallas,ds1374";
139 reg = <0x68>;
140 };
141 };
142
143 i2c@3100 {
144 #address-cells = <1>;
145 #size-cells = <0>;
146 cell-index = <1>;
147 compatible = "fsl-i2c";
148 reg = <0x3100 0x100>;
149 interrupts = <43 2>;
150 interrupt-parent = <&mpic>;
151 dfsrr;
152 };
153
154 serial0: serial@4500 {
155 cell-index = <0>;
156 device_type = "serial";
157 compatible = "ns16550";
158 reg = <0x4500 0x100>;
159 clock-frequency = <0>;
160 interrupts = <42 2>;
161 interrupt-parent = <&mpic>;
162 };
163
164 serial1: serial@4600 {
165 cell-index = <1>;
166 device_type = "serial";
167 compatible = "ns16550";
168 reg = <0x4600 0x100>;
169 clock-frequency = <0>;
170 interrupts = <42 2>;
171 interrupt-parent = <&mpic>;
172 };
173
174 L2: l2-cache-controller@20000 {
175 compatible = "fsl,mpc8569-l2-cache-controller";
176 reg = <0x20000 0x1000>;
177 cache-line-size = <32>; // 32 bytes
178 cache-size = <0x80000>; // L2, 512K
179 interrupt-parent = <&mpic>;
180 interrupts = <16 2>;
181 };
182
183 dma@21300 {
184 #address-cells = <1>;
185 #size-cells = <1>;
186 compatible = "fsl,mpc8569-dma", "fsl,eloplus-dma";
187 reg = <0x21300 0x4>;
188 ranges = <0x0 0x21100 0x200>;
189 cell-index = <0>;
190 dma-channel@0 {
191 compatible = "fsl,mpc8569-dma-channel",
192 "fsl,eloplus-dma-channel";
193 reg = <0x0 0x80>;
194 cell-index = <0>;
195 interrupt-parent = <&mpic>;
196 interrupts = <20 2>;
197 };
198 dma-channel@80 {
199 compatible = "fsl,mpc8569-dma-channel",
200 "fsl,eloplus-dma-channel";
201 reg = <0x80 0x80>;
202 cell-index = <1>;
203 interrupt-parent = <&mpic>;
204 interrupts = <21 2>;
205 };
206 dma-channel@100 {
207 compatible = "fsl,mpc8569-dma-channel",
208 "fsl,eloplus-dma-channel";
209 reg = <0x100 0x80>;
210 cell-index = <2>;
211 interrupt-parent = <&mpic>;
212 interrupts = <22 2>;
213 };
214 dma-channel@180 {
215 compatible = "fsl,mpc8569-dma-channel",
216 "fsl,eloplus-dma-channel";
217 reg = <0x180 0x80>;
218 cell-index = <3>;
219 interrupt-parent = <&mpic>;
220 interrupts = <23 2>;
221 };
222 };
223
224 sdhci@2e000 {
225 compatible = "fsl,mpc8569-esdhc", "fsl,esdhc";
226 reg = <0x2e000 0x1000>;
227 interrupts = <72 0x8>;
228 interrupt-parent = <&mpic>;
229 /* Filled in by U-Boot */
230 clock-frequency = <0>;
231 status = "disabled";
232 };
233
234 crypto@30000 {
235 compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
236 "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
237 reg = <0x30000 0x10000>;
238 interrupts = <45 2 58 2>;
239 interrupt-parent = <&mpic>;
240 fsl,num-channels = <4>;
241 fsl,channel-fifo-len = <24>;
242 fsl,exec-units-mask = <0xbfe>;
243 fsl,descriptor-types-mask = <0x3ab0ebf>;
244 };
245
246 mpic: pic@40000 {
247 interrupt-controller;
248 #address-cells = <0>;
249 #interrupt-cells = <2>;
250 reg = <0x40000 0x40000>;
251 compatible = "chrp,open-pic";
252 device_type = "open-pic";
253 };
254
255 msi@41600 {
256 compatible = "fsl,mpc8568-msi", "fsl,mpic-msi";
257 reg = <0x41600 0x80>;
258 msi-available-ranges = <0 0x100>;
259 interrupts = <
260 0xe0 0
261 0xe1 0
262 0xe2 0
263 0xe3 0
264 0xe4 0
265 0xe5 0
266 0xe6 0
267 0xe7 0>;
268 interrupt-parent = <&mpic>;
269 };
270
271 global-utilities@e0000 {
272 compatible = "fsl,mpc8569-guts";
273 reg = <0xe0000 0x1000>;
274 fsl,has-rstcr;
275 };
276
277 par_io@e0100 {
278 #address-cells = <1>;
279 #size-cells = <1>;
280 reg = <0xe0100 0x100>;
281 ranges = <0x0 0xe0100 0x100>;
282 device_type = "par_io";
283 num-ports = <7>;
284
285 qe_pio_e: gpio-controller@80 {
286 #gpio-cells = <2>;
287 compatible = "fsl,mpc8569-qe-pario-bank",
288 "fsl,mpc8323-qe-pario-bank";
289 reg = <0x80 0x18>;
290 gpio-controller;
291 };
292
293 pio1: ucc_pin@01 {
294 pio-map = <
295 /* port pin dir open_drain assignment has_irq */
296 0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
297 0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */
298 0x2 0x0b 0x2 0x0 0x1 0x0 /* CLK12*/
299 0x0 0x0 0x1 0x0 0x3 0x0 /* ENET1_TXD0_SER1_TXD0 */
300 0x0 0x1 0x1 0x0 0x3 0x0 /* ENET1_TXD1_SER1_TXD1 */
301 0x0 0x2 0x1 0x0 0x1 0x0 /* ENET1_TXD2_SER1_TXD2 */
302 0x0 0x3 0x1 0x0 0x2 0x0 /* ENET1_TXD3_SER1_TXD3 */
303 0x0 0x6 0x2 0x0 0x3 0x0 /* ENET1_RXD0_SER1_RXD0 */
304 0x0 0x7 0x2 0x0 0x1 0x0 /* ENET1_RXD1_SER1_RXD1 */
305 0x0 0x8 0x2 0x0 0x2 0x0 /* ENET1_RXD2_SER1_RXD2 */
306 0x0 0x9 0x2 0x0 0x2 0x0 /* ENET1_RXD3_SER1_RXD3 */
307 0x0 0x4 0x1 0x0 0x2 0x0 /* ENET1_TX_EN_SER1_RTS_B */
308 0x0 0xc 0x2 0x0 0x3 0x0 /* ENET1_RX_DV_SER1_CTS_B */
309 0x2 0x8 0x2 0x0 0x1 0x0 /* ENET1_GRXCLK */
310 0x2 0x14 0x1 0x0 0x2 0x0>; /* ENET1_GTXCLK */
311 };
312
313 pio2: ucc_pin@02 {
314 pio-map = <
315 /* port pin dir open_drain assignment has_irq */
316 0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
317 0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */
318 0x2 0x10 0x2 0x0 0x3 0x0 /* CLK17 */
319 0x0 0xe 0x1 0x0 0x2 0x0 /* ENET2_TXD0_SER2_TXD0 */
320 0x0 0xf 0x1 0x0 0x2 0x0 /* ENET2_TXD1_SER2_TXD1 */
321 0x0 0x10 0x1 0x0 0x1 0x0 /* ENET2_TXD2_SER2_TXD2 */
322 0x0 0x11 0x1 0x0 0x1 0x0 /* ENET2_TXD3_SER2_TXD3 */
323 0x0 0x14 0x2 0x0 0x2 0x0 /* ENET2_RXD0_SER2_RXD0 */
324 0x0 0x15 0x2 0x0 0x1 0x0 /* ENET2_RXD1_SER2_RXD1 */
325 0x0 0x16 0x2 0x0 0x1 0x0 /* ENET2_RXD2_SER2_RXD2 */
326 0x0 0x17 0x2 0x0 0x1 0x0 /* ENET2_RXD3_SER2_RXD3 */
327 0x0 0x12 0x1 0x0 0x2 0x0 /* ENET2_TX_EN_SER2_RTS_B */
328 0x0 0x1a 0x2 0x0 0x3 0x0 /* ENET2_RX_DV_SER2_CTS_B */
329 0x2 0x3 0x2 0x0 0x1 0x0 /* ENET2_GRXCLK */
330 0x2 0x2 0x1 0x0 0x2 0x0>; /* ENET2_GTXCLK */
331 };
332
333 pio3: ucc_pin@03 {
334 pio-map = <
335 /* port pin dir open_drain assignment has_irq */
336 0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
337 0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */
338 0x2 0x0b 0x2 0x0 0x1 0x0 /* CLK12*/
339 0x0 0x1d 0x1 0x0 0x2 0x0 /* ENET3_TXD0_SER3_TXD0 */
340 0x0 0x1e 0x1 0x0 0x3 0x0 /* ENET3_TXD1_SER3_TXD1 */
341 0x0 0x1f 0x1 0x0 0x2 0x0 /* ENET3_TXD2_SER3_TXD2 */
342 0x1 0x0 0x1 0x0 0x3 0x0 /* ENET3_TXD3_SER3_TXD3 */
343 0x1 0x3 0x2 0x0 0x3 0x0 /* ENET3_RXD0_SER3_RXD0 */
344 0x1 0x4 0x2 0x0 0x1 0x0 /* ENET3_RXD1_SER3_RXD1 */
345 0x1 0x5 0x2 0x0 0x2 0x0 /* ENET3_RXD2_SER3_RXD2 */
346 0x1 0x6 0x2 0x0 0x3 0x0 /* ENET3_RXD3_SER3_RXD3 */
347 0x1 0x1 0x1 0x0 0x1 0x0 /* ENET3_TX_EN_SER3_RTS_B */
348 0x1 0x9 0x2 0x0 0x3 0x0 /* ENET3_RX_DV_SER3_CTS_B */
349 0x2 0x9 0x2 0x0 0x2 0x0 /* ENET3_GRXCLK */
350 0x2 0x19 0x1 0x0 0x2 0x0>; /* ENET3_GTXCLK */
351 };
352
353 pio4: ucc_pin@04 {
354 pio-map = <
355 /* port pin dir open_drain assignment has_irq */
356 0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
357 0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */
358 0x2 0x10 0x2 0x0 0x3 0x0 /* CLK17 */
359 0x1 0xc 0x1 0x0 0x2 0x0 /* ENET4_TXD0_SER4_TXD0 */
360 0x1 0xd 0x1 0x0 0x2 0x0 /* ENET4_TXD1_SER4_TXD1 */
361 0x1 0xe 0x1 0x0 0x1 0x0 /* ENET4_TXD2_SER4_TXD2 */
362 0x1 0xf 0x1 0x0 0x2 0x0 /* ENET4_TXD3_SER4_TXD3 */
363 0x1 0x12 0x2 0x0 0x2 0x0 /* ENET4_RXD0_SER4_RXD0 */
364 0x1 0x13 0x2 0x0 0x1 0x0 /* ENET4_RXD1_SER4_RXD1 */
365 0x1 0x14 0x2 0x0 0x1 0x0 /* ENET4_RXD2_SER4_RXD2 */
366 0x1 0x15 0x2 0x0 0x2 0x0 /* ENET4_RXD3_SER4_RXD3 */
367 0x1 0x10 0x1 0x0 0x2 0x0 /* ENET4_TX_EN_SER4_RTS_B */
368 0x1 0x18 0x2 0x0 0x3 0x0 /* ENET4_RX_DV_SER4_CTS_B */
369 0x2 0x11 0x2 0x0 0x2 0x0 /* ENET4_GRXCLK */
370 0x2 0x18 0x1 0x0 0x2 0x0>; /* ENET4_GTXCLK */
371 };
372 };
373 };
374
375 qe@e0080000 {
376 #address-cells = <1>;
377 #size-cells = <1>;
378 device_type = "qe";
379 compatible = "fsl,qe";
380 ranges = <0x0 0xe0080000 0x40000>;
381 reg = <0xe0080000 0x480>;
382 brg-frequency = <0>;
383 bus-frequency = <0>;
384 fsl,qe-num-riscs = <4>;
385 fsl,qe-num-snums = <46>;
386
387 qeic: interrupt-controller@80 {
388 interrupt-controller;
389 compatible = "fsl,qe-ic";
390 #address-cells = <0>;
391 #interrupt-cells = <1>;
392 reg = <0x80 0x80>;
393 interrupts = <46 2 46 2>; //high:30 low:30
394 interrupt-parent = <&mpic>;
395 };
396
397 spi@4c0 {
398 #address-cells = <1>;
399 #size-cells = <0>;
400 compatible = "fsl,mpc8569-qe-spi", "fsl,spi";
401 reg = <0x4c0 0x40>;
402 cell-index = <0>;
403 interrupts = <2>;
404 interrupt-parent = <&qeic>;
405 gpios = <&qe_pio_e 30 0>;
406 mode = "cpu-qe";
407
408 serial-flash@0 {
409 compatible = "stm,m25p40";
410 reg = <0>;
411 spi-max-frequency = <25000000>;
412 };
413 };
414
415 spi@500 {
416 cell-index = <1>;
417 compatible = "fsl,spi";
418 reg = <0x500 0x40>;
419 interrupts = <1>;
420 interrupt-parent = <&qeic>;
421 mode = "cpu";
422 };
423
424 enet0: ucc@2000 {
425 device_type = "network";
426 compatible = "ucc_geth";
427 cell-index = <1>;
428 reg = <0x2000 0x200>;
429 interrupts = <32>;
430 interrupt-parent = <&qeic>;
431 local-mac-address = [ 00 00 00 00 00 00 ];
432 rx-clock-name = "none";
433 tx-clock-name = "clk12";
434 pio-handle = <&pio1>;
435 phy-handle = <&qe_phy0>;
436 phy-connection-type = "rgmii-id";
437 };
438
439 mdio@2120 {
440 #address-cells = <1>;
441 #size-cells = <0>;
442 reg = <0x2120 0x18>;
443 compatible = "fsl,ucc-mdio";
444
445 qe_phy0: ethernet-phy@07 {
446 interrupt-parent = <&mpic>;
447 interrupts = <1 1>;
448 reg = <0x7>;
449 device_type = "ethernet-phy";
450 };
451 qe_phy1: ethernet-phy@01 {
452 interrupt-parent = <&mpic>;
453 interrupts = <2 1>;
454 reg = <0x1>;
455 device_type = "ethernet-phy";
456 };
457 qe_phy2: ethernet-phy@02 {
458 interrupt-parent = <&mpic>;
459 interrupts = <3 1>;
460 reg = <0x2>;
461 device_type = "ethernet-phy";
462 };
463 qe_phy3: ethernet-phy@03 {
464 interrupt-parent = <&mpic>;
465 interrupts = <4 1>;
466 reg = <0x3>;
467 device_type = "ethernet-phy";
468 };
469 };
470
471 enet2: ucc@2200 {
472 device_type = "network";
473 compatible = "ucc_geth";
474 cell-index = <3>;
475 reg = <0x2200 0x200>;
476 interrupts = <34>;
477 interrupt-parent = <&qeic>;
478 local-mac-address = [ 00 00 00 00 00 00 ];
479 rx-clock-name = "none";
480 tx-clock-name = "clk12";
481 pio-handle = <&pio3>;
482 phy-handle = <&qe_phy2>;
483 phy-connection-type = "rgmii-id";
484 };
485
486 enet1: ucc@3000 {
487 device_type = "network";
488 compatible = "ucc_geth";
489 cell-index = <2>;
490 reg = <0x3000 0x200>;
491 interrupts = <33>;
492 interrupt-parent = <&qeic>;
493 local-mac-address = [ 00 00 00 00 00 00 ];
494 rx-clock-name = "none";
495 tx-clock-name = "clk17";
496 pio-handle = <&pio2>;
497 phy-handle = <&qe_phy1>;
498 phy-connection-type = "rgmii-id";
499 };
500
501 enet3: ucc@3200 {
502 device_type = "network";
503 compatible = "ucc_geth";
504 cell-index = <4>;
505 reg = <0x3200 0x200>;
506 interrupts = <35>;
507 interrupt-parent = <&qeic>;
508 local-mac-address = [ 00 00 00 00 00 00 ];
509 rx-clock-name = "none";
510 tx-clock-name = "clk17";
511 pio-handle = <&pio4>;
512 phy-handle = <&qe_phy3>;
513 phy-connection-type = "rgmii-id";
514 };
515
516 muram@10000 {
517 #address-cells = <1>;
518 #size-cells = <1>;
519 compatible = "fsl,qe-muram", "fsl,cpm-muram";
520 ranges = <0x0 0x10000 0x20000>;
521
522 data-only@0 {
523 compatible = "fsl,qe-muram-data",
524 "fsl,cpm-muram-data";
525 reg = <0x0 0x20000>;
526 };
527 };
528
529 };
530
531 /* PCI Express */
532 pci1: pcie@e000a000 {
533 compatible = "fsl,mpc8548-pcie";
534 device_type = "pci";
535 #interrupt-cells = <1>;
536 #size-cells = <2>;
537 #address-cells = <3>;
538 reg = <0xe000a000 0x1000>;
539 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
540 interrupt-map = <
541 /* IDSEL 0x0 (PEX) */
542 00000 0x0 0x0 0x1 &mpic 0x0 0x1
543 00000 0x0 0x0 0x2 &mpic 0x1 0x1
544 00000 0x0 0x0 0x3 &mpic 0x2 0x1
545 00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
546
547 interrupt-parent = <&mpic>;
548 interrupts = <26 2>;
549 bus-range = <0 255>;
550 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
551 0x1000000 0x0 0x00000000 0xe2800000 0x0 0x00800000>;
552 clock-frequency = <33333333>;
553 pcie@0 {
554 reg = <0x0 0x0 0x0 0x0 0x0>;
555 #size-cells = <2>;
556 #address-cells = <3>;
557 device_type = "pci";
558 ranges = <0x2000000 0x0 0xa0000000
559 0x2000000 0x0 0xa0000000
560 0x0 0x10000000
561
562 0x1000000 0x0 0x0
563 0x1000000 0x0 0x0
564 0x0 0x800000>;
565 };
566 };
567
568 rio0: rapidio@e00c00000 {
569 #address-cells = <2>;
570 #size-cells = <2>;
571 compatible = "fsl,mpc8569-rapidio", "fsl,rapidio-delta";
572 reg = <0xe00c0000 0x20000>;
573 ranges = <0x0 0x0 0xc0000000 0x0 0x20000000>;
574 interrupts = <48 2 /* error */
575 49 2 /* bell_outb */
576 50 2 /* bell_inb */
577 53 2 /* msg1_tx */
578 54 2 /* msg1_rx */
579 55 2 /* msg2_tx */
580 56 2 /* msg2_rx */>;
581 interrupt-parent = <&mpic>;
582 };
583};
diff --git a/arch/powerpc/boot/dts/mpc8572ds.dts b/arch/powerpc/boot/dts/mpc8572ds.dts
index 6e79a4169088..cafc1285c140 100644
--- a/arch/powerpc/boot/dts/mpc8572ds.dts
+++ b/arch/powerpc/boot/dts/mpc8572ds.dts
@@ -182,9 +182,21 @@
182 device_type = "soc"; 182 device_type = "soc";
183 compatible = "simple-bus"; 183 compatible = "simple-bus";
184 ranges = <0x0 0 0xffe00000 0x100000>; 184 ranges = <0x0 0 0xffe00000 0x100000>;
185 reg = <0 0xffe00000 0 0x1000>; // CCSRBAR & soc regs, remove once parse code for immrbase fixed
186 bus-frequency = <0>; // Filled out by uboot. 185 bus-frequency = <0>; // Filled out by uboot.
187 186
187 ecm-law@0 {
188 compatible = "fsl,ecm-law";
189 reg = <0x0 0x1000>;
190 fsl,num-laws = <12>;
191 };
192
193 ecm@1000 {
194 compatible = "fsl,mpc8572-ecm", "fsl,ecm";
195 reg = <0x1000 0x1000>;
196 interrupts = <17 2>;
197 interrupt-parent = <&mpic>;
198 };
199
188 memory-controller@2000 { 200 memory-controller@2000 {
189 compatible = "fsl,mpc8572-memory-controller"; 201 compatible = "fsl,mpc8572-memory-controller";
190 reg = <0x2000 0x1000>; 202 reg = <0x2000 0x1000>;
@@ -514,7 +526,6 @@
514 }; 526 };
515 527
516 pci0: pcie@ffe08000 { 528 pci0: pcie@ffe08000 {
517 cell-index = <0>;
518 compatible = "fsl,mpc8548-pcie"; 529 compatible = "fsl,mpc8548-pcie";
519 device_type = "pci"; 530 device_type = "pci";
520 #interrupt-cells = <1>; 531 #interrupt-cells = <1>;
@@ -724,7 +735,6 @@
724 }; 735 };
725 736
726 pci1: pcie@ffe09000 { 737 pci1: pcie@ffe09000 {
727 cell-index = <1>;
728 compatible = "fsl,mpc8548-pcie"; 738 compatible = "fsl,mpc8548-pcie";
729 device_type = "pci"; 739 device_type = "pci";
730 #interrupt-cells = <1>; 740 #interrupt-cells = <1>;
@@ -761,7 +771,6 @@
761 }; 771 };
762 772
763 pci2: pcie@ffe0a000 { 773 pci2: pcie@ffe0a000 {
764 cell-index = <2>;
765 compatible = "fsl,mpc8548-pcie"; 774 compatible = "fsl,mpc8548-pcie";
766 device_type = "pci"; 775 device_type = "pci";
767 #interrupt-cells = <1>; 776 #interrupt-cells = <1>;
diff --git a/arch/powerpc/boot/dts/mpc8572ds_36b.dts b/arch/powerpc/boot/dts/mpc8572ds_36b.dts
index dbd81a764742..f6365db3b97d 100644
--- a/arch/powerpc/boot/dts/mpc8572ds_36b.dts
+++ b/arch/powerpc/boot/dts/mpc8572ds_36b.dts
@@ -182,9 +182,21 @@
182 device_type = "soc"; 182 device_type = "soc";
183 compatible = "simple-bus"; 183 compatible = "simple-bus";
184 ranges = <0x0 0xf 0xffe00000 0x100000>; 184 ranges = <0x0 0xf 0xffe00000 0x100000>;
185 reg = <0xf 0xffe00000 0 0x1000>; // CCSRBAR & soc regs, remove once parse code for immrbase fixed
186 bus-frequency = <0>; // Filled out by uboot. 185 bus-frequency = <0>; // Filled out by uboot.
187 186
187 ecm-law@0 {
188 compatible = "fsl,ecm-law";
189 reg = <0x0 0x1000>;
190 fsl,num-laws = <12>;
191 };
192
193 ecm@1000 {
194 compatible = "fsl,mpc8572-ecm", "fsl,ecm";
195 reg = <0x1000 0x1000>;
196 interrupts = <17 2>;
197 interrupt-parent = <&mpic>;
198 };
199
188 memory-controller@2000 { 200 memory-controller@2000 {
189 compatible = "fsl,mpc8572-memory-controller"; 201 compatible = "fsl,mpc8572-memory-controller";
190 reg = <0x2000 0x1000>; 202 reg = <0x2000 0x1000>;
@@ -514,7 +526,6 @@
514 }; 526 };
515 527
516 pci0: pcie@fffe08000 { 528 pci0: pcie@fffe08000 {
517 cell-index = <0>;
518 compatible = "fsl,mpc8548-pcie"; 529 compatible = "fsl,mpc8548-pcie";
519 device_type = "pci"; 530 device_type = "pci";
520 #interrupt-cells = <1>; 531 #interrupt-cells = <1>;
@@ -522,7 +533,7 @@
522 #address-cells = <3>; 533 #address-cells = <3>;
523 reg = <0xf 0xffe08000 0 0x1000>; 534 reg = <0xf 0xffe08000 0 0x1000>;
524 bus-range = <0 255>; 535 bus-range = <0 255>;
525 ranges = <0x2000000 0x0 0xc0000000 0xc 0x00000000 0x0 0x20000000 536 ranges = <0x2000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000
526 0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x00010000>; 537 0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x00010000>;
527 clock-frequency = <33333333>; 538 clock-frequency = <33333333>;
528 interrupt-parent = <&mpic>; 539 interrupt-parent = <&mpic>;
@@ -649,8 +660,8 @@
649 #size-cells = <2>; 660 #size-cells = <2>;
650 #address-cells = <3>; 661 #address-cells = <3>;
651 device_type = "pci"; 662 device_type = "pci";
652 ranges = <0x2000000 0x0 0xc0000000 663 ranges = <0x2000000 0x0 0xe0000000
653 0x2000000 0x0 0xc0000000 664 0x2000000 0x0 0xe0000000
654 0x0 0x20000000 665 0x0 0x20000000
655 666
656 0x1000000 0x0 0x0 667 0x1000000 0x0 0x0
@@ -660,8 +671,8 @@
660 reg = <0x0 0x0 0x0 0x0 0x0>; 671 reg = <0x0 0x0 0x0 0x0 0x0>;
661 #size-cells = <2>; 672 #size-cells = <2>;
662 #address-cells = <3>; 673 #address-cells = <3>;
663 ranges = <0x2000000 0x0 0xc0000000 674 ranges = <0x2000000 0x0 0xe0000000
664 0x2000000 0x0 0xc0000000 675 0x2000000 0x0 0xe0000000
665 0x0 0x20000000 676 0x0 0x20000000
666 677
667 0x1000000 0x0 0x0 678 0x1000000 0x0 0x0
@@ -724,7 +735,6 @@
724 }; 735 };
725 736
726 pci1: pcie@fffe09000 { 737 pci1: pcie@fffe09000 {
727 cell-index = <1>;
728 compatible = "fsl,mpc8548-pcie"; 738 compatible = "fsl,mpc8548-pcie";
729 device_type = "pci"; 739 device_type = "pci";
730 #interrupt-cells = <1>; 740 #interrupt-cells = <1>;
@@ -732,7 +742,7 @@
732 #address-cells = <3>; 742 #address-cells = <3>;
733 reg = <0xf 0xffe09000 0 0x1000>; 743 reg = <0xf 0xffe09000 0 0x1000>;
734 bus-range = <0 255>; 744 bus-range = <0 255>;
735 ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000 745 ranges = <0x2000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
736 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x00010000>; 746 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x00010000>;
737 clock-frequency = <33333333>; 747 clock-frequency = <33333333>;
738 interrupt-parent = <&mpic>; 748 interrupt-parent = <&mpic>;
@@ -750,8 +760,8 @@
750 #size-cells = <2>; 760 #size-cells = <2>;
751 #address-cells = <3>; 761 #address-cells = <3>;
752 device_type = "pci"; 762 device_type = "pci";
753 ranges = <0x2000000 0x0 0xc0000000 763 ranges = <0x2000000 0x0 0xe0000000
754 0x2000000 0x0 0xc0000000 764 0x2000000 0x0 0xe0000000
755 0x0 0x20000000 765 0x0 0x20000000
756 766
757 0x1000000 0x0 0x0 767 0x1000000 0x0 0x0
@@ -761,7 +771,6 @@
761 }; 771 };
762 772
763 pci2: pcie@fffe0a000 { 773 pci2: pcie@fffe0a000 {
764 cell-index = <2>;
765 compatible = "fsl,mpc8548-pcie"; 774 compatible = "fsl,mpc8548-pcie";
766 device_type = "pci"; 775 device_type = "pci";
767 #interrupt-cells = <1>; 776 #interrupt-cells = <1>;
@@ -769,7 +778,7 @@
769 #address-cells = <3>; 778 #address-cells = <3>;
770 reg = <0xf 0xffe0a000 0 0x1000>; 779 reg = <0xf 0xffe0a000 0 0x1000>;
771 bus-range = <0 255>; 780 bus-range = <0 255>;
772 ranges = <0x2000000 0x0 0xc0000000 0xc 0x40000000 0x0 0x20000000 781 ranges = <0x2000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000
773 0x1000000 0x0 0x00000000 0xf 0xffc20000 0x0 0x00010000>; 782 0x1000000 0x0 0x00000000 0xf 0xffc20000 0x0 0x00010000>;
774 clock-frequency = <33333333>; 783 clock-frequency = <33333333>;
775 interrupt-parent = <&mpic>; 784 interrupt-parent = <&mpic>;
@@ -787,8 +796,8 @@
787 #size-cells = <2>; 796 #size-cells = <2>;
788 #address-cells = <3>; 797 #address-cells = <3>;
789 device_type = "pci"; 798 device_type = "pci";
790 ranges = <0x2000000 0x0 0xc0000000 799 ranges = <0x2000000 0x0 0xe0000000
791 0x2000000 0x0 0xc0000000 800 0x2000000 0x0 0xe0000000
792 0x0 0x20000000 801 0x0 0x20000000
793 802
794 0x1000000 0x0 0x0 803 0x1000000 0x0 0x0
diff --git a/arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts b/arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts
index 2bc0c7189653..5bd1011fde96 100644
--- a/arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts
+++ b/arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts
@@ -59,9 +59,21 @@
59 device_type = "soc"; 59 device_type = "soc";
60 compatible = "simple-bus"; 60 compatible = "simple-bus";
61 ranges = <0x0 0xffe00000 0x100000>; 61 ranges = <0x0 0xffe00000 0x100000>;
62 reg = <0xffe00000 0x1000>; // CCSRBAR & soc regs, remove once parse code for immrbase fixed
63 bus-frequency = <0>; // Filled out by uboot. 62 bus-frequency = <0>; // Filled out by uboot.
64 63
64 ecm-law@0 {
65 compatible = "fsl,ecm-law";
66 reg = <0x0 0x1000>;
67 fsl,num-laws = <12>;
68 };
69
70 ecm@1000 {
71 compatible = "fsl,mpc8572-ecm", "fsl,ecm";
72 reg = <0x1000 0x1000>;
73 interrupts = <17 2>;
74 interrupt-parent = <&mpic>;
75 };
76
65 memory-controller@2000 { 77 memory-controller@2000 {
66 compatible = "fsl,mpc8572-memory-controller"; 78 compatible = "fsl,mpc8572-memory-controller";
67 reg = <0x2000 0x1000>; 79 reg = <0x2000 0x1000>;
@@ -238,7 +250,6 @@
238 }; 250 };
239 251
240 pci0: pcie@ffe08000 { 252 pci0: pcie@ffe08000 {
241 cell-index = <0>;
242 compatible = "fsl,mpc8548-pcie"; 253 compatible = "fsl,mpc8548-pcie";
243 device_type = "pci"; 254 device_type = "pci";
244 #interrupt-cells = <1>; 255 #interrupt-cells = <1>;
@@ -448,7 +459,6 @@
448 }; 459 };
449 460
450 pci1: pcie@ffe09000 { 461 pci1: pcie@ffe09000 {
451 cell-index = <1>;
452 compatible = "fsl,mpc8548-pcie"; 462 compatible = "fsl,mpc8548-pcie";
453 device_type = "pci"; 463 device_type = "pci";
454 #interrupt-cells = <1>; 464 #interrupt-cells = <1>;
diff --git a/arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts b/arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts
index 159cb3a875f0..0efc3456e297 100644
--- a/arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts
+++ b/arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts
@@ -58,7 +58,6 @@
58 device_type = "soc"; 58 device_type = "soc";
59 compatible = "simple-bus"; 59 compatible = "simple-bus";
60 ranges = <0x0 0xffe00000 0x100000>; 60 ranges = <0x0 0xffe00000 0x100000>;
61 reg = <0xffe00000 0x1000>; // CCSRBAR & soc regs, remove once parse code for immrbase fixed
62 bus-frequency = <0>; // Filled out by uboot. 61 bus-frequency = <0>; // Filled out by uboot.
63 62
64 L2: l2-cache-controller@20000 { 63 L2: l2-cache-controller@20000 {
@@ -196,7 +195,6 @@
196 }; 195 };
197 196
198 pci2: pcie@ffe0a000 { 197 pci2: pcie@ffe0a000 {
199 cell-index = <2>;
200 compatible = "fsl,mpc8548-pcie"; 198 compatible = "fsl,mpc8548-pcie";
201 device_type = "pci"; 199 device_type = "pci";
202 #interrupt-cells = <1>; 200 #interrupt-cells = <1>;
diff --git a/arch/powerpc/boot/dts/mpc8610_hpcd.dts b/arch/powerpc/boot/dts/mpc8610_hpcd.dts
index 1bd3ebe11437..cfc2c60d1f5f 100644
--- a/arch/powerpc/boot/dts/mpc8610_hpcd.dts
+++ b/arch/powerpc/boot/dts/mpc8610_hpcd.dts
@@ -112,9 +112,21 @@
112 device_type = "soc"; 112 device_type = "soc";
113 compatible = "fsl,mpc8610-immr", "simple-bus"; 113 compatible = "fsl,mpc8610-immr", "simple-bus";
114 ranges = <0x0 0xe0000000 0x00100000>; 114 ranges = <0x0 0xe0000000 0x00100000>;
115 reg = <0xe0000000 0x1000>;
116 bus-frequency = <0>; 115 bus-frequency = <0>;
117 116
117 mcm-law@0 {
118 compatible = "fsl,mcm-law";
119 reg = <0x0 0x1000>;
120 fsl,num-laws = <10>;
121 };
122
123 mcm@1000 {
124 compatible = "fsl,mpc8610-mcm", "fsl,mcm";
125 reg = <0x1000 0x1000>;
126 interrupts = <17 2>;
127 interrupt-parent = <&mpic>;
128 };
129
118 i2c@3000 { 130 i2c@3000 {
119 #address-cells = <1>; 131 #address-cells = <1>;
120 #size-cells = <0>; 132 #size-cells = <0>;
@@ -316,7 +328,6 @@
316 }; 328 };
317 329
318 pci0: pci@e0008000 { 330 pci0: pci@e0008000 {
319 cell-index = <0>;
320 compatible = "fsl,mpc8610-pci"; 331 compatible = "fsl,mpc8610-pci";
321 device_type = "pci"; 332 device_type = "pci";
322 #interrupt-cells = <1>; 333 #interrupt-cells = <1>;
@@ -346,7 +357,6 @@
346 }; 357 };
347 358
348 pci1: pcie@e000a000 { 359 pci1: pcie@e000a000 {
349 cell-index = <1>;
350 compatible = "fsl,mpc8641-pcie"; 360 compatible = "fsl,mpc8641-pcie";
351 device_type = "pci"; 361 device_type = "pci";
352 #interrupt-cells = <1>; 362 #interrupt-cells = <1>;
diff --git a/arch/powerpc/boot/dts/mpc8641_hpcn.dts b/arch/powerpc/boot/dts/mpc8641_hpcn.dts
index d72beb192460..848320e4d3c4 100644
--- a/arch/powerpc/boot/dts/mpc8641_hpcn.dts
+++ b/arch/powerpc/boot/dts/mpc8641_hpcn.dts
@@ -114,9 +114,21 @@
114 device_type = "soc"; 114 device_type = "soc";
115 compatible = "simple-bus"; 115 compatible = "simple-bus";
116 ranges = <0x00000000 0xffe00000 0x00100000>; 116 ranges = <0x00000000 0xffe00000 0x00100000>;
117 reg = <0xffe00000 0x00001000>; // CCSRBAR
118 bus-frequency = <0>; 117 bus-frequency = <0>;
119 118
119 mcm-law@0 {
120 compatible = "fsl,mcm-law";
121 reg = <0x0 0x1000>;
122 fsl,num-laws = <10>;
123 };
124
125 mcm@1000 {
126 compatible = "fsl,mpc8641-mcm", "fsl,mcm";
127 reg = <0x1000 0x1000>;
128 interrupts = <17 2>;
129 interrupt-parent = <&mpic>;
130 };
131
120 i2c@3000 { 132 i2c@3000 {
121 #address-cells = <1>; 133 #address-cells = <1>;
122 #size-cells = <0>; 134 #size-cells = <0>;
@@ -357,7 +369,6 @@
357 }; 369 };
358 370
359 pci0: pcie@ffe08000 { 371 pci0: pcie@ffe08000 {
360 cell-index = <0>;
361 compatible = "fsl,mpc8641-pcie"; 372 compatible = "fsl,mpc8641-pcie";
362 device_type = "pci"; 373 device_type = "pci";
363 #interrupt-cells = <1>; 374 #interrupt-cells = <1>;
@@ -566,7 +577,6 @@
566 }; 577 };
567 578
568 pci1: pcie@ffe09000 { 579 pci1: pcie@ffe09000 {
569 cell-index = <1>;
570 compatible = "fsl,mpc8641-pcie"; 580 compatible = "fsl,mpc8641-pcie";
571 device_type = "pci"; 581 device_type = "pci";
572 #interrupt-cells = <1>; 582 #interrupt-cells = <1>;
diff --git a/arch/powerpc/boot/dts/mpc8641_hpcn_36b.dts b/arch/powerpc/boot/dts/mpc8641_hpcn_36b.dts
new file mode 100644
index 000000000000..8be8e701e1d3
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc8641_hpcn_36b.dts
@@ -0,0 +1,609 @@
1/*
2 * MPC8641 HPCN Device Tree Source
3 *
4 * Copyright 2008-2009 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/dts-v1/;
13
14/ {
15 model = "MPC8641HPCN";
16 compatible = "fsl,mpc8641hpcn";
17 #address-cells = <2>;
18 #size-cells = <2>;
19
20 aliases {
21 ethernet0 = &enet0;
22 ethernet1 = &enet1;
23 ethernet2 = &enet2;
24 ethernet3 = &enet3;
25 serial0 = &serial0;
26 serial1 = &serial1;
27 pci0 = &pci0;
28 pci1 = &pci1;
29 };
30
31 cpus {
32 #address-cells = <1>;
33 #size-cells = <0>;
34
35 PowerPC,8641@0 {
36 device_type = "cpu";
37 reg = <0>;
38 d-cache-line-size = <32>; // 32 bytes
39 i-cache-line-size = <32>; // 32 bytes
40 d-cache-size = <32768>; // L1, 32K
41 i-cache-size = <32768>; // L1, 32K
42 timebase-frequency = <0>; // 33 MHz, from uboot
43 bus-frequency = <0>; // From uboot
44 clock-frequency = <0>; // From uboot
45 };
46 PowerPC,8641@1 {
47 device_type = "cpu";
48 reg = <1>;
49 d-cache-line-size = <32>; // 32 bytes
50 i-cache-line-size = <32>; // 32 bytes
51 d-cache-size = <32768>; // L1, 32K
52 i-cache-size = <32768>; // L1, 32K
53 timebase-frequency = <0>; // 33 MHz, from uboot
54 bus-frequency = <0>; // From uboot
55 clock-frequency = <0>; // From uboot
56 };
57 };
58
59 memory {
60 device_type = "memory";
61 reg = <0x0 0x00000000 0x0 0x40000000>; // 1G at 0x0
62 };
63
64 localbus@fffe05000 {
65 #address-cells = <2>;
66 #size-cells = <1>;
67 compatible = "fsl,mpc8641-localbus", "simple-bus";
68 reg = <0x0f 0xffe05000 0x0 0x1000>;
69 interrupts = <19 2>;
70 interrupt-parent = <&mpic>;
71
72 ranges = <0 0 0xf 0xef800000 0x00800000
73 2 0 0xf 0xffdf8000 0x00008000
74 3 0 0xf 0xffdf0000 0x00008000>;
75
76 flash@0,0 {
77 compatible = "cfi-flash";
78 reg = <0 0 0x00800000>;
79 bank-width = <2>;
80 device-width = <2>;
81 #address-cells = <1>;
82 #size-cells = <1>;
83 partition@0 {
84 label = "kernel";
85 reg = <0x00000000 0x00300000>;
86 };
87 partition@300000 {
88 label = "firmware b";
89 reg = <0x00300000 0x00100000>;
90 read-only;
91 };
92 partition@400000 {
93 label = "fs";
94 reg = <0x00400000 0x00300000>;
95 };
96 partition@700000 {
97 label = "firmware a";
98 reg = <0x00700000 0x00100000>;
99 read-only;
100 };
101 };
102 };
103
104 soc8641@fffe00000 {
105 #address-cells = <1>;
106 #size-cells = <1>;
107 device_type = "soc";
108 compatible = "simple-bus";
109 ranges = <0x00000000 0x0f 0xffe00000 0x00100000>;
110 bus-frequency = <0>;
111
112 mcm-law@0 {
113 compatible = "fsl,mcm-law";
114 reg = <0x0 0x1000>;
115 fsl,num-laws = <10>;
116 };
117
118 mcm@1000 {
119 compatible = "fsl,mpc8641-mcm", "fsl,mcm";
120 reg = <0x1000 0x1000>;
121 interrupts = <17 2>;
122 interrupt-parent = <&mpic>;
123 };
124
125 i2c@3000 {
126 #address-cells = <1>;
127 #size-cells = <0>;
128 cell-index = <0>;
129 compatible = "fsl-i2c";
130 reg = <0x3000 0x100>;
131 interrupts = <43 2>;
132 interrupt-parent = <&mpic>;
133 dfsrr;
134 };
135
136 i2c@3100 {
137 #address-cells = <1>;
138 #size-cells = <0>;
139 cell-index = <1>;
140 compatible = "fsl-i2c";
141 reg = <0x3100 0x100>;
142 interrupts = <43 2>;
143 interrupt-parent = <&mpic>;
144 dfsrr;
145 };
146
147 dma@21300 {
148 #address-cells = <1>;
149 #size-cells = <1>;
150 compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma";
151 reg = <0x21300 0x4>;
152 ranges = <0x0 0x21100 0x200>;
153 cell-index = <0>;
154 dma-channel@0 {
155 compatible = "fsl,mpc8641-dma-channel",
156 "fsl,eloplus-dma-channel";
157 reg = <0x0 0x80>;
158 cell-index = <0>;
159 interrupt-parent = <&mpic>;
160 interrupts = <20 2>;
161 };
162 dma-channel@80 {
163 compatible = "fsl,mpc8641-dma-channel",
164 "fsl,eloplus-dma-channel";
165 reg = <0x80 0x80>;
166 cell-index = <1>;
167 interrupt-parent = <&mpic>;
168 interrupts = <21 2>;
169 };
170 dma-channel@100 {
171 compatible = "fsl,mpc8641-dma-channel",
172 "fsl,eloplus-dma-channel";
173 reg = <0x100 0x80>;
174 cell-index = <2>;
175 interrupt-parent = <&mpic>;
176 interrupts = <22 2>;
177 };
178 dma-channel@180 {
179 compatible = "fsl,mpc8641-dma-channel",
180 "fsl,eloplus-dma-channel";
181 reg = <0x180 0x80>;
182 cell-index = <3>;
183 interrupt-parent = <&mpic>;
184 interrupts = <23 2>;
185 };
186 };
187
188 enet0: ethernet@24000 {
189 #address-cells = <1>;
190 #size-cells = <1>;
191 cell-index = <0>;
192 device_type = "network";
193 model = "TSEC";
194 compatible = "gianfar";
195 reg = <0x24000 0x1000>;
196 ranges = <0x0 0x24000 0x1000>;
197 local-mac-address = [ 00 00 00 00 00 00 ];
198 interrupts = <29 2 30 2 34 2>;
199 interrupt-parent = <&mpic>;
200 tbi-handle = <&tbi0>;
201 phy-handle = <&phy0>;
202 phy-connection-type = "rgmii-id";
203
204 mdio@520 {
205 #address-cells = <1>;
206 #size-cells = <0>;
207 compatible = "fsl,gianfar-mdio";
208 reg = <0x520 0x20>;
209
210 phy0: ethernet-phy@0 {
211 interrupt-parent = <&mpic>;
212 interrupts = <10 1>;
213 reg = <0>;
214 device_type = "ethernet-phy";
215 };
216 phy1: ethernet-phy@1 {
217 interrupt-parent = <&mpic>;
218 interrupts = <10 1>;
219 reg = <1>;
220 device_type = "ethernet-phy";
221 };
222 phy2: ethernet-phy@2 {
223 interrupt-parent = <&mpic>;
224 interrupts = <10 1>;
225 reg = <2>;
226 device_type = "ethernet-phy";
227 };
228 phy3: ethernet-phy@3 {
229 interrupt-parent = <&mpic>;
230 interrupts = <10 1>;
231 reg = <3>;
232 device_type = "ethernet-phy";
233 };
234 tbi0: tbi-phy@11 {
235 reg = <0x11>;
236 device_type = "tbi-phy";
237 };
238 };
239 };
240
241 enet1: ethernet@25000 {
242 #address-cells = <1>;
243 #size-cells = <1>;
244 cell-index = <1>;
245 device_type = "network";
246 model = "TSEC";
247 compatible = "gianfar";
248 reg = <0x25000 0x1000>;
249 ranges = <0x0 0x25000 0x1000>;
250 local-mac-address = [ 00 00 00 00 00 00 ];
251 interrupts = <35 2 36 2 40 2>;
252 interrupt-parent = <&mpic>;
253 tbi-handle = <&tbi1>;
254 phy-handle = <&phy1>;
255 phy-connection-type = "rgmii-id";
256
257 mdio@520 {
258 #address-cells = <1>;
259 #size-cells = <0>;
260 compatible = "fsl,gianfar-tbi";
261 reg = <0x520 0x20>;
262
263 tbi1: tbi-phy@11 {
264 reg = <0x11>;
265 device_type = "tbi-phy";
266 };
267 };
268 };
269
270 enet2: ethernet@26000 {
271 #address-cells = <1>;
272 #size-cells = <1>;
273 cell-index = <2>;
274 device_type = "network";
275 model = "TSEC";
276 compatible = "gianfar";
277 reg = <0x26000 0x1000>;
278 ranges = <0x0 0x26000 0x1000>;
279 local-mac-address = [ 00 00 00 00 00 00 ];
280 interrupts = <31 2 32 2 33 2>;
281 interrupt-parent = <&mpic>;
282 tbi-handle = <&tbi2>;
283 phy-handle = <&phy2>;
284 phy-connection-type = "rgmii-id";
285
286 mdio@520 {
287 #address-cells = <1>;
288 #size-cells = <0>;
289 compatible = "fsl,gianfar-tbi";
290 reg = <0x520 0x20>;
291
292 tbi2: tbi-phy@11 {
293 reg = <0x11>;
294 device_type = "tbi-phy";
295 };
296 };
297 };
298
299 enet3: ethernet@27000 {
300 #address-cells = <1>;
301 #size-cells = <1>;
302 cell-index = <3>;
303 device_type = "network";
304 model = "TSEC";
305 compatible = "gianfar";
306 reg = <0x27000 0x1000>;
307 ranges = <0x0 0x27000 0x1000>;
308 local-mac-address = [ 00 00 00 00 00 00 ];
309 interrupts = <37 2 38 2 39 2>;
310 interrupt-parent = <&mpic>;
311 tbi-handle = <&tbi3>;
312 phy-handle = <&phy3>;
313 phy-connection-type = "rgmii-id";
314
315 mdio@520 {
316 #address-cells = <1>;
317 #size-cells = <0>;
318 compatible = "fsl,gianfar-tbi";
319 reg = <0x520 0x20>;
320
321 tbi3: tbi-phy@11 {
322 reg = <0x11>;
323 device_type = "tbi-phy";
324 };
325 };
326 };
327
328 serial0: serial@4500 {
329 cell-index = <0>;
330 device_type = "serial";
331 compatible = "ns16550";
332 reg = <0x4500 0x100>;
333 clock-frequency = <0>;
334 interrupts = <42 2>;
335 interrupt-parent = <&mpic>;
336 };
337
338 serial1: serial@4600 {
339 cell-index = <1>;
340 device_type = "serial";
341 compatible = "ns16550";
342 reg = <0x4600 0x100>;
343 clock-frequency = <0>;
344 interrupts = <28 2>;
345 interrupt-parent = <&mpic>;
346 };
347
348 mpic: pic@40000 {
349 interrupt-controller;
350 #address-cells = <0>;
351 #interrupt-cells = <2>;
352 reg = <0x40000 0x40000>;
353 compatible = "chrp,open-pic";
354 device_type = "open-pic";
355 };
356
357 global-utilities@e0000 {
358 compatible = "fsl,mpc8641-guts";
359 reg = <0xe0000 0x1000>;
360 fsl,has-rstcr;
361 };
362 };
363
364 pci0: pcie@fffe08000 {
365 cell-index = <0>;
366 compatible = "fsl,mpc8641-pcie";
367 device_type = "pci";
368 #interrupt-cells = <1>;
369 #size-cells = <2>;
370 #address-cells = <3>;
371 reg = <0x0f 0xffe08000 0x0 0x1000>;
372 bus-range = <0x0 0xff>;
373 ranges = <0x02000000 0x0 0xe0000000 0x0c 0x00000000 0x0 0x20000000
374 0x01000000 0x0 0x00000000 0x0f 0xffc00000 0x0 0x00010000>;
375 clock-frequency = <33333333>;
376 interrupt-parent = <&mpic>;
377 interrupts = <24 2>;
378 interrupt-map-mask = <0xff00 0 0 7>;
379 interrupt-map = <
380 /* IDSEL 0x11 func 0 - PCI slot 1 */
381 0x8800 0 0 1 &mpic 2 1
382 0x8800 0 0 2 &mpic 3 1
383 0x8800 0 0 3 &mpic 4 1
384 0x8800 0 0 4 &mpic 1 1
385
386 /* IDSEL 0x11 func 1 - PCI slot 1 */
387 0x8900 0 0 1 &mpic 2 1
388 0x8900 0 0 2 &mpic 3 1
389 0x8900 0 0 3 &mpic 4 1
390 0x8900 0 0 4 &mpic 1 1
391
392 /* IDSEL 0x11 func 2 - PCI slot 1 */
393 0x8a00 0 0 1 &mpic 2 1
394 0x8a00 0 0 2 &mpic 3 1
395 0x8a00 0 0 3 &mpic 4 1
396 0x8a00 0 0 4 &mpic 1 1
397
398 /* IDSEL 0x11 func 3 - PCI slot 1 */
399 0x8b00 0 0 1 &mpic 2 1
400 0x8b00 0 0 2 &mpic 3 1
401 0x8b00 0 0 3 &mpic 4 1
402 0x8b00 0 0 4 &mpic 1 1
403
404 /* IDSEL 0x11 func 4 - PCI slot 1 */
405 0x8c00 0 0 1 &mpic 2 1
406 0x8c00 0 0 2 &mpic 3 1
407 0x8c00 0 0 3 &mpic 4 1
408 0x8c00 0 0 4 &mpic 1 1
409
410 /* IDSEL 0x11 func 5 - PCI slot 1 */
411 0x8d00 0 0 1 &mpic 2 1
412 0x8d00 0 0 2 &mpic 3 1
413 0x8d00 0 0 3 &mpic 4 1
414 0x8d00 0 0 4 &mpic 1 1
415
416 /* IDSEL 0x11 func 6 - PCI slot 1 */
417 0x8e00 0 0 1 &mpic 2 1
418 0x8e00 0 0 2 &mpic 3 1
419 0x8e00 0 0 3 &mpic 4 1
420 0x8e00 0 0 4 &mpic 1 1
421
422 /* IDSEL 0x11 func 7 - PCI slot 1 */
423 0x8f00 0 0 1 &mpic 2 1
424 0x8f00 0 0 2 &mpic 3 1
425 0x8f00 0 0 3 &mpic 4 1
426 0x8f00 0 0 4 &mpic 1 1
427
428 /* IDSEL 0x12 func 0 - PCI slot 2 */
429 0x9000 0 0 1 &mpic 3 1
430 0x9000 0 0 2 &mpic 4 1
431 0x9000 0 0 3 &mpic 1 1
432 0x9000 0 0 4 &mpic 2 1
433
434 /* IDSEL 0x12 func 1 - PCI slot 2 */
435 0x9100 0 0 1 &mpic 3 1
436 0x9100 0 0 2 &mpic 4 1
437 0x9100 0 0 3 &mpic 1 1
438 0x9100 0 0 4 &mpic 2 1
439
440 /* IDSEL 0x12 func 2 - PCI slot 2 */
441 0x9200 0 0 1 &mpic 3 1
442 0x9200 0 0 2 &mpic 4 1
443 0x9200 0 0 3 &mpic 1 1
444 0x9200 0 0 4 &mpic 2 1
445
446 /* IDSEL 0x12 func 3 - PCI slot 2 */
447 0x9300 0 0 1 &mpic 3 1
448 0x9300 0 0 2 &mpic 4 1
449 0x9300 0 0 3 &mpic 1 1
450 0x9300 0 0 4 &mpic 2 1
451
452 /* IDSEL 0x12 func 4 - PCI slot 2 */
453 0x9400 0 0 1 &mpic 3 1
454 0x9400 0 0 2 &mpic 4 1
455 0x9400 0 0 3 &mpic 1 1
456 0x9400 0 0 4 &mpic 2 1
457
458 /* IDSEL 0x12 func 5 - PCI slot 2 */
459 0x9500 0 0 1 &mpic 3 1
460 0x9500 0 0 2 &mpic 4 1
461 0x9500 0 0 3 &mpic 1 1
462 0x9500 0 0 4 &mpic 2 1
463
464 /* IDSEL 0x12 func 6 - PCI slot 2 */
465 0x9600 0 0 1 &mpic 3 1
466 0x9600 0 0 2 &mpic 4 1
467 0x9600 0 0 3 &mpic 1 1
468 0x9600 0 0 4 &mpic 2 1
469
470 /* IDSEL 0x12 func 7 - PCI slot 2 */
471 0x9700 0 0 1 &mpic 3 1
472 0x9700 0 0 2 &mpic 4 1
473 0x9700 0 0 3 &mpic 1 1
474 0x9700 0 0 4 &mpic 2 1
475
476 // IDSEL 0x1c USB
477 0xe000 0 0 1 &i8259 12 2
478 0xe100 0 0 2 &i8259 9 2
479 0xe200 0 0 3 &i8259 10 2
480 0xe300 0 0 4 &i8259 11 2
481
482 // IDSEL 0x1d Audio
483 0xe800 0 0 1 &i8259 6 2
484
485 // IDSEL 0x1e Legacy
486 0xf000 0 0 1 &i8259 7 2
487 0xf100 0 0 1 &i8259 7 2
488
489 // IDSEL 0x1f IDE/SATA
490 0xf800 0 0 1 &i8259 14 2
491 0xf900 0 0 1 &i8259 5 2
492 >;
493
494 pcie@0 {
495 reg = <0 0 0 0 0>;
496 #size-cells = <2>;
497 #address-cells = <3>;
498 device_type = "pci";
499 ranges = <0x02000000 0x0 0xe0000000
500 0x02000000 0x0 0xe0000000
501 0x0 0x20000000
502
503 0x01000000 0x0 0x00000000
504 0x01000000 0x0 0x00000000
505 0x0 0x00010000>;
506 uli1575@0 {
507 reg = <0 0 0 0 0>;
508 #size-cells = <2>;
509 #address-cells = <3>;
510 ranges = <0x02000000 0x0 0xe0000000
511 0x02000000 0x0 0xe0000000
512 0x0 0x20000000
513 0x01000000 0x0 0x00000000
514 0x01000000 0x0 0x00000000
515 0x0 0x00010000>;
516 isa@1e {
517 device_type = "isa";
518 #interrupt-cells = <2>;
519 #size-cells = <1>;
520 #address-cells = <2>;
521 reg = <0xf000 0 0 0 0>;
522 ranges = <1 0 0x01000000 0 0
523 0x00001000>;
524 interrupt-parent = <&i8259>;
525
526 i8259: interrupt-controller@20 {
527 reg = <1 0x20 2
528 1 0xa0 2
529 1 0x4d0 2>;
530 interrupt-controller;
531 device_type = "interrupt-controller";
532 #address-cells = <0>;
533 #interrupt-cells = <2>;
534 compatible = "chrp,iic";
535 interrupts = <9 2>;
536 interrupt-parent = <&mpic>;
537 };
538
539 i8042@60 {
540 #size-cells = <0>;
541 #address-cells = <1>;
542 reg = <1 0x60 1 1 0x64 1>;
543 interrupts = <1 3 12 3>;
544 interrupt-parent =
545 <&i8259>;
546
547 keyboard@0 {
548 reg = <0>;
549 compatible = "pnpPNP,303";
550 };
551
552 mouse@1 {
553 reg = <1>;
554 compatible = "pnpPNP,f03";
555 };
556 };
557
558 rtc@70 {
559 compatible =
560 "pnpPNP,b00";
561 reg = <1 0x70 2>;
562 };
563
564 gpio@400 {
565 reg = <1 0x400 0x80>;
566 };
567 };
568 };
569 };
570
571 };
572
573 pci1: pcie@fffe09000 {
574 cell-index = <1>;
575 compatible = "fsl,mpc8641-pcie";
576 device_type = "pci";
577 #interrupt-cells = <1>;
578 #size-cells = <2>;
579 #address-cells = <3>;
580 reg = <0x0f 0xffe09000 0x0 0x1000>;
581 bus-range = <0x0 0xff>;
582 ranges = <0x02000000 0x0 0xe0000000 0x0c 0x20000000 0x0 0x20000000
583 0x01000000 0x0 0x00000000 0x0f 0xffc10000 0x0 0x00010000>;
584 clock-frequency = <33333333>;
585 interrupt-parent = <&mpic>;
586 interrupts = <25 2>;
587 interrupt-map-mask = <0xf800 0 0 7>;
588 interrupt-map = <
589 /* IDSEL 0x0 */
590 0x0000 0 0 1 &mpic 4 1
591 0x0000 0 0 2 &mpic 5 1
592 0x0000 0 0 3 &mpic 6 1
593 0x0000 0 0 4 &mpic 7 1
594 >;
595 pcie@0 {
596 reg = <0 0 0 0 0>;
597 #size-cells = <2>;
598 #address-cells = <3>;
599 device_type = "pci";
600 ranges = <0x02000000 0x0 0xe0000000
601 0x02000000 0x0 0xe0000000
602 0x0 0x20000000
603
604 0x01000000 0x0 0x00000000
605 0x01000000 0x0 0x00000000
606 0x0 0x00010000>;
607 };
608 };
609};
diff --git a/arch/powerpc/boot/dts/p2020ds.dts b/arch/powerpc/boot/dts/p2020ds.dts
new file mode 100644
index 000000000000..11019142813c
--- /dev/null
+++ b/arch/powerpc/boot/dts/p2020ds.dts
@@ -0,0 +1,704 @@
1/*
2 * P2020 DS Device Tree Source
3 *
4 * Copyright 2009 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/dts-v1/;
13/ {
14 model = "fsl,P2020";
15 compatible = "fsl,P2020DS";
16 #address-cells = <2>;
17 #size-cells = <2>;
18
19 aliases {
20 ethernet0 = &enet0;
21 ethernet1 = &enet1;
22 ethernet2 = &enet2;
23 serial0 = &serial0;
24 serial1 = &serial1;
25 pci0 = &pci0;
26 pci1 = &pci1;
27 pci2 = &pci2;
28 };
29
30 cpus {
31 #address-cells = <1>;
32 #size-cells = <0>;
33
34 PowerPC,P2020@0 {
35 device_type = "cpu";
36 reg = <0x0>;
37 next-level-cache = <&L2>;
38 };
39
40 PowerPC,P2020@1 {
41 device_type = "cpu";
42 reg = <0x1>;
43 next-level-cache = <&L2>;
44 };
45 };
46
47 memory {
48 device_type = "memory";
49 };
50
51 localbus@ffe05000 {
52 #address-cells = <2>;
53 #size-cells = <1>;
54 compatible = "fsl,elbc", "simple-bus";
55 reg = <0 0xffe05000 0 0x1000>;
56 interrupts = <19 2>;
57 interrupt-parent = <&mpic>;
58
59 ranges = <0x0 0x0 0x0 0xe8000000 0x08000000
60 0x1 0x0 0x0 0xe0000000 0x08000000
61 0x2 0x0 0x0 0xffa00000 0x00040000
62 0x3 0x0 0x0 0xffdf0000 0x00008000
63 0x4 0x0 0x0 0xffa40000 0x00040000
64 0x5 0x0 0x0 0xffa80000 0x00040000
65 0x6 0x0 0x0 0xffac0000 0x00040000>;
66
67 nor@0,0 {
68 #address-cells = <1>;
69 #size-cells = <1>;
70 compatible = "cfi-flash";
71 reg = <0x0 0x0 0x8000000>;
72 bank-width = <2>;
73 device-width = <1>;
74
75 ramdisk@0 {
76 reg = <0x0 0x03000000>;
77 read-only;
78 };
79
80 diagnostic@3000000 {
81 reg = <0x03000000 0x00e00000>;
82 read-only;
83 };
84
85 dink@3e00000 {
86 reg = <0x03e00000 0x00200000>;
87 read-only;
88 };
89
90 kernel@4000000 {
91 reg = <0x04000000 0x00400000>;
92 read-only;
93 };
94
95 jffs2@4400000 {
96 reg = <0x04400000 0x03b00000>;
97 };
98
99 dtb@7f00000 {
100 reg = <0x07f00000 0x00080000>;
101 read-only;
102 };
103
104 u-boot@7f80000 {
105 reg = <0x07f80000 0x00080000>;
106 read-only;
107 };
108 };
109
110 nand@2,0 {
111 #address-cells = <1>;
112 #size-cells = <1>;
113 compatible = "fsl,elbc-fcm-nand";
114 reg = <0x2 0x0 0x40000>;
115
116 u-boot@0 {
117 reg = <0x0 0x02000000>;
118 read-only;
119 };
120
121 jffs2@2000000 {
122 reg = <0x02000000 0x10000000>;
123 };
124
125 ramdisk@12000000 {
126 reg = <0x12000000 0x08000000>;
127 read-only;
128 };
129
130 kernel@1a000000 {
131 reg = <0x1a000000 0x04000000>;
132 };
133
134 dtb@1e000000 {
135 reg = <0x1e000000 0x01000000>;
136 read-only;
137 };
138
139 empty@1f000000 {
140 reg = <0x1f000000 0x21000000>;
141 };
142 };
143
144 nand@4,0 {
145 compatible = "fsl,elbc-fcm-nand";
146 reg = <0x4 0x0 0x40000>;
147 };
148
149 nand@5,0 {
150 compatible = "fsl,elbc-fcm-nand";
151 reg = <0x5 0x0 0x40000>;
152 };
153
154 nand@6,0 {
155 compatible = "fsl,elbc-fcm-nand";
156 reg = <0x6 0x0 0x40000>;
157 };
158 };
159
160 soc@ffe00000 {
161 #address-cells = <1>;
162 #size-cells = <1>;
163 device_type = "soc";
164 compatible = "fsl,p2020-immr", "simple-bus";
165 ranges = <0x0 0 0xffe00000 0x100000>;
166 bus-frequency = <0>; // Filled out by uboot.
167
168 ecm-law@0 {
169 compatible = "fsl,ecm-law";
170 reg = <0x0 0x1000>;
171 fsl,num-laws = <12>;
172 };
173
174 ecm@1000 {
175 compatible = "fsl,p2020-ecm", "fsl,ecm";
176 reg = <0x1000 0x1000>;
177 interrupts = <17 2>;
178 interrupt-parent = <&mpic>;
179 };
180
181 memory-controller@2000 {
182 compatible = "fsl,p2020-memory-controller";
183 reg = <0x2000 0x1000>;
184 interrupt-parent = <&mpic>;
185 interrupts = <18 2>;
186 };
187
188 i2c@3000 {
189 #address-cells = <1>;
190 #size-cells = <0>;
191 cell-index = <0>;
192 compatible = "fsl-i2c";
193 reg = <0x3000 0x100>;
194 interrupts = <43 2>;
195 interrupt-parent = <&mpic>;
196 dfsrr;
197 };
198
199 i2c@3100 {
200 #address-cells = <1>;
201 #size-cells = <0>;
202 cell-index = <1>;
203 compatible = "fsl-i2c";
204 reg = <0x3100 0x100>;
205 interrupts = <43 2>;
206 interrupt-parent = <&mpic>;
207 dfsrr;
208 };
209
210 serial0: serial@4500 {
211 cell-index = <0>;
212 device_type = "serial";
213 compatible = "ns16550";
214 reg = <0x4500 0x100>;
215 clock-frequency = <0>;
216 interrupts = <42 2>;
217 interrupt-parent = <&mpic>;
218 };
219
220 serial1: serial@4600 {
221 cell-index = <1>;
222 device_type = "serial";
223 compatible = "ns16550";
224 reg = <0x4600 0x100>;
225 clock-frequency = <0>;
226 interrupts = <42 2>;
227 interrupt-parent = <&mpic>;
228 };
229
230 spi@7000 {
231 compatible = "fsl,espi";
232 reg = <0x7000 0x1000>;
233 interrupts = <59 0x2>;
234 interrupt-parent = <&mpic>;
235 };
236
237 dma@c300 {
238 #address-cells = <1>;
239 #size-cells = <1>;
240 compatible = "fsl,eloplus-dma";
241 reg = <0xc300 0x4>;
242 ranges = <0x0 0xc100 0x200>;
243 cell-index = <1>;
244 dma-channel@0 {
245 compatible = "fsl,eloplus-dma-channel";
246 reg = <0x0 0x80>;
247 cell-index = <0>;
248 interrupt-parent = <&mpic>;
249 interrupts = <76 2>;
250 };
251 dma-channel@80 {
252 compatible = "fsl,eloplus-dma-channel";
253 reg = <0x80 0x80>;
254 cell-index = <1>;
255 interrupt-parent = <&mpic>;
256 interrupts = <77 2>;
257 };
258 dma-channel@100 {
259 compatible = "fsl,eloplus-dma-channel";
260 reg = <0x100 0x80>;
261 cell-index = <2>;
262 interrupt-parent = <&mpic>;
263 interrupts = <78 2>;
264 };
265 dma-channel@180 {
266 compatible = "fsl,eloplus-dma-channel";
267 reg = <0x180 0x80>;
268 cell-index = <3>;
269 interrupt-parent = <&mpic>;
270 interrupts = <79 2>;
271 };
272 };
273
274 gpio: gpio-controller@f000 {
275 #gpio-cells = <2>;
276 compatible = "fsl,mpc8572-gpio";
277 reg = <0xf000 0x100>;
278 interrupts = <47 0x2>;
279 interrupt-parent = <&mpic>;
280 gpio-controller;
281 };
282
283 L2: l2-cache-controller@20000 {
284 compatible = "fsl,p2020-l2-cache-controller";
285 reg = <0x20000 0x1000>;
286 cache-line-size = <32>; // 32 bytes
287 cache-size = <0x80000>; // L2, 512k
288 interrupt-parent = <&mpic>;
289 interrupts = <16 2>;
290 };
291
292 dma@21300 {
293 #address-cells = <1>;
294 #size-cells = <1>;
295 compatible = "fsl,eloplus-dma";
296 reg = <0x21300 0x4>;
297 ranges = <0x0 0x21100 0x200>;
298 cell-index = <0>;
299 dma-channel@0 {
300 compatible = "fsl,eloplus-dma-channel";
301 reg = <0x0 0x80>;
302 cell-index = <0>;
303 interrupt-parent = <&mpic>;
304 interrupts = <20 2>;
305 };
306 dma-channel@80 {
307 compatible = "fsl,eloplus-dma-channel";
308 reg = <0x80 0x80>;
309 cell-index = <1>;
310 interrupt-parent = <&mpic>;
311 interrupts = <21 2>;
312 };
313 dma-channel@100 {
314 compatible = "fsl,eloplus-dma-channel";
315 reg = <0x100 0x80>;
316 cell-index = <2>;
317 interrupt-parent = <&mpic>;
318 interrupts = <22 2>;
319 };
320 dma-channel@180 {
321 compatible = "fsl,eloplus-dma-channel";
322 reg = <0x180 0x80>;
323 cell-index = <3>;
324 interrupt-parent = <&mpic>;
325 interrupts = <23 2>;
326 };
327 };
328
329 usb@22000 {
330 #address-cells = <1>;
331 #size-cells = <0>;
332 compatible = "fsl-usb2-dr";
333 reg = <0x22000 0x1000>;
334 interrupt-parent = <&mpic>;
335 interrupts = <28 0x2>;
336 phy_type = "ulpi";
337 };
338
339 enet0: ethernet@24000 {
340 #address-cells = <1>;
341 #size-cells = <1>;
342 cell-index = <0>;
343 device_type = "network";
344 model = "eTSEC";
345 compatible = "gianfar";
346 reg = <0x24000 0x1000>;
347 ranges = <0x0 0x24000 0x1000>;
348 local-mac-address = [ 00 00 00 00 00 00 ];
349 interrupts = <29 2 30 2 34 2>;
350 interrupt-parent = <&mpic>;
351 tbi-handle = <&tbi0>;
352 phy-handle = <&phy0>;
353 phy-connection-type = "rgmii-id";
354
355 mdio@520 {
356 #address-cells = <1>;
357 #size-cells = <0>;
358 compatible = "fsl,gianfar-mdio";
359 reg = <0x520 0x20>;
360
361 phy0: ethernet-phy@0 {
362 interrupt-parent = <&mpic>;
363 interrupts = <3 1>;
364 reg = <0x0>;
365 };
366 phy1: ethernet-phy@1 {
367 interrupt-parent = <&mpic>;
368 interrupts = <3 1>;
369 reg = <0x1>;
370 };
371 phy2: ethernet-phy@2 {
372 interrupt-parent = <&mpic>;
373 interrupts = <3 1>;
374 reg = <0x2>;
375 };
376 tbi0: tbi-phy@11 {
377 reg = <0x11>;
378 device_type = "tbi-phy";
379 };
380 };
381 };
382
383 enet1: ethernet@25000 {
384 #address-cells = <1>;
385 #size-cells = <1>;
386 cell-index = <1>;
387 device_type = "network";
388 model = "eTSEC";
389 compatible = "gianfar";
390 reg = <0x25000 0x1000>;
391 ranges = <0x0 0x25000 0x1000>;
392 local-mac-address = [ 00 00 00 00 00 00 ];
393 interrupts = <35 2 36 2 40 2>;
394 interrupt-parent = <&mpic>;
395 tbi-handle = <&tbi1>;
396 phy-handle = <&phy1>;
397 phy-connection-type = "rgmii-id";
398
399 mdio@520 {
400 #address-cells = <1>;
401 #size-cells = <0>;
402 compatible = "fsl,gianfar-tbi";
403 reg = <0x520 0x20>;
404
405 tbi1: tbi-phy@11 {
406 reg = <0x11>;
407 device_type = "tbi-phy";
408 };
409 };
410 };
411
412 enet2: ethernet@26000 {
413 #address-cells = <1>;
414 #size-cells = <1>;
415 cell-index = <2>;
416 device_type = "network";
417 model = "eTSEC";
418 compatible = "gianfar";
419 reg = <0x26000 0x1000>;
420 ranges = <0x0 0x26000 0x1000>;
421 local-mac-address = [ 00 00 00 00 00 00 ];
422 interrupts = <31 2 32 2 33 2>;
423 interrupt-parent = <&mpic>;
424 tbi-handle = <&tbi2>;
425 phy-handle = <&phy2>;
426 phy-connection-type = "rgmii-id";
427
428 mdio@520 {
429 #address-cells = <1>;
430 #size-cells = <0>;
431 compatible = "fsl,gianfar-tbi";
432 reg = <0x520 0x20>;
433
434 tbi2: tbi-phy@11 {
435 reg = <0x11>;
436 device_type = "tbi-phy";
437 };
438 };
439 };
440
441 sdhci@2e000 {
442 compatible = "fsl,p2020-esdhc", "fsl,esdhc";
443 reg = <0x2e000 0x1000>;
444 interrupts = <72 0x2>;
445 interrupt-parent = <&mpic>;
446 /* Filled in by U-Boot */
447 clock-frequency = <0>;
448 };
449
450 crypto@30000 {
451 compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
452 "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
453 reg = <0x30000 0x10000>;
454 interrupts = <45 2 58 2>;
455 interrupt-parent = <&mpic>;
456 fsl,num-channels = <4>;
457 fsl,channel-fifo-len = <24>;
458 fsl,exec-units-mask = <0xbfe>;
459 fsl,descriptor-types-mask = <0x3ab0ebf>;
460 };
461
462 mpic: pic@40000 {
463 interrupt-controller;
464 #address-cells = <0>;
465 #interrupt-cells = <2>;
466 reg = <0x40000 0x40000>;
467 compatible = "chrp,open-pic";
468 device_type = "open-pic";
469 };
470
471 msi@41600 {
472 compatible = "fsl,mpic-msi";
473 reg = <0x41600 0x80>;
474 msi-available-ranges = <0 0x100>;
475 interrupts = <
476 0xe0 0
477 0xe1 0
478 0xe2 0
479 0xe3 0
480 0xe4 0
481 0xe5 0
482 0xe6 0
483 0xe7 0>;
484 interrupt-parent = <&mpic>;
485 };
486
487 global-utilities@e0000 { //global utilities block
488 compatible = "fsl,p2020-guts";
489 reg = <0xe0000 0x1000>;
490 fsl,has-rstcr;
491 };
492 };
493
494 pci0: pcie@ffe08000 {
495 compatible = "fsl,mpc8548-pcie";
496 device_type = "pci";
497 #interrupt-cells = <1>;
498 #size-cells = <2>;
499 #address-cells = <3>;
500 reg = <0 0xffe08000 0 0x1000>;
501 bus-range = <0 255>;
502 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
503 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
504 clock-frequency = <33333333>;
505 interrupt-parent = <&mpic>;
506 interrupts = <24 2>;
507 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
508 interrupt-map = <
509 /* IDSEL 0x0 */
510 0000 0x0 0x0 0x1 &mpic 0x8 0x1
511 0000 0x0 0x0 0x2 &mpic 0x9 0x1
512 0000 0x0 0x0 0x3 &mpic 0xa 0x1
513 0000 0x0 0x0 0x4 &mpic 0xb 0x1
514 >;
515 pcie@0 {
516 reg = <0x0 0x0 0x0 0x0 0x0>;
517 #size-cells = <2>;
518 #address-cells = <3>;
519 device_type = "pci";
520 ranges = <0x2000000 0x0 0x80000000
521 0x2000000 0x0 0x80000000
522 0x0 0x20000000
523
524 0x1000000 0x0 0x0
525 0x1000000 0x0 0x0
526 0x0 0x10000>;
527 };
528 };
529
530 pci1: pcie@ffe09000 {
531 compatible = "fsl,mpc8548-pcie";
532 device_type = "pci";
533 #interrupt-cells = <1>;
534 #size-cells = <2>;
535 #address-cells = <3>;
536 reg = <0 0xffe09000 0 0x1000>;
537 bus-range = <0 255>;
538 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
539 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
540 clock-frequency = <33333333>;
541 interrupt-parent = <&mpic>;
542 interrupts = <25 2>;
543 interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
544 interrupt-map = <
545
546 // IDSEL 0x11 func 0 - PCI slot 1
547 0x8800 0x0 0x0 0x1 &i8259 0x9 0x2
548 0x8800 0x0 0x0 0x2 &i8259 0xa 0x2
549
550 // IDSEL 0x11 func 1 - PCI slot 1
551 0x8900 0x0 0x0 0x1 &i8259 0x9 0x2
552 0x8900 0x0 0x0 0x2 &i8259 0xa 0x2
553
554 // IDSEL 0x11 func 2 - PCI slot 1
555 0x8a00 0x0 0x0 0x1 &i8259 0x9 0x2
556 0x8a00 0x0 0x0 0x2 &i8259 0xa 0x2
557
558 // IDSEL 0x11 func 3 - PCI slot 1
559 0x8b00 0x0 0x0 0x1 &i8259 0x9 0x2
560 0x8b00 0x0 0x0 0x2 &i8259 0xa 0x2
561
562 // IDSEL 0x11 func 4 - PCI slot 1
563 0x8c00 0x0 0x0 0x1 &i8259 0x9 0x2
564 0x8c00 0x0 0x0 0x2 &i8259 0xa 0x2
565
566 // IDSEL 0x11 func 5 - PCI slot 1
567 0x8d00 0x0 0x0 0x1 &i8259 0x9 0x2
568 0x8d00 0x0 0x0 0x2 &i8259 0xa 0x2
569
570 // IDSEL 0x11 func 6 - PCI slot 1
571 0x8e00 0x0 0x0 0x1 &i8259 0x9 0x2
572 0x8e00 0x0 0x0 0x2 &i8259 0xa 0x2
573
574 // IDSEL 0x11 func 7 - PCI slot 1
575 0x8f00 0x0 0x0 0x1 &i8259 0x9 0x2
576 0x8f00 0x0 0x0 0x2 &i8259 0xa 0x2
577
578 // IDSEL 0x1d Audio
579 0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
580
581 // IDSEL 0x1e Legacy
582 0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
583 0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
584
585 // IDSEL 0x1f IDE/SATA
586 0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
587 0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
588 >;
589
590 pcie@0 {
591 reg = <0x0 0x0 0x0 0x0 0x0>;
592 #size-cells = <2>;
593 #address-cells = <3>;
594 device_type = "pci";
595 ranges = <0x2000000 0x0 0xa0000000
596 0x2000000 0x0 0xa0000000
597 0x0 0x20000000
598
599 0x1000000 0x0 0x0
600 0x1000000 0x0 0x0
601 0x0 0x10000>;
602 uli1575@0 {
603 reg = <0x0 0x0 0x0 0x0 0x0>;
604 #size-cells = <2>;
605 #address-cells = <3>;
606 ranges = <0x2000000 0x0 0xa0000000
607 0x2000000 0x0 0xa0000000
608 0x0 0x20000000
609
610 0x1000000 0x0 0x0
611 0x1000000 0x0 0x0
612 0x0 0x10000>;
613 isa@1e {
614 device_type = "isa";
615 #interrupt-cells = <2>;
616 #size-cells = <1>;
617 #address-cells = <2>;
618 reg = <0xf000 0x0 0x0 0x0 0x0>;
619 ranges = <0x1 0x0 0x1000000 0x0 0x0
620 0x1000>;
621 interrupt-parent = <&i8259>;
622
623 i8259: interrupt-controller@20 {
624 reg = <0x1 0x20 0x2
625 0x1 0xa0 0x2
626 0x1 0x4d0 0x2>;
627 interrupt-controller;
628 device_type = "interrupt-controller";
629 #address-cells = <0>;
630 #interrupt-cells = <2>;
631 compatible = "chrp,iic";
632 interrupts = <4 1>;
633 interrupt-parent = <&mpic>;
634 };
635
636 i8042@60 {
637 #size-cells = <0>;
638 #address-cells = <1>;
639 reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
640 interrupts = <1 3 12 3>;
641 interrupt-parent =
642 <&i8259>;
643
644 keyboard@0 {
645 reg = <0x0>;
646 compatible = "pnpPNP,303";
647 };
648
649 mouse@1 {
650 reg = <0x1>;
651 compatible = "pnpPNP,f03";
652 };
653 };
654
655 rtc@70 {
656 compatible = "pnpPNP,b00";
657 reg = <0x1 0x70 0x2>;
658 };
659
660 gpio@400 {
661 reg = <0x1 0x400 0x80>;
662 };
663 };
664 };
665 };
666
667 };
668
669 pci2: pcie@ffe0a000 {
670 compatible = "fsl,mpc8548-pcie";
671 device_type = "pci";
672 #interrupt-cells = <1>;
673 #size-cells = <2>;
674 #address-cells = <3>;
675 reg = <0 0xffe0a000 0 0x1000>;
676 bus-range = <0 255>;
677 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
678 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
679 clock-frequency = <33333333>;
680 interrupt-parent = <&mpic>;
681 interrupts = <26 2>;
682 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
683 interrupt-map = <
684 /* IDSEL 0x0 */
685 0000 0x0 0x0 0x1 &mpic 0x0 0x1
686 0000 0x0 0x0 0x2 &mpic 0x1 0x1
687 0000 0x0 0x0 0x3 &mpic 0x2 0x1
688 0000 0x0 0x0 0x4 &mpic 0x3 0x1
689 >;
690 pcie@0 {
691 reg = <0x0 0x0 0x0 0x0 0x0>;
692 #size-cells = <2>;
693 #address-cells = <3>;
694 device_type = "pci";
695 ranges = <0x2000000 0x0 0xc0000000
696 0x2000000 0x0 0xc0000000
697 0x0 0x20000000
698
699 0x1000000 0x0 0x0
700 0x1000000 0x0 0x0
701 0x0 0x10000>;
702 };
703 };
704};
diff --git a/arch/powerpc/boot/dts/sbc8349.dts b/arch/powerpc/boot/dts/sbc8349.dts
index a36dbbc48694..5fb6f6684b0e 100644
--- a/arch/powerpc/boot/dts/sbc8349.dts
+++ b/arch/powerpc/boot/dts/sbc8349.dts
@@ -278,7 +278,6 @@
278 }; 278 };
279 279
280 pci0: pci@e0008500 { 280 pci0: pci@e0008500 {
281 cell-index = <1>;
282 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 281 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
283 interrupt-map = < 282 interrupt-map = <
284 283
diff --git a/arch/powerpc/boot/dts/sbc8548.dts b/arch/powerpc/boot/dts/sbc8548.dts
index b1f1416ac998..9eefe00ed253 100644
--- a/arch/powerpc/boot/dts/sbc8548.dts
+++ b/arch/powerpc/boot/dts/sbc8548.dts
@@ -151,10 +151,22 @@
151 #size-cells = <1>; 151 #size-cells = <1>;
152 device_type = "soc"; 152 device_type = "soc";
153 ranges = <0x00000000 0xe0000000 0x00100000>; 153 ranges = <0x00000000 0xe0000000 0x00100000>;
154 reg = <0xe0000000 0x00001000>; // CCSRBAR
155 bus-frequency = <0>; 154 bus-frequency = <0>;
156 compatible = "simple-bus"; 155 compatible = "simple-bus";
157 156
157 ecm-law@0 {
158 compatible = "fsl,ecm-law";
159 reg = <0x0 0x1000>;
160 fsl,num-laws = <10>;
161 };
162
163 ecm@1000 {
164 compatible = "fsl,mpc8548-ecm", "fsl,ecm";
165 reg = <0x1000 0x1000>;
166 interrupts = <17 2>;
167 interrupt-parent = <&mpic>;
168 };
169
158 memory-controller@2000 { 170 memory-controller@2000 {
159 compatible = "fsl,mpc8548-memory-controller"; 171 compatible = "fsl,mpc8548-memory-controller";
160 reg = <0x2000 0x1000>; 172 reg = <0x2000 0x1000>;
@@ -350,7 +362,6 @@
350 }; 362 };
351 363
352 pci0: pci@e0008000 { 364 pci0: pci@e0008000 {
353 cell-index = <0>;
354 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 365 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
355 interrupt-map = < 366 interrupt-map = <
356 /* IDSEL 0x01 (PCI-X slot) @66MHz */ 367 /* IDSEL 0x01 (PCI-X slot) @66MHz */
@@ -380,7 +391,6 @@
380 }; 391 };
381 392
382 pci2: pcie@e000a000 { 393 pci2: pcie@e000a000 {
383 cell-index = <2>;
384 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 394 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
385 interrupt-map = < 395 interrupt-map = <
386 396
diff --git a/arch/powerpc/boot/dts/sbc8560.dts b/arch/powerpc/boot/dts/sbc8560.dts
index c4564b81e473..239d57a55cf4 100644
--- a/arch/powerpc/boot/dts/sbc8560.dts
+++ b/arch/powerpc/boot/dts/sbc8560.dts
@@ -57,9 +57,21 @@
57 #size-cells = <1>; 57 #size-cells = <1>;
58 device_type = "soc"; 58 device_type = "soc";
59 ranges = <0x0 0xff700000 0x00100000>; 59 ranges = <0x0 0xff700000 0x00100000>;
60 reg = <0xff700000 0x00100000>;
61 clock-frequency = <0>; 60 clock-frequency = <0>;
62 61
62 ecm-law@0 {
63 compatible = "fsl,ecm-law";
64 reg = <0x0 0x1000>;
65 fsl,num-laws = <8>;
66 };
67
68 ecm@1000 {
69 compatible = "fsl,mpc8560-ecm", "fsl,ecm";
70 reg = <0x1000 0x1000>;
71 interrupts = <17 2>;
72 interrupt-parent = <&mpic>;
73 };
74
63 memory-controller@2000 { 75 memory-controller@2000 {
64 compatible = "fsl,mpc8560-memory-controller"; 76 compatible = "fsl,mpc8560-memory-controller";
65 reg = <0x2000 0x1000>; 77 reg = <0x2000 0x1000>;
@@ -296,7 +308,6 @@
296 }; 308 };
297 309
298 pci0: pci@ff708000 { 310 pci0: pci@ff708000 {
299 cell-index = <0>;
300 #interrupt-cells = <1>; 311 #interrupt-cells = <1>;
301 #size-cells = <2>; 312 #size-cells = <2>;
302 #address-cells = <3>; 313 #address-cells = <3>;
diff --git a/arch/powerpc/boot/dts/sbc8641d.dts b/arch/powerpc/boot/dts/sbc8641d.dts
index e3e914e78caa..ee5538feb455 100644
--- a/arch/powerpc/boot/dts/sbc8641d.dts
+++ b/arch/powerpc/boot/dts/sbc8641d.dts
@@ -126,9 +126,21 @@
126 device_type = "soc"; 126 device_type = "soc";
127 compatible = "simple-bus"; 127 compatible = "simple-bus";
128 ranges = <0x00000000 0xf8000000 0x00100000>; 128 ranges = <0x00000000 0xf8000000 0x00100000>;
129 reg = <0xf8000000 0x00001000>; // CCSRBAR
130 bus-frequency = <0>; 129 bus-frequency = <0>;
131 130
131 mcm-law@0 {
132 compatible = "fsl,mcm-law";
133 reg = <0x0 0x1000>;
134 fsl,num-laws = <10>;
135 };
136
137 mcm@1000 {
138 compatible = "fsl,mpc8641-mcm", "fsl,mcm";
139 reg = <0x1000 0x1000>;
140 interrupts = <17 2>;
141 interrupt-parent = <&mpic>;
142 };
143
132 i2c@3000 { 144 i2c@3000 {
133 #address-cells = <1>; 145 #address-cells = <1>;
134 #size-cells = <0>; 146 #size-cells = <0>;
@@ -371,7 +383,6 @@
371 }; 383 };
372 384
373 pci0: pcie@f8008000 { 385 pci0: pcie@f8008000 {
374 cell-index = <0>;
375 compatible = "fsl,mpc8641-pcie"; 386 compatible = "fsl,mpc8641-pcie";
376 device_type = "pci"; 387 device_type = "pci";
377 #interrupt-cells = <1>; 388 #interrupt-cells = <1>;
@@ -410,7 +421,6 @@
410 }; 421 };
411 422
412 pci1: pcie@f8009000 { 423 pci1: pcie@f8009000 {
413 cell-index = <1>;
414 compatible = "fsl,mpc8641-pcie"; 424 compatible = "fsl,mpc8641-pcie";
415 device_type = "pci"; 425 device_type = "pci";
416 #interrupt-cells = <1>; 426 #interrupt-cells = <1>;
diff --git a/arch/powerpc/boot/dts/sequoia.dts b/arch/powerpc/boot/dts/sequoia.dts
index 43cc68bd3192..739dd0da2416 100644
--- a/arch/powerpc/boot/dts/sequoia.dts
+++ b/arch/powerpc/boot/dts/sequoia.dts
@@ -199,6 +199,28 @@
199 }; 199 };
200 }; 200 };
201 201
202 ndfc@3,0 {
203 compatible = "ibm,ndfc";
204 reg = <0x00000003 0x00000000 0x00002000>;
205 ccr = <0x00001000>;
206 bank-settings = <0x80002222>;
207 #address-cells = <1>;
208 #size-cells = <1>;
209
210 nand {
211 #address-cells = <1>;
212 #size-cells = <1>;
213
214 partition@0 {
215 label = "u-boot";
216 reg = <0x00000000 0x00084000>;
217 };
218 partition@84000 {
219 label = "user";
220 reg = <0x00000000 0x01f7c000>;
221 };
222 };
223 };
202 }; 224 };
203 225
204 UART0: serial@ef600300 { 226 UART0: serial@ef600300 {
diff --git a/arch/powerpc/boot/dts/socrates.dts b/arch/powerpc/boot/dts/socrates.dts
index 7a6ae75a1e57..feb4ef6bd144 100644
--- a/arch/powerpc/boot/dts/socrates.dts
+++ b/arch/powerpc/boot/dts/socrates.dts
@@ -55,10 +55,22 @@
55 device_type = "soc"; 55 device_type = "soc";
56 56
57 ranges = <0x00000000 0xe0000000 0x00100000>; 57 ranges = <0x00000000 0xe0000000 0x00100000>;
58 reg = <0xe0000000 0x00001000>; // CCSRBAR 1M
59 bus-frequency = <0>; // Filled in by U-Boot 58 bus-frequency = <0>; // Filled in by U-Boot
60 compatible = "fsl,mpc8544-immr", "simple-bus"; 59 compatible = "fsl,mpc8544-immr", "simple-bus";
61 60
61 ecm-law@0 {
62 compatible = "fsl,ecm-law";
63 reg = <0x0 0x1000>;
64 fsl,num-laws = <10>;
65 };
66
67 ecm@1000 {
68 compatible = "fsl,mpc8544-ecm", "fsl,ecm";
69 reg = <0x1000 0x1000>;
70 interrupts = <17 2>;
71 interrupt-parent = <&mpic>;
72 };
73
62 memory-controller@2000 { 74 memory-controller@2000 {
63 compatible = "fsl,mpc8544-memory-controller"; 75 compatible = "fsl,mpc8544-memory-controller";
64 reg = <0x2000 0x1000>; 76 reg = <0x2000 0x1000>;
@@ -314,7 +326,6 @@
314 }; 326 };
315 327
316 pci0: pci@e0008000 { 328 pci0: pci@e0008000 {
317 cell-index = <0>;
318 #interrupt-cells = <1>; 329 #interrupt-cells = <1>;
319 #size-cells = <2>; 330 #size-cells = <2>;
320 #address-cells = <3>; 331 #address-cells = <3>;
diff --git a/arch/powerpc/boot/dts/stx_gp3_8560.dts b/arch/powerpc/boot/dts/stx_gp3_8560.dts
index ea6b15152de3..b670d03fbcd9 100644
--- a/arch/powerpc/boot/dts/stx_gp3_8560.dts
+++ b/arch/powerpc/boot/dts/stx_gp3_8560.dts
@@ -52,10 +52,22 @@
52 #size-cells = <1>; 52 #size-cells = <1>;
53 device_type = "soc"; 53 device_type = "soc";
54 ranges = <0 0xfdf00000 0x100000>; 54 ranges = <0 0xfdf00000 0x100000>;
55 reg = <0xfdf00000 0x1000>;
56 bus-frequency = <0>; 55 bus-frequency = <0>;
57 compatible = "fsl,mpc8560-immr", "simple-bus"; 56 compatible = "fsl,mpc8560-immr", "simple-bus";
58 57
58 ecm-law@0 {
59 compatible = "fsl,ecm-law";
60 reg = <0x0 0x1000>;
61 fsl,num-laws = <8>;
62 };
63
64 ecm@1000 {
65 compatible = "fsl,mpc8560-ecm", "fsl,ecm";
66 reg = <0x1000 0x1000>;
67 interrupts = <17 2>;
68 interrupt-parent = <&mpic>;
69 };
70
59 memory-controller@2000 { 71 memory-controller@2000 {
60 compatible = "fsl,mpc8540-memory-controller"; 72 compatible = "fsl,mpc8540-memory-controller";
61 reg = <0x2000 0x1000>; 73 reg = <0x2000 0x1000>;
@@ -251,7 +263,6 @@
251 }; 263 };
252 264
253 pci0: pci@fdf08000 { 265 pci0: pci@fdf08000 {
254 cell-index = <0>;
255 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 266 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
256 interrupt-map = < 267 interrupt-map = <
257 268
diff --git a/arch/powerpc/boot/dts/tqm8540.dts b/arch/powerpc/boot/dts/tqm8540.dts
index b6f1fc6eb960..71347537b83e 100644
--- a/arch/powerpc/boot/dts/tqm8540.dts
+++ b/arch/powerpc/boot/dts/tqm8540.dts
@@ -54,10 +54,22 @@
54 #size-cells = <1>; 54 #size-cells = <1>;
55 device_type = "soc"; 55 device_type = "soc";
56 ranges = <0x0 0xe0000000 0x100000>; 56 ranges = <0x0 0xe0000000 0x100000>;
57 reg = <0xe0000000 0x200>;
58 bus-frequency = <0>; 57 bus-frequency = <0>;
59 compatible = "fsl,mpc8540-immr", "simple-bus"; 58 compatible = "fsl,mpc8540-immr", "simple-bus";
60 59
60 ecm-law@0 {
61 compatible = "fsl,ecm-law";
62 reg = <0x0 0x1000>;
63 fsl,num-laws = <8>;
64 };
65
66 ecm@1000 {
67 compatible = "fsl,mpc8540-ecm", "fsl,ecm";
68 reg = <0x1000 0x1000>;
69 interrupts = <17 2>;
70 interrupt-parent = <&mpic>;
71 };
72
61 memory-controller@2000 { 73 memory-controller@2000 {
62 compatible = "fsl,mpc8540-memory-controller"; 74 compatible = "fsl,mpc8540-memory-controller";
63 reg = <0x2000 0x1000>; 75 reg = <0x2000 0x1000>;
@@ -266,7 +278,6 @@
266 }; 278 };
267 279
268 pci0: pci@e0008000 { 280 pci0: pci@e0008000 {
269 cell-index = <0>;
270 #interrupt-cells = <1>; 281 #interrupt-cells = <1>;
271 #size-cells = <2>; 282 #size-cells = <2>;
272 #address-cells = <3>; 283 #address-cells = <3>;
diff --git a/arch/powerpc/boot/dts/tqm8541.dts b/arch/powerpc/boot/dts/tqm8541.dts
index fa6a3d54a8a5..b30f63753d41 100644
--- a/arch/powerpc/boot/dts/tqm8541.dts
+++ b/arch/powerpc/boot/dts/tqm8541.dts
@@ -53,10 +53,22 @@
53 #size-cells = <1>; 53 #size-cells = <1>;
54 device_type = "soc"; 54 device_type = "soc";
55 ranges = <0x0 0xe0000000 0x100000>; 55 ranges = <0x0 0xe0000000 0x100000>;
56 reg = <0xe0000000 0x200>;
57 bus-frequency = <0>; 56 bus-frequency = <0>;
58 compatible = "fsl,mpc8541-immr", "simple-bus"; 57 compatible = "fsl,mpc8541-immr", "simple-bus";
59 58
59 ecm-law@0 {
60 compatible = "fsl,ecm-law";
61 reg = <0x0 0x1000>;
62 fsl,num-laws = <8>;
63 };
64
65 ecm@1000 {
66 compatible = "fsl,mpc8541-ecm", "fsl,ecm";
67 reg = <0x1000 0x1000>;
68 interrupts = <17 2>;
69 interrupt-parent = <&mpic>;
70 };
71
60 memory-controller@2000 { 72 memory-controller@2000 {
61 compatible = "fsl,mpc8540-memory-controller"; 73 compatible = "fsl,mpc8540-memory-controller";
62 reg = <0x2000 0x1000>; 74 reg = <0x2000 0x1000>;
@@ -288,7 +300,6 @@
288 }; 300 };
289 301
290 pci0: pci@e0008000 { 302 pci0: pci@e0008000 {
291 cell-index = <0>;
292 #interrupt-cells = <1>; 303 #interrupt-cells = <1>;
293 #size-cells = <2>; 304 #size-cells = <2>;
294 #address-cells = <3>; 305 #address-cells = <3>;
diff --git a/arch/powerpc/boot/dts/tqm8548-bigflash.dts b/arch/powerpc/boot/dts/tqm8548-bigflash.dts
index 00f7ed7a2455..61f25e15fd66 100644
--- a/arch/powerpc/boot/dts/tqm8548-bigflash.dts
+++ b/arch/powerpc/boot/dts/tqm8548-bigflash.dts
@@ -55,10 +55,22 @@
55 #size-cells = <1>; 55 #size-cells = <1>;
56 device_type = "soc"; 56 device_type = "soc";
57 ranges = <0x0 0xa0000000 0x100000>; 57 ranges = <0x0 0xa0000000 0x100000>;
58 reg = <0xa0000000 0x1000>; // CCSRBAR
59 bus-frequency = <0>; 58 bus-frequency = <0>;
60 compatible = "fsl,mpc8548-immr", "simple-bus"; 59 compatible = "fsl,mpc8548-immr", "simple-bus";
61 60
61 ecm-law@0 {
62 compatible = "fsl,ecm-law";
63 reg = <0x0 0x1000>;
64 fsl,num-laws = <10>;
65 };
66
67 ecm@1000 {
68 compatible = "fsl,mpc8548-ecm", "fsl,ecm";
69 reg = <0x1000 0x1000>;
70 interrupts = <17 2>;
71 interrupt-parent = <&mpic>;
72 };
73
62 memory-controller@2000 { 74 memory-controller@2000 {
63 compatible = "fsl,mpc8548-memory-controller"; 75 compatible = "fsl,mpc8548-memory-controller";
64 reg = <0x2000 0x1000>; 76 reg = <0x2000 0x1000>;
@@ -419,7 +431,6 @@
419 }; 431 };
420 432
421 pci0: pci@a0008000 { 433 pci0: pci@a0008000 {
422 cell-index = <0>;
423 #interrupt-cells = <1>; 434 #interrupt-cells = <1>;
424 #size-cells = <2>; 435 #size-cells = <2>;
425 #address-cells = <3>; 436 #address-cells = <3>;
@@ -441,7 +452,6 @@
441 }; 452 };
442 453
443 pci1: pcie@a000a000 { 454 pci1: pcie@a000a000 {
444 cell-index = <2>;
445 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 455 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
446 interrupt-map = < 456 interrupt-map = <
447 /* IDSEL 0x0 (PEX) */ 457 /* IDSEL 0x0 (PEX) */
diff --git a/arch/powerpc/boot/dts/tqm8548.dts b/arch/powerpc/boot/dts/tqm8548.dts
index 673e4a778ac8..025759c7c955 100644
--- a/arch/powerpc/boot/dts/tqm8548.dts
+++ b/arch/powerpc/boot/dts/tqm8548.dts
@@ -55,10 +55,22 @@
55 #size-cells = <1>; 55 #size-cells = <1>;
56 device_type = "soc"; 56 device_type = "soc";
57 ranges = <0x0 0xe0000000 0x100000>; 57 ranges = <0x0 0xe0000000 0x100000>;
58 reg = <0xe0000000 0x1000>; // CCSRBAR
59 bus-frequency = <0>; 58 bus-frequency = <0>;
60 compatible = "fsl,mpc8548-immr", "simple-bus"; 59 compatible = "fsl,mpc8548-immr", "simple-bus";
61 60
61 ecm-law@0 {
62 compatible = "fsl,ecm-law";
63 reg = <0x0 0x1000>;
64 fsl,num-laws = <10>;
65 };
66
67 ecm@1000 {
68 compatible = "fsl,mpc8548-ecm", "fsl,ecm";
69 reg = <0x1000 0x1000>;
70 interrupts = <17 2>;
71 interrupt-parent = <&mpic>;
72 };
73
62 memory-controller@2000 { 74 memory-controller@2000 {
63 compatible = "fsl,mpc8548-memory-controller"; 75 compatible = "fsl,mpc8548-memory-controller";
64 reg = <0x2000 0x1000>; 76 reg = <0x2000 0x1000>;
@@ -419,7 +431,6 @@
419 }; 431 };
420 432
421 pci0: pci@e0008000 { 433 pci0: pci@e0008000 {
422 cell-index = <0>;
423 #interrupt-cells = <1>; 434 #interrupt-cells = <1>;
424 #size-cells = <2>; 435 #size-cells = <2>;
425 #address-cells = <3>; 436 #address-cells = <3>;
@@ -441,7 +452,6 @@
441 }; 452 };
442 453
443 pci1: pcie@e000a000 { 454 pci1: pcie@e000a000 {
444 cell-index = <2>;
445 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 455 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
446 interrupt-map = < 456 interrupt-map = <
447 /* IDSEL 0x0 (PEX) */ 457 /* IDSEL 0x0 (PEX) */
diff --git a/arch/powerpc/boot/dts/tqm8555.dts b/arch/powerpc/boot/dts/tqm8555.dts
index 6a99f1eef7ad..95e287381836 100644
--- a/arch/powerpc/boot/dts/tqm8555.dts
+++ b/arch/powerpc/boot/dts/tqm8555.dts
@@ -53,10 +53,22 @@
53 #size-cells = <1>; 53 #size-cells = <1>;
54 device_type = "soc"; 54 device_type = "soc";
55 ranges = <0x0 0xe0000000 0x100000>; 55 ranges = <0x0 0xe0000000 0x100000>;
56 reg = <0xe0000000 0x200>;
57 bus-frequency = <0>; 56 bus-frequency = <0>;
58 compatible = "fsl,mpc8555-immr", "simple-bus"; 57 compatible = "fsl,mpc8555-immr", "simple-bus";
59 58
59 ecm-law@0 {
60 compatible = "fsl,ecm-law";
61 reg = <0x0 0x1000>;
62 fsl,num-laws = <8>;
63 };
64
65 ecm@1000 {
66 compatible = "fsl,mpc8555-ecm", "fsl,ecm";
67 reg = <0x1000 0x1000>;
68 interrupts = <17 2>;
69 interrupt-parent = <&mpic>;
70 };
71
60 memory-controller@2000 { 72 memory-controller@2000 {
61 compatible = "fsl,mpc8540-memory-controller"; 73 compatible = "fsl,mpc8540-memory-controller";
62 reg = <0x2000 0x1000>; 74 reg = <0x2000 0x1000>;
@@ -288,7 +300,6 @@
288 }; 300 };
289 301
290 pci0: pci@e0008000 { 302 pci0: pci@e0008000 {
291 cell-index = <0>;
292 #interrupt-cells = <1>; 303 #interrupt-cells = <1>;
293 #size-cells = <2>; 304 #size-cells = <2>;
294 #address-cells = <3>; 305 #address-cells = <3>;
diff --git a/arch/powerpc/boot/dts/tqm8560.dts b/arch/powerpc/boot/dts/tqm8560.dts
index b6c2d71defd3..ff70580a8f4c 100644
--- a/arch/powerpc/boot/dts/tqm8560.dts
+++ b/arch/powerpc/boot/dts/tqm8560.dts
@@ -55,10 +55,22 @@
55 #size-cells = <1>; 55 #size-cells = <1>;
56 device_type = "soc"; 56 device_type = "soc";
57 ranges = <0x0 0xe0000000 0x100000>; 57 ranges = <0x0 0xe0000000 0x100000>;
58 reg = <0xe0000000 0x200>;
59 bus-frequency = <0>; 58 bus-frequency = <0>;
60 compatible = "fsl,mpc8560-immr", "simple-bus"; 59 compatible = "fsl,mpc8560-immr", "simple-bus";
61 60
61 ecm-law@0 {
62 compatible = "fsl,ecm-law";
63 reg = <0x0 0x1000>;
64 fsl,num-laws = <8>;
65 };
66
67 ecm@1000 {
68 compatible = "fsl,mpc8560-ecm", "fsl,ecm";
69 reg = <0x1000 0x1000>;
70 interrupts = <17 2>;
71 interrupt-parent = <&mpic>;
72 };
73
62 memory-controller@2000 { 74 memory-controller@2000 {
63 compatible = "fsl,mpc8540-memory-controller"; 75 compatible = "fsl,mpc8540-memory-controller";
64 reg = <0x2000 0x1000>; 76 reg = <0x2000 0x1000>;
@@ -359,7 +371,6 @@
359 }; 371 };
360 372
361 pci0: pci@e0008000 { 373 pci0: pci@e0008000 {
362 cell-index = <0>;
363 #interrupt-cells = <1>; 374 #interrupt-cells = <1>;
364 #size-cells = <2>; 375 #size-cells = <2>;
365 #address-cells = <3>; 376 #address-cells = <3>;
diff --git a/arch/powerpc/boot/dts/virtex440-ml510.dts b/arch/powerpc/boot/dts/virtex440-ml510.dts
new file mode 100644
index 000000000000..81a8dc2c6365
--- /dev/null
+++ b/arch/powerpc/boot/dts/virtex440-ml510.dts
@@ -0,0 +1,465 @@
1/*
2 * Xilinx ML510 Reference Design support
3 *
4 * This DTS file was created for the ml510_bsb1_pcores_ppc440 reference design.
5 * The reference design contains a bug which prevent PCI DMA from working
6 * properly. A description of the bug is given in the plbv46_pci section. It
7 * needs to be fixed by the user until Xilinx updates their reference design.
8 *
9 * Copyright 2009, Roderick Colenbrander
10 */
11
12/dts-v1/;
13/ {
14 #address-cells = <1>;
15 #size-cells = <1>;
16 compatible = "xlnx,ml510-ref-design", "xlnx,virtex440";
17 dcr-parent = <&ppc440_0>;
18 DDR2_SDRAM_DIMM0: memory@0 {
19 device_type = "memory";
20 reg = < 0x0 0x20000000 >;
21 } ;
22 alias {
23 ethernet0 = &Hard_Ethernet_MAC;
24 serial0 = &RS232_Uart_1;
25 } ;
26 chosen {
27 bootargs = "console=ttyS0 root=/dev/ram";
28 linux,stdout-path = "/plb@0/serial@83e00000";
29 } ;
30 cpus {
31 #address-cells = <1>;
32 #cpus = <0x1>;
33 #size-cells = <0>;
34 ppc440_0: cpu@0 {
35 #address-cells = <1>;
36 #size-cells = <1>;
37 clock-frequency = <300000000>;
38 compatible = "PowerPC,440", "ibm,ppc440";
39 d-cache-line-size = <0x20>;
40 d-cache-size = <0x8000>;
41 dcr-access-method = "native";
42 dcr-controller ;
43 device_type = "cpu";
44 i-cache-line-size = <0x20>;
45 i-cache-size = <0x8000>;
46 model = "PowerPC,440";
47 reg = <0>;
48 timebase-frequency = <300000000>;
49 xlnx,apu-control = <0x2000>;
50 xlnx,apu-udi-0 = <0x0>;
51 xlnx,apu-udi-1 = <0x0>;
52 xlnx,apu-udi-10 = <0x0>;
53 xlnx,apu-udi-11 = <0x0>;
54 xlnx,apu-udi-12 = <0x0>;
55 xlnx,apu-udi-13 = <0x0>;
56 xlnx,apu-udi-14 = <0x0>;
57 xlnx,apu-udi-15 = <0x0>;
58 xlnx,apu-udi-2 = <0x0>;
59 xlnx,apu-udi-3 = <0x0>;
60 xlnx,apu-udi-4 = <0x0>;
61 xlnx,apu-udi-5 = <0x0>;
62 xlnx,apu-udi-6 = <0x0>;
63 xlnx,apu-udi-7 = <0x0>;
64 xlnx,apu-udi-8 = <0x0>;
65 xlnx,apu-udi-9 = <0x0>;
66 xlnx,dcr-autolock-enable = <0x1>;
67 xlnx,dcu-rd-ld-cache-plb-prio = <0x0>;
68 xlnx,dcu-rd-noncache-plb-prio = <0x0>;
69 xlnx,dcu-rd-touch-plb-prio = <0x0>;
70 xlnx,dcu-rd-urgent-plb-prio = <0x0>;
71 xlnx,dcu-wr-flush-plb-prio = <0x0>;
72 xlnx,dcu-wr-store-plb-prio = <0x0>;
73 xlnx,dcu-wr-urgent-plb-prio = <0x0>;
74 xlnx,dma0-control = <0x0>;
75 xlnx,dma0-plb-prio = <0x0>;
76 xlnx,dma0-rxchannelctrl = <0x1010000>;
77 xlnx,dma0-rxirqtimer = <0x3ff>;
78 xlnx,dma0-txchannelctrl = <0x1010000>;
79 xlnx,dma0-txirqtimer = <0x3ff>;
80 xlnx,dma1-control = <0x0>;
81 xlnx,dma1-plb-prio = <0x0>;
82 xlnx,dma1-rxchannelctrl = <0x1010000>;
83 xlnx,dma1-rxirqtimer = <0x3ff>;
84 xlnx,dma1-txchannelctrl = <0x1010000>;
85 xlnx,dma1-txirqtimer = <0x3ff>;
86 xlnx,dma2-control = <0x0>;
87 xlnx,dma2-plb-prio = <0x0>;
88 xlnx,dma2-rxchannelctrl = <0x1010000>;
89 xlnx,dma2-rxirqtimer = <0x3ff>;
90 xlnx,dma2-txchannelctrl = <0x1010000>;
91 xlnx,dma2-txirqtimer = <0x3ff>;
92 xlnx,dma3-control = <0x0>;
93 xlnx,dma3-plb-prio = <0x0>;
94 xlnx,dma3-rxchannelctrl = <0x1010000>;
95 xlnx,dma3-rxirqtimer = <0x3ff>;
96 xlnx,dma3-txchannelctrl = <0x1010000>;
97 xlnx,dma3-txirqtimer = <0x3ff>;
98 xlnx,endian-reset = <0x0>;
99 xlnx,generate-plb-timespecs = <0x1>;
100 xlnx,icu-rd-fetch-plb-prio = <0x0>;
101 xlnx,icu-rd-spec-plb-prio = <0x0>;
102 xlnx,icu-rd-touch-plb-prio = <0x0>;
103 xlnx,interconnect-imask = <0xffffffff>;
104 xlnx,mplb-allow-lock-xfer = <0x1>;
105 xlnx,mplb-arb-mode = <0x0>;
106 xlnx,mplb-awidth = <0x20>;
107 xlnx,mplb-counter = <0x500>;
108 xlnx,mplb-dwidth = <0x80>;
109 xlnx,mplb-max-burst = <0x8>;
110 xlnx,mplb-native-dwidth = <0x80>;
111 xlnx,mplb-p2p = <0x0>;
112 xlnx,mplb-prio-dcur = <0x2>;
113 xlnx,mplb-prio-dcuw = <0x3>;
114 xlnx,mplb-prio-icu = <0x4>;
115 xlnx,mplb-prio-splb0 = <0x1>;
116 xlnx,mplb-prio-splb1 = <0x0>;
117 xlnx,mplb-read-pipe-enable = <0x1>;
118 xlnx,mplb-sync-tattribute = <0x0>;
119 xlnx,mplb-wdog-enable = <0x1>;
120 xlnx,mplb-write-pipe-enable = <0x1>;
121 xlnx,mplb-write-post-enable = <0x1>;
122 xlnx,num-dma = <0x0>;
123 xlnx,pir = <0xf>;
124 xlnx,ppc440mc-addr-base = <0x0>;
125 xlnx,ppc440mc-addr-high = <0x1fffffff>;
126 xlnx,ppc440mc-arb-mode = <0x0>;
127 xlnx,ppc440mc-bank-conflict-mask = <0x1800000>;
128 xlnx,ppc440mc-control = <0xf810008f>;
129 xlnx,ppc440mc-max-burst = <0x8>;
130 xlnx,ppc440mc-prio-dcur = <0x2>;
131 xlnx,ppc440mc-prio-dcuw = <0x3>;
132 xlnx,ppc440mc-prio-icu = <0x4>;
133 xlnx,ppc440mc-prio-splb0 = <0x1>;
134 xlnx,ppc440mc-prio-splb1 = <0x0>;
135 xlnx,ppc440mc-row-conflict-mask = <0x7ffe00>;
136 xlnx,ppcdm-asyncmode = <0x0>;
137 xlnx,ppcds-asyncmode = <0x0>;
138 xlnx,user-reset = <0x0>;
139 } ;
140 } ;
141 plb_v46_0: plb@0 {
142 #address-cells = <1>;
143 #size-cells = <1>;
144 compatible = "xlnx,plb-v46-1.03.a", "simple-bus";
145 ranges ;
146 FLASH: flash@fc000000 {
147 bank-width = <2>;
148 compatible = "xlnx,xps-mch-emc-2.00.a", "cfi-flash";
149 reg = < 0xfc000000 0x2000000 >;
150 xlnx,family = "virtex5";
151 xlnx,include-datawidth-matching-0 = <0x1>;
152 xlnx,include-datawidth-matching-1 = <0x0>;
153 xlnx,include-datawidth-matching-2 = <0x0>;
154 xlnx,include-datawidth-matching-3 = <0x0>;
155 xlnx,include-negedge-ioregs = <0x0>;
156 xlnx,include-plb-ipif = <0x1>;
157 xlnx,include-wrbuf = <0x1>;
158 xlnx,max-mem-width = <0x10>;
159 xlnx,mch-native-dwidth = <0x20>;
160 xlnx,mch-plb-clk-period-ps = <0x2710>;
161 xlnx,mch-splb-awidth = <0x20>;
162 xlnx,mch0-accessbuf-depth = <0x10>;
163 xlnx,mch0-protocol = <0x0>;
164 xlnx,mch0-rddatabuf-depth = <0x10>;
165 xlnx,mch1-accessbuf-depth = <0x10>;
166 xlnx,mch1-protocol = <0x0>;
167 xlnx,mch1-rddatabuf-depth = <0x10>;
168 xlnx,mch2-accessbuf-depth = <0x10>;
169 xlnx,mch2-protocol = <0x0>;
170 xlnx,mch2-rddatabuf-depth = <0x10>;
171 xlnx,mch3-accessbuf-depth = <0x10>;
172 xlnx,mch3-protocol = <0x0>;
173 xlnx,mch3-rddatabuf-depth = <0x10>;
174 xlnx,mem0-width = <0x10>;
175 xlnx,mem1-width = <0x20>;
176 xlnx,mem2-width = <0x20>;
177 xlnx,mem3-width = <0x20>;
178 xlnx,num-banks-mem = <0x1>;
179 xlnx,num-channels = <0x2>;
180 xlnx,priority-mode = <0x0>;
181 xlnx,synch-mem-0 = <0x0>;
182 xlnx,synch-mem-1 = <0x0>;
183 xlnx,synch-mem-2 = <0x0>;
184 xlnx,synch-mem-3 = <0x0>;
185 xlnx,synch-pipedelay-0 = <0x2>;
186 xlnx,synch-pipedelay-1 = <0x2>;
187 xlnx,synch-pipedelay-2 = <0x2>;
188 xlnx,synch-pipedelay-3 = <0x2>;
189 xlnx,tavdv-ps-mem-0 = <0x1adb0>;
190 xlnx,tavdv-ps-mem-1 = <0x3a98>;
191 xlnx,tavdv-ps-mem-2 = <0x3a98>;
192 xlnx,tavdv-ps-mem-3 = <0x3a98>;
193 xlnx,tcedv-ps-mem-0 = <0x1adb0>;
194 xlnx,tcedv-ps-mem-1 = <0x3a98>;
195 xlnx,tcedv-ps-mem-2 = <0x3a98>;
196 xlnx,tcedv-ps-mem-3 = <0x3a98>;
197 xlnx,thzce-ps-mem-0 = <0x88b8>;
198 xlnx,thzce-ps-mem-1 = <0x1b58>;
199 xlnx,thzce-ps-mem-2 = <0x1b58>;
200 xlnx,thzce-ps-mem-3 = <0x1b58>;
201 xlnx,thzoe-ps-mem-0 = <0x1b58>;
202 xlnx,thzoe-ps-mem-1 = <0x1b58>;
203 xlnx,thzoe-ps-mem-2 = <0x1b58>;
204 xlnx,thzoe-ps-mem-3 = <0x1b58>;
205 xlnx,tlzwe-ps-mem-0 = <0x88b8>;
206 xlnx,tlzwe-ps-mem-1 = <0x0>;
207 xlnx,tlzwe-ps-mem-2 = <0x0>;
208 xlnx,tlzwe-ps-mem-3 = <0x0>;
209 xlnx,twc-ps-mem-0 = <0x1adb0>;
210 xlnx,twc-ps-mem-1 = <0x3a98>;
211 xlnx,twc-ps-mem-2 = <0x3a98>;
212 xlnx,twc-ps-mem-3 = <0x3a98>;
213 xlnx,twp-ps-mem-0 = <0x11170>;
214 xlnx,twp-ps-mem-1 = <0x2ee0>;
215 xlnx,twp-ps-mem-2 = <0x2ee0>;
216 xlnx,twp-ps-mem-3 = <0x2ee0>;
217 xlnx,xcl0-linesize = <0x4>;
218 xlnx,xcl0-writexfer = <0x1>;
219 xlnx,xcl1-linesize = <0x4>;
220 xlnx,xcl1-writexfer = <0x1>;
221 xlnx,xcl2-linesize = <0x4>;
222 xlnx,xcl2-writexfer = <0x1>;
223 xlnx,xcl3-linesize = <0x4>;
224 xlnx,xcl3-writexfer = <0x1>;
225 } ;
226 Hard_Ethernet_MAC: xps-ll-temac@81c00000 {
227 #address-cells = <1>;
228 #size-cells = <1>;
229 compatible = "xlnx,compound";
230 ethernet@81c00000 {
231 compatible = "xlnx,xps-ll-temac-1.01.b";
232 device_type = "network";
233 interrupt-parent = <&xps_intc_0>;
234 interrupts = < 8 2 >;
235 llink-connected = <&Hard_Ethernet_MAC_fifo>;
236 local-mac-address = [ 02 00 00 00 00 00 ];
237 reg = < 0x81c00000 0x40 >;
238 xlnx,bus2core-clk-ratio = <0x1>;
239 xlnx,phy-type = <0x3>;
240 xlnx,phyaddr = <0x1>;
241 xlnx,rxcsum = <0x0>;
242 xlnx,rxfifo = <0x8000>;
243 xlnx,temac-type = <0x0>;
244 xlnx,txcsum = <0x0>;
245 xlnx,txfifo = <0x8000>;
246 } ;
247 } ;
248 Hard_Ethernet_MAC_fifo: xps-ll-fifo@81a00000 {
249 compatible = "xlnx,xps-ll-fifo-1.01.a";
250 interrupt-parent = <&xps_intc_0>;
251 interrupts = < 6 2 >;
252 reg = < 0x81a00000 0x10000 >;
253 xlnx,family = "virtex5";
254 } ;
255 IIC_EEPROM: i2c@81600000 {
256 compatible = "xlnx,xps-iic-2.00.a";
257 interrupt-parent = <&xps_intc_0>;
258 interrupts = < 9 2 >;
259 reg = < 0x81600000 0x10000 >;
260 xlnx,clk-freq = <0x5f5e100>;
261 xlnx,family = "virtex5";
262 xlnx,gpo-width = <0x1>;
263 xlnx,iic-freq = <0x186a0>;
264 xlnx,scl-inertial-delay = <0x5>;
265 xlnx,sda-inertial-delay = <0x5>;
266 xlnx,ten-bit-adr = <0x0>;
267 } ;
268 LCD_OPTIONAL: gpio@81420000 {
269 compatible = "xlnx,xps-gpio-1.00.a";
270 reg = < 0x81420000 0x10000 >;
271 xlnx,all-inputs = <0x0>;
272 xlnx,all-inputs-2 = <0x0>;
273 xlnx,dout-default = <0x0>;
274 xlnx,dout-default-2 = <0x0>;
275 xlnx,family = "virtex5";
276 xlnx,gpio-width = <0xb>;
277 xlnx,interrupt-present = <0x0>;
278 xlnx,is-bidir = <0x1>;
279 xlnx,is-bidir-2 = <0x1>;
280 xlnx,is-dual = <0x0>;
281 xlnx,tri-default = <0xffffffff>;
282 xlnx,tri-default-2 = <0xffffffff>;
283 } ;
284 LEDs_4Bit: gpio@81400000 {
285 compatible = "xlnx,xps-gpio-1.00.a";
286 reg = < 0x81400000 0x10000 >;
287 xlnx,all-inputs = <0x0>;
288 xlnx,all-inputs-2 = <0x0>;
289 xlnx,dout-default = <0x0>;
290 xlnx,dout-default-2 = <0x0>;
291 xlnx,family = "virtex5";
292 xlnx,gpio-width = <0x4>;
293 xlnx,interrupt-present = <0x0>;
294 xlnx,is-bidir = <0x1>;
295 xlnx,is-bidir-2 = <0x1>;
296 xlnx,is-dual = <0x0>;
297 xlnx,tri-default = <0xffffffff>;
298 xlnx,tri-default-2 = <0xffffffff>;
299 } ;
300 RS232_Uart_1: serial@83e00000 {
301 clock-frequency = <100000000>;
302 compatible = "xlnx,xps-uart16550-2.00.b", "ns16550";
303 current-speed = <9600>;
304 device_type = "serial";
305 interrupt-parent = <&xps_intc_0>;
306 interrupts = < 11 2 >;
307 reg = < 0x83e00000 0x10000 >;
308 reg-offset = <0x1003>;
309 reg-shift = <2>;
310 xlnx,family = "virtex5";
311 xlnx,has-external-rclk = <0x0>;
312 xlnx,has-external-xin = <0x0>;
313 xlnx,is-a-16550 = <0x1>;
314 } ;
315 SPI_EEPROM: xps-spi@feff8000 {
316 compatible = "xlnx,xps-spi-2.00.b";
317 interrupt-parent = <&xps_intc_0>;
318 interrupts = < 10 2 >;
319 reg = < 0xfeff8000 0x80 >;
320 xlnx,family = "virtex5";
321 xlnx,fifo-exist = <0x1>;
322 xlnx,num-ss-bits = <0x1>;
323 xlnx,num-transfer-bits = <0x8>;
324 xlnx,sck-ratio = <0x80>;
325 } ;
326 SysACE_CompactFlash: sysace@83600000 {
327 compatible = "xlnx,xps-sysace-1.00.a";
328 interrupt-parent = <&xps_intc_0>;
329 interrupts = < 7 2 >;
330 reg = < 0x83600000 0x10000 >;
331 xlnx,family = "virtex5";
332 xlnx,mem-width = <0x10>;
333 } ;
334 plbv46_pci_0: plbv46-pci@85e00000 {
335 #size-cells = <2>;
336 #address-cells = <3>;
337 compatible = "xlnx,plbv46-pci-1.03.a";
338 device_type = "pci";
339 reg = < 0x85e00000 0x10000 >;
340
341 /*
342 * The default ML510 BSB has C_IPIFBAR2PCIBAR_0 set to
343 * 0 which means that a read/write to the memory mapped
344 * i/o region (which starts at 0xa0000000) for pci
345 * bar 0 on the plb side translates to 0.
346 * It is important to set this value to 0xa0000000, so
347 * that inbound and outbound pci transactions work
348 * properly including DMA.
349 */
350 ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x20000000
351 0x01000000 0 0x00000000 0xf0000000 0 0x00010000>;
352
353 #interrupt-cells = <1>;
354 interrupt-parent = <&xps_intc_0>;
355 interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
356 interrupt-map = <
357 /* IRQ mapping for pci slots and ALI M1533
358 * periperhals. In total there are 5 interrupt
359 * lines connected to a xps_intc controller.
360 * Four of them are PCI IRQ A, B, C, D and
361 * which correspond to respectively xpx_intc
362 * 5, 4, 3 and 2. The fifth interrupt line is
363 * connected to the south bridge and this one
364 * uses irq 1 and is active high instead of
365 * active low.
366 *
367 * The M1533 contains various peripherals
368 * including AC97 audio, a modem, USB, IDE and
369 * some power management stuff. The modem
370 * isn't connected on the ML510 and the power
371 * management core also isn't used.
372 */
373
374 /* IDSEL 0x16 / dev=6, bus=0 / PCI slot 3 */
375 0x3000 0 0 1 &xps_intc_0 3 2
376 0x3000 0 0 2 &xps_intc_0 2 2
377 0x3000 0 0 3 &xps_intc_0 5 2
378 0x3000 0 0 4 &xps_intc_0 4 2
379
380 /* IDSEL 0x13 / dev=3, bus=1 / PCI slot 4 */
381 /*
382 0x11800 0 0 1 &xps_intc_0 5 0 2
383 0x11800 0 0 2 &xps_intc_0 4 0 2
384 0x11800 0 0 3 &xps_intc_0 3 0 2
385 0x11800 0 0 4 &xps_intc_0 2 0 2
386 */
387
388 /* According to the datasheet + schematic
389 * ABCD [FPGA] of slot 5 is mapped to DABC.
390 * Testing showed that at least A maps to B,
391 * the mapping of the other pins is a guess
392 * and for that reason the lines have been
393 * commented out.
394 */
395 /* IDSEL 0x15 / dev=5, bus=0 / PCI slot 5 */
396 0x2800 0 0 1 &xps_intc_0 4 2
397 /*
398 0x2800 0 0 2 &xps_intc_0 3 2
399 0x2800 0 0 3 &xps_intc_0 2 2
400 0x2800 0 0 4 &xps_intc_0 5 2
401 */
402
403 /* IDSEL 0x12 / dev=2, bus=1 / PCI slot 6 */
404 /*
405 0x11000 0 0 1 &xps_intc_0 4 0 2
406 0x11000 0 0 2 &xps_intc_0 3 0 2
407 0x11000 0 0 3 &xps_intc_0 2 0 2
408 0x11000 0 0 4 &xps_intc_0 5 0 2
409 */
410
411 /* IDSEL 0x11 / dev=1, bus=0 / AC97 audio */
412 0x0800 0 0 1 &i8259 7 2
413
414 /* IDSEL 0x1b / dev=11, bus=0 / IDE */
415 0x5800 0 0 1 &i8259 14 2
416
417 /* IDSEL 0x1f / dev 15, bus=0 / 2x USB 1.1 */
418 0x7800 0 0 1 &i8259 7 2
419 >;
420 ali_m1533 {
421 #size-cells = <1>;
422 #address-cells = <2>;
423 i8259: interrupt-controller@20 {
424 reg = <1 0x20 2
425 1 0xa0 2
426 1 0x4d0 2>;
427 interrupt-controller;
428 device_type = "interrupt-controller";
429 #address-cells = <0>;
430 #interrupt-cells = <2>;
431 compatible = "chrp,iic";
432
433 /* south bridge irq is active high */
434 interrupts = <1 3>;
435 interrupt-parent = <&xps_intc_0>;
436 };
437 };
438 } ;
439 xps_bram_if_cntlr_1: xps-bram-if-cntlr@ffff0000 {
440 compatible = "xlnx,xps-bram-if-cntlr-1.00.a";
441 reg = < 0xffff0000 0x10000 >;
442 xlnx,family = "virtex5";
443 } ;
444 xps_intc_0: interrupt-controller@81800000 {
445 #interrupt-cells = <0x2>;
446 compatible = "xlnx,xps-intc-1.00.a";
447 interrupt-controller ;
448 reg = < 0x81800000 0x10000 >;
449 xlnx,num-intr-inputs = <0xc>;
450 } ;
451 xps_tft_0: tft@86e00000 {
452 compatible = "xlnx,xps-tft-1.00.a";
453 reg = < 0x86e00000 0x10000 >;
454 xlnx,dcr-splb-slave-if = <0x1>;
455 xlnx,default-tft-base-addr = <0x0>;
456 xlnx,family = "virtex5";
457 xlnx,i2c-slave-addr = <0x76>;
458 xlnx,mplb-awidth = <0x20>;
459 xlnx,mplb-dwidth = <0x80>;
460 xlnx,mplb-native-dwidth = <0x40>;
461 xlnx,mplb-smallest-slave = <0x20>;
462 xlnx,tft-interface = <0x1>;
463 } ;
464 } ;
465} ;
diff --git a/arch/powerpc/boot/dts/warp.dts b/arch/powerpc/boot/dts/warp.dts
index 7e183ff9a317..01bfb56bbe80 100644
--- a/arch/powerpc/boot/dts/warp.dts
+++ b/arch/powerpc/boot/dts/warp.dts
@@ -1,7 +1,7 @@
1/* 1/*
2 * Device Tree Source for PIKA Warp 2 * Device Tree Source for PIKA Warp
3 * 3 *
4 * Copyright (c) 2008 PIKA Technologies 4 * Copyright (c) 2008-2009 PIKA Technologies
5 * Sean MacLennan <smaclennan@pikatech.com> 5 * Sean MacLennan <smaclennan@pikatech.com>
6 * 6 *
7 * This file is licensed under the terms of the GNU General Public 7 * This file is licensed under the terms of the GNU General Public
@@ -158,7 +158,7 @@
158 158
159 partition@0 { 159 partition@0 {
160 label = "splash"; 160 label = "splash";
161 reg = <0x00000000 0x00020000>; 161 reg = <0x00000000 0x00010000>;
162 }; 162 };
163 partition@300000 { 163 partition@300000 {
164 label = "fpga"; 164 label = "fpga";
@@ -244,28 +244,27 @@
244 }; 244 };
245 245
246 GPIO0: gpio@ef600b00 { 246 GPIO0: gpio@ef600b00 {
247 compatible = "ibm,gpio-440ep"; 247 compatible = "ibm,ppc4xx-gpio";
248 reg = <0xef600b00 0x00000048>; 248 reg = <0xef600b00 0x00000048>;
249 #gpio-cells = <2>; 249 #gpio-cells = <2>;
250 gpio-controller; 250 gpio-controller;
251 }; 251 };
252 252
253 GPIO1: gpio@ef600c00 { 253 GPIO1: gpio@ef600c00 {
254 compatible = "ibm,gpio-440ep"; 254 compatible = "ibm,ppc4xx-gpio";
255 reg = <0xef600c00 0x00000048>; 255 reg = <0xef600c00 0x00000048>;
256 #gpio-cells = <2>; 256 #gpio-cells = <2>;
257 gpio-controller; 257 gpio-controller;
258 };
258 259
259 led@31 { 260 power-leds {
260 compatible = "linux,gpio-led"; 261 compatible = "gpio-leds";
261 linux,name = ":green:"; 262 green {
262 gpios = <&GPIO1 31 0>; 263 gpios = <&GPIO1 0 0>;
263 }; 264 default-state = "on";
264 265 };
265 led@30 { 266 red {
266 compatible = "linux,gpio-led"; 267 gpios = <&GPIO1 1 0>;
267 linux,name = ":red:";
268 gpios = <&GPIO1 30 0>;
269 }; 268 };
270 }; 269 };
271 270
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-10 08:39:00 -0500