1 files changed, 0 insertions, 60 deletions

diff --git a/arch/powerpc/boot/ebony.c b/arch/powerpc/boot/ebony.c
index 68beb4947190..f61364c47a76 100644
--- a/arch/powerpc/boot/ebony.c
+++ b/arch/powerpc/boot/ebony.c
@@ -31,66 +31,6 @@
 
 static u8 *ebony_mac0, *ebony_mac1;
 
-/* Calculate 440GP clocks */
-void ibm440gp_fixup_clocks(unsigned int sysclk, unsigned int ser_clk)
-{
-        u32 sys0 = mfdcr(DCRN_CPC0_SYS0);
-        u32 cr0 = mfdcr(DCRN_CPC0_CR0);
-        u32 cpu, plb, opb, ebc, tb, uart0, uart1, m;
-        u32 opdv = CPC0_SYS0_OPDV(sys0);
-        u32 epdv = CPC0_SYS0_EPDV(sys0);
-
-        if (sys0 & CPC0_SYS0_BYPASS) {
-                /* Bypass system PLL */
-                cpu = plb = sysclk;
-        } else {
-                if (sys0 & CPC0_SYS0_EXTSL)
-                        /* PerClk */
-                        m = CPC0_SYS0_FWDVB(sys0) * opdv * epdv;
-                else
-                        /* CPU clock */
-                        m = CPC0_SYS0_FBDV(sys0) * CPC0_SYS0_FWDVA(sys0);
-                cpu = sysclk * m / CPC0_SYS0_FWDVA(sys0);
-                plb = sysclk * m / CPC0_SYS0_FWDVB(sys0);
-        }
-
-        opb = plb / opdv;
-        ebc = opb / epdv;
-
-        /* FIXME: Check if this is for all 440GP, or just Ebony */
-        if ((mfpvr() & 0xf0000fff) == 0x40000440)
-                /* Rev. B 440GP, use external system clock */
-                tb = sysclk;
-        else
-                /* Rev. C 440GP, errata force us to use internal clock */
-                tb = cpu;
-
-        if (cr0 & CPC0_CR0_U0EC)
-                /* External UART clock */
-                uart0 = ser_clk;
-        else
-                /* Internal UART clock */
-                uart0 = plb / CPC0_CR0_UDIV(cr0);
-
-        if (cr0 & CPC0_CR0_U1EC)
-                /* External UART clock */
-                uart1 = ser_clk;
-        else
-                /* Internal UART clock */
-                uart1 = plb / CPC0_CR0_UDIV(cr0);
-
-        printf("PPC440GP: SysClk = %dMHz (%x)\n\r",
-               (sysclk + 500000) / 1000000, sysclk);
-
-        dt_fixup_cpu_clocks(cpu, tb, 0);
-
-        dt_fixup_clock("/plb", plb);
-        dt_fixup_clock("/plb/opb", opb);
-        dt_fixup_clock("/plb/opb/ebc", ebc);
-        dt_fixup_clock("/plb/opb/serial@40000200", uart0);
-        dt_fixup_clock("/plb/opb/serial@40000300", uart1);
-}
-
 #define EBONY_FPGA_PATH         "/plb/opb/ebc/fpga"
 #define EBONY_FPGA_FLASH_SEL    0x01
 #define EBONY_SMALL_FLASH_PATH  "/plb/opb/ebc/small-flash"