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-rw-r--r--arch/powerpc/boot/dts/tqm8548-bigflash.dts8
-rw-r--r--arch/powerpc/boot/dts/tqm8548.dts3
2 files changed, 9 insertions, 2 deletions
diff --git a/arch/powerpc/boot/dts/tqm8548-bigflash.dts b/arch/powerpc/boot/dts/tqm8548-bigflash.dts
index 64d2d5bbcdf1..4199e89b4e50 100644
--- a/arch/powerpc/boot/dts/tqm8548-bigflash.dts
+++ b/arch/powerpc/boot/dts/tqm8548-bigflash.dts
@@ -50,13 +50,14 @@
50 reg = <0x00000000 0x00000000>; // Filled in by U-Boot 50 reg = <0x00000000 0x00000000>; // Filled in by U-Boot
51 }; 51 };
52 52
53 soc8548@a0000000 { 53 soc@a0000000 {
54 #address-cells = <1>; 54 #address-cells = <1>;
55 #size-cells = <1>; 55 #size-cells = <1>;
56 device_type = "soc"; 56 device_type = "soc";
57 ranges = <0x0 0xa0000000 0x100000>; 57 ranges = <0x0 0xa0000000 0x100000>;
58 reg = <0xa0000000 0x1000>; // CCSRBAR 58 reg = <0xa0000000 0x1000>; // CCSRBAR
59 bus-frequency = <0>; 59 bus-frequency = <0>;
60 compatible = "fsl,mpc8548-immr", "simple-bus";
60 61
61 memory-controller@2000 { 62 memory-controller@2000 {
62 compatible = "fsl,mpc8548-memory-controller"; 63 compatible = "fsl,mpc8548-memory-controller";
@@ -83,6 +84,11 @@
83 interrupts = <43 2>; 84 interrupts = <43 2>;
84 interrupt-parent = <&mpic>; 85 interrupt-parent = <&mpic>;
85 dfsrr; 86 dfsrr;
87
88 rtc@68 {
89 compatible = "dallas,ds1337";
90 reg = <0x68>;
91 };
86 }; 92 };
87 93
88 i2c@3100 { 94 i2c@3100 {
diff --git a/arch/powerpc/boot/dts/tqm8548.dts b/arch/powerpc/boot/dts/tqm8548.dts
index 2563112cabd3..58ee4185454b 100644
--- a/arch/powerpc/boot/dts/tqm8548.dts
+++ b/arch/powerpc/boot/dts/tqm8548.dts
@@ -50,13 +50,14 @@
50 reg = <0x00000000 0x00000000>; // Filled in by U-Boot 50 reg = <0x00000000 0x00000000>; // Filled in by U-Boot
51 }; 51 };
52 52
53 soc8548@e0000000 { 53 soc@e0000000 {
54 #address-cells = <1>; 54 #address-cells = <1>;
55 #size-cells = <1>; 55 #size-cells = <1>;
56 device_type = "soc"; 56 device_type = "soc";
57 ranges = <0x0 0xe0000000 0x100000>; 57 ranges = <0x0 0xe0000000 0x100000>;
58 reg = <0xe0000000 0x1000>; // CCSRBAR 58 reg = <0xe0000000 0x1000>; // CCSRBAR
59 bus-frequency = <0>; 59 bus-frequency = <0>;
60 compatible = "fsl,mpc8548-immr", "simple-bus";
60 61
61 memory-controller@2000 { 62 memory-controller@2000 {
62 compatible = "fsl,mpc8548-memory-controller"; 63 compatible = "fsl,mpc8548-memory-controller";