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-rw-r--r--arch/powerpc/boot/dts/ksi8560.dts4
-rw-r--r--arch/powerpc/boot/dts/pq2fads.dts20
-rw-r--r--arch/powerpc/boot/dts/sbc8548.dts4
-rw-r--r--arch/powerpc/boot/dts/sbc8560.dts4
-rw-r--r--arch/powerpc/boot/dts/socrates.dts9
-rw-r--r--arch/powerpc/boot/dts/stx_gp3_8560.dts4
-rw-r--r--arch/powerpc/boot/dts/tqm8540.dts4
-rw-r--r--arch/powerpc/boot/dts/tqm8541.dts4
-rw-r--r--arch/powerpc/boot/dts/tqm8555.dts4
-rw-r--r--arch/powerpc/boot/dts/tqm8560.dts4
10 files changed, 35 insertions, 26 deletions
diff --git a/arch/powerpc/boot/dts/ksi8560.dts b/arch/powerpc/boot/dts/ksi8560.dts
index 308fe7c29dea..c9cfd374bffb 100644
--- a/arch/powerpc/boot/dts/ksi8560.dts
+++ b/arch/powerpc/boot/dts/ksi8560.dts
@@ -57,14 +57,14 @@
57 bus-frequency = <0>; /* Fixed by bootwrapper */ 57 bus-frequency = <0>; /* Fixed by bootwrapper */
58 58
59 memory-controller@2000 { 59 memory-controller@2000 {
60 compatible = "fsl,8540-memory-controller"; 60 compatible = "fsl,mpc8540-memory-controller";
61 reg = <0x2000 0x1000>; 61 reg = <0x2000 0x1000>;
62 interrupt-parent = <&mpic>; 62 interrupt-parent = <&mpic>;
63 interrupts = <0x12 0x2>; 63 interrupts = <0x12 0x2>;
64 }; 64 };
65 65
66 L2: l2-cache-controller@20000 { 66 L2: l2-cache-controller@20000 {
67 compatible = "fsl,8540-l2-cache-controller"; 67 compatible = "fsl,mpc8540-l2-cache-controller";
68 reg = <0x20000 0x1000>; 68 reg = <0x20000 0x1000>;
69 cache-line-size = <0x20>; /* 32 bytes */ 69 cache-line-size = <0x20>; /* 32 bytes */
70 cache-size = <0x40000>; /* L2, 256K */ 70 cache-size = <0x40000>; /* L2, 256K */
diff --git a/arch/powerpc/boot/dts/pq2fads.dts b/arch/powerpc/boot/dts/pq2fads.dts
index b2d61091b36d..0bb669376743 100644
--- a/arch/powerpc/boot/dts/pq2fads.dts
+++ b/arch/powerpc/boot/dts/pq2fads.dts
@@ -17,6 +17,14 @@
17 #address-cells = <1>; 17 #address-cells = <1>;
18 #size-cells = <1>; 18 #size-cells = <1>;
19 19
20 aliases {
21 ethernet0 = &enet0;
22 ethernet1 = &enet1;
23 serial0 = &serial0;
24 serial1 = &serial1;
25 pci0 = &pci0;
26 };
27
20 cpus { 28 cpus {
21 #address-cells = <1>; 29 #address-cells = <1>;
22 #size-cells = <0>; 30 #size-cells = <0>;
@@ -45,7 +53,7 @@
45 #size-cells = <1>; 53 #size-cells = <1>;
46 reg = <0xf0010100 0x60>; 54 reg = <0xf0010100 0x60>;
47 55
48 ranges = <0x0 0x0 0xfe000000 0x800000 56 ranges = <0x0 0x0 0xff800000 0x800000
49 0x1 0x0 0xf4500000 0x8000 57 0x1 0x0 0xf4500000 0x8000
50 0x8 0x0 0xf8200000 0x8000>; 58 0x8 0x0 0xf8200000 0x8000>;
51 59
@@ -71,7 +79,7 @@
71 }; 79 };
72 }; 80 };
73 81
74 pci@f0010800 { 82 pci0: pci@f0010800 {
75 device_type = "pci"; 83 device_type = "pci";
76 reg = <0xf0010800 0x10c 0xf00101ac 0x8 0xf00101c4 0x8>; 84 reg = <0xf0010800 0x10c 0xf00101ac 0x8 0xf00101c4 0x8>;
77 compatible = "fsl,mpc8280-pci", "fsl,pq2-pci"; 85 compatible = "fsl,mpc8280-pci", "fsl,pq2-pci";
@@ -142,7 +150,7 @@
142 reg = <0x119f0 0x10 0x115f0 0x10>; 150 reg = <0x119f0 0x10 0x115f0 0x10>;
143 }; 151 };
144 152
145 serial@11a00 { 153 serial0: serial@11a00 {
146 device_type = "serial"; 154 device_type = "serial";
147 compatible = "fsl,mpc8280-scc-uart", 155 compatible = "fsl,mpc8280-scc-uart",
148 "fsl,cpm2-scc-uart"; 156 "fsl,cpm2-scc-uart";
@@ -153,7 +161,7 @@
153 fsl,cpm-command = <0x800000>; 161 fsl,cpm-command = <0x800000>;
154 }; 162 };
155 163
156 serial@11a20 { 164 serial1: serial@11a20 {
157 device_type = "serial"; 165 device_type = "serial";
158 compatible = "fsl,mpc8280-scc-uart", 166 compatible = "fsl,mpc8280-scc-uart",
159 "fsl,cpm2-scc-uart"; 167 "fsl,cpm2-scc-uart";
@@ -164,7 +172,7 @@
164 fsl,cpm-command = <0x4a00000>; 172 fsl,cpm-command = <0x4a00000>;
165 }; 173 };
166 174
167 ethernet@11320 { 175 enet0: ethernet@11320 {
168 device_type = "network"; 176 device_type = "network";
169 compatible = "fsl,mpc8280-fcc-enet", 177 compatible = "fsl,mpc8280-fcc-enet",
170 "fsl,cpm2-fcc-enet"; 178 "fsl,cpm2-fcc-enet";
@@ -176,7 +184,7 @@
176 fsl,cpm-command = <0x16200300>; 184 fsl,cpm-command = <0x16200300>;
177 }; 185 };
178 186
179 ethernet@11340 { 187 enet1: ethernet@11340 {
180 device_type = "network"; 188 device_type = "network";
181 compatible = "fsl,mpc8280-fcc-enet", 189 compatible = "fsl,mpc8280-fcc-enet",
182 "fsl,cpm2-fcc-enet"; 190 "fsl,cpm2-fcc-enet";
diff --git a/arch/powerpc/boot/dts/sbc8548.dts b/arch/powerpc/boot/dts/sbc8548.dts
index 9c5079fec4f2..b1f1416ac998 100644
--- a/arch/powerpc/boot/dts/sbc8548.dts
+++ b/arch/powerpc/boot/dts/sbc8548.dts
@@ -156,14 +156,14 @@
156 compatible = "simple-bus"; 156 compatible = "simple-bus";
157 157
158 memory-controller@2000 { 158 memory-controller@2000 {
159 compatible = "fsl,8548-memory-controller"; 159 compatible = "fsl,mpc8548-memory-controller";
160 reg = <0x2000 0x1000>; 160 reg = <0x2000 0x1000>;
161 interrupt-parent = <&mpic>; 161 interrupt-parent = <&mpic>;
162 interrupts = <0x12 0x2>; 162 interrupts = <0x12 0x2>;
163 }; 163 };
164 164
165 L2: l2-cache-controller@20000 { 165 L2: l2-cache-controller@20000 {
166 compatible = "fsl,8548-l2-cache-controller"; 166 compatible = "fsl,mpc8548-l2-cache-controller";
167 reg = <0x20000 0x1000>; 167 reg = <0x20000 0x1000>;
168 cache-line-size = <0x20>; // 32 bytes 168 cache-line-size = <0x20>; // 32 bytes
169 cache-size = <0x80000>; // L2, 512K 169 cache-size = <0x80000>; // L2, 512K
diff --git a/arch/powerpc/boot/dts/sbc8560.dts b/arch/powerpc/boot/dts/sbc8560.dts
index b772405a9a0a..c4564b81e473 100644
--- a/arch/powerpc/boot/dts/sbc8560.dts
+++ b/arch/powerpc/boot/dts/sbc8560.dts
@@ -61,14 +61,14 @@
61 clock-frequency = <0>; 61 clock-frequency = <0>;
62 62
63 memory-controller@2000 { 63 memory-controller@2000 {
64 compatible = "fsl,8560-memory-controller"; 64 compatible = "fsl,mpc8560-memory-controller";
65 reg = <0x2000 0x1000>; 65 reg = <0x2000 0x1000>;
66 interrupt-parent = <&mpic>; 66 interrupt-parent = <&mpic>;
67 interrupts = <0x12 0x2>; 67 interrupts = <0x12 0x2>;
68 }; 68 };
69 69
70 L2: l2-cache-controller@20000 { 70 L2: l2-cache-controller@20000 {
71 compatible = "fsl,8560-l2-cache-controller"; 71 compatible = "fsl,mpc8560-l2-cache-controller";
72 reg = <0x20000 0x1000>; 72 reg = <0x20000 0x1000>;
73 cache-line-size = <0x20>; // 32 bytes 73 cache-line-size = <0x20>; // 32 bytes
74 cache-size = <0x40000>; // L2, 256K 74 cache-size = <0x40000>; // L2, 256K
diff --git a/arch/powerpc/boot/dts/socrates.dts b/arch/powerpc/boot/dts/socrates.dts
index b8d0fc6f0042..7a6ae75a1e57 100644
--- a/arch/powerpc/boot/dts/socrates.dts
+++ b/arch/powerpc/boot/dts/socrates.dts
@@ -52,6 +52,7 @@
52 soc8544@e0000000 { 52 soc8544@e0000000 {
53 #address-cells = <1>; 53 #address-cells = <1>;
54 #size-cells = <1>; 54 #size-cells = <1>;
55 device_type = "soc";
55 56
56 ranges = <0x00000000 0xe0000000 0x00100000>; 57 ranges = <0x00000000 0xe0000000 0x00100000>;
57 reg = <0xe0000000 0x00001000>; // CCSRBAR 1M 58 reg = <0xe0000000 0x00001000>; // CCSRBAR 1M
@@ -78,11 +79,11 @@
78 #address-cells = <1>; 79 #address-cells = <1>;
79 #size-cells = <0>; 80 #size-cells = <0>;
80 cell-index = <0>; 81 cell-index = <0>;
81 compatible = "fsl-i2c"; 82 compatible = "fsl,mpc8544-i2c", "fsl-i2c";
82 reg = <0x3000 0x100>; 83 reg = <0x3000 0x100>;
83 interrupts = <43 2>; 84 interrupts = <43 2>;
84 interrupt-parent = <&mpic>; 85 interrupt-parent = <&mpic>;
85 dfsrr; 86 fsl,preserve-clocking;
86 87
87 dtt@28 { 88 dtt@28 {
88 compatible = "winbond,w83782d"; 89 compatible = "winbond,w83782d";
@@ -110,11 +111,11 @@
110 #address-cells = <1>; 111 #address-cells = <1>;
111 #size-cells = <0>; 112 #size-cells = <0>;
112 cell-index = <1>; 113 cell-index = <1>;
113 compatible = "fsl-i2c"; 114 compatible = "fsl,mpc8544-i2c", "fsl-i2c";
114 reg = <0x3100 0x100>; 115 reg = <0x3100 0x100>;
115 interrupts = <43 2>; 116 interrupts = <43 2>;
116 interrupt-parent = <&mpic>; 117 interrupt-parent = <&mpic>;
117 dfsrr; 118 fsl,preserve-clocking;
118 }; 119 };
119 120
120 enet0: ethernet@24000 { 121 enet0: ethernet@24000 {
diff --git a/arch/powerpc/boot/dts/stx_gp3_8560.dts b/arch/powerpc/boot/dts/stx_gp3_8560.dts
index 8b173957fb5f..ea6b15152de3 100644
--- a/arch/powerpc/boot/dts/stx_gp3_8560.dts
+++ b/arch/powerpc/boot/dts/stx_gp3_8560.dts
@@ -57,14 +57,14 @@
57 compatible = "fsl,mpc8560-immr", "simple-bus"; 57 compatible = "fsl,mpc8560-immr", "simple-bus";
58 58
59 memory-controller@2000 { 59 memory-controller@2000 {
60 compatible = "fsl,8540-memory-controller"; 60 compatible = "fsl,mpc8540-memory-controller";
61 reg = <0x2000 0x1000>; 61 reg = <0x2000 0x1000>;
62 interrupt-parent = <&mpic>; 62 interrupt-parent = <&mpic>;
63 interrupts = <18 2>; 63 interrupts = <18 2>;
64 }; 64 };
65 65
66 L2: l2-cache-controller@20000 { 66 L2: l2-cache-controller@20000 {
67 compatible = "fsl,8540-l2-cache-controller"; 67 compatible = "fsl,mpc8540-l2-cache-controller";
68 reg = <0x20000 0x1000>; 68 reg = <0x20000 0x1000>;
69 cache-line-size = <32>; 69 cache-line-size = <32>;
70 cache-size = <0x40000>; // L2, 256K 70 cache-size = <0x40000>; // L2, 256K
diff --git a/arch/powerpc/boot/dts/tqm8540.dts b/arch/powerpc/boot/dts/tqm8540.dts
index ac9413a29f9f..231bae756637 100644
--- a/arch/powerpc/boot/dts/tqm8540.dts
+++ b/arch/powerpc/boot/dts/tqm8540.dts
@@ -59,14 +59,14 @@
59 compatible = "fsl,mpc8540-immr", "simple-bus"; 59 compatible = "fsl,mpc8540-immr", "simple-bus";
60 60
61 memory-controller@2000 { 61 memory-controller@2000 {
62 compatible = "fsl,8540-memory-controller"; 62 compatible = "fsl,mpc8540-memory-controller";
63 reg = <0x2000 0x1000>; 63 reg = <0x2000 0x1000>;
64 interrupt-parent = <&mpic>; 64 interrupt-parent = <&mpic>;
65 interrupts = <18 2>; 65 interrupts = <18 2>;
66 }; 66 };
67 67
68 L2: l2-cache-controller@20000 { 68 L2: l2-cache-controller@20000 {
69 compatible = "fsl,8540-l2-cache-controller"; 69 compatible = "fsl,mpc8540-l2-cache-controller";
70 reg = <0x20000 0x1000>; 70 reg = <0x20000 0x1000>;
71 cache-line-size = <32>; 71 cache-line-size = <32>;
72 cache-size = <0x40000>; // L2, 256K 72 cache-size = <0x40000>; // L2, 256K
diff --git a/arch/powerpc/boot/dts/tqm8541.dts b/arch/powerpc/boot/dts/tqm8541.dts
index c71bb5dd5e5e..4356a1f08295 100644
--- a/arch/powerpc/boot/dts/tqm8541.dts
+++ b/arch/powerpc/boot/dts/tqm8541.dts
@@ -58,14 +58,14 @@
58 compatible = "fsl,mpc8541-immr", "simple-bus"; 58 compatible = "fsl,mpc8541-immr", "simple-bus";
59 59
60 memory-controller@2000 { 60 memory-controller@2000 {
61 compatible = "fsl,8540-memory-controller"; 61 compatible = "fsl,mpc8540-memory-controller";
62 reg = <0x2000 0x1000>; 62 reg = <0x2000 0x1000>;
63 interrupt-parent = <&mpic>; 63 interrupt-parent = <&mpic>;
64 interrupts = <18 2>; 64 interrupts = <18 2>;
65 }; 65 };
66 66
67 L2: l2-cache-controller@20000 { 67 L2: l2-cache-controller@20000 {
68 compatible = "fsl,8540-l2-cache-controller"; 68 compatible = "fsl,mpc8540-l2-cache-controller";
69 reg = <0x20000 0x1000>; 69 reg = <0x20000 0x1000>;
70 cache-line-size = <32>; 70 cache-line-size = <32>;
71 cache-size = <0x40000>; // L2, 256K 71 cache-size = <0x40000>; // L2, 256K
diff --git a/arch/powerpc/boot/dts/tqm8555.dts b/arch/powerpc/boot/dts/tqm8555.dts
index a133ded6dddb..06d366ebbda3 100644
--- a/arch/powerpc/boot/dts/tqm8555.dts
+++ b/arch/powerpc/boot/dts/tqm8555.dts
@@ -58,14 +58,14 @@
58 compatible = "fsl,mpc8555-immr", "simple-bus"; 58 compatible = "fsl,mpc8555-immr", "simple-bus";
59 59
60 memory-controller@2000 { 60 memory-controller@2000 {
61 compatible = "fsl,8540-memory-controller"; 61 compatible = "fsl,mpc8540-memory-controller";
62 reg = <0x2000 0x1000>; 62 reg = <0x2000 0x1000>;
63 interrupt-parent = <&mpic>; 63 interrupt-parent = <&mpic>;
64 interrupts = <18 2>; 64 interrupts = <18 2>;
65 }; 65 };
66 66
67 L2: l2-cache-controller@20000 { 67 L2: l2-cache-controller@20000 {
68 compatible = "fsl,8540-l2-cache-controller"; 68 compatible = "fsl,mpc8540-l2-cache-controller";
69 reg = <0x20000 0x1000>; 69 reg = <0x20000 0x1000>;
70 cache-line-size = <32>; 70 cache-line-size = <32>;
71 cache-size = <0x40000>; // L2, 256K 71 cache-size = <0x40000>; // L2, 256K
diff --git a/arch/powerpc/boot/dts/tqm8560.dts b/arch/powerpc/boot/dts/tqm8560.dts
index 649e2e576267..feff915e0492 100644
--- a/arch/powerpc/boot/dts/tqm8560.dts
+++ b/arch/powerpc/boot/dts/tqm8560.dts
@@ -60,14 +60,14 @@
60 compatible = "fsl,mpc8560-immr", "simple-bus"; 60 compatible = "fsl,mpc8560-immr", "simple-bus";
61 61
62 memory-controller@2000 { 62 memory-controller@2000 {
63 compatible = "fsl,8540-memory-controller"; 63 compatible = "fsl,mpc8540-memory-controller";
64 reg = <0x2000 0x1000>; 64 reg = <0x2000 0x1000>;
65 interrupt-parent = <&mpic>; 65 interrupt-parent = <&mpic>;
66 interrupts = <18 2>; 66 interrupts = <18 2>;
67 }; 67 };
68 68
69 L2: l2-cache-controller@20000 { 69 L2: l2-cache-controller@20000 {
70 compatible = "fsl,8540-l2-cache-controller"; 70 compatible = "fsl,mpc8540-l2-cache-controller";
71 reg = <0x20000 0x1000>; 71 reg = <0x20000 0x1000>;
72 cache-line-size = <32>; 72 cache-line-size = <32>;
73 cache-size = <0x40000>; // L2, 256K 73 cache-size = <0x40000>; // L2, 256K
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-28 03:53:00 -0500