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-rw-r--r--arch/powerpc/boot/dts/asp834x-redboot.dts282
-rw-r--r--arch/powerpc/boot/dts/bamboo.dts142
-rw-r--r--arch/powerpc/boot/dts/c2k.dts371
-rw-r--r--arch/powerpc/boot/dts/canyonlands.dts226
-rw-r--r--arch/powerpc/boot/dts/ebony.dts164
-rw-r--r--arch/powerpc/boot/dts/ep405.dts100
-rw-r--r--arch/powerpc/boot/dts/glacier.dts262
-rw-r--r--arch/powerpc/boot/dts/haleakala.dts138
-rw-r--r--arch/powerpc/boot/dts/holly.dts122
-rw-r--r--arch/powerpc/boot/dts/katmai.dts210
-rw-r--r--arch/powerpc/boot/dts/kilauea.dts186
-rw-r--r--arch/powerpc/boot/dts/ksi8560.dts64
-rw-r--r--arch/powerpc/boot/dts/makalu.dts186
-rw-r--r--arch/powerpc/boot/dts/mpc5121ads.dts310
-rw-r--r--arch/powerpc/boot/dts/mpc7448hpc2.dts2
-rw-r--r--arch/powerpc/boot/dts/mpc8272ads.dts32
-rw-r--r--arch/powerpc/boot/dts/mpc8313erdb.dts50
-rw-r--r--arch/powerpc/boot/dts/mpc8315erdb.dts50
-rw-r--r--arch/powerpc/boot/dts/mpc832x_mds.dts50
-rw-r--r--arch/powerpc/boot/dts/mpc832x_rdb.dts86
-rw-r--r--arch/powerpc/boot/dts/mpc8349emitx.dts47
-rw-r--r--arch/powerpc/boot/dts/mpc8349emitxgp.dts47
-rw-r--r--arch/powerpc/boot/dts/mpc834x_mds.dts50
-rw-r--r--arch/powerpc/boot/dts/mpc836x_mds.dts48
-rw-r--r--arch/powerpc/boot/dts/mpc836x_rdk.dts432
-rw-r--r--arch/powerpc/boot/dts/mpc8377_mds.dts69
-rw-r--r--arch/powerpc/boot/dts/mpc8377_rdb.dts49
-rw-r--r--arch/powerpc/boot/dts/mpc8378_mds.dts48
-rw-r--r--arch/powerpc/boot/dts/mpc8378_rdb.dts49
-rw-r--r--arch/powerpc/boot/dts/mpc8379_mds.dts48
-rw-r--r--arch/powerpc/boot/dts/mpc8379_rdb.dts49
-rw-r--r--arch/powerpc/boot/dts/mpc8536ds.dts432
-rw-r--r--arch/powerpc/boot/dts/mpc8540ads.dts46
-rw-r--r--arch/powerpc/boot/dts/mpc8541cds.dts57
-rw-r--r--arch/powerpc/boot/dts/mpc8544ds.dts32
-rw-r--r--arch/powerpc/boot/dts/mpc8548cds.dts57
-rw-r--r--arch/powerpc/boot/dts/mpc8555cds.dts57
-rw-r--r--arch/powerpc/boot/dts/mpc8560ads.dts44
-rw-r--r--arch/powerpc/boot/dts/mpc8568mds.dts60
-rw-r--r--arch/powerpc/boot/dts/mpc8572ds.dts116
-rw-r--r--arch/powerpc/boot/dts/mpc8610_hpcd.dts20
-rw-r--r--arch/powerpc/boot/dts/mpc8641_hpcn.dts43
-rw-r--r--arch/powerpc/boot/dts/mpc866ads.dts11
-rw-r--r--arch/powerpc/boot/dts/mpc885ads.dts11
-rw-r--r--arch/powerpc/boot/dts/ps3.dts16
-rw-r--r--arch/powerpc/boot/dts/rainier.dts163
-rw-r--r--arch/powerpc/boot/dts/sam440ep.dts293
-rw-r--r--arch/powerpc/boot/dts/sbc8349.dts49
-rw-r--r--arch/powerpc/boot/dts/sbc8548.dts57
-rw-r--r--arch/powerpc/boot/dts/sbc8560.dts46
-rw-r--r--arch/powerpc/boot/dts/sbc8641d.dts41
-rw-r--r--arch/powerpc/boot/dts/sequoia.dts172
-rw-r--r--arch/powerpc/boot/dts/storcenter.dts1
-rw-r--r--arch/powerpc/boot/dts/stx_gp3_8560.dts45
-rw-r--r--arch/powerpc/boot/dts/taishan.dts241
-rw-r--r--arch/powerpc/boot/dts/tqm5200.dts14
-rw-r--r--arch/powerpc/boot/dts/tqm8540.dts49
-rw-r--r--arch/powerpc/boot/dts/tqm8541.dts60
-rw-r--r--arch/powerpc/boot/dts/tqm8548-bigflash.dts406
-rw-r--r--arch/powerpc/boot/dts/tqm8548.dts411
-rw-r--r--arch/powerpc/boot/dts/tqm8555.dts60
-rw-r--r--arch/powerpc/boot/dts/tqm8560.dts114
-rw-r--r--arch/powerpc/boot/dts/virtex440-ml507.dts296
-rw-r--r--arch/powerpc/boot/dts/walnut.dts118
-rw-r--r--arch/powerpc/boot/dts/warp.dts145
-rw-r--r--arch/powerpc/boot/dts/yosemite.dts146
66 files changed, 6309 insertions, 1589 deletions
diff --git a/arch/powerpc/boot/dts/asp834x-redboot.dts b/arch/powerpc/boot/dts/asp834x-redboot.dts
new file mode 100644
index 000000000000..8b1bb0e41905
--- /dev/null
+++ b/arch/powerpc/boot/dts/asp834x-redboot.dts
@@ -0,0 +1,282 @@
1/*
2 * Analogue & Micro ASP8347 Device Tree Source
3 *
4 * Copyright 2008 Codehermit
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/dts-v1/;
13
14/ {
15 model = "Analogue & Micro ASP8347E";
16 compatible = "analogue-and-micro,asp8347e";
17 #address-cells = <1>;
18 #size-cells = <1>;
19
20 aliases {
21 ethernet0 = &enet0;
22 ethernet1 = &enet1;
23 serial0 = &serial0;
24 serial1 = &serial1;
25 };
26
27 cpus {
28 #address-cells = <1>;
29 #size-cells = <0>;
30
31 PowerPC,8347@0 {
32 device_type = "cpu";
33 reg = <0x0>;
34 d-cache-line-size = <32>;
35 i-cache-line-size = <32>;
36 d-cache-size = <32768>;
37 i-cache-size = <32768>;
38 timebase-frequency = <0>; // from bootloader
39 bus-frequency = <0>; // from bootloader
40 clock-frequency = <0>; // from bootloader
41 };
42 };
43
44 memory {
45 device_type = "memory";
46 reg = <0x00000000 0x8000000>; // 128MB at 0
47 };
48
49 localbus@ff005000 {
50 #address-cells = <2>;
51 #size-cells = <1>;
52 compatible = "fsl,mpc8347e-localbus",
53 "fsl,pq2pro-localbus",
54 "simple-bus";
55 reg = <0xff005000 0x1000>;
56 interrupts = <77 0x8>;
57 interrupt-parent = <&ipic>;
58
59 ranges = <
60 0 0 0xf0000000 0x02000000
61 >;
62
63 flash@0,0 {
64 compatible = "cfi-flash";
65 reg = <0 0 0x02000000>;
66 bank-width = <2>;
67 device-width = <2>;
68 };
69 };
70
71 soc8349@ff000000 {
72 #address-cells = <1>;
73 #size-cells = <1>;
74 device_type = "soc";
75 ranges = <0x0 0xff000000 0x00100000>;
76 reg = <0xff000000 0x00000200>;
77 bus-frequency = <0>;
78
79 wdt@200 {
80 device_type = "watchdog";
81 compatible = "mpc83xx_wdt";
82 reg = <0x200 0x100>;
83 };
84
85 i2c@3000 {
86 #address-cells = <1>;
87 #size-cells = <0>;
88 cell-index = <0>;
89 compatible = "fsl-i2c";
90 reg = <0x3000 0x100>;
91 interrupts = <14 0x8>;
92 interrupt-parent = <&ipic>;
93 dfsrr;
94
95 rtc@68 {
96 compatible = "dallas,ds1374";
97 reg = <0x68>;
98 };
99 };
100
101 i2c@3100 {
102 #address-cells = <1>;
103 #size-cells = <0>;
104 cell-index = <1>;
105 compatible = "fsl-i2c";
106 reg = <0x3100 0x100>;
107 interrupts = <15 0x8>;
108 interrupt-parent = <&ipic>;
109 dfsrr;
110 };
111
112 spi@7000 {
113 cell-index = <0>;
114 compatible = "fsl,spi";
115 reg = <0x7000 0x1000>;
116 interrupts = <16 0x8>;
117 interrupt-parent = <&ipic>;
118 mode = "cpu";
119 };
120
121 dma@82a8 {
122 #address-cells = <1>;
123 #size-cells = <1>;
124 compatible = "fsl,mpc8347-dma", "fsl,elo-dma";
125 reg = <0x82a8 4>;
126 ranges = <0 0x8100 0x1a8>;
127 interrupt-parent = <&ipic>;
128 interrupts = <71 8>;
129 cell-index = <0>;
130 dma-channel@0 {
131 compatible = "fsl,mpc8347-dma-channel", "fsl,elo-dma-channel";
132 reg = <0 0x80>;
133 interrupt-parent = <&ipic>;
134 interrupts = <71 8>;
135 };
136 dma-channel@80 {
137 compatible = "fsl,mpc8347-dma-channel", "fsl,elo-dma-channel";
138 reg = <0x80 0x80>;
139 interrupt-parent = <&ipic>;
140 interrupts = <71 8>;
141 };
142 dma-channel@100 {
143 compatible = "fsl,mpc8347-dma-channel", "fsl,elo-dma-channel";
144 reg = <0x100 0x80>;
145 interrupt-parent = <&ipic>;
146 interrupts = <71 8>;
147 };
148 dma-channel@180 {
149 compatible = "fsl,mpc8347-dma-channel", "fsl,elo-dma-channel";
150 reg = <0x180 0x28>;
151 interrupt-parent = <&ipic>;
152 interrupts = <71 8>;
153 };
154 };
155
156 /* phy type (ULPI or SERIAL) are only types supported for MPH */
157 /* port = 0 or 1 */
158 usb@22000 {
159 compatible = "fsl-usb2-mph";
160 reg = <0x22000 0x1000>;
161 #address-cells = <1>;
162 #size-cells = <0>;
163 interrupt-parent = <&ipic>;
164 interrupts = <39 0x8>;
165 phy_type = "ulpi";
166 port1;
167 };
168 /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
169 usb@23000 {
170 compatible = "fsl-usb2-dr";
171 reg = <0x23000 0x1000>;
172 #address-cells = <1>;
173 #size-cells = <0>;
174 interrupt-parent = <&ipic>;
175 interrupts = <38 0x8>;
176 dr_mode = "otg";
177 phy_type = "ulpi";
178 };
179
180 mdio@24520 {
181 #address-cells = <1>;
182 #size-cells = <0>;
183 compatible = "fsl,gianfar-mdio";
184 reg = <0x24520 0x20>;
185
186 phy0: ethernet-phy@0 {
187 interrupt-parent = <&ipic>;
188 interrupts = <17 0x8>;
189 reg = <0x1>;
190 device_type = "ethernet-phy";
191 };
192 phy1: ethernet-phy@1 {
193 interrupt-parent = <&ipic>;
194 interrupts = <18 0x8>;
195 reg = <0x2>;
196 device_type = "ethernet-phy";
197 };
198 };
199
200 enet0: ethernet@24000 {
201 cell-index = <0>;
202 device_type = "network";
203 model = "TSEC";
204 compatible = "gianfar";
205 reg = <0x24000 0x1000>;
206 local-mac-address = [ 00 08 e5 11 32 33 ];
207 interrupts = <32 0x8 33 0x8 34 0x8>;
208 interrupt-parent = <&ipic>;
209 phy-handle = <&phy0>;
210 linux,network-index = <0>;
211 };
212
213 enet1: ethernet@25000 {
214 cell-index = <1>;
215 device_type = "network";
216 model = "TSEC";
217 compatible = "gianfar";
218 reg = <0x25000 0x1000>;
219 local-mac-address = [ 00 08 e5 11 32 34 ];
220 interrupts = <35 0x8 36 0x8 37 0x8>;
221 interrupt-parent = <&ipic>;
222 phy-handle = <&phy1>;
223 linux,network-index = <1>;
224 };
225
226 serial0: serial@4500 {
227 cell-index = <0>;
228 device_type = "serial";
229 compatible = "ns16550";
230 reg = <0x4500 0x100>;
231 clock-frequency = <400000000>;
232 interrupts = <9 0x8>;
233 interrupt-parent = <&ipic>;
234 };
235
236 serial1: serial@4600 {
237 cell-index = <1>;
238 device_type = "serial";
239 compatible = "ns16550";
240 reg = <0x4600 0x100>;
241 clock-frequency = <400000000>;
242 interrupts = <10 0x8>;
243 interrupt-parent = <&ipic>;
244 };
245
246 /* May need to remove if on a part without crypto engine */
247 crypto@30000 {
248 device_type = "crypto";
249 model = "SEC2";
250 compatible = "talitos";
251 reg = <0x30000 0x10000>;
252 interrupts = <11 0x8>;
253 interrupt-parent = <&ipic>;
254 num-channels = <4>;
255 channel-fifo-len = <24>;
256 exec-units-mask = <0x0000007e>;
257 /* desc mask is for rev2.0,
258 * we need runtime fixup for >2.0 */
259 descriptor-types-mask = <0x01010ebf>;
260 };
261
262 /* IPIC
263 * interrupts cell = <intr #, sense>
264 * sense values match linux IORESOURCE_IRQ_* defines:
265 * sense == 8: Level, low assertion
266 * sense == 2: Edge, high-to-low change
267 */
268 ipic: pic@700 {
269 interrupt-controller;
270 #address-cells = <0>;
271 #interrupt-cells = <2>;
272 reg = <0x700 0x100>;
273 device_type = "ipic";
274 };
275 };
276
277 chosen {
278 bootargs = "console=ttyS0,38400 root=/dev/mtdblock3 rootfstype=jffs2";
279 linux,stdout-path = &serial0;
280 };
281
282};
diff --git a/arch/powerpc/boot/dts/bamboo.dts b/arch/powerpc/boot/dts/bamboo.dts
index ba2521bdaab1..6ce0cc2c0208 100644
--- a/arch/powerpc/boot/dts/bamboo.dts
+++ b/arch/powerpc/boot/dts/bamboo.dts
@@ -11,12 +11,14 @@
11 * any warranty of any kind, whether express or implied. 11 * any warranty of any kind, whether express or implied.
12 */ 12 */
13 13
14/dts-v1/;
15
14/ { 16/ {
15 #address-cells = <2>; 17 #address-cells = <2>;
16 #size-cells = <1>; 18 #size-cells = <1>;
17 model = "amcc,bamboo"; 19 model = "amcc,bamboo";
18 compatible = "amcc,bamboo"; 20 compatible = "amcc,bamboo";
19 dcr-parent = <&/cpus/cpu@0>; 21 dcr-parent = <&{/cpus/cpu@0}>;
20 22
21 aliases { 23 aliases {
22 ethernet0 = &EMAC0; 24 ethernet0 = &EMAC0;
@@ -34,13 +36,13 @@
34 cpu@0 { 36 cpu@0 {
35 device_type = "cpu"; 37 device_type = "cpu";
36 model = "PowerPC,440EP"; 38 model = "PowerPC,440EP";
37 reg = <0>; 39 reg = <0x00000000>;
38 clock-frequency = <0>; /* Filled in by zImage */ 40 clock-frequency = <0>; /* Filled in by zImage */
39 timebase-frequency = <0>; /* Filled in by zImage */ 41 timebase-frequency = <0>; /* Filled in by zImage */
40 i-cache-line-size = <20>; 42 i-cache-line-size = <32>;
41 d-cache-line-size = <20>; 43 d-cache-line-size = <32>;
42 i-cache-size = <8000>; 44 i-cache-size = <32768>;
43 d-cache-size = <8000>; 45 d-cache-size = <32768>;
44 dcr-controller; 46 dcr-controller;
45 dcr-access-method = "native"; 47 dcr-access-method = "native";
46 }; 48 };
@@ -48,14 +50,14 @@
48 50
49 memory { 51 memory {
50 device_type = "memory"; 52 device_type = "memory";
51 reg = <0 0 0>; /* Filled in by zImage */ 53 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by zImage */
52 }; 54 };
53 55
54 UIC0: interrupt-controller0 { 56 UIC0: interrupt-controller0 {
55 compatible = "ibm,uic-440ep","ibm,uic"; 57 compatible = "ibm,uic-440ep","ibm,uic";
56 interrupt-controller; 58 interrupt-controller;
57 cell-index = <0>; 59 cell-index = <0>;
58 dcr-reg = <0c0 009>; 60 dcr-reg = <0x0c0 0x009>;
59 #address-cells = <0>; 61 #address-cells = <0>;
60 #size-cells = <0>; 62 #size-cells = <0>;
61 #interrupt-cells = <2>; 63 #interrupt-cells = <2>;
@@ -65,22 +67,22 @@
65 compatible = "ibm,uic-440ep","ibm,uic"; 67 compatible = "ibm,uic-440ep","ibm,uic";
66 interrupt-controller; 68 interrupt-controller;
67 cell-index = <1>; 69 cell-index = <1>;
68 dcr-reg = <0d0 009>; 70 dcr-reg = <0x0d0 0x009>;
69 #address-cells = <0>; 71 #address-cells = <0>;
70 #size-cells = <0>; 72 #size-cells = <0>;
71 #interrupt-cells = <2>; 73 #interrupt-cells = <2>;
72 interrupts = <1e 4 1f 4>; /* cascade */ 74 interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
73 interrupt-parent = <&UIC0>; 75 interrupt-parent = <&UIC0>;
74 }; 76 };
75 77
76 SDR0: sdr { 78 SDR0: sdr {
77 compatible = "ibm,sdr-440ep"; 79 compatible = "ibm,sdr-440ep";
78 dcr-reg = <00e 002>; 80 dcr-reg = <0x00e 0x002>;
79 }; 81 };
80 82
81 CPR0: cpr { 83 CPR0: cpr {
82 compatible = "ibm,cpr-440ep"; 84 compatible = "ibm,cpr-440ep";
83 dcr-reg = <00c 002>; 85 dcr-reg = <0x00c 0x002>;
84 }; 86 };
85 87
86 plb { 88 plb {
@@ -92,29 +94,29 @@
92 94
93 SDRAM0: sdram { 95 SDRAM0: sdram {
94 compatible = "ibm,sdram-440ep", "ibm,sdram-405gp"; 96 compatible = "ibm,sdram-440ep", "ibm,sdram-405gp";
95 dcr-reg = <010 2>; 97 dcr-reg = <0x010 0x002>;
96 }; 98 };
97 99
98 DMA0: dma { 100 DMA0: dma {
99 compatible = "ibm,dma-440ep", "ibm,dma-440gp"; 101 compatible = "ibm,dma-440ep", "ibm,dma-440gp";
100 dcr-reg = <100 027>; 102 dcr-reg = <0x100 0x027>;
101 }; 103 };
102 104
103 MAL0: mcmal { 105 MAL0: mcmal {
104 compatible = "ibm,mcmal-440ep", "ibm,mcmal-440gp", "ibm,mcmal"; 106 compatible = "ibm,mcmal-440ep", "ibm,mcmal-440gp", "ibm,mcmal";
105 dcr-reg = <180 62>; 107 dcr-reg = <0x180 0x062>;
106 num-tx-chans = <4>; 108 num-tx-chans = <4>;
107 num-rx-chans = <2>; 109 num-rx-chans = <2>;
108 interrupt-parent = <&MAL0>; 110 interrupt-parent = <&MAL0>;
109 interrupts = <0 1 2 3 4>; 111 interrupts = <0x0 0x1 0x2 0x3 0x4>;
110 #interrupt-cells = <1>; 112 #interrupt-cells = <1>;
111 #address-cells = <0>; 113 #address-cells = <0>;
112 #size-cells = <0>; 114 #size-cells = <0>;
113 interrupt-map = </*TXEOB*/ 0 &UIC0 a 4 115 interrupt-map = </*TXEOB*/ 0x0 &UIC0 0xa 0x4
114 /*RXEOB*/ 1 &UIC0 b 4 116 /*RXEOB*/ 0x1 &UIC0 0xb 0x4
115 /*SERR*/ 2 &UIC1 0 4 117 /*SERR*/ 0x2 &UIC1 0x0 0x4
116 /*TXDE*/ 3 &UIC1 1 4 118 /*TXDE*/ 0x3 &UIC1 0x1 0x4
117 /*RXDE*/ 4 &UIC1 2 4>; 119 /*RXDE*/ 0x4 &UIC1 0x2 0x4>;
118 }; 120 };
119 121
120 POB0: opb { 122 POB0: opb {
@@ -124,101 +126,101 @@
124 /* Bamboo is oddball in the 44x world and doesn't use the ERPN 126 /* Bamboo is oddball in the 44x world and doesn't use the ERPN
125 * bits. 127 * bits.
126 */ 128 */
127 ranges = <00000000 0 00000000 80000000 129 ranges = <0x00000000 0x00000000 0x00000000 0x80000000
128 80000000 0 80000000 80000000>; 130 0x80000000 0x00000000 0x80000000 0x80000000>;
129 interrupt-parent = <&UIC1>; 131 interrupt-parent = <&UIC1>;
130 interrupts = <7 4>; 132 interrupts = <0x7 0x4>;
131 clock-frequency = <0>; /* Filled in by zImage */ 133 clock-frequency = <0>; /* Filled in by zImage */
132 134
133 EBC0: ebc { 135 EBC0: ebc {
134 compatible = "ibm,ebc-440ep", "ibm,ebc-440gp", "ibm,ebc"; 136 compatible = "ibm,ebc-440ep", "ibm,ebc-440gp", "ibm,ebc";
135 dcr-reg = <012 2>; 137 dcr-reg = <0x012 0x002>;
136 #address-cells = <2>; 138 #address-cells = <2>;
137 #size-cells = <1>; 139 #size-cells = <1>;
138 clock-frequency = <0>; /* Filled in by zImage */ 140 clock-frequency = <0>; /* Filled in by zImage */
139 interrupts = <5 1>; 141 interrupts = <0x5 0x1>;
140 interrupt-parent = <&UIC1>; 142 interrupt-parent = <&UIC1>;
141 }; 143 };
142 144
143 UART0: serial@ef600300 { 145 UART0: serial@ef600300 {
144 device_type = "serial"; 146 device_type = "serial";
145 compatible = "ns16550"; 147 compatible = "ns16550";
146 reg = <ef600300 8>; 148 reg = <0xef600300 0x00000008>;
147 virtual-reg = <ef600300>; 149 virtual-reg = <0xef600300>;
148 clock-frequency = <0>; /* Filled in by zImage */ 150 clock-frequency = <0>; /* Filled in by zImage */
149 current-speed = <1c200>; 151 current-speed = <115200>;
150 interrupt-parent = <&UIC0>; 152 interrupt-parent = <&UIC0>;
151 interrupts = <0 4>; 153 interrupts = <0x0 0x4>;
152 }; 154 };
153 155
154 UART1: serial@ef600400 { 156 UART1: serial@ef600400 {
155 device_type = "serial"; 157 device_type = "serial";
156 compatible = "ns16550"; 158 compatible = "ns16550";
157 reg = <ef600400 8>; 159 reg = <0xef600400 0x00000008>;
158 virtual-reg = <ef600400>; 160 virtual-reg = <0xef600400>;
159 clock-frequency = <0>; 161 clock-frequency = <0>;
160 current-speed = <0>; 162 current-speed = <0>;
161 interrupt-parent = <&UIC0>; 163 interrupt-parent = <&UIC0>;
162 interrupts = <1 4>; 164 interrupts = <0x1 0x4>;
163 }; 165 };
164 166
165 UART2: serial@ef600500 { 167 UART2: serial@ef600500 {
166 device_type = "serial"; 168 device_type = "serial";
167 compatible = "ns16550"; 169 compatible = "ns16550";
168 reg = <ef600500 8>; 170 reg = <0xef600500 0x00000008>;
169 virtual-reg = <ef600500>; 171 virtual-reg = <0xef600500>;
170 clock-frequency = <0>; 172 clock-frequency = <0>;
171 current-speed = <0>; 173 current-speed = <0>;
172 interrupt-parent = <&UIC0>; 174 interrupt-parent = <&UIC0>;
173 interrupts = <3 4>; 175 interrupts = <0x3 0x4>;
174 }; 176 };
175 177
176 UART3: serial@ef600600 { 178 UART3: serial@ef600600 {
177 device_type = "serial"; 179 device_type = "serial";
178 compatible = "ns16550"; 180 compatible = "ns16550";
179 reg = <ef600600 8>; 181 reg = <0xef600600 0x00000008>;
180 virtual-reg = <ef600600>; 182 virtual-reg = <0xef600600>;
181 clock-frequency = <0>; 183 clock-frequency = <0>;
182 current-speed = <0>; 184 current-speed = <0>;
183 interrupt-parent = <&UIC0>; 185 interrupt-parent = <&UIC0>;
184 interrupts = <4 4>; 186 interrupts = <0x4 0x4>;
185 }; 187 };
186 188
187 IIC0: i2c@ef600700 { 189 IIC0: i2c@ef600700 {
188 compatible = "ibm,iic-440ep", "ibm,iic-440gp", "ibm,iic"; 190 compatible = "ibm,iic-440ep", "ibm,iic-440gp", "ibm,iic";
189 reg = <ef600700 14>; 191 reg = <0xef600700 0x00000014>;
190 interrupt-parent = <&UIC0>; 192 interrupt-parent = <&UIC0>;
191 interrupts = <2 4>; 193 interrupts = <0x2 0x4>;
192 }; 194 };
193 195
194 IIC1: i2c@ef600800 { 196 IIC1: i2c@ef600800 {
195 compatible = "ibm,iic-440ep", "ibm,iic-440gp", "ibm,iic"; 197 compatible = "ibm,iic-440ep", "ibm,iic-440gp", "ibm,iic";
196 reg = <ef600800 14>; 198 reg = <0xef600800 0x00000014>;
197 interrupt-parent = <&UIC0>; 199 interrupt-parent = <&UIC0>;
198 interrupts = <7 4>; 200 interrupts = <0x7 0x4>;
199 }; 201 };
200 202
201 ZMII0: emac-zmii@ef600d00 { 203 ZMII0: emac-zmii@ef600d00 {
202 compatible = "ibm,zmii-440ep", "ibm,zmii-440gp", "ibm,zmii"; 204 compatible = "ibm,zmii-440ep", "ibm,zmii-440gp", "ibm,zmii";
203 reg = <ef600d00 c>; 205 reg = <0xef600d00 0x0000000c>;
204 }; 206 };
205 207
206 EMAC0: ethernet@ef600e00 { 208 EMAC0: ethernet@ef600e00 {
207 device_type = "network"; 209 device_type = "network";
208 compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac"; 210 compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac";
209 interrupt-parent = <&UIC1>; 211 interrupt-parent = <&UIC1>;
210 interrupts = <1c 4 1d 4>; 212 interrupts = <0x1c 0x4 0x1d 0x4>;
211 reg = <ef600e00 70>; 213 reg = <0xef600e00 0x00000070>;
212 local-mac-address = [000000000000]; 214 local-mac-address = [000000000000];
213 mal-device = <&MAL0>; 215 mal-device = <&MAL0>;
214 mal-tx-channel = <0 1>; 216 mal-tx-channel = <0 1>;
215 mal-rx-channel = <0>; 217 mal-rx-channel = <0>;
216 cell-index = <0>; 218 cell-index = <0>;
217 max-frame-size = <5dc>; 219 max-frame-size = <1500>;
218 rx-fifo-size = <1000>; 220 rx-fifo-size = <4096>;
219 tx-fifo-size = <800>; 221 tx-fifo-size = <2048>;
220 phy-mode = "rmii"; 222 phy-mode = "rmii";
221 phy-map = <00000000>; 223 phy-map = <0x00000000>;
222 zmii-device = <&ZMII0>; 224 zmii-device = <&ZMII0>;
223 zmii-channel = <0>; 225 zmii-channel = <0>;
224 }; 226 };
@@ -227,26 +229,26 @@
227 device_type = "network"; 229 device_type = "network";
228 compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac"; 230 compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac";
229 interrupt-parent = <&UIC1>; 231 interrupt-parent = <&UIC1>;
230 interrupts = <1e 4 1f 4>; 232 interrupts = <0x1e 0x4 0x1f 0x4>;
231 reg = <ef600f00 70>; 233 reg = <0xef600f00 0x00000070>;
232 local-mac-address = [000000000000]; 234 local-mac-address = [000000000000];
233 mal-device = <&MAL0>; 235 mal-device = <&MAL0>;
234 mal-tx-channel = <2 3>; 236 mal-tx-channel = <2 3>;
235 mal-rx-channel = <1>; 237 mal-rx-channel = <1>;
236 cell-index = <1>; 238 cell-index = <1>;
237 max-frame-size = <5dc>; 239 max-frame-size = <1500>;
238 rx-fifo-size = <1000>; 240 rx-fifo-size = <4096>;
239 tx-fifo-size = <800>; 241 tx-fifo-size = <2048>;
240 phy-mode = "rmii"; 242 phy-mode = "rmii";
241 phy-map = <00000000>; 243 phy-map = <0x00000000>;
242 zmii-device = <&ZMII0>; 244 zmii-device = <&ZMII0>;
243 zmii-channel = <1>; 245 zmii-channel = <1>;
244 }; 246 };
245 247
246 usb@ef601000 { 248 usb@ef601000 {
247 compatible = "ohci-be"; 249 compatible = "ohci-be";
248 reg = <ef601000 80>; 250 reg = <0xef601000 0x00000080>;
249 interrupts = <8 1 9 1>; 251 interrupts = <0x8 0x1 0x9 0x1>;
250 interrupt-parent = < &UIC1 >; 252 interrupt-parent = < &UIC1 >;
251 }; 253 };
252 }; 254 };
@@ -258,35 +260,35 @@
258 #address-cells = <3>; 260 #address-cells = <3>;
259 compatible = "ibm,plb440ep-pci", "ibm,plb-pci"; 261 compatible = "ibm,plb440ep-pci", "ibm,plb-pci";
260 primary; 262 primary;
261 reg = <0 eec00000 8 /* Config space access */ 263 reg = <0x00000000 0xeec00000 0x00000008 /* Config space access */
262 0 eed00000 4 /* IACK */ 264 0x00000000 0xeed00000 0x00000004 /* IACK */
263 0 eed00000 4 /* Special cycle */ 265 0x00000000 0xeed00000 0x00000004 /* Special cycle */
264 0 ef400000 40>; /* Internal registers */ 266 0x00000000 0xef400000 0x00000040>; /* Internal registers */
265 267
266 /* Outbound ranges, one memory and one IO, 268 /* Outbound ranges, one memory and one IO,
267 * later cannot be changed. Chip supports a second 269 * later cannot be changed. Chip supports a second
268 * IO range but we don't use it for now 270 * IO range but we don't use it for now
269 */ 271 */
270 ranges = <02000000 0 a0000000 0 a0000000 0 20000000 272 ranges = <0x02000000 0x00000000 0xa0000000 0x00000000 0xa0000000 0x00000000 0x20000000
271 01000000 0 00000000 0 e8000000 0 00010000>; 273 0x01000000 0x00000000 0x00000000 0x00000000 0xe8000000 0x00000000 0x00010000>;
272 274
273 /* Inbound 2GB range starting at 0 */ 275 /* Inbound 2GB range starting at 0 */
274 dma-ranges = <42000000 0 0 0 0 0 80000000>; 276 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
275 277
276 /* Bamboo has all 4 IRQ pins tied together per slot */ 278 /* Bamboo has all 4 IRQ pins tied together per slot */
277 interrupt-map-mask = <f800 0 0 0>; 279 interrupt-map-mask = <0xf800 0x0 0x0 0x0>;
278 interrupt-map = < 280 interrupt-map = <
279 /* IDSEL 1 */ 281 /* IDSEL 1 */
280 0800 0 0 0 &UIC0 1c 8 282 0x800 0x0 0x0 0x0 &UIC0 0x1c 0x8
281 283
282 /* IDSEL 2 */ 284 /* IDSEL 2 */
283 1000 0 0 0 &UIC0 1b 8 285 0x1000 0x0 0x0 0x0 &UIC0 0x1b 0x8
284 286
285 /* IDSEL 3 */ 287 /* IDSEL 3 */
286 1800 0 0 0 &UIC0 1a 8 288 0x1800 0x0 0x0 0x0 &UIC0 0x1a 0x8
287 289
288 /* IDSEL 4 */ 290 /* IDSEL 4 */
289 2000 0 0 0 &UIC0 19 8 291 0x2000 0x0 0x0 0x0 &UIC0 0x19 0x8
290 >; 292 >;
291 }; 293 };
292 }; 294 };
diff --git a/arch/powerpc/boot/dts/c2k.dts b/arch/powerpc/boot/dts/c2k.dts
new file mode 100644
index 000000000000..f5d625fa3e52
--- /dev/null
+++ b/arch/powerpc/boot/dts/c2k.dts
@@ -0,0 +1,371 @@
1/* Device Tree Source for GEFanuc C2K
2 *
3 * Author: Remi Machet <rmachet@slac.stanford.edu>
4 *
5 * Originated from prpmc2800.dts
6 *
7 * 2008 (c) Stanford University
8 * 2007 (c) MontaVista, Software, Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published
12 * by the Free Software Foundation.
13 */
14
15/dts-v1/;
16
17/ {
18 #address-cells = <1>;
19 #size-cells = <1>;
20 model = "C2K";
21 compatible = "GEFanuc,C2K";
22 coherency-off;
23
24 aliases {
25 pci0 = &PCI0;
26 pci1 = &PCI1;
27 };
28
29 cpus {
30 #address-cells = <1>;
31 #size-cells = <0>;
32
33 cpu@0 {
34 device_type = "cpu";
35 compatible = "PowerPC,7447";
36 reg = <0>;
37 clock-frequency = <996000000>; /* 996 MHz */
38 bus-frequency = <166666667>; /* 166.6666 MHz */
39 timebase-frequency = <41666667>; /* 166.6666/4 MHz */
40 i-cache-line-size = <32>;
41 d-cache-line-size = <32>;
42 i-cache-size = <32768>;
43 d-cache-size = <32768>;
44 };
45 };
46
47 memory {
48 device_type = "memory";
49 reg = <0x00000000 0x40000000>; /* 1GB */
50 };
51
52 system-controller@d8000000 { /* Marvell Discovery */
53 #address-cells = <1>;
54 #size-cells = <1>;
55 model = "mv64460";
56 compatible = "marvell,mv64360";
57 clock-frequency = <166666667>; /* 166.66... MHz */
58 reg = <0xd8000000 0x00010000>;
59 virtual-reg = <0xd8000000>;
60 ranges = <0xd4000000 0xd4000000 0x01000000 /* PCI 0 I/O Space */
61 0x80000000 0x80000000 0x08000000 /* PCI 0 MEM Space */
62 0xd0000000 0xd0000000 0x01000000 /* PCI 1 I/O Space */
63 0xa0000000 0xa0000000 0x08000000 /* PCI 1 MEM Space */
64 0xd8100000 0xd8100000 0x00010000 /* FPGA */
65 0xd8110000 0xd8110000 0x00010000 /* FPGA USARTs */
66 0xf8000000 0xf8000000 0x08000000 /* User FLASH */
67 0x00000000 0xd8000000 0x00010000 /* Bridge's regs */
68 0xd8140000 0xd8140000 0x00040000>; /* Integrated SRAM */
69
70 mdio@2000 {
71 #address-cells = <1>;
72 #size-cells = <0>;
73 compatible = "marvell,mv64360-mdio";
74 reg = <0x2000 4>;
75 PHY0: ethernet-phy@0 {
76 device_type = "ethernet-phy";
77 interrupts = <76>; /* GPP 12 */
78 interrupt-parent = <&PIC>;
79 reg = <0>;
80 };
81 PHY1: ethernet-phy@1 {
82 device_type = "ethernet-phy";
83 interrupts = <76>; /* GPP 12 */
84 interrupt-parent = <&PIC>;
85 reg = <1>;
86 };
87 PHY2: ethernet-phy@2 {
88 device_type = "ethernet-phy";
89 interrupts = <76>; /* GPP 12 */
90 interrupt-parent = <&PIC>;
91 reg = <2>;
92 };
93 };
94
95 ethernet-group@2000 {
96 #address-cells = <1>;
97 #size-cells = <0>;
98 compatible = "marvell,mv64360-eth-group";
99 reg = <0x2000 0x2000>;
100 ethernet@0 {
101 device_type = "network";
102 compatible = "marvell,mv64360-eth";
103 reg = <0>;
104 interrupts = <32>;
105 interrupt-parent = <&PIC>;
106 phy = <&PHY0>;
107 local-mac-address = [ 00 00 00 00 00 00 ];
108 };
109 ethernet@1 {
110 device_type = "network";
111 compatible = "marvell,mv64360-eth";
112 reg = <1>;
113 interrupts = <33>;
114 interrupt-parent = <&PIC>;
115 phy = <&PHY1>;
116 local-mac-address = [ 00 00 00 00 00 00 ];
117 };
118 ethernet@2 {
119 device_type = "network";
120 compatible = "marvell,mv64360-eth";
121 reg = <2>;
122 interrupts = <34>;
123 interrupt-parent = <&PIC>;
124 phy = <&PHY2>;
125 local-mac-address = [ 00 00 00 00 00 00 ];
126 };
127 };
128
129 SDMA0: sdma@4000 {
130 compatible = "marvell,mv64360-sdma";
131 reg = <0x4000 0xc18>;
132 virtual-reg = <0xd8004000>;
133 interrupt-base = <0>;
134 interrupts = <36>;
135 interrupt-parent = <&PIC>;
136 };
137
138 SDMA1: sdma@6000 {
139 compatible = "marvell,mv64360-sdma";
140 reg = <0x6000 0xc18>;
141 virtual-reg = <0xd8006000>;
142 interrupt-base = <0>;
143 interrupts = <38>;
144 interrupt-parent = <&PIC>;
145 };
146
147 BRG0: brg@b200 {
148 compatible = "marvell,mv64360-brg";
149 reg = <0xb200 0x8>;
150 clock-src = <8>;
151 clock-frequency = <133333333>;
152 current-speed = <115200>;
153 };
154
155 BRG1: brg@b208 {
156 compatible = "marvell,mv64360-brg";
157 reg = <0xb208 0x8>;
158 clock-src = <8>;
159 clock-frequency = <133333333>;
160 current-speed = <115200>;
161 };
162
163 CUNIT: cunit@f200 {
164 reg = <0xf200 0x200>;
165 };
166
167 MPSCROUTING: mpscrouting@b400 {
168 reg = <0xb400 0xc>;
169 };
170
171 MPSCINTR: mpscintr@b800 {
172 reg = <0xb800 0x100>;
173 virtual-reg = <0xd800b800>;
174 };
175
176 MPSC0: mpsc@8000 {
177 device_type = "serial";
178 compatible = "marvell,mv64360-mpsc";
179 reg = <0x8000 0x38>;
180 virtual-reg = <0xd8008000>;
181 sdma = <&SDMA0>;
182 brg = <&BRG0>;
183 cunit = <&CUNIT>;
184 mpscrouting = <&MPSCROUTING>;
185 mpscintr = <&MPSCINTR>;
186 cell-index = <0>;
187 interrupts = <40>;
188 interrupt-parent = <&PIC>;
189 };
190
191 MPSC1: mpsc@9000 {
192 device_type = "serial";
193 compatible = "marvell,mv64360-mpsc";
194 reg = <0x9000 0x38>;
195 virtual-reg = <0xd8009000>;
196 sdma = <&SDMA1>;
197 brg = <&BRG1>;
198 cunit = <&CUNIT>;
199 mpscrouting = <&MPSCROUTING>;
200 mpscintr = <&MPSCINTR>;
201 cell-index = <1>;
202 interrupts = <42>;
203 interrupt-parent = <&PIC>;
204 };
205
206 wdt@b410 { /* watchdog timer */
207 compatible = "marvell,mv64360-wdt";
208 reg = <0xb410 0x8>;
209 };
210
211 i2c@c000 {
212 compatible = "marvell,mv64360-i2c";
213 reg = <0xc000 0x20>;
214 virtual-reg = <0xd800c000>;
215 interrupts = <37>;
216 interrupt-parent = <&PIC>;
217 };
218
219 PIC: pic {
220 #interrupt-cells = <1>;
221 #address-cells = <0>;
222 compatible = "marvell,mv64360-pic";
223 reg = <0x0000 0x88>;
224 interrupt-controller;
225 };
226
227 mpp@f000 {
228 compatible = "marvell,mv64360-mpp";
229 reg = <0xf000 0x10>;
230 };
231
232 gpp@f100 {
233 compatible = "marvell,mv64360-gpp";
234 reg = <0xf100 0x20>;
235 };
236
237 PCI0: pci@80000000 {
238 #address-cells = <3>;
239 #size-cells = <2>;
240 #interrupt-cells = <1>;
241 device_type = "pci";
242 compatible = "marvell,mv64360-pci";
243 reg = <0x0cf8 0x8>;
244 ranges = <0x01000000 0x0 0x00000000 0xd4000000 0x0 0x01000000
245 0x02000000 0x0 0x80000000 0x80000000 0x0 0x08000000>;
246 bus-range = <0 255>;
247 clock-frequency = <66000000>;
248 interrupt-pci-iack = <0x0c34>;
249 interrupt-parent = <&PIC>;
250 interrupt-map-mask = <0x0000 0x0 0x0 0x7>;
251 interrupt-map = <
252 /* Only one interrupt line for PMC0 slot (INTA) */
253 0x0000 0 0 1 &PIC 88
254 >;
255 };
256
257
258 PCI1: pci@a0000000 {
259 #address-cells = <3>;
260 #size-cells = <2>;
261 #interrupt-cells = <1>;
262 device_type = "pci";
263 compatible = "marvell,mv64360-pci";
264 reg = <0x0c78 0x8>;
265 ranges = <0x01000000 0x0 0x00000000 0xd0000000 0x0 0x01000000
266 0x02000000 0x0 0x80000000 0xa0000000 0x0 0x08000000>;
267 bus-range = <0 255>;
268 clock-frequency = <66000000>;
269 interrupt-pci-iack = <0x0cb4>;
270 interrupt-parent = <&PIC>;
271 interrupt-map-mask = <0xf800 0x00 0x00 0x7>;
272 interrupt-map = <
273 /* IDSEL 0x01: PMC1 ? */
274 0x0800 0 0 1 &PIC 88
275 /* IDSEL 0x02: cPCI bridge */
276 0x1000 0 0 1 &PIC 88
277 /* IDSEL 0x03: USB controller */
278 0x1800 0 0 1 &PIC 91
279 /* IDSEL 0x04: SATA controller */
280 0x2000 0 0 1 &PIC 95
281 >;
282 };
283
284 cpu-error@0070 {
285 compatible = "marvell,mv64360-cpu-error";
286 reg = <0x0070 0x10 0x0128 0x28>;
287 interrupts = <3>;
288 interrupt-parent = <&PIC>;
289 };
290
291 sram-ctrl@0380 {
292 compatible = "marvell,mv64360-sram-ctrl";
293 reg = <0x0380 0x80>;
294 interrupts = <13>;
295 interrupt-parent = <&PIC>;
296 };
297
298 pci-error@1d40 {
299 compatible = "marvell,mv64360-pci-error";
300 reg = <0x1d40 0x40 0x0c28 0x4>;
301 interrupts = <12>;
302 interrupt-parent = <&PIC>;
303 };
304
305 pci-error@1dc0 {
306 compatible = "marvell,mv64360-pci-error";
307 reg = <0x1dc0 0x40 0x0ca8 0x4>;
308 interrupts = <16>;
309 interrupt-parent = <&PIC>;
310 };
311
312 mem-ctrl@1400 {
313 compatible = "marvell,mv64360-mem-ctrl";
314 reg = <0x1400 0x60>;
315 interrupts = <17>;
316 interrupt-parent = <&PIC>;
317 };
318 /* Devices attached to the device controller */
319 devicebus@045c {
320 #address-cells = <2>;
321 #size-cells = <1>;
322 compatible = "marvell,mv64306-devctrl";
323 reg = <0x45C 0x88>;
324 interrupts = <1>;
325 interrupt-parent = <&PIC>;
326 ranges = <0 0 0xd8100000 0x10000
327 2 0 0xd8110000 0x10000
328 4 0 0xf8000000 0x8000000>;
329 fpga@0,0 {
330 compatible = "sbs,fpga-c2k";
331 reg = <0 0 0x10000>;
332 };
333 fpga_usart@2,0 {
334 compatible = "sbs,fpga_usart-c2k";
335 reg = <2 0 0x10000>;
336 };
337 nor_flash@4,0 {
338 compatible = "cfi-flash";
339 reg = <4 0 0x8000000>; /* 128MB */
340 bank-width = <4>;
341 device-width = <1>;
342 #address-cells = <1>;
343 #size-cells = <1>;
344 partition@0 {
345 label = "boot";
346 reg = <0x00000000 0x00080000>;
347 };
348 partition@40000 {
349 label = "kernel";
350 reg = <0x00080000 0x00400000>;
351 };
352 partition@440000 {
353 label = "initrd";
354 reg = <0x00480000 0x00B80000>;
355 };
356 partition@1000000 {
357 label = "rootfs";
358 reg = <0x01000000 0x06800000>;
359 };
360 partition@7800000 {
361 label = "recovery";
362 reg = <0x07800000 0x00800000>;
363 read-only;
364 };
365 };
366 };
367 };
368 chosen {
369 linux,stdout-path = &MPSC0;
370 };
371};
diff --git a/arch/powerpc/boot/dts/canyonlands.dts b/arch/powerpc/boot/dts/canyonlands.dts
index 39634124929b..79fe412c11c9 100644
--- a/arch/powerpc/boot/dts/canyonlands.dts
+++ b/arch/powerpc/boot/dts/canyonlands.dts
@@ -8,12 +8,14 @@
8 * any warranty of any kind, whether express or implied. 8 * any warranty of any kind, whether express or implied.
9 */ 9 */
10 10
11/dts-v1/;
12
11/ { 13/ {
12 #address-cells = <2>; 14 #address-cells = <2>;
13 #size-cells = <1>; 15 #size-cells = <1>;
14 model = "amcc,canyonlands"; 16 model = "amcc,canyonlands";
15 compatible = "amcc,canyonlands"; 17 compatible = "amcc,canyonlands";
16 dcr-parent = <&/cpus/cpu@0>; 18 dcr-parent = <&{/cpus/cpu@0}>;
17 19
18 aliases { 20 aliases {
19 ethernet0 = &EMAC0; 21 ethernet0 = &EMAC0;
@@ -29,13 +31,13 @@
29 cpu@0 { 31 cpu@0 {
30 device_type = "cpu"; 32 device_type = "cpu";
31 model = "PowerPC,460EX"; 33 model = "PowerPC,460EX";
32 reg = <0>; 34 reg = <0x00000000>;
33 clock-frequency = <0>; /* Filled in by U-Boot */ 35 clock-frequency = <0>; /* Filled in by U-Boot */
34 timebase-frequency = <0>; /* Filled in by U-Boot */ 36 timebase-frequency = <0>; /* Filled in by U-Boot */
35 i-cache-line-size = <20>; 37 i-cache-line-size = <32>;
36 d-cache-line-size = <20>; 38 d-cache-line-size = <32>;
37 i-cache-size = <8000>; 39 i-cache-size = <32768>;
38 d-cache-size = <8000>; 40 d-cache-size = <32768>;
39 dcr-controller; 41 dcr-controller;
40 dcr-access-method = "native"; 42 dcr-access-method = "native";
41 }; 43 };
@@ -43,14 +45,14 @@
43 45
44 memory { 46 memory {
45 device_type = "memory"; 47 device_type = "memory";
46 reg = <0 0 0>; /* Filled in by U-Boot */ 48 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
47 }; 49 };
48 50
49 UIC0: interrupt-controller0 { 51 UIC0: interrupt-controller0 {
50 compatible = "ibm,uic-460ex","ibm,uic"; 52 compatible = "ibm,uic-460ex","ibm,uic";
51 interrupt-controller; 53 interrupt-controller;
52 cell-index = <0>; 54 cell-index = <0>;
53 dcr-reg = <0c0 009>; 55 dcr-reg = <0x0c0 0x009>;
54 #address-cells = <0>; 56 #address-cells = <0>;
55 #size-cells = <0>; 57 #size-cells = <0>;
56 #interrupt-cells = <2>; 58 #interrupt-cells = <2>;
@@ -60,11 +62,11 @@
60 compatible = "ibm,uic-460ex","ibm,uic"; 62 compatible = "ibm,uic-460ex","ibm,uic";
61 interrupt-controller; 63 interrupt-controller;
62 cell-index = <1>; 64 cell-index = <1>;
63 dcr-reg = <0d0 009>; 65 dcr-reg = <0x0d0 0x009>;
64 #address-cells = <0>; 66 #address-cells = <0>;
65 #size-cells = <0>; 67 #size-cells = <0>;
66 #interrupt-cells = <2>; 68 #interrupt-cells = <2>;
67 interrupts = <1e 4 1f 4>; /* cascade */ 69 interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
68 interrupt-parent = <&UIC0>; 70 interrupt-parent = <&UIC0>;
69 }; 71 };
70 72
@@ -72,11 +74,11 @@
72 compatible = "ibm,uic-460ex","ibm,uic"; 74 compatible = "ibm,uic-460ex","ibm,uic";
73 interrupt-controller; 75 interrupt-controller;
74 cell-index = <2>; 76 cell-index = <2>;
75 dcr-reg = <0e0 009>; 77 dcr-reg = <0x0e0 0x009>;
76 #address-cells = <0>; 78 #address-cells = <0>;
77 #size-cells = <0>; 79 #size-cells = <0>;
78 #interrupt-cells = <2>; 80 #interrupt-cells = <2>;
79 interrupts = <a 4 b 4>; /* cascade */ 81 interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
80 interrupt-parent = <&UIC0>; 82 interrupt-parent = <&UIC0>;
81 }; 83 };
82 84
@@ -84,22 +86,22 @@
84 compatible = "ibm,uic-460ex","ibm,uic"; 86 compatible = "ibm,uic-460ex","ibm,uic";
85 interrupt-controller; 87 interrupt-controller;
86 cell-index = <3>; 88 cell-index = <3>;
87 dcr-reg = <0f0 009>; 89 dcr-reg = <0x0f0 0x009>;
88 #address-cells = <0>; 90 #address-cells = <0>;
89 #size-cells = <0>; 91 #size-cells = <0>;
90 #interrupt-cells = <2>; 92 #interrupt-cells = <2>;
91 interrupts = <10 4 11 4>; /* cascade */ 93 interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
92 interrupt-parent = <&UIC0>; 94 interrupt-parent = <&UIC0>;
93 }; 95 };
94 96
95 SDR0: sdr { 97 SDR0: sdr {
96 compatible = "ibm,sdr-460ex"; 98 compatible = "ibm,sdr-460ex";
97 dcr-reg = <00e 002>; 99 dcr-reg = <0x00e 0x002>;
98 }; 100 };
99 101
100 CPR0: cpr { 102 CPR0: cpr {
101 compatible = "ibm,cpr-460ex"; 103 compatible = "ibm,cpr-460ex";
102 dcr-reg = <00c 002>; 104 dcr-reg = <0x00c 0x002>;
103 }; 105 };
104 106
105 plb { 107 plb {
@@ -111,74 +113,74 @@
111 113
112 SDRAM0: sdram { 114 SDRAM0: sdram {
113 compatible = "ibm,sdram-460ex", "ibm,sdram-405gp"; 115 compatible = "ibm,sdram-460ex", "ibm,sdram-405gp";
114 dcr-reg = <010 2>; 116 dcr-reg = <0x010 0x002>;
115 }; 117 };
116 118
117 MAL0: mcmal { 119 MAL0: mcmal {
118 compatible = "ibm,mcmal-460ex", "ibm,mcmal2"; 120 compatible = "ibm,mcmal-460ex", "ibm,mcmal2";
119 dcr-reg = <180 62>; 121 dcr-reg = <0x180 0x062>;
120 num-tx-chans = <2>; 122 num-tx-chans = <2>;
121 num-rx-chans = <10>; 123 num-rx-chans = <16>;
122 #address-cells = <0>; 124 #address-cells = <0>;
123 #size-cells = <0>; 125 #size-cells = <0>;
124 interrupt-parent = <&UIC2>; 126 interrupt-parent = <&UIC2>;
125 interrupts = < /*TXEOB*/ 6 4 127 interrupts = < /*TXEOB*/ 0x6 0x4
126 /*RXEOB*/ 7 4 128 /*RXEOB*/ 0x7 0x4
127 /*SERR*/ 3 4 129 /*SERR*/ 0x3 0x4
128 /*TXDE*/ 4 4 130 /*TXDE*/ 0x4 0x4
129 /*RXDE*/ 5 4>; 131 /*RXDE*/ 0x5 0x4>;
130 }; 132 };
131 133
132 POB0: opb { 134 POB0: opb {
133 compatible = "ibm,opb-460ex", "ibm,opb"; 135 compatible = "ibm,opb-460ex", "ibm,opb";
134 #address-cells = <1>; 136 #address-cells = <1>;
135 #size-cells = <1>; 137 #size-cells = <1>;
136 ranges = <b0000000 4 b0000000 50000000>; 138 ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>;
137 clock-frequency = <0>; /* Filled in by U-Boot */ 139 clock-frequency = <0>; /* Filled in by U-Boot */
138 140
139 EBC0: ebc { 141 EBC0: ebc {
140 compatible = "ibm,ebc-460ex", "ibm,ebc"; 142 compatible = "ibm,ebc-460ex", "ibm,ebc";
141 dcr-reg = <012 2>; 143 dcr-reg = <0x012 0x002>;
142 #address-cells = <2>; 144 #address-cells = <2>;
143 #size-cells = <1>; 145 #size-cells = <1>;
144 clock-frequency = <0>; /* Filled in by U-Boot */ 146 clock-frequency = <0>; /* Filled in by U-Boot */
145 /* ranges property is supplied by U-Boot */ 147 /* ranges property is supplied by U-Boot */
146 interrupts = <6 4>; 148 interrupts = <0x6 0x4>;
147 interrupt-parent = <&UIC1>; 149 interrupt-parent = <&UIC1>;
148 150
149 nor_flash@0,0 { 151 nor_flash@0,0 {
150 compatible = "amd,s29gl512n", "cfi-flash"; 152 compatible = "amd,s29gl512n", "cfi-flash";
151 bank-width = <2>; 153 bank-width = <2>;
152 reg = <0 000000 4000000>; 154 reg = <0x00000000 0x00000000 0x04000000>;
153 #address-cells = <1>; 155 #address-cells = <1>;
154 #size-cells = <1>; 156 #size-cells = <1>;
155 partition@0 { 157 partition@0 {
156 label = "kernel"; 158 label = "kernel";
157 reg = <0 1e0000>; 159 reg = <0x00000000 0x001e0000>;
158 }; 160 };
159 partition@1e0000 { 161 partition@1e0000 {
160 label = "dtb"; 162 label = "dtb";
161 reg = <1e0000 20000>; 163 reg = <0x001e0000 0x00020000>;
162 }; 164 };
163 partition@200000 { 165 partition@200000 {
164 label = "ramdisk"; 166 label = "ramdisk";
165 reg = <200000 1400000>; 167 reg = <0x00200000 0x01400000>;
166 }; 168 };
167 partition@1600000 { 169 partition@1600000 {
168 label = "jffs2"; 170 label = "jffs2";
169 reg = <1600000 400000>; 171 reg = <0x01600000 0x00400000>;
170 }; 172 };
171 partition@1a00000 { 173 partition@1a00000 {
172 label = "user"; 174 label = "user";
173 reg = <1a00000 2560000>; 175 reg = <0x01a00000 0x02560000>;
174 }; 176 };
175 partition@3f60000 { 177 partition@3f60000 {
176 label = "env"; 178 label = "env";
177 reg = <3f60000 40000>; 179 reg = <0x03f60000 0x00040000>;
178 }; 180 };
179 partition@3fa0000 { 181 partition@3fa0000 {
180 label = "u-boot"; 182 label = "u-boot";
181 reg = <3fa0000 60000>; 183 reg = <0x03fa0000 0x00060000>;
182 }; 184 };
183 }; 185 };
184 }; 186 };
@@ -186,103 +188,103 @@
186 UART0: serial@ef600300 { 188 UART0: serial@ef600300 {
187 device_type = "serial"; 189 device_type = "serial";
188 compatible = "ns16550"; 190 compatible = "ns16550";
189 reg = <ef600300 8>; 191 reg = <0xef600300 0x00000008>;
190 virtual-reg = <ef600300>; 192 virtual-reg = <0xef600300>;
191 clock-frequency = <0>; /* Filled in by U-Boot */ 193 clock-frequency = <0>; /* Filled in by U-Boot */
192 current-speed = <0>; /* Filled in by U-Boot */ 194 current-speed = <0>; /* Filled in by U-Boot */
193 interrupt-parent = <&UIC1>; 195 interrupt-parent = <&UIC1>;
194 interrupts = <1 4>; 196 interrupts = <0x1 0x4>;
195 }; 197 };
196 198
197 UART1: serial@ef600400 { 199 UART1: serial@ef600400 {
198 device_type = "serial"; 200 device_type = "serial";
199 compatible = "ns16550"; 201 compatible = "ns16550";
200 reg = <ef600400 8>; 202 reg = <0xef600400 0x00000008>;
201 virtual-reg = <ef600400>; 203 virtual-reg = <0xef600400>;
202 clock-frequency = <0>; /* Filled in by U-Boot */ 204 clock-frequency = <0>; /* Filled in by U-Boot */
203 current-speed = <0>; /* Filled in by U-Boot */ 205 current-speed = <0>; /* Filled in by U-Boot */
204 interrupt-parent = <&UIC0>; 206 interrupt-parent = <&UIC0>;
205 interrupts = <1 4>; 207 interrupts = <0x1 0x4>;
206 }; 208 };
207 209
208 UART2: serial@ef600500 { 210 UART2: serial@ef600500 {
209 device_type = "serial"; 211 device_type = "serial";
210 compatible = "ns16550"; 212 compatible = "ns16550";
211 reg = <ef600500 8>; 213 reg = <0xef600500 0x00000008>;
212 virtual-reg = <ef600500>; 214 virtual-reg = <0xef600500>;
213 clock-frequency = <0>; /* Filled in by U-Boot */ 215 clock-frequency = <0>; /* Filled in by U-Boot */
214 current-speed = <0>; /* Filled in by U-Boot */ 216 current-speed = <0>; /* Filled in by U-Boot */
215 interrupt-parent = <&UIC1>; 217 interrupt-parent = <&UIC1>;
216 interrupts = <1d 4>; 218 interrupts = <0x1d 0x4>;
217 }; 219 };
218 220
219 UART3: serial@ef600600 { 221 UART3: serial@ef600600 {
220 device_type = "serial"; 222 device_type = "serial";
221 compatible = "ns16550"; 223 compatible = "ns16550";
222 reg = <ef600600 8>; 224 reg = <0xef600600 0x00000008>;
223 virtual-reg = <ef600600>; 225 virtual-reg = <0xef600600>;
224 clock-frequency = <0>; /* Filled in by U-Boot */ 226 clock-frequency = <0>; /* Filled in by U-Boot */
225 current-speed = <0>; /* Filled in by U-Boot */ 227 current-speed = <0>; /* Filled in by U-Boot */
226 interrupt-parent = <&UIC1>; 228 interrupt-parent = <&UIC1>;
227 interrupts = <1e 4>; 229 interrupts = <0x1e 0x4>;
228 }; 230 };
229 231
230 IIC0: i2c@ef600700 { 232 IIC0: i2c@ef600700 {
231 compatible = "ibm,iic-460ex", "ibm,iic"; 233 compatible = "ibm,iic-460ex", "ibm,iic";
232 reg = <ef600700 14>; 234 reg = <0xef600700 0x00000014>;
233 interrupt-parent = <&UIC0>; 235 interrupt-parent = <&UIC0>;
234 interrupts = <2 4>; 236 interrupts = <0x2 0x4>;
235 }; 237 };
236 238
237 IIC1: i2c@ef600800 { 239 IIC1: i2c@ef600800 {
238 compatible = "ibm,iic-460ex", "ibm,iic"; 240 compatible = "ibm,iic-460ex", "ibm,iic";
239 reg = <ef600800 14>; 241 reg = <0xef600800 0x00000014>;
240 interrupt-parent = <&UIC0>; 242 interrupt-parent = <&UIC0>;
241 interrupts = <3 4>; 243 interrupts = <0x3 0x4>;
242 }; 244 };
243 245
244 ZMII0: emac-zmii@ef600d00 { 246 ZMII0: emac-zmii@ef600d00 {
245 compatible = "ibm,zmii-460ex", "ibm,zmii"; 247 compatible = "ibm,zmii-460ex", "ibm,zmii";
246 reg = <ef600d00 c>; 248 reg = <0xef600d00 0x0000000c>;
247 }; 249 };
248 250
249 RGMII0: emac-rgmii@ef601500 { 251 RGMII0: emac-rgmii@ef601500 {
250 compatible = "ibm,rgmii-460ex", "ibm,rgmii"; 252 compatible = "ibm,rgmii-460ex", "ibm,rgmii";
251 reg = <ef601500 8>; 253 reg = <0xef601500 0x00000008>;
252 has-mdio; 254 has-mdio;
253 }; 255 };
254 256
255 TAH0: emac-tah@ef601350 { 257 TAH0: emac-tah@ef601350 {
256 compatible = "ibm,tah-460ex", "ibm,tah"; 258 compatible = "ibm,tah-460ex", "ibm,tah";
257 reg = <ef601350 30>; 259 reg = <0xef601350 0x00000030>;
258 }; 260 };
259 261
260 TAH1: emac-tah@ef601450 { 262 TAH1: emac-tah@ef601450 {
261 compatible = "ibm,tah-460ex", "ibm,tah"; 263 compatible = "ibm,tah-460ex", "ibm,tah";
262 reg = <ef601450 30>; 264 reg = <0xef601450 0x00000030>;
263 }; 265 };
264 266
265 EMAC0: ethernet@ef600e00 { 267 EMAC0: ethernet@ef600e00 {
266 device_type = "network"; 268 device_type = "network";
267 compatible = "ibm,emac-460ex", "ibm,emac4"; 269 compatible = "ibm,emac-460ex", "ibm,emac4sync";
268 interrupt-parent = <&EMAC0>; 270 interrupt-parent = <&EMAC0>;
269 interrupts = <0 1>; 271 interrupts = <0x0 0x1>;
270 #interrupt-cells = <1>; 272 #interrupt-cells = <1>;
271 #address-cells = <0>; 273 #address-cells = <0>;
272 #size-cells = <0>; 274 #size-cells = <0>;
273 interrupt-map = </*Status*/ 0 &UIC2 10 4 275 interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4
274 /*Wake*/ 1 &UIC2 14 4>; 276 /*Wake*/ 0x1 &UIC2 0x14 0x4>;
275 reg = <ef600e00 70>; 277 reg = <0xef600e00 0x000000c4>;
276 local-mac-address = [000000000000]; /* Filled in by U-Boot */ 278 local-mac-address = [000000000000]; /* Filled in by U-Boot */
277 mal-device = <&MAL0>; 279 mal-device = <&MAL0>;
278 mal-tx-channel = <0>; 280 mal-tx-channel = <0>;
279 mal-rx-channel = <0>; 281 mal-rx-channel = <0>;
280 cell-index = <0>; 282 cell-index = <0>;
281 max-frame-size = <2328>; 283 max-frame-size = <9000>;
282 rx-fifo-size = <1000>; 284 rx-fifo-size = <4096>;
283 tx-fifo-size = <800>; 285 tx-fifo-size = <2048>;
284 phy-mode = "rgmii"; 286 phy-mode = "rgmii";
285 phy-map = <00000000>; 287 phy-map = <0x00000000>;
286 rgmii-device = <&RGMII0>; 288 rgmii-device = <&RGMII0>;
287 rgmii-channel = <0>; 289 rgmii-channel = <0>;
288 tah-device = <&TAH0>; 290 tah-device = <&TAH0>;
@@ -293,25 +295,25 @@
293 295
294 EMAC1: ethernet@ef600f00 { 296 EMAC1: ethernet@ef600f00 {
295 device_type = "network"; 297 device_type = "network";
296 compatible = "ibm,emac-460ex", "ibm,emac4"; 298 compatible = "ibm,emac-460ex", "ibm,emac4sync";
297 interrupt-parent = <&EMAC1>; 299 interrupt-parent = <&EMAC1>;
298 interrupts = <0 1>; 300 interrupts = <0x0 0x1>;
299 #interrupt-cells = <1>; 301 #interrupt-cells = <1>;
300 #address-cells = <0>; 302 #address-cells = <0>;
301 #size-cells = <0>; 303 #size-cells = <0>;
302 interrupt-map = </*Status*/ 0 &UIC2 11 4 304 interrupt-map = </*Status*/ 0x0 &UIC2 0x11 0x4
303 /*Wake*/ 1 &UIC2 15 4>; 305 /*Wake*/ 0x1 &UIC2 0x15 0x4>;
304 reg = <ef600f00 70>; 306 reg = <0xef600f00 0x000000c4>;
305 local-mac-address = [000000000000]; /* Filled in by U-Boot */ 307 local-mac-address = [000000000000]; /* Filled in by U-Boot */
306 mal-device = <&MAL0>; 308 mal-device = <&MAL0>;
307 mal-tx-channel = <1>; 309 mal-tx-channel = <1>;
308 mal-rx-channel = <8>; 310 mal-rx-channel = <8>;
309 cell-index = <1>; 311 cell-index = <1>;
310 max-frame-size = <2328>; 312 max-frame-size = <9000>;
311 rx-fifo-size = <1000>; 313 rx-fifo-size = <4096>;
312 tx-fifo-size = <800>; 314 tx-fifo-size = <2048>;
313 phy-mode = "rgmii"; 315 phy-mode = "rgmii";
314 phy-map = <00000000>; 316 phy-map = <0x00000000>;
315 rgmii-device = <&RGMII0>; 317 rgmii-device = <&RGMII0>;
316 rgmii-channel = <1>; 318 rgmii-channel = <1>;
317 tah-device = <&TAH1>; 319 tah-device = <&TAH1>;
@@ -331,27 +333,27 @@
331 primary; 333 primary;
332 large-inbound-windows; 334 large-inbound-windows;
333 enable-msi-hole; 335 enable-msi-hole;
334 reg = <c 0ec00000 8 /* Config space access */ 336 reg = <0x0000000c 0x0ec00000 0x00000008 /* Config space access */
335 0 0 0 /* no IACK cycles */ 337 0x00000000 0x00000000 0x00000000 /* no IACK cycles */
336 c 0ed00000 4 /* Special cycles */ 338 0x0000000c 0x0ed00000 0x00000004 /* Special cycles */
337 c 0ec80000 100 /* Internal registers */ 339 0x0000000c 0x0ec80000 0x00000100 /* Internal registers */
338 c 0ec80100 fc>; /* Internal messaging registers */ 340 0x0000000c 0x0ec80100 0x000000fc>; /* Internal messaging registers */
339 341
340 /* Outbound ranges, one memory and one IO, 342 /* Outbound ranges, one memory and one IO,
341 * later cannot be changed 343 * later cannot be changed
342 */ 344 */
343 ranges = <02000000 0 80000000 0000000d 80000000 0 80000000 345 ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000
344 01000000 0 00000000 0000000c 08000000 0 00010000>; 346 0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>;
345 347
346 /* Inbound 2GB range starting at 0 */ 348 /* Inbound 2GB range starting at 0 */
347 dma-ranges = <42000000 0 0 0 0 0 80000000>; 349 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
348 350
349 /* This drives busses 0 to 0x3f */ 351 /* This drives busses 0 to 0x3f */
350 bus-range = <0 3f>; 352 bus-range = <0x0 0x3f>;
351 353
352 /* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */ 354 /* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */
353 interrupt-map-mask = <0000 0 0 0>; 355 interrupt-map-mask = <0x0 0x0 0x0 0x0>;
354 interrupt-map = < 0000 0 0 0 &UIC1 0 8 >; 356 interrupt-map = < 0x0 0x0 0x0 0x0 &UIC1 0x0 0x8 >;
355 }; 357 };
356 358
357 PCIE0: pciex@d00000000 { 359 PCIE0: pciex@d00000000 {
@@ -361,23 +363,23 @@
361 #address-cells = <3>; 363 #address-cells = <3>;
362 compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex"; 364 compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
363 primary; 365 primary;
364 port = <0>; /* port number */ 366 port = <0x0>; /* port number */
365 reg = <d 00000000 20000000 /* Config space access */ 367 reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */
366 c 08010000 00001000>; /* Registers */ 368 0x0000000c 0x08010000 0x00001000>; /* Registers */
367 dcr-reg = <100 020>; 369 dcr-reg = <0x100 0x020>;
368 sdr-base = <300>; 370 sdr-base = <0x300>;
369 371
370 /* Outbound ranges, one memory and one IO, 372 /* Outbound ranges, one memory and one IO,
371 * later cannot be changed 373 * later cannot be changed
372 */ 374 */
373 ranges = <02000000 0 80000000 0000000e 00000000 0 80000000 375 ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000
374 01000000 0 00000000 0000000f 80000000 0 00010000>; 376 0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;
375 377
376 /* Inbound 2GB range starting at 0 */ 378 /* Inbound 2GB range starting at 0 */
377 dma-ranges = <42000000 0 0 0 0 0 80000000>; 379 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
378 380
379 /* This drives busses 40 to 0x7f */ 381 /* This drives busses 40 to 0x7f */
380 bus-range = <40 7f>; 382 bus-range = <0x40 0x7f>;
381 383
382 /* Legacy interrupts (note the weird polarity, the bridge seems 384 /* Legacy interrupts (note the weird polarity, the bridge seems
383 * to invert PCIe legacy interrupts). 385 * to invert PCIe legacy interrupts).
@@ -387,12 +389,12 @@
387 * below are basically de-swizzled numbers. 389 * below are basically de-swizzled numbers.
388 * The real slot is on idsel 0, so the swizzling is 1:1 390 * The real slot is on idsel 0, so the swizzling is 1:1
389 */ 391 */
390 interrupt-map-mask = <0000 0 0 7>; 392 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
391 interrupt-map = < 393 interrupt-map = <
392 0000 0 0 1 &UIC3 c 4 /* swizzled int A */ 394 0x0 0x0 0x0 0x1 &UIC3 0xc 0x4 /* swizzled int A */
393 0000 0 0 2 &UIC3 d 4 /* swizzled int B */ 395 0x0 0x0 0x0 0x2 &UIC3 0xd 0x4 /* swizzled int B */
394 0000 0 0 3 &UIC3 e 4 /* swizzled int C */ 396 0x0 0x0 0x0 0x3 &UIC3 0xe 0x4 /* swizzled int C */
395 0000 0 0 4 &UIC3 f 4 /* swizzled int D */>; 397 0x0 0x0 0x0 0x4 &UIC3 0xf 0x4 /* swizzled int D */>;
396 }; 398 };
397 399
398 PCIE1: pciex@d20000000 { 400 PCIE1: pciex@d20000000 {
@@ -402,23 +404,23 @@
402 #address-cells = <3>; 404 #address-cells = <3>;
403 compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex"; 405 compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
404 primary; 406 primary;
405 port = <1>; /* port number */ 407 port = <0x1>; /* port number */
406 reg = <d 20000000 20000000 /* Config space access */ 408 reg = <0x0000000d 0x20000000 0x20000000 /* Config space access */
407 c 08011000 00001000>; /* Registers */ 409 0x0000000c 0x08011000 0x00001000>; /* Registers */
408 dcr-reg = <120 020>; 410 dcr-reg = <0x120 0x020>;
409 sdr-base = <340>; 411 sdr-base = <0x340>;
410 412
411 /* Outbound ranges, one memory and one IO, 413 /* Outbound ranges, one memory and one IO,
412 * later cannot be changed 414 * later cannot be changed
413 */ 415 */
414 ranges = <02000000 0 80000000 0000000e 80000000 0 80000000 416 ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000
415 01000000 0 00000000 0000000f 80010000 0 00010000>; 417 0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>;
416 418
417 /* Inbound 2GB range starting at 0 */ 419 /* Inbound 2GB range starting at 0 */
418 dma-ranges = <42000000 0 0 0 0 0 80000000>; 420 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
419 421
420 /* This drives busses 80 to 0xbf */ 422 /* This drives busses 80 to 0xbf */
421 bus-range = <80 bf>; 423 bus-range = <0x80 0xbf>;
422 424
423 /* Legacy interrupts (note the weird polarity, the bridge seems 425 /* Legacy interrupts (note the weird polarity, the bridge seems
424 * to invert PCIe legacy interrupts). 426 * to invert PCIe legacy interrupts).
@@ -428,12 +430,12 @@
428 * below are basically de-swizzled numbers. 430 * below are basically de-swizzled numbers.
429 * The real slot is on idsel 0, so the swizzling is 1:1 431 * The real slot is on idsel 0, so the swizzling is 1:1
430 */ 432 */
431 interrupt-map-mask = <0000 0 0 7>; 433 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
432 interrupt-map = < 434 interrupt-map = <
433 0000 0 0 1 &UIC3 10 4 /* swizzled int A */ 435 0x0 0x0 0x0 0x1 &UIC3 0x10 0x4 /* swizzled int A */
434 0000 0 0 2 &UIC3 11 4 /* swizzled int B */ 436 0x0 0x0 0x0 0x2 &UIC3 0x11 0x4 /* swizzled int B */
435 0000 0 0 3 &UIC3 12 4 /* swizzled int C */ 437 0x0 0x0 0x0 0x3 &UIC3 0x12 0x4 /* swizzled int C */
436 0000 0 0 4 &UIC3 13 4 /* swizzled int D */>; 438 0x0 0x0 0x0 0x4 &UIC3 0x13 0x4 /* swizzled int D */>;
437 }; 439 };
438 }; 440 };
439}; 441};
diff --git a/arch/powerpc/boot/dts/ebony.dts b/arch/powerpc/boot/dts/ebony.dts
index 5079dc890e0e..ec2d142291b4 100644
--- a/arch/powerpc/boot/dts/ebony.dts
+++ b/arch/powerpc/boot/dts/ebony.dts
@@ -11,12 +11,14 @@
11 * any warranty of any kind, whether express or implied. 11 * any warranty of any kind, whether express or implied.
12 */ 12 */
13 13
14/dts-v1/;
15
14/ { 16/ {
15 #address-cells = <2>; 17 #address-cells = <2>;
16 #size-cells = <1>; 18 #size-cells = <1>;
17 model = "ibm,ebony"; 19 model = "ibm,ebony";
18 compatible = "ibm,ebony"; 20 compatible = "ibm,ebony";
19 dcr-parent = <&/cpus/cpu@0>; 21 dcr-parent = <&{/cpus/cpu@0}>;
20 22
21 aliases { 23 aliases {
22 ethernet0 = &EMAC0; 24 ethernet0 = &EMAC0;
@@ -32,13 +34,13 @@
32 cpu@0 { 34 cpu@0 {
33 device_type = "cpu"; 35 device_type = "cpu";
34 model = "PowerPC,440GP"; 36 model = "PowerPC,440GP";
35 reg = <0>; 37 reg = <0x00000000>;
36 clock-frequency = <0>; // Filled in by zImage 38 clock-frequency = <0>; // Filled in by zImage
37 timebase-frequency = <0>; // Filled in by zImage 39 timebase-frequency = <0>; // Filled in by zImage
38 i-cache-line-size = <20>; 40 i-cache-line-size = <32>;
39 d-cache-line-size = <20>; 41 d-cache-line-size = <32>;
40 i-cache-size = <8000>; /* 32 kB */ 42 i-cache-size = <32768>; /* 32 kB */
41 d-cache-size = <8000>; /* 32 kB */ 43 d-cache-size = <32768>; /* 32 kB */
42 dcr-controller; 44 dcr-controller;
43 dcr-access-method = "native"; 45 dcr-access-method = "native";
44 }; 46 };
@@ -46,14 +48,14 @@
46 48
47 memory { 49 memory {
48 device_type = "memory"; 50 device_type = "memory";
49 reg = <0 0 0>; // Filled in by zImage 51 reg = <0x00000000 0x00000000 0x00000000>; // Filled in by zImage
50 }; 52 };
51 53
52 UIC0: interrupt-controller0 { 54 UIC0: interrupt-controller0 {
53 compatible = "ibm,uic-440gp", "ibm,uic"; 55 compatible = "ibm,uic-440gp", "ibm,uic";
54 interrupt-controller; 56 interrupt-controller;
55 cell-index = <0>; 57 cell-index = <0>;
56 dcr-reg = <0c0 009>; 58 dcr-reg = <0x0c0 0x009>;
57 #address-cells = <0>; 59 #address-cells = <0>;
58 #size-cells = <0>; 60 #size-cells = <0>;
59 #interrupt-cells = <2>; 61 #interrupt-cells = <2>;
@@ -64,17 +66,17 @@
64 compatible = "ibm,uic-440gp", "ibm,uic"; 66 compatible = "ibm,uic-440gp", "ibm,uic";
65 interrupt-controller; 67 interrupt-controller;
66 cell-index = <1>; 68 cell-index = <1>;
67 dcr-reg = <0d0 009>; 69 dcr-reg = <0x0d0 0x009>;
68 #address-cells = <0>; 70 #address-cells = <0>;
69 #size-cells = <0>; 71 #size-cells = <0>;
70 #interrupt-cells = <2>; 72 #interrupt-cells = <2>;
71 interrupts = <1e 4 1f 4>; /* cascade */ 73 interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
72 interrupt-parent = <&UIC0>; 74 interrupt-parent = <&UIC0>;
73 }; 75 };
74 76
75 CPC0: cpc { 77 CPC0: cpc {
76 compatible = "ibm,cpc-440gp"; 78 compatible = "ibm,cpc-440gp";
77 dcr-reg = <0b0 003 0e0 010>; 79 dcr-reg = <0x0b0 0x003 0x0e0 0x010>;
78 // FIXME: anything else? 80 // FIXME: anything else?
79 }; 81 };
80 82
@@ -87,37 +89,37 @@
87 89
88 SDRAM0: memory-controller { 90 SDRAM0: memory-controller {
89 compatible = "ibm,sdram-440gp"; 91 compatible = "ibm,sdram-440gp";
90 dcr-reg = <010 2>; 92 dcr-reg = <0x010 0x002>;
91 // FIXME: anything else? 93 // FIXME: anything else?
92 }; 94 };
93 95
94 SRAM0: sram { 96 SRAM0: sram {
95 compatible = "ibm,sram-440gp"; 97 compatible = "ibm,sram-440gp";
96 dcr-reg = <020 8 00a 1>; 98 dcr-reg = <0x020 0x008 0x00a 0x001>;
97 }; 99 };
98 100
99 DMA0: dma { 101 DMA0: dma {
100 // FIXME: ??? 102 // FIXME: ???
101 compatible = "ibm,dma-440gp"; 103 compatible = "ibm,dma-440gp";
102 dcr-reg = <100 027>; 104 dcr-reg = <0x100 0x027>;
103 }; 105 };
104 106
105 MAL0: mcmal { 107 MAL0: mcmal {
106 compatible = "ibm,mcmal-440gp", "ibm,mcmal"; 108 compatible = "ibm,mcmal-440gp", "ibm,mcmal";
107 dcr-reg = <180 62>; 109 dcr-reg = <0x180 0x062>;
108 num-tx-chans = <4>; 110 num-tx-chans = <4>;
109 num-rx-chans = <4>; 111 num-rx-chans = <4>;
110 interrupt-parent = <&MAL0>; 112 interrupt-parent = <&MAL0>;
111 interrupts = <0 1 2 3 4>; 113 interrupts = <0x0 0x1 0x2 0x3 0x4>;
112 #interrupt-cells = <1>; 114 #interrupt-cells = <1>;
113 #address-cells = <0>; 115 #address-cells = <0>;
114 #size-cells = <0>; 116 #size-cells = <0>;
115 interrupt-map = </*TXEOB*/ 0 &UIC0 a 4 117 interrupt-map = </*TXEOB*/ 0x0 &UIC0 0xa 0x4
116 /*RXEOB*/ 1 &UIC0 b 4 118 /*RXEOB*/ 0x1 &UIC0 0xb 0x4
117 /*SERR*/ 2 &UIC1 0 4 119 /*SERR*/ 0x2 &UIC1 0x0 0x4
118 /*TXDE*/ 3 &UIC1 1 4 120 /*TXDE*/ 0x3 &UIC1 0x1 0x4
119 /*RXDE*/ 4 &UIC1 2 4>; 121 /*RXDE*/ 0x4 &UIC1 0x2 0x4>;
120 interrupt-map-mask = <ffffffff>; 122 interrupt-map-mask = <0xffffffff>;
121 }; 123 };
122 124
123 POB0: opb { 125 POB0: opb {
@@ -126,34 +128,34 @@
126 #size-cells = <1>; 128 #size-cells = <1>;
127 /* Wish there was a nicer way of specifying a full 32-bit 129 /* Wish there was a nicer way of specifying a full 32-bit
128 range */ 130 range */
129 ranges = <00000000 1 00000000 80000000 131 ranges = <0x00000000 0x00000001 0x00000000 0x80000000
130 80000000 1 80000000 80000000>; 132 0x80000000 0x00000001 0x80000000 0x80000000>;
131 dcr-reg = <090 00b>; 133 dcr-reg = <0x090 0x00b>;
132 interrupt-parent = <&UIC1>; 134 interrupt-parent = <&UIC1>;
133 interrupts = <7 4>; 135 interrupts = <0x7 0x4>;
134 clock-frequency = <0>; // Filled in by zImage 136 clock-frequency = <0>; // Filled in by zImage
135 137
136 EBC0: ebc { 138 EBC0: ebc {
137 compatible = "ibm,ebc-440gp", "ibm,ebc"; 139 compatible = "ibm,ebc-440gp", "ibm,ebc";
138 dcr-reg = <012 2>; 140 dcr-reg = <0x012 0x002>;
139 #address-cells = <2>; 141 #address-cells = <2>;
140 #size-cells = <1>; 142 #size-cells = <1>;
141 clock-frequency = <0>; // Filled in by zImage 143 clock-frequency = <0>; // Filled in by zImage
142 // ranges property is supplied by zImage 144 // ranges property is supplied by zImage
143 // based on firmware's configuration of the 145 // based on firmware's configuration of the
144 // EBC bridge 146 // EBC bridge
145 interrupts = <5 4>; 147 interrupts = <0x5 0x4>;
146 interrupt-parent = <&UIC1>; 148 interrupt-parent = <&UIC1>;
147 149
148 small-flash@0,80000 { 150 small-flash@0,80000 {
149 compatible = "jedec-flash"; 151 compatible = "jedec-flash";
150 bank-width = <1>; 152 bank-width = <1>;
151 reg = <0 80000 80000>; 153 reg = <0x00000000 0x00080000 0x00080000>;
152 #address-cells = <1>; 154 #address-cells = <1>;
153 #size-cells = <1>; 155 #size-cells = <1>;
154 partition@0 { 156 partition@0 {
155 label = "OpenBIOS"; 157 label = "OpenBIOS";
156 reg = <0 80000>; 158 reg = <0x00000000 0x00080000>;
157 read-only; 159 read-only;
158 }; 160 };
159 }; 161 };
@@ -161,101 +163,101 @@
161 nvram@1,0 { 163 nvram@1,0 {
162 /* NVRAM & RTC */ 164 /* NVRAM & RTC */
163 compatible = "ds1743-nvram"; 165 compatible = "ds1743-nvram";
164 #bytes = <2000>; 166 #bytes = <0x2000>;
165 reg = <1 0 2000>; 167 reg = <0x00000001 0x00000000 0x00002000>;
166 }; 168 };
167 169
168 large-flash@2,0 { 170 large-flash@2,0 {
169 compatible = "jedec-flash"; 171 compatible = "jedec-flash";
170 bank-width = <1>; 172 bank-width = <1>;
171 reg = <2 0 400000>; 173 reg = <0x00000002 0x00000000 0x00400000>;
172 #address-cells = <1>; 174 #address-cells = <1>;
173 #size-cells = <1>; 175 #size-cells = <1>;
174 partition@0 { 176 partition@0 {
175 label = "fs"; 177 label = "fs";
176 reg = <0 380000>; 178 reg = <0x00000000 0x00380000>;
177 }; 179 };
178 partition@380000 { 180 partition@380000 {
179 label = "firmware"; 181 label = "firmware";
180 reg = <380000 80000>; 182 reg = <0x00380000 0x00080000>;
181 }; 183 };
182 }; 184 };
183 185
184 ir@3,0 { 186 ir@3,0 {
185 reg = <3 0 10>; 187 reg = <0x00000003 0x00000000 0x00000010>;
186 }; 188 };
187 189
188 fpga@7,0 { 190 fpga@7,0 {
189 compatible = "Ebony-FPGA"; 191 compatible = "Ebony-FPGA";
190 reg = <7 0 10>; 192 reg = <0x00000007 0x00000000 0x00000010>;
191 virtual-reg = <e8300000>; 193 virtual-reg = <0xe8300000>;
192 }; 194 };
193 }; 195 };
194 196
195 UART0: serial@40000200 { 197 UART0: serial@40000200 {
196 device_type = "serial"; 198 device_type = "serial";
197 compatible = "ns16550"; 199 compatible = "ns16550";
198 reg = <40000200 8>; 200 reg = <0x40000200 0x00000008>;
199 virtual-reg = <e0000200>; 201 virtual-reg = <0xe0000200>;
200 clock-frequency = <A8C000>; 202 clock-frequency = <11059200>;
201 current-speed = <2580>; 203 current-speed = <9600>;
202 interrupt-parent = <&UIC0>; 204 interrupt-parent = <&UIC0>;
203 interrupts = <0 4>; 205 interrupts = <0x0 0x4>;
204 }; 206 };
205 207
206 UART1: serial@40000300 { 208 UART1: serial@40000300 {
207 device_type = "serial"; 209 device_type = "serial";
208 compatible = "ns16550"; 210 compatible = "ns16550";
209 reg = <40000300 8>; 211 reg = <0x40000300 0x00000008>;
210 virtual-reg = <e0000300>; 212 virtual-reg = <0xe0000300>;
211 clock-frequency = <A8C000>; 213 clock-frequency = <11059200>;
212 current-speed = <2580>; 214 current-speed = <9600>;
213 interrupt-parent = <&UIC0>; 215 interrupt-parent = <&UIC0>;
214 interrupts = <1 4>; 216 interrupts = <0x1 0x4>;
215 }; 217 };
216 218
217 IIC0: i2c@40000400 { 219 IIC0: i2c@40000400 {
218 /* FIXME */ 220 /* FIXME */
219 compatible = "ibm,iic-440gp", "ibm,iic"; 221 compatible = "ibm,iic-440gp", "ibm,iic";
220 reg = <40000400 14>; 222 reg = <0x40000400 0x00000014>;
221 interrupt-parent = <&UIC0>; 223 interrupt-parent = <&UIC0>;
222 interrupts = <2 4>; 224 interrupts = <0x2 0x4>;
223 }; 225 };
224 IIC1: i2c@40000500 { 226 IIC1: i2c@40000500 {
225 /* FIXME */ 227 /* FIXME */
226 compatible = "ibm,iic-440gp", "ibm,iic"; 228 compatible = "ibm,iic-440gp", "ibm,iic";
227 reg = <40000500 14>; 229 reg = <0x40000500 0x00000014>;
228 interrupt-parent = <&UIC0>; 230 interrupt-parent = <&UIC0>;
229 interrupts = <3 4>; 231 interrupts = <0x3 0x4>;
230 }; 232 };
231 233
232 GPIO0: gpio@40000700 { 234 GPIO0: gpio@40000700 {
233 /* FIXME */ 235 /* FIXME */
234 compatible = "ibm,gpio-440gp"; 236 compatible = "ibm,gpio-440gp";
235 reg = <40000700 20>; 237 reg = <0x40000700 0x00000020>;
236 }; 238 };
237 239
238 ZMII0: emac-zmii@40000780 { 240 ZMII0: emac-zmii@40000780 {
239 compatible = "ibm,zmii-440gp", "ibm,zmii"; 241 compatible = "ibm,zmii-440gp", "ibm,zmii";
240 reg = <40000780 c>; 242 reg = <0x40000780 0x0000000c>;
241 }; 243 };
242 244
243 EMAC0: ethernet@40000800 { 245 EMAC0: ethernet@40000800 {
244 device_type = "network"; 246 device_type = "network";
245 compatible = "ibm,emac-440gp", "ibm,emac"; 247 compatible = "ibm,emac-440gp", "ibm,emac";
246 interrupt-parent = <&UIC1>; 248 interrupt-parent = <&UIC1>;
247 interrupts = <1c 4 1d 4>; 249 interrupts = <0x1c 0x4 0x1d 0x4>;
248 reg = <40000800 70>; 250 reg = <0x40000800 0x00000070>;
249 local-mac-address = [000000000000]; // Filled in by zImage 251 local-mac-address = [000000000000]; // Filled in by zImage
250 mal-device = <&MAL0>; 252 mal-device = <&MAL0>;
251 mal-tx-channel = <0 1>; 253 mal-tx-channel = <0 1>;
252 mal-rx-channel = <0>; 254 mal-rx-channel = <0>;
253 cell-index = <0>; 255 cell-index = <0>;
254 max-frame-size = <5dc>; 256 max-frame-size = <1500>;
255 rx-fifo-size = <1000>; 257 rx-fifo-size = <4096>;
256 tx-fifo-size = <800>; 258 tx-fifo-size = <2048>;
257 phy-mode = "rmii"; 259 phy-mode = "rmii";
258 phy-map = <00000001>; 260 phy-map = <0x00000001>;
259 zmii-device = <&ZMII0>; 261 zmii-device = <&ZMII0>;
260 zmii-channel = <0>; 262 zmii-channel = <0>;
261 }; 263 };
@@ -263,18 +265,18 @@
263 device_type = "network"; 265 device_type = "network";
264 compatible = "ibm,emac-440gp", "ibm,emac"; 266 compatible = "ibm,emac-440gp", "ibm,emac";
265 interrupt-parent = <&UIC1>; 267 interrupt-parent = <&UIC1>;
266 interrupts = <1e 4 1f 4>; 268 interrupts = <0x1e 0x4 0x1f 0x4>;
267 reg = <40000900 70>; 269 reg = <0x40000900 0x00000070>;
268 local-mac-address = [000000000000]; // Filled in by zImage 270 local-mac-address = [000000000000]; // Filled in by zImage
269 mal-device = <&MAL0>; 271 mal-device = <&MAL0>;
270 mal-tx-channel = <2 3>; 272 mal-tx-channel = <2 3>;
271 mal-rx-channel = <1>; 273 mal-rx-channel = <1>;
272 cell-index = <1>; 274 cell-index = <1>;
273 max-frame-size = <5dc>; 275 max-frame-size = <1500>;
274 rx-fifo-size = <1000>; 276 rx-fifo-size = <4096>;
275 tx-fifo-size = <800>; 277 tx-fifo-size = <2048>;
276 phy-mode = "rmii"; 278 phy-mode = "rmii";
277 phy-map = <00000001>; 279 phy-map = <0x00000001>;
278 zmii-device = <&ZMII0>; 280 zmii-device = <&ZMII0>;
279 zmii-channel = <1>; 281 zmii-channel = <1>;
280 }; 282 };
@@ -282,9 +284,9 @@
282 284
283 GPT0: gpt@40000a00 { 285 GPT0: gpt@40000a00 {
284 /* FIXME */ 286 /* FIXME */
285 reg = <40000a00 d4>; 287 reg = <0x40000a00 0x000000d4>;
286 interrupt-parent = <&UIC0>; 288 interrupt-parent = <&UIC0>;
287 interrupts = <12 4 13 4 14 4 15 4 16 4>; 289 interrupts = <0x12 0x4 0x13 0x4 0x14 0x4 0x15 0x4 0x16 0x4>;
288 }; 290 };
289 291
290 }; 292 };
@@ -296,35 +298,35 @@
296 #address-cells = <3>; 298 #address-cells = <3>;
297 compatible = "ibm,plb440gp-pcix", "ibm,plb-pcix"; 299 compatible = "ibm,plb440gp-pcix", "ibm,plb-pcix";
298 primary; 300 primary;
299 reg = <2 0ec00000 8 /* Config space access */ 301 reg = <0x00000002 0x0ec00000 0x00000008 /* Config space access */
300 0 0 0 /* no IACK cycles */ 302 0x00000000 0x00000000 0x00000000 /* no IACK cycles */
301 2 0ed00000 4 /* Special cycles */ 303 0x00000002 0x0ed00000 0x00000004 /* Special cycles */
302 2 0ec80000 f0 /* Internal registers */ 304 0x00000002 0x0ec80000 0x000000f0 /* Internal registers */
303 2 0ec80100 fc>; /* Internal messaging registers */ 305 0x00000002 0x0ec80100 0x000000fc>; /* Internal messaging registers */
304 306
305 /* Outbound ranges, one memory and one IO, 307 /* Outbound ranges, one memory and one IO,
306 * later cannot be changed 308 * later cannot be changed
307 */ 309 */
308 ranges = <02000000 0 80000000 00000003 80000000 0 80000000 310 ranges = <0x02000000 0x00000000 0x80000000 0x00000003 0x80000000 0x00000000 0x80000000
309 01000000 0 00000000 00000002 08000000 0 00010000>; 311 0x01000000 0x00000000 0x00000000 0x00000002 0x08000000 0x00000000 0x00010000>;
310 312
311 /* Inbound 2GB range starting at 0 */ 313 /* Inbound 2GB range starting at 0 */
312 dma-ranges = <42000000 0 0 0 0 0 80000000>; 314 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
313 315
314 /* Ebony has all 4 IRQ pins tied together per slot */ 316 /* Ebony has all 4 IRQ pins tied together per slot */
315 interrupt-map-mask = <f800 0 0 0>; 317 interrupt-map-mask = <0xf800 0x0 0x0 0x0>;
316 interrupt-map = < 318 interrupt-map = <
317 /* IDSEL 1 */ 319 /* IDSEL 1 */
318 0800 0 0 0 &UIC0 17 8 320 0x800 0x0 0x0 0x0 &UIC0 0x17 0x8
319 321
320 /* IDSEL 2 */ 322 /* IDSEL 2 */
321 1000 0 0 0 &UIC0 18 8 323 0x1000 0x0 0x0 0x0 &UIC0 0x18 0x8
322 324
323 /* IDSEL 3 */ 325 /* IDSEL 3 */
324 1800 0 0 0 &UIC0 19 8 326 0x1800 0x0 0x0 0x0 &UIC0 0x19 0x8
325 327
326 /* IDSEL 4 */ 328 /* IDSEL 4 */
327 2000 0 0 0 &UIC0 1a 8 329 0x2000 0x0 0x0 0x0 &UIC0 0x1a 0x8
328 >; 330 >;
329 }; 331 };
330 }; 332 };
diff --git a/arch/powerpc/boot/dts/ep405.dts b/arch/powerpc/boot/dts/ep405.dts
index 92938557ac8a..53ef06cc2134 100644
--- a/arch/powerpc/boot/dts/ep405.dts
+++ b/arch/powerpc/boot/dts/ep405.dts
@@ -9,12 +9,14 @@
9 * any warranty of any kind, whether express or implied. 9 * any warranty of any kind, whether express or implied.
10 */ 10 */
11 11
12/dts-v1/;
13
12/ { 14/ {
13 #address-cells = <1>; 15 #address-cells = <1>;
14 #size-cells = <1>; 16 #size-cells = <1>;
15 model = "ep405"; 17 model = "ep405";
16 compatible = "ep405"; 18 compatible = "ep405";
17 dcr-parent = <&/cpus/cpu@0>; 19 dcr-parent = <&{/cpus/cpu@0}>;
18 20
19 aliases { 21 aliases {
20 ethernet0 = &EMAC; 22 ethernet0 = &EMAC;
@@ -29,13 +31,13 @@
29 cpu@0 { 31 cpu@0 {
30 device_type = "cpu"; 32 device_type = "cpu";
31 model = "PowerPC,405GP"; 33 model = "PowerPC,405GP";
32 reg = <0>; 34 reg = <0x00000000>;
33 clock-frequency = <bebc200>; /* Filled in by zImage */ 35 clock-frequency = <200000000>; /* Filled in by zImage */
34 timebase-frequency = <0>; /* Filled in by zImage */ 36 timebase-frequency = <0>; /* Filled in by zImage */
35 i-cache-line-size = <20>; 37 i-cache-line-size = <32>;
36 d-cache-line-size = <20>; 38 d-cache-line-size = <32>;
37 i-cache-size = <4000>; 39 i-cache-size = <16384>;
38 d-cache-size = <4000>; 40 d-cache-size = <16384>;
39 dcr-controller; 41 dcr-controller;
40 dcr-access-method = "native"; 42 dcr-access-method = "native";
41 }; 43 };
@@ -43,14 +45,14 @@
43 45
44 memory { 46 memory {
45 device_type = "memory"; 47 device_type = "memory";
46 reg = <0 0>; /* Filled in by zImage */ 48 reg = <0x00000000 0x00000000>; /* Filled in by zImage */
47 }; 49 };
48 50
49 UIC0: interrupt-controller { 51 UIC0: interrupt-controller {
50 compatible = "ibm,uic"; 52 compatible = "ibm,uic";
51 interrupt-controller; 53 interrupt-controller;
52 cell-index = <0>; 54 cell-index = <0>;
53 dcr-reg = <0c0 9>; 55 dcr-reg = <0x0c0 0x009>;
54 #address-cells = <0>; 56 #address-cells = <0>;
55 #size-cells = <0>; 57 #size-cells = <0>;
56 #interrupt-cells = <2>; 58 #interrupt-cells = <2>;
@@ -65,91 +67,91 @@
65 67
66 SDRAM0: memory-controller { 68 SDRAM0: memory-controller {
67 compatible = "ibm,sdram-405gp"; 69 compatible = "ibm,sdram-405gp";
68 dcr-reg = <010 2>; 70 dcr-reg = <0x010 0x002>;
69 }; 71 };
70 72
71 MAL: mcmal { 73 MAL: mcmal {
72 compatible = "ibm,mcmal-405gp", "ibm,mcmal"; 74 compatible = "ibm,mcmal-405gp", "ibm,mcmal";
73 dcr-reg = <180 62>; 75 dcr-reg = <0x180 0x062>;
74 num-tx-chans = <1>; 76 num-tx-chans = <1>;
75 num-rx-chans = <1>; 77 num-rx-chans = <1>;
76 interrupt-parent = <&UIC0>; 78 interrupt-parent = <&UIC0>;
77 interrupts = < 79 interrupts = <
78 b 4 /* TXEOB */ 80 0xb 0x4 /* TXEOB */
79 c 4 /* RXEOB */ 81 0xc 0x4 /* RXEOB */
80 a 4 /* SERR */ 82 0xa 0x4 /* SERR */
81 d 4 /* TXDE */ 83 0xd 0x4 /* TXDE */
82 e 4 /* RXDE */>; 84 0xe 0x4 /* RXDE */>;
83 }; 85 };
84 86
85 POB0: opb { 87 POB0: opb {
86 compatible = "ibm,opb-405gp", "ibm,opb"; 88 compatible = "ibm,opb-405gp", "ibm,opb";
87 #address-cells = <1>; 89 #address-cells = <1>;
88 #size-cells = <1>; 90 #size-cells = <1>;
89 ranges = <ef600000 ef600000 a00000>; 91 ranges = <0xef600000 0xef600000 0x00a00000>;
90 dcr-reg = <0a0 5>; 92 dcr-reg = <0x0a0 0x005>;
91 clock-frequency = <0>; /* Filled in by zImage */ 93 clock-frequency = <0>; /* Filled in by zImage */
92 94
93 UART0: serial@ef600300 { 95 UART0: serial@ef600300 {
94 device_type = "serial"; 96 device_type = "serial";
95 compatible = "ns16550"; 97 compatible = "ns16550";
96 reg = <ef600300 8>; 98 reg = <0xef600300 0x00000008>;
97 virtual-reg = <ef600300>; 99 virtual-reg = <0xef600300>;
98 clock-frequency = <0>; /* Filled in by zImage */ 100 clock-frequency = <0>; /* Filled in by zImage */
99 current-speed = <2580>; 101 current-speed = <9600>;
100 interrupt-parent = <&UIC0>; 102 interrupt-parent = <&UIC0>;
101 interrupts = <0 4>; 103 interrupts = <0x0 0x4>;
102 }; 104 };
103 105
104 UART1: serial@ef600400 { 106 UART1: serial@ef600400 {
105 device_type = "serial"; 107 device_type = "serial";
106 compatible = "ns16550"; 108 compatible = "ns16550";
107 reg = <ef600400 8>; 109 reg = <0xef600400 0x00000008>;
108 virtual-reg = <ef600400>; 110 virtual-reg = <0xef600400>;
109 clock-frequency = <0>; /* Filled in by zImage */ 111 clock-frequency = <0>; /* Filled in by zImage */
110 current-speed = <2580>; 112 current-speed = <9600>;
111 interrupt-parent = <&UIC0>; 113 interrupt-parent = <&UIC0>;
112 interrupts = <1 4>; 114 interrupts = <0x1 0x4>;
113 }; 115 };
114 116
115 IIC: i2c@ef600500 { 117 IIC: i2c@ef600500 {
116 compatible = "ibm,iic-405gp", "ibm,iic"; 118 compatible = "ibm,iic-405gp", "ibm,iic";
117 reg = <ef600500 11>; 119 reg = <0xef600500 0x00000011>;
118 interrupt-parent = <&UIC0>; 120 interrupt-parent = <&UIC0>;
119 interrupts = <2 4>; 121 interrupts = <0x2 0x4>;
120 }; 122 };
121 123
122 GPIO: gpio@ef600700 { 124 GPIO: gpio@ef600700 {
123 compatible = "ibm,gpio-405gp"; 125 compatible = "ibm,gpio-405gp";
124 reg = <ef600700 20>; 126 reg = <0xef600700 0x00000020>;
125 }; 127 };
126 128
127 EMAC: ethernet@ef600800 { 129 EMAC: ethernet@ef600800 {
128 linux,network-index = <0>; 130 linux,network-index = <0x0>;
129 device_type = "network"; 131 device_type = "network";
130 compatible = "ibm,emac-405gp", "ibm,emac"; 132 compatible = "ibm,emac-405gp", "ibm,emac";
131 interrupt-parent = <&UIC0>; 133 interrupt-parent = <&UIC0>;
132 interrupts = < 134 interrupts = <
133 f 4 /* Ethernet */ 135 0xf 0x4 /* Ethernet */
134 9 4 /* Ethernet Wake Up */>; 136 0x9 0x4 /* Ethernet Wake Up */>;
135 local-mac-address = [000000000000]; /* Filled in by zImage */ 137 local-mac-address = [000000000000]; /* Filled in by zImage */
136 reg = <ef600800 70>; 138 reg = <0xef600800 0x00000070>;
137 mal-device = <&MAL>; 139 mal-device = <&MAL>;
138 mal-tx-channel = <0>; 140 mal-tx-channel = <0>;
139 mal-rx-channel = <0>; 141 mal-rx-channel = <0>;
140 cell-index = <0>; 142 cell-index = <0>;
141 max-frame-size = <5dc>; 143 max-frame-size = <1500>;
142 rx-fifo-size = <1000>; 144 rx-fifo-size = <4096>;
143 tx-fifo-size = <800>; 145 tx-fifo-size = <2048>;
144 phy-mode = "rmii"; 146 phy-mode = "rmii";
145 phy-map = <00000000>; 147 phy-map = <0x00000000>;
146 }; 148 };
147 149
148 }; 150 };
149 151
150 EBC0: ebc { 152 EBC0: ebc {
151 compatible = "ibm,ebc-405gp", "ibm,ebc"; 153 compatible = "ibm,ebc-405gp", "ibm,ebc";
152 dcr-reg = <012 2>; 154 dcr-reg = <0x012 0x002>;
153 #address-cells = <2>; 155 #address-cells = <2>;
154 #size-cells = <1>; 156 #size-cells = <1>;
155 157
@@ -163,13 +165,13 @@
163 /* NVRAM and RTC */ 165 /* NVRAM and RTC */
164 nvrtc@4,200000 { 166 nvrtc@4,200000 {
165 compatible = "ds1742"; 167 compatible = "ds1742";
166 reg = <4 200000 0>; /* size fixed up by zImage */ 168 reg = <0x00000004 0x00200000 0x00000000>; /* size fixed up by zImage */
167 }; 169 };
168 170
169 /* "BCSR" CPLD contains a PCI irq controller */ 171 /* "BCSR" CPLD contains a PCI irq controller */
170 bcsr@4,0 { 172 bcsr@4,0 {
171 compatible = "ep405-bcsr"; 173 compatible = "ep405-bcsr";
172 reg = <4 0 10>; 174 reg = <0x00000004 0x00000000 0x00000010>;
173 interrupt-controller; 175 interrupt-controller;
174 /* Routing table */ 176 /* Routing table */
175 irq-routing = [ 00 /* SYSERR */ 177 irq-routing = [ 00 /* SYSERR */
@@ -198,26 +200,26 @@
198 #address-cells = <3>; 200 #address-cells = <3>;
199 compatible = "ibm,plb405gp-pci", "ibm,plb-pci"; 201 compatible = "ibm,plb405gp-pci", "ibm,plb-pci";
200 primary; 202 primary;
201 reg = <eec00000 8 /* Config space access */ 203 reg = <0xeec00000 0x00000008 /* Config space access */
202 eed80000 4 /* IACK */ 204 0xeed80000 0x00000004 /* IACK */
203 eed80000 4 /* Special cycle */ 205 0xeed80000 0x00000004 /* Special cycle */
204 ef480000 40>; /* Internal registers */ 206 0xef480000 0x00000040>; /* Internal registers */
205 207
206 /* Outbound ranges, one memory and one IO, 208 /* Outbound ranges, one memory and one IO,
207 * later cannot be changed. Chip supports a second 209 * later cannot be changed. Chip supports a second
208 * IO range but we don't use it for now 210 * IO range but we don't use it for now
209 */ 211 */
210 ranges = <02000000 0 80000000 80000000 0 20000000 212 ranges = <0x02000000 0x00000000 0x80000000 0x80000000 0x00000000 0x20000000
211 01000000 0 00000000 e8000000 0 00010000>; 213 0x01000000 0x00000000 0x00000000 0xe8000000 0x00000000 0x00010000>;
212 214
213 /* Inbound 2GB range starting at 0 */ 215 /* Inbound 2GB range starting at 0 */
214 dma-ranges = <42000000 0 0 0 0 80000000>; 216 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>;
215 217
216 /* That's all I know about IRQs on that thing ... */ 218 /* That's all I know about IRQs on that thing ... */
217 interrupt-map-mask = <f800 0 0 0>; 219 interrupt-map-mask = <0xf800 0x0 0x0 0x0>;
218 interrupt-map = < 220 interrupt-map = <
219 /* USB */ 221 /* USB */
220 7000 0 0 0 &UIC0 1e 8 /* IRQ5 */ 222 0x7000 0x0 0x0 0x0 &UIC0 0x1e 0x8 /* IRQ5 */
221 >; 223 >;
222 }; 224 };
223 }; 225 };
diff --git a/arch/powerpc/boot/dts/glacier.dts b/arch/powerpc/boot/dts/glacier.dts
index 0f2fc077d8db..24cf0dba120c 100644
--- a/arch/powerpc/boot/dts/glacier.dts
+++ b/arch/powerpc/boot/dts/glacier.dts
@@ -8,12 +8,14 @@
8 * any warranty of any kind, whether express or implied. 8 * any warranty of any kind, whether express or implied.
9 */ 9 */
10 10
11/dts-v1/;
12
11/ { 13/ {
12 #address-cells = <2>; 14 #address-cells = <2>;
13 #size-cells = <1>; 15 #size-cells = <1>;
14 model = "amcc,glacier"; 16 model = "amcc,glacier";
15 compatible = "amcc,glacier", "amcc,canyonlands"; 17 compatible = "amcc,glacier", "amcc,canyonlands";
16 dcr-parent = <&/cpus/cpu@0>; 18 dcr-parent = <&{/cpus/cpu@0}>;
17 19
18 aliases { 20 aliases {
19 ethernet0 = &EMAC0; 21 ethernet0 = &EMAC0;
@@ -31,13 +33,13 @@
31 cpu@0 { 33 cpu@0 {
32 device_type = "cpu"; 34 device_type = "cpu";
33 model = "PowerPC,460GT"; 35 model = "PowerPC,460GT";
34 reg = <0>; 36 reg = <0x00000000>;
35 clock-frequency = <0>; /* Filled in by U-Boot */ 37 clock-frequency = <0>; /* Filled in by U-Boot */
36 timebase-frequency = <0>; /* Filled in by U-Boot */ 38 timebase-frequency = <0>; /* Filled in by U-Boot */
37 i-cache-line-size = <20>; 39 i-cache-line-size = <32>;
38 d-cache-line-size = <20>; 40 d-cache-line-size = <32>;
39 i-cache-size = <8000>; 41 i-cache-size = <32768>;
40 d-cache-size = <8000>; 42 d-cache-size = <32768>;
41 dcr-controller; 43 dcr-controller;
42 dcr-access-method = "native"; 44 dcr-access-method = "native";
43 }; 45 };
@@ -45,14 +47,14 @@
45 47
46 memory { 48 memory {
47 device_type = "memory"; 49 device_type = "memory";
48 reg = <0 0 0>; /* Filled in by U-Boot */ 50 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
49 }; 51 };
50 52
51 UIC0: interrupt-controller0 { 53 UIC0: interrupt-controller0 {
52 compatible = "ibm,uic-460gt","ibm,uic"; 54 compatible = "ibm,uic-460gt","ibm,uic";
53 interrupt-controller; 55 interrupt-controller;
54 cell-index = <0>; 56 cell-index = <0>;
55 dcr-reg = <0c0 009>; 57 dcr-reg = <0x0c0 0x009>;
56 #address-cells = <0>; 58 #address-cells = <0>;
57 #size-cells = <0>; 59 #size-cells = <0>;
58 #interrupt-cells = <2>; 60 #interrupt-cells = <2>;
@@ -62,11 +64,11 @@
62 compatible = "ibm,uic-460gt","ibm,uic"; 64 compatible = "ibm,uic-460gt","ibm,uic";
63 interrupt-controller; 65 interrupt-controller;
64 cell-index = <1>; 66 cell-index = <1>;
65 dcr-reg = <0d0 009>; 67 dcr-reg = <0x0d0 0x009>;
66 #address-cells = <0>; 68 #address-cells = <0>;
67 #size-cells = <0>; 69 #size-cells = <0>;
68 #interrupt-cells = <2>; 70 #interrupt-cells = <2>;
69 interrupts = <1e 4 1f 4>; /* cascade */ 71 interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
70 interrupt-parent = <&UIC0>; 72 interrupt-parent = <&UIC0>;
71 }; 73 };
72 74
@@ -74,11 +76,11 @@
74 compatible = "ibm,uic-460gt","ibm,uic"; 76 compatible = "ibm,uic-460gt","ibm,uic";
75 interrupt-controller; 77 interrupt-controller;
76 cell-index = <2>; 78 cell-index = <2>;
77 dcr-reg = <0e0 009>; 79 dcr-reg = <0x0e0 0x009>;
78 #address-cells = <0>; 80 #address-cells = <0>;
79 #size-cells = <0>; 81 #size-cells = <0>;
80 #interrupt-cells = <2>; 82 #interrupt-cells = <2>;
81 interrupts = <a 4 b 4>; /* cascade */ 83 interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
82 interrupt-parent = <&UIC0>; 84 interrupt-parent = <&UIC0>;
83 }; 85 };
84 86
@@ -86,22 +88,22 @@
86 compatible = "ibm,uic-460gt","ibm,uic"; 88 compatible = "ibm,uic-460gt","ibm,uic";
87 interrupt-controller; 89 interrupt-controller;
88 cell-index = <3>; 90 cell-index = <3>;
89 dcr-reg = <0f0 009>; 91 dcr-reg = <0x0f0 0x009>;
90 #address-cells = <0>; 92 #address-cells = <0>;
91 #size-cells = <0>; 93 #size-cells = <0>;
92 #interrupt-cells = <2>; 94 #interrupt-cells = <2>;
93 interrupts = <10 4 11 4>; /* cascade */ 95 interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
94 interrupt-parent = <&UIC0>; 96 interrupt-parent = <&UIC0>;
95 }; 97 };
96 98
97 SDR0: sdr { 99 SDR0: sdr {
98 compatible = "ibm,sdr-460gt"; 100 compatible = "ibm,sdr-460gt";
99 dcr-reg = <00e 002>; 101 dcr-reg = <0x00e 0x002>;
100 }; 102 };
101 103
102 CPR0: cpr { 104 CPR0: cpr {
103 compatible = "ibm,cpr-460gt"; 105 compatible = "ibm,cpr-460gt";
104 dcr-reg = <00c 002>; 106 dcr-reg = <0x00c 0x002>;
105 }; 107 };
106 108
107 plb { 109 plb {
@@ -113,75 +115,75 @@
113 115
114 SDRAM0: sdram { 116 SDRAM0: sdram {
115 compatible = "ibm,sdram-460gt", "ibm,sdram-405gp"; 117 compatible = "ibm,sdram-460gt", "ibm,sdram-405gp";
116 dcr-reg = <010 2>; 118 dcr-reg = <0x010 0x002>;
117 }; 119 };
118 120
119 MAL0: mcmal { 121 MAL0: mcmal {
120 compatible = "ibm,mcmal-460gt", "ibm,mcmal2"; 122 compatible = "ibm,mcmal-460gt", "ibm,mcmal2";
121 dcr-reg = <180 62>; 123 dcr-reg = <0x180 0x062>;
122 num-tx-chans = <4>; 124 num-tx-chans = <4>;
123 num-rx-chans = <20>; 125 num-rx-chans = <32>;
124 #address-cells = <0>; 126 #address-cells = <0>;
125 #size-cells = <0>; 127 #size-cells = <0>;
126 interrupt-parent = <&UIC2>; 128 interrupt-parent = <&UIC2>;
127 interrupts = < /*TXEOB*/ 6 4 129 interrupts = < /*TXEOB*/ 0x6 0x4
128 /*RXEOB*/ 7 4 130 /*RXEOB*/ 0x7 0x4
129 /*SERR*/ 3 4 131 /*SERR*/ 0x3 0x4
130 /*TXDE*/ 4 4 132 /*TXDE*/ 0x4 0x4
131 /*RXDE*/ 5 4>; 133 /*RXDE*/ 0x5 0x4>;
132 desc-base-addr-high = <8>; 134 desc-base-addr-high = <0x8>;
133 }; 135 };
134 136
135 POB0: opb { 137 POB0: opb {
136 compatible = "ibm,opb-460gt", "ibm,opb"; 138 compatible = "ibm,opb-460gt", "ibm,opb";
137 #address-cells = <1>; 139 #address-cells = <1>;
138 #size-cells = <1>; 140 #size-cells = <1>;
139 ranges = <b0000000 4 b0000000 50000000>; 141 ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>;
140 clock-frequency = <0>; /* Filled in by U-Boot */ 142 clock-frequency = <0>; /* Filled in by U-Boot */
141 143
142 EBC0: ebc { 144 EBC0: ebc {
143 compatible = "ibm,ebc-460gt", "ibm,ebc"; 145 compatible = "ibm,ebc-460gt", "ibm,ebc";
144 dcr-reg = <012 2>; 146 dcr-reg = <0x012 0x002>;
145 #address-cells = <2>; 147 #address-cells = <2>;
146 #size-cells = <1>; 148 #size-cells = <1>;
147 clock-frequency = <0>; /* Filled in by U-Boot */ 149 clock-frequency = <0>; /* Filled in by U-Boot */
148 /* ranges property is supplied by U-Boot */ 150 /* ranges property is supplied by U-Boot */
149 interrupts = <6 4>; 151 interrupts = <0x6 0x4>;
150 interrupt-parent = <&UIC1>; 152 interrupt-parent = <&UIC1>;
151 153
152 nor_flash@0,0 { 154 nor_flash@0,0 {
153 compatible = "amd,s29gl512n", "cfi-flash"; 155 compatible = "amd,s29gl512n", "cfi-flash";
154 bank-width = <2>; 156 bank-width = <2>;
155 reg = <0 000000 4000000>; 157 reg = <0x00000000 0x00000000 0x04000000>;
156 #address-cells = <1>; 158 #address-cells = <1>;
157 #size-cells = <1>; 159 #size-cells = <1>;
158 partition@0 { 160 partition@0 {
159 label = "kernel"; 161 label = "kernel";
160 reg = <0 1e0000>; 162 reg = <0x00000000 0x001e0000>;
161 }; 163 };
162 partition@1e0000 { 164 partition@1e0000 {
163 label = "dtb"; 165 label = "dtb";
164 reg = <1e0000 20000>; 166 reg = <0x001e0000 0x00020000>;
165 }; 167 };
166 partition@200000 { 168 partition@200000 {
167 label = "ramdisk"; 169 label = "ramdisk";
168 reg = <200000 1400000>; 170 reg = <0x00200000 0x01400000>;
169 }; 171 };
170 partition@1600000 { 172 partition@1600000 {
171 label = "jffs2"; 173 label = "jffs2";
172 reg = <1600000 400000>; 174 reg = <0x01600000 0x00400000>;
173 }; 175 };
174 partition@1a00000 { 176 partition@1a00000 {
175 label = "user"; 177 label = "user";
176 reg = <1a00000 2560000>; 178 reg = <0x01a00000 0x02560000>;
177 }; 179 };
178 partition@3f60000 { 180 partition@3f60000 {
179 label = "env"; 181 label = "env";
180 reg = <3f60000 40000>; 182 reg = <0x03f60000 0x00040000>;
181 }; 183 };
182 partition@3fa0000 { 184 partition@3fa0000 {
183 label = "u-boot"; 185 label = "u-boot";
184 reg = <3fa0000 60000>; 186 reg = <0x03fa0000 0x00060000>;
185 }; 187 };
186 }; 188 };
187 }; 189 };
@@ -189,109 +191,109 @@
189 UART0: serial@ef600300 { 191 UART0: serial@ef600300 {
190 device_type = "serial"; 192 device_type = "serial";
191 compatible = "ns16550"; 193 compatible = "ns16550";
192 reg = <ef600300 8>; 194 reg = <0xef600300 0x00000008>;
193 virtual-reg = <ef600300>; 195 virtual-reg = <0xef600300>;
194 clock-frequency = <0>; /* Filled in by U-Boot */ 196 clock-frequency = <0>; /* Filled in by U-Boot */
195 current-speed = <0>; /* Filled in by U-Boot */ 197 current-speed = <0>; /* Filled in by U-Boot */
196 interrupt-parent = <&UIC1>; 198 interrupt-parent = <&UIC1>;
197 interrupts = <1 4>; 199 interrupts = <0x1 0x4>;
198 }; 200 };
199 201
200 UART1: serial@ef600400 { 202 UART1: serial@ef600400 {
201 device_type = "serial"; 203 device_type = "serial";
202 compatible = "ns16550"; 204 compatible = "ns16550";
203 reg = <ef600400 8>; 205 reg = <0xef600400 0x00000008>;
204 virtual-reg = <ef600400>; 206 virtual-reg = <0xef600400>;
205 clock-frequency = <0>; /* Filled in by U-Boot */ 207 clock-frequency = <0>; /* Filled in by U-Boot */
206 current-speed = <0>; /* Filled in by U-Boot */ 208 current-speed = <0>; /* Filled in by U-Boot */
207 interrupt-parent = <&UIC0>; 209 interrupt-parent = <&UIC0>;
208 interrupts = <1 4>; 210 interrupts = <0x1 0x4>;
209 }; 211 };
210 212
211 UART2: serial@ef600500 { 213 UART2: serial@ef600500 {
212 device_type = "serial"; 214 device_type = "serial";
213 compatible = "ns16550"; 215 compatible = "ns16550";
214 reg = <ef600500 8>; 216 reg = <0xef600500 0x00000008>;
215 virtual-reg = <ef600500>; 217 virtual-reg = <0xef600500>;
216 clock-frequency = <0>; /* Filled in by U-Boot */ 218 clock-frequency = <0>; /* Filled in by U-Boot */
217 current-speed = <0>; /* Filled in by U-Boot */ 219 current-speed = <0>; /* Filled in by U-Boot */
218 interrupt-parent = <&UIC1>; 220 interrupt-parent = <&UIC1>;
219 interrupts = <1d 4>; 221 interrupts = <0x1d 0x4>;
220 }; 222 };
221 223
222 UART3: serial@ef600600 { 224 UART3: serial@ef600600 {
223 device_type = "serial"; 225 device_type = "serial";
224 compatible = "ns16550"; 226 compatible = "ns16550";
225 reg = <ef600600 8>; 227 reg = <0xef600600 0x00000008>;
226 virtual-reg = <ef600600>; 228 virtual-reg = <0xef600600>;
227 clock-frequency = <0>; /* Filled in by U-Boot */ 229 clock-frequency = <0>; /* Filled in by U-Boot */
228 current-speed = <0>; /* Filled in by U-Boot */ 230 current-speed = <0>; /* Filled in by U-Boot */
229 interrupt-parent = <&UIC1>; 231 interrupt-parent = <&UIC1>;
230 interrupts = <1e 4>; 232 interrupts = <0x1e 0x4>;
231 }; 233 };
232 234
233 IIC0: i2c@ef600700 { 235 IIC0: i2c@ef600700 {
234 compatible = "ibm,iic-460gt", "ibm,iic"; 236 compatible = "ibm,iic-460gt", "ibm,iic";
235 reg = <ef600700 14>; 237 reg = <0xef600700 0x00000014>;
236 interrupt-parent = <&UIC0>; 238 interrupt-parent = <&UIC0>;
237 interrupts = <2 4>; 239 interrupts = <0x2 0x4>;
238 }; 240 };
239 241
240 IIC1: i2c@ef600800 { 242 IIC1: i2c@ef600800 {
241 compatible = "ibm,iic-460gt", "ibm,iic"; 243 compatible = "ibm,iic-460gt", "ibm,iic";
242 reg = <ef600800 14>; 244 reg = <0xef600800 0x00000014>;
243 interrupt-parent = <&UIC0>; 245 interrupt-parent = <&UIC0>;
244 interrupts = <3 4>; 246 interrupts = <0x3 0x4>;
245 }; 247 };
246 248
247 ZMII0: emac-zmii@ef600d00 { 249 ZMII0: emac-zmii@ef600d00 {
248 compatible = "ibm,zmii-460gt", "ibm,zmii"; 250 compatible = "ibm,zmii-460gt", "ibm,zmii";
249 reg = <ef600d00 c>; 251 reg = <0xef600d00 0x0000000c>;
250 }; 252 };
251 253
252 RGMII0: emac-rgmii@ef601500 { 254 RGMII0: emac-rgmii@ef601500 {
253 compatible = "ibm,rgmii-460gt", "ibm,rgmii"; 255 compatible = "ibm,rgmii-460gt", "ibm,rgmii";
254 reg = <ef601500 8>; 256 reg = <0xef601500 0x00000008>;
255 has-mdio; 257 has-mdio;
256 }; 258 };
257 259
258 RGMII1: emac-rgmii@ef601600 { 260 RGMII1: emac-rgmii@ef601600 {
259 compatible = "ibm,rgmii-460gt", "ibm,rgmii"; 261 compatible = "ibm,rgmii-460gt", "ibm,rgmii";
260 reg = <ef601600 8>; 262 reg = <0xef601600 0x00000008>;
261 has-mdio; 263 has-mdio;
262 }; 264 };
263 265
264 TAH0: emac-tah@ef601350 { 266 TAH0: emac-tah@ef601350 {
265 compatible = "ibm,tah-460gt", "ibm,tah"; 267 compatible = "ibm,tah-460gt", "ibm,tah";
266 reg = <ef601350 30>; 268 reg = <0xef601350 0x00000030>;
267 }; 269 };
268 270
269 TAH1: emac-tah@ef601450 { 271 TAH1: emac-tah@ef601450 {
270 compatible = "ibm,tah-460gt", "ibm,tah"; 272 compatible = "ibm,tah-460gt", "ibm,tah";
271 reg = <ef601450 30>; 273 reg = <0xef601450 0x00000030>;
272 }; 274 };
273 275
274 EMAC0: ethernet@ef600e00 { 276 EMAC0: ethernet@ef600e00 {
275 device_type = "network"; 277 device_type = "network";
276 compatible = "ibm,emac-460gt", "ibm,emac4"; 278 compatible = "ibm,emac-460gt", "ibm,emac4";
277 interrupt-parent = <&EMAC0>; 279 interrupt-parent = <&EMAC0>;
278 interrupts = <0 1>; 280 interrupts = <0x0 0x1>;
279 #interrupt-cells = <1>; 281 #interrupt-cells = <1>;
280 #address-cells = <0>; 282 #address-cells = <0>;
281 #size-cells = <0>; 283 #size-cells = <0>;
282 interrupt-map = </*Status*/ 0 &UIC2 10 4 284 interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4
283 /*Wake*/ 1 &UIC2 14 4>; 285 /*Wake*/ 0x1 &UIC2 0x14 0x4>;
284 reg = <ef600e00 70>; 286 reg = <0xef600e00 0x00000074>;
285 local-mac-address = [000000000000]; /* Filled in by U-Boot */ 287 local-mac-address = [000000000000]; /* Filled in by U-Boot */
286 mal-device = <&MAL0>; 288 mal-device = <&MAL0>;
287 mal-tx-channel = <0>; 289 mal-tx-channel = <0>;
288 mal-rx-channel = <0>; 290 mal-rx-channel = <0>;
289 cell-index = <0>; 291 cell-index = <0>;
290 max-frame-size = <2328>; 292 max-frame-size = <9000>;
291 rx-fifo-size = <1000>; 293 rx-fifo-size = <4096>;
292 tx-fifo-size = <800>; 294 tx-fifo-size = <2048>;
293 phy-mode = "rgmii"; 295 phy-mode = "rgmii";
294 phy-map = <00000000>; 296 phy-map = <0x00000000>;
295 rgmii-device = <&RGMII0>; 297 rgmii-device = <&RGMII0>;
296 rgmii-channel = <0>; 298 rgmii-channel = <0>;
297 tah-device = <&TAH0>; 299 tah-device = <&TAH0>;
@@ -304,23 +306,23 @@
304 device_type = "network"; 306 device_type = "network";
305 compatible = "ibm,emac-460gt", "ibm,emac4"; 307 compatible = "ibm,emac-460gt", "ibm,emac4";
306 interrupt-parent = <&EMAC1>; 308 interrupt-parent = <&EMAC1>;
307 interrupts = <0 1>; 309 interrupts = <0x0 0x1>;
308 #interrupt-cells = <1>; 310 #interrupt-cells = <1>;
309 #address-cells = <0>; 311 #address-cells = <0>;
310 #size-cells = <0>; 312 #size-cells = <0>;
311 interrupt-map = </*Status*/ 0 &UIC2 11 4 313 interrupt-map = </*Status*/ 0x0 &UIC2 0x11 0x4
312 /*Wake*/ 1 &UIC2 15 4>; 314 /*Wake*/ 0x1 &UIC2 0x15 0x4>;
313 reg = <ef600f00 70>; 315 reg = <0xef600f00 0x00000074>;
314 local-mac-address = [000000000000]; /* Filled in by U-Boot */ 316 local-mac-address = [000000000000]; /* Filled in by U-Boot */
315 mal-device = <&MAL0>; 317 mal-device = <&MAL0>;
316 mal-tx-channel = <1>; 318 mal-tx-channel = <1>;
317 mal-rx-channel = <8>; 319 mal-rx-channel = <8>;
318 cell-index = <1>; 320 cell-index = <1>;
319 max-frame-size = <2328>; 321 max-frame-size = <9000>;
320 rx-fifo-size = <1000>; 322 rx-fifo-size = <4096>;
321 tx-fifo-size = <800>; 323 tx-fifo-size = <2048>;
322 phy-mode = "rgmii"; 324 phy-mode = "rgmii";
323 phy-map = <00000000>; 325 phy-map = <0x00000000>;
324 rgmii-device = <&RGMII0>; 326 rgmii-device = <&RGMII0>;
325 rgmii-channel = <1>; 327 rgmii-channel = <1>;
326 tah-device = <&TAH1>; 328 tah-device = <&TAH1>;
@@ -334,23 +336,23 @@
334 device_type = "network"; 336 device_type = "network";
335 compatible = "ibm,emac-460gt", "ibm,emac4"; 337 compatible = "ibm,emac-460gt", "ibm,emac4";
336 interrupt-parent = <&EMAC2>; 338 interrupt-parent = <&EMAC2>;
337 interrupts = <0 1>; 339 interrupts = <0x0 0x1>;
338 #interrupt-cells = <1>; 340 #interrupt-cells = <1>;
339 #address-cells = <0>; 341 #address-cells = <0>;
340 #size-cells = <0>; 342 #size-cells = <0>;
341 interrupt-map = </*Status*/ 0 &UIC2 12 4 343 interrupt-map = </*Status*/ 0x0 &UIC2 0x12 0x4
342 /*Wake*/ 1 &UIC2 16 4>; 344 /*Wake*/ 0x1 &UIC2 0x16 0x4>;
343 reg = <ef601100 70>; 345 reg = <0xef601100 0x00000074>;
344 local-mac-address = [000000000000]; /* Filled in by U-Boot */ 346 local-mac-address = [000000000000]; /* Filled in by U-Boot */
345 mal-device = <&MAL0>; 347 mal-device = <&MAL0>;
346 mal-tx-channel = <2>; 348 mal-tx-channel = <2>;
347 mal-rx-channel = <10>; 349 mal-rx-channel = <16>;
348 cell-index = <2>; 350 cell-index = <2>;
349 max-frame-size = <2328>; 351 max-frame-size = <9000>;
350 rx-fifo-size = <1000>; 352 rx-fifo-size = <4096>;
351 tx-fifo-size = <800>; 353 tx-fifo-size = <2048>;
352 phy-mode = "rgmii"; 354 phy-mode = "rgmii";
353 phy-map = <00000000>; 355 phy-map = <0x00000000>;
354 rgmii-device = <&RGMII1>; 356 rgmii-device = <&RGMII1>;
355 rgmii-channel = <0>; 357 rgmii-channel = <0>;
356 has-inverted-stacr-oc; 358 has-inverted-stacr-oc;
@@ -362,23 +364,23 @@
362 device_type = "network"; 364 device_type = "network";
363 compatible = "ibm,emac-460gt", "ibm,emac4"; 365 compatible = "ibm,emac-460gt", "ibm,emac4";
364 interrupt-parent = <&EMAC3>; 366 interrupt-parent = <&EMAC3>;
365 interrupts = <0 1>; 367 interrupts = <0x0 0x1>;
366 #interrupt-cells = <1>; 368 #interrupt-cells = <1>;
367 #address-cells = <0>; 369 #address-cells = <0>;
368 #size-cells = <0>; 370 #size-cells = <0>;
369 interrupt-map = </*Status*/ 0 &UIC2 13 4 371 interrupt-map = </*Status*/ 0x0 &UIC2 0x13 0x4
370 /*Wake*/ 1 &UIC2 17 4>; 372 /*Wake*/ 0x1 &UIC2 0x17 0x4>;
371 reg = <ef601200 70>; 373 reg = <0xef601200 0x00000074>;
372 local-mac-address = [000000000000]; /* Filled in by U-Boot */ 374 local-mac-address = [000000000000]; /* Filled in by U-Boot */
373 mal-device = <&MAL0>; 375 mal-device = <&MAL0>;
374 mal-tx-channel = <3>; 376 mal-tx-channel = <3>;
375 mal-rx-channel = <18>; 377 mal-rx-channel = <24>;
376 cell-index = <3>; 378 cell-index = <3>;
377 max-frame-size = <2328>; 379 max-frame-size = <9000>;
378 rx-fifo-size = <1000>; 380 rx-fifo-size = <4096>;
379 tx-fifo-size = <800>; 381 tx-fifo-size = <2048>;
380 phy-mode = "rgmii"; 382 phy-mode = "rgmii";
381 phy-map = <00000000>; 383 phy-map = <0x00000000>;
382 rgmii-device = <&RGMII1>; 384 rgmii-device = <&RGMII1>;
383 rgmii-channel = <1>; 385 rgmii-channel = <1>;
384 has-inverted-stacr-oc; 386 has-inverted-stacr-oc;
@@ -396,27 +398,27 @@
396 primary; 398 primary;
397 large-inbound-windows; 399 large-inbound-windows;
398 enable-msi-hole; 400 enable-msi-hole;
399 reg = <c 0ec00000 8 /* Config space access */ 401 reg = <0x0000000c 0x0ec00000 0x00000008 /* Config space access */
400 0 0 0 /* no IACK cycles */ 402 0x00000000 0x00000000 0x00000000 /* no IACK cycles */
401 c 0ed00000 4 /* Special cycles */ 403 0x0000000c 0x0ed00000 0x00000004 /* Special cycles */
402 c 0ec80000 100 /* Internal registers */ 404 0x0000000c 0x0ec80000 0x00000100 /* Internal registers */
403 c 0ec80100 fc>; /* Internal messaging registers */ 405 0x0000000c 0x0ec80100 0x000000fc>; /* Internal messaging registers */
404 406
405 /* Outbound ranges, one memory and one IO, 407 /* Outbound ranges, one memory and one IO,
406 * later cannot be changed 408 * later cannot be changed
407 */ 409 */
408 ranges = <02000000 0 80000000 0000000d 80000000 0 80000000 410 ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000
409 01000000 0 00000000 0000000c 08000000 0 00010000>; 411 0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>;
410 412
411 /* Inbound 2GB range starting at 0 */ 413 /* Inbound 2GB range starting at 0 */
412 dma-ranges = <42000000 0 0 0 0 0 80000000>; 414 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
413 415
414 /* This drives busses 0 to 0x3f */ 416 /* This drives busses 0 to 0x3f */
415 bus-range = <0 3f>; 417 bus-range = <0x0 0x3f>;
416 418
417 /* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */ 419 /* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */
418 interrupt-map-mask = <0000 0 0 0>; 420 interrupt-map-mask = <0x0 0x0 0x0 0x0>;
419 interrupt-map = < 0000 0 0 0 &UIC1 0 8 >; 421 interrupt-map = < 0x0 0x0 0x0 0x0 &UIC1 0x0 0x8 >;
420 }; 422 };
421 423
422 PCIE0: pciex@d00000000 { 424 PCIE0: pciex@d00000000 {
@@ -426,23 +428,23 @@
426 #address-cells = <3>; 428 #address-cells = <3>;
427 compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex"; 429 compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
428 primary; 430 primary;
429 port = <0>; /* port number */ 431 port = <0x0>; /* port number */
430 reg = <d 00000000 20000000 /* Config space access */ 432 reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */
431 c 08010000 00001000>; /* Registers */ 433 0x0000000c 0x08010000 0x00001000>; /* Registers */
432 dcr-reg = <100 020>; 434 dcr-reg = <0x100 0x020>;
433 sdr-base = <300>; 435 sdr-base = <0x300>;
434 436
435 /* Outbound ranges, one memory and one IO, 437 /* Outbound ranges, one memory and one IO,
436 * later cannot be changed 438 * later cannot be changed
437 */ 439 */
438 ranges = <02000000 0 80000000 0000000e 00000000 0 80000000 440 ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000
439 01000000 0 00000000 0000000f 80000000 0 00010000>; 441 0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;
440 442
441 /* Inbound 2GB range starting at 0 */ 443 /* Inbound 2GB range starting at 0 */
442 dma-ranges = <42000000 0 0 0 0 0 80000000>; 444 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
443 445
444 /* This drives busses 40 to 0x7f */ 446 /* This drives busses 40 to 0x7f */
445 bus-range = <40 7f>; 447 bus-range = <0x40 0x7f>;
446 448
447 /* Legacy interrupts (note the weird polarity, the bridge seems 449 /* Legacy interrupts (note the weird polarity, the bridge seems
448 * to invert PCIe legacy interrupts). 450 * to invert PCIe legacy interrupts).
@@ -452,12 +454,12 @@
452 * below are basically de-swizzled numbers. 454 * below are basically de-swizzled numbers.
453 * The real slot is on idsel 0, so the swizzling is 1:1 455 * The real slot is on idsel 0, so the swizzling is 1:1
454 */ 456 */
455 interrupt-map-mask = <0000 0 0 7>; 457 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
456 interrupt-map = < 458 interrupt-map = <
457 0000 0 0 1 &UIC3 c 4 /* swizzled int A */ 459 0x0 0x0 0x0 0x1 &UIC3 0xc 0x4 /* swizzled int A */
458 0000 0 0 2 &UIC3 d 4 /* swizzled int B */ 460 0x0 0x0 0x0 0x2 &UIC3 0xd 0x4 /* swizzled int B */
459 0000 0 0 3 &UIC3 e 4 /* swizzled int C */ 461 0x0 0x0 0x0 0x3 &UIC3 0xe 0x4 /* swizzled int C */
460 0000 0 0 4 &UIC3 f 4 /* swizzled int D */>; 462 0x0 0x0 0x0 0x4 &UIC3 0xf 0x4 /* swizzled int D */>;
461 }; 463 };
462 464
463 PCIE1: pciex@d20000000 { 465 PCIE1: pciex@d20000000 {
@@ -467,23 +469,23 @@
467 #address-cells = <3>; 469 #address-cells = <3>;
468 compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex"; 470 compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
469 primary; 471 primary;
470 port = <1>; /* port number */ 472 port = <0x1>; /* port number */
471 reg = <d 20000000 20000000 /* Config space access */ 473 reg = <0x0000000d 0x20000000 0x20000000 /* Config space access */
472 c 08011000 00001000>; /* Registers */ 474 0x0000000c 0x08011000 0x00001000>; /* Registers */
473 dcr-reg = <120 020>; 475 dcr-reg = <0x120 0x020>;
474 sdr-base = <340>; 476 sdr-base = <0x340>;
475 477
476 /* Outbound ranges, one memory and one IO, 478 /* Outbound ranges, one memory and one IO,
477 * later cannot be changed 479 * later cannot be changed
478 */ 480 */
479 ranges = <02000000 0 80000000 0000000e 80000000 0 80000000 481 ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000
480 01000000 0 00000000 0000000f 80010000 0 00010000>; 482 0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>;
481 483
482 /* Inbound 2GB range starting at 0 */ 484 /* Inbound 2GB range starting at 0 */
483 dma-ranges = <42000000 0 0 0 0 0 80000000>; 485 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
484 486
485 /* This drives busses 80 to 0xbf */ 487 /* This drives busses 80 to 0xbf */
486 bus-range = <80 bf>; 488 bus-range = <0x80 0xbf>;
487 489
488 /* Legacy interrupts (note the weird polarity, the bridge seems 490 /* Legacy interrupts (note the weird polarity, the bridge seems
489 * to invert PCIe legacy interrupts). 491 * to invert PCIe legacy interrupts).
@@ -493,12 +495,12 @@
493 * below are basically de-swizzled numbers. 495 * below are basically de-swizzled numbers.
494 * The real slot is on idsel 0, so the swizzling is 1:1 496 * The real slot is on idsel 0, so the swizzling is 1:1
495 */ 497 */
496 interrupt-map-mask = <0000 0 0 7>; 498 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
497 interrupt-map = < 499 interrupt-map = <
498 0000 0 0 1 &UIC3 10 4 /* swizzled int A */ 500 0x0 0x0 0x0 0x1 &UIC3 0x10 0x4 /* swizzled int A */
499 0000 0 0 2 &UIC3 11 4 /* swizzled int B */ 501 0x0 0x0 0x0 0x2 &UIC3 0x11 0x4 /* swizzled int B */
500 0000 0 0 3 &UIC3 12 4 /* swizzled int C */ 502 0x0 0x0 0x0 0x3 &UIC3 0x12 0x4 /* swizzled int C */
501 0000 0 0 4 &UIC3 13 4 /* swizzled int D */>; 503 0x0 0x0 0x0 0x4 &UIC3 0x13 0x4 /* swizzled int D */>;
502 }; 504 };
503 }; 505 };
504}; 506};
diff --git a/arch/powerpc/boot/dts/haleakala.dts b/arch/powerpc/boot/dts/haleakala.dts
index b5d95ac24dbf..513bc43a71af 100644
--- a/arch/powerpc/boot/dts/haleakala.dts
+++ b/arch/powerpc/boot/dts/haleakala.dts
@@ -8,12 +8,14 @@
8 * any warranty of any kind, whether express or implied. 8 * any warranty of any kind, whether express or implied.
9 */ 9 */
10 10
11/dts-v1/;
12
11/ { 13/ {
12 #address-cells = <1>; 14 #address-cells = <1>;
13 #size-cells = <1>; 15 #size-cells = <1>;
14 model = "amcc,haleakala"; 16 model = "amcc,haleakala";
15 compatible = "amcc,haleakala", "amcc,kilauea"; 17 compatible = "amcc,haleakala", "amcc,kilauea";
16 dcr-parent = <&/cpus/cpu@0>; 18 dcr-parent = <&{/cpus/cpu@0}>;
17 19
18 aliases { 20 aliases {
19 ethernet0 = &EMAC0; 21 ethernet0 = &EMAC0;
@@ -28,13 +30,13 @@
28 cpu@0 { 30 cpu@0 {
29 device_type = "cpu"; 31 device_type = "cpu";
30 model = "PowerPC,405EXr"; 32 model = "PowerPC,405EXr";
31 reg = <0>; 33 reg = <0x00000000>;
32 clock-frequency = <0>; /* Filled in by U-Boot */ 34 clock-frequency = <0>; /* Filled in by U-Boot */
33 timebase-frequency = <0>; /* Filled in by U-Boot */ 35 timebase-frequency = <0>; /* Filled in by U-Boot */
34 i-cache-line-size = <20>; 36 i-cache-line-size = <32>;
35 d-cache-line-size = <20>; 37 d-cache-line-size = <32>;
36 i-cache-size = <4000>; /* 16 kB */ 38 i-cache-size = <16384>; /* 16 kB */
37 d-cache-size = <4000>; /* 16 kB */ 39 d-cache-size = <16384>; /* 16 kB */
38 dcr-controller; 40 dcr-controller;
39 dcr-access-method = "native"; 41 dcr-access-method = "native";
40 }; 42 };
@@ -42,14 +44,14 @@
42 44
43 memory { 45 memory {
44 device_type = "memory"; 46 device_type = "memory";
45 reg = <0 0>; /* Filled in by U-Boot */ 47 reg = <0x00000000 0x00000000>; /* Filled in by U-Boot */
46 }; 48 };
47 49
48 UIC0: interrupt-controller { 50 UIC0: interrupt-controller {
49 compatible = "ibm,uic-405exr", "ibm,uic"; 51 compatible = "ibm,uic-405exr", "ibm,uic";
50 interrupt-controller; 52 interrupt-controller;
51 cell-index = <0>; 53 cell-index = <0>;
52 dcr-reg = <0c0 009>; 54 dcr-reg = <0x0c0 0x009>;
53 #address-cells = <0>; 55 #address-cells = <0>;
54 #size-cells = <0>; 56 #size-cells = <0>;
55 #interrupt-cells = <2>; 57 #interrupt-cells = <2>;
@@ -59,11 +61,11 @@
59 compatible = "ibm,uic-405exr","ibm,uic"; 61 compatible = "ibm,uic-405exr","ibm,uic";
60 interrupt-controller; 62 interrupt-controller;
61 cell-index = <1>; 63 cell-index = <1>;
62 dcr-reg = <0d0 009>; 64 dcr-reg = <0x0d0 0x009>;
63 #address-cells = <0>; 65 #address-cells = <0>;
64 #size-cells = <0>; 66 #size-cells = <0>;
65 #interrupt-cells = <2>; 67 #interrupt-cells = <2>;
66 interrupts = <1e 4 1f 4>; /* cascade */ 68 interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
67 interrupt-parent = <&UIC0>; 69 interrupt-parent = <&UIC0>;
68 }; 70 };
69 71
@@ -71,11 +73,11 @@
71 compatible = "ibm,uic-405exr","ibm,uic"; 73 compatible = "ibm,uic-405exr","ibm,uic";
72 interrupt-controller; 74 interrupt-controller;
73 cell-index = <2>; 75 cell-index = <2>;
74 dcr-reg = <0e0 009>; 76 dcr-reg = <0x0e0 0x009>;
75 #address-cells = <0>; 77 #address-cells = <0>;
76 #size-cells = <0>; 78 #size-cells = <0>;
77 #interrupt-cells = <2>; 79 #interrupt-cells = <2>;
78 interrupts = <1c 4 1d 4>; /* cascade */ 80 interrupts = <0x1c 0x4 0x1d 0x4>; /* cascade */
79 interrupt-parent = <&UIC0>; 81 interrupt-parent = <&UIC0>;
80 }; 82 };
81 83
@@ -88,72 +90,72 @@
88 90
89 SDRAM0: memory-controller { 91 SDRAM0: memory-controller {
90 compatible = "ibm,sdram-405exr"; 92 compatible = "ibm,sdram-405exr";
91 dcr-reg = <010 2>; 93 dcr-reg = <0x010 0x002>;
92 }; 94 };
93 95
94 MAL0: mcmal { 96 MAL0: mcmal {
95 compatible = "ibm,mcmal-405exr", "ibm,mcmal2"; 97 compatible = "ibm,mcmal-405exr", "ibm,mcmal2";
96 dcr-reg = <180 62>; 98 dcr-reg = <0x180 0x062>;
97 num-tx-chans = <2>; 99 num-tx-chans = <2>;
98 num-rx-chans = <2>; 100 num-rx-chans = <2>;
99 interrupt-parent = <&MAL0>; 101 interrupt-parent = <&MAL0>;
100 interrupts = <0 1 2 3 4>; 102 interrupts = <0x0 0x1 0x2 0x3 0x4>;
101 #interrupt-cells = <1>; 103 #interrupt-cells = <1>;
102 #address-cells = <0>; 104 #address-cells = <0>;
103 #size-cells = <0>; 105 #size-cells = <0>;
104 interrupt-map = </*TXEOB*/ 0 &UIC0 a 4 106 interrupt-map = </*TXEOB*/ 0x0 &UIC0 0xa 0x4
105 /*RXEOB*/ 1 &UIC0 b 4 107 /*RXEOB*/ 0x1 &UIC0 0xb 0x4
106 /*SERR*/ 2 &UIC1 0 4 108 /*SERR*/ 0x2 &UIC1 0x0 0x4
107 /*TXDE*/ 3 &UIC1 1 4 109 /*TXDE*/ 0x3 &UIC1 0x1 0x4
108 /*RXDE*/ 4 &UIC1 2 4>; 110 /*RXDE*/ 0x4 &UIC1 0x2 0x4>;
109 interrupt-map-mask = <ffffffff>; 111 interrupt-map-mask = <0xffffffff>;
110 }; 112 };
111 113
112 POB0: opb { 114 POB0: opb {
113 compatible = "ibm,opb-405exr", "ibm,opb"; 115 compatible = "ibm,opb-405exr", "ibm,opb";
114 #address-cells = <1>; 116 #address-cells = <1>;
115 #size-cells = <1>; 117 #size-cells = <1>;
116 ranges = <80000000 80000000 10000000 118 ranges = <0x80000000 0x80000000 0x10000000
117 ef600000 ef600000 a00000 119 0xef600000 0xef600000 0x00a00000
118 f0000000 f0000000 10000000>; 120 0xf0000000 0xf0000000 0x10000000>;
119 dcr-reg = <0a0 5>; 121 dcr-reg = <0x0a0 0x005>;
120 clock-frequency = <0>; /* Filled in by U-Boot */ 122 clock-frequency = <0>; /* Filled in by U-Boot */
121 123
122 EBC0: ebc { 124 EBC0: ebc {
123 compatible = "ibm,ebc-405exr", "ibm,ebc"; 125 compatible = "ibm,ebc-405exr", "ibm,ebc";
124 dcr-reg = <012 2>; 126 dcr-reg = <0x012 0x002>;
125 #address-cells = <2>; 127 #address-cells = <2>;
126 #size-cells = <1>; 128 #size-cells = <1>;
127 clock-frequency = <0>; /* Filled in by U-Boot */ 129 clock-frequency = <0>; /* Filled in by U-Boot */
128 /* ranges property is supplied by U-Boot */ 130 /* ranges property is supplied by U-Boot */
129 interrupts = <5 1>; 131 interrupts = <0x5 0x1>;
130 interrupt-parent = <&UIC1>; 132 interrupt-parent = <&UIC1>;
131 133
132 nor_flash@0,0 { 134 nor_flash@0,0 {
133 compatible = "amd,s29gl512n", "cfi-flash"; 135 compatible = "amd,s29gl512n", "cfi-flash";
134 bank-width = <2>; 136 bank-width = <2>;
135 reg = <0 000000 4000000>; 137 reg = <0x00000000 0x00000000 0x04000000>;
136 #address-cells = <1>; 138 #address-cells = <1>;
137 #size-cells = <1>; 139 #size-cells = <1>;
138 partition@0 { 140 partition@0 {
139 label = "kernel"; 141 label = "kernel";
140 reg = <0 200000>; 142 reg = <0x00000000 0x00200000>;
141 }; 143 };
142 partition@200000 { 144 partition@200000 {
143 label = "root"; 145 label = "root";
144 reg = <200000 200000>; 146 reg = <0x00200000 0x00200000>;
145 }; 147 };
146 partition@400000 { 148 partition@400000 {
147 label = "user"; 149 label = "user";
148 reg = <400000 3b60000>; 150 reg = <0x00400000 0x03b60000>;
149 }; 151 };
150 partition@3f60000 { 152 partition@3f60000 {
151 label = "env"; 153 label = "env";
152 reg = <3f60000 40000>; 154 reg = <0x03f60000 0x00040000>;
153 }; 155 };
154 partition@3fa0000 { 156 partition@3fa0000 {
155 label = "u-boot"; 157 label = "u-boot";
156 reg = <3fa0000 60000>; 158 reg = <0x03fa0000 0x00060000>;
157 }; 159 };
158 }; 160 };
159 }; 161 };
@@ -161,68 +163,68 @@
161 UART0: serial@ef600200 { 163 UART0: serial@ef600200 {
162 device_type = "serial"; 164 device_type = "serial";
163 compatible = "ns16550"; 165 compatible = "ns16550";
164 reg = <ef600200 8>; 166 reg = <0xef600200 0x00000008>;
165 virtual-reg = <ef600200>; 167 virtual-reg = <0xef600200>;
166 clock-frequency = <0>; /* Filled in by U-Boot */ 168 clock-frequency = <0>; /* Filled in by U-Boot */
167 current-speed = <0>; 169 current-speed = <0>;
168 interrupt-parent = <&UIC0>; 170 interrupt-parent = <&UIC0>;
169 interrupts = <1a 4>; 171 interrupts = <0x1a 0x4>;
170 }; 172 };
171 173
172 UART1: serial@ef600300 { 174 UART1: serial@ef600300 {
173 device_type = "serial"; 175 device_type = "serial";
174 compatible = "ns16550"; 176 compatible = "ns16550";
175 reg = <ef600300 8>; 177 reg = <0xef600300 0x00000008>;
176 virtual-reg = <ef600300>; 178 virtual-reg = <0xef600300>;
177 clock-frequency = <0>; /* Filled in by U-Boot */ 179 clock-frequency = <0>; /* Filled in by U-Boot */
178 current-speed = <0>; 180 current-speed = <0>;
179 interrupt-parent = <&UIC0>; 181 interrupt-parent = <&UIC0>;
180 interrupts = <1 4>; 182 interrupts = <0x1 0x4>;
181 }; 183 };
182 184
183 IIC0: i2c@ef600400 { 185 IIC0: i2c@ef600400 {
184 compatible = "ibm,iic-405exr", "ibm,iic"; 186 compatible = "ibm,iic-405exr", "ibm,iic";
185 reg = <ef600400 14>; 187 reg = <0xef600400 0x00000014>;
186 interrupt-parent = <&UIC0>; 188 interrupt-parent = <&UIC0>;
187 interrupts = <2 4>; 189 interrupts = <0x2 0x4>;
188 }; 190 };
189 191
190 IIC1: i2c@ef600500 { 192 IIC1: i2c@ef600500 {
191 compatible = "ibm,iic-405exr", "ibm,iic"; 193 compatible = "ibm,iic-405exr", "ibm,iic";
192 reg = <ef600500 14>; 194 reg = <0xef600500 0x00000014>;
193 interrupt-parent = <&UIC0>; 195 interrupt-parent = <&UIC0>;
194 interrupts = <7 4>; 196 interrupts = <0x7 0x4>;
195 }; 197 };
196 198
197 199
198 RGMII0: emac-rgmii@ef600b00 { 200 RGMII0: emac-rgmii@ef600b00 {
199 compatible = "ibm,rgmii-405exr", "ibm,rgmii"; 201 compatible = "ibm,rgmii-405exr", "ibm,rgmii";
200 reg = <ef600b00 104>; 202 reg = <0xef600b00 0x00000104>;
201 has-mdio; 203 has-mdio;
202 }; 204 };
203 205
204 EMAC0: ethernet@ef600900 { 206 EMAC0: ethernet@ef600900 {
205 linux,network-index = <0>; 207 linux,network-index = <0x0>;
206 device_type = "network"; 208 device_type = "network";
207 compatible = "ibm,emac-405exr", "ibm,emac4"; 209 compatible = "ibm,emac-405exr", "ibm,emac4sync";
208 interrupt-parent = <&EMAC0>; 210 interrupt-parent = <&EMAC0>;
209 interrupts = <0 1>; 211 interrupts = <0x0 0x1>;
210 #interrupt-cells = <1>; 212 #interrupt-cells = <1>;
211 #address-cells = <0>; 213 #address-cells = <0>;
212 #size-cells = <0>; 214 #size-cells = <0>;
213 interrupt-map = </*Status*/ 0 &UIC0 18 4 215 interrupt-map = </*Status*/ 0x0 &UIC0 0x18 0x4
214 /*Wake*/ 1 &UIC1 1d 4>; 216 /*Wake*/ 0x1 &UIC1 0x1d 0x4>;
215 reg = <ef600900 70>; 217 reg = <0xef600900 0x000000c4>;
216 local-mac-address = [000000000000]; /* Filled in by U-Boot */ 218 local-mac-address = [000000000000]; /* Filled in by U-Boot */
217 mal-device = <&MAL0>; 219 mal-device = <&MAL0>;
218 mal-tx-channel = <0>; 220 mal-tx-channel = <0>;
219 mal-rx-channel = <0>; 221 mal-rx-channel = <0>;
220 cell-index = <0>; 222 cell-index = <0>;
221 max-frame-size = <2328>; 223 max-frame-size = <9000>;
222 rx-fifo-size = <1000>; 224 rx-fifo-size = <4096>;
223 tx-fifo-size = <800>; 225 tx-fifo-size = <2048>;
224 phy-mode = "rgmii"; 226 phy-mode = "rgmii";
225 phy-map = <00000000>; 227 phy-map = <0x00000000>;
226 rgmii-device = <&RGMII0>; 228 rgmii-device = <&RGMII0>;
227 rgmii-channel = <0>; 229 rgmii-channel = <0>;
228 has-inverted-stacr-oc; 230 has-inverted-stacr-oc;
@@ -237,23 +239,23 @@
237 #address-cells = <3>; 239 #address-cells = <3>;
238 compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex"; 240 compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex";
239 primary; 241 primary;
240 port = <0>; /* port number */ 242 port = <0x0>; /* port number */
241 reg = <a0000000 20000000 /* Config space access */ 243 reg = <0xa0000000 0x20000000 /* Config space access */
242 ef000000 00001000>; /* Registers */ 244 0xef000000 0x00001000>; /* Registers */
243 dcr-reg = <040 020>; 245 dcr-reg = <0x040 0x020>;
244 sdr-base = <400>; 246 sdr-base = <0x400>;
245 247
246 /* Outbound ranges, one memory and one IO, 248 /* Outbound ranges, one memory and one IO,
247 * later cannot be changed 249 * later cannot be changed
248 */ 250 */
249 ranges = <02000000 0 80000000 90000000 0 08000000 251 ranges = <0x02000000 0x00000000 0x80000000 0x90000000 0x00000000 0x08000000
250 01000000 0 00000000 e0000000 0 00010000>; 252 0x01000000 0x00000000 0x00000000 0xe0000000 0x00000000 0x00010000>;
251 253
252 /* Inbound 2GB range starting at 0 */ 254 /* Inbound 2GB range starting at 0 */
253 dma-ranges = <42000000 0 0 0 0 80000000>; 255 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>;
254 256
255 /* This drives busses 0x00 to 0x3f */ 257 /* This drives busses 0x00 to 0x3f */
256 bus-range = <00 3f>; 258 bus-range = <0x0 0x3f>;
257 259
258 /* Legacy interrupts (note the weird polarity, the bridge seems 260 /* Legacy interrupts (note the weird polarity, the bridge seems
259 * to invert PCIe legacy interrupts). 261 * to invert PCIe legacy interrupts).
@@ -263,12 +265,12 @@
263 * below are basically de-swizzled numbers. 265 * below are basically de-swizzled numbers.
264 * The real slot is on idsel 0, so the swizzling is 1:1 266 * The real slot is on idsel 0, so the swizzling is 1:1
265 */ 267 */
266 interrupt-map-mask = <0000 0 0 7>; 268 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
267 interrupt-map = < 269 interrupt-map = <
268 0000 0 0 1 &UIC2 0 4 /* swizzled int A */ 270 0x0 0x0 0x0 0x1 &UIC2 0x0 0x4 /* swizzled int A */
269 0000 0 0 2 &UIC2 1 4 /* swizzled int B */ 271 0x0 0x0 0x0 0x2 &UIC2 0x1 0x4 /* swizzled int B */
270 0000 0 0 3 &UIC2 2 4 /* swizzled int C */ 272 0x0 0x0 0x0 0x3 &UIC2 0x2 0x4 /* swizzled int C */
271 0000 0 0 4 &UIC2 3 4 /* swizzled int D */>; 273 0x0 0x0 0x0 0x4 &UIC2 0x3 0x4 /* swizzled int D */>;
272 }; 274 };
273 }; 275 };
274}; 276};
diff --git a/arch/powerpc/boot/dts/holly.dts b/arch/powerpc/boot/dts/holly.dts
index b5d87895fe06..f87fe7b9ced9 100644
--- a/arch/powerpc/boot/dts/holly.dts
+++ b/arch/powerpc/boot/dts/holly.dts
@@ -10,6 +10,8 @@
10 * any warranty of any kind, whether express or implied. 10 * any warranty of any kind, whether express or implied.
11 */ 11 */
12 12
13/dts-v1/;
14
13/ { 15/ {
14 model = "41K7339"; 16 model = "41K7339";
15 compatible = "ibm,holly"; 17 compatible = "ibm,holly";
@@ -21,22 +23,22 @@
21 #size-cells =<0>; 23 #size-cells =<0>;
22 PowerPC,750CL@0 { 24 PowerPC,750CL@0 {
23 device_type = "cpu"; 25 device_type = "cpu";
24 reg = <0>; 26 reg = <0x00000000>;
25 d-cache-line-size = <20>; 27 d-cache-line-size = <32>;
26 i-cache-line-size = <20>; 28 i-cache-line-size = <32>;
27 d-cache-size = <8000>; 29 d-cache-size = <32768>;
28 i-cache-size = <8000>; 30 i-cache-size = <32768>;
29 d-cache-sets = <80>; 31 d-cache-sets = <128>;
30 i-cache-sets = <80>; 32 i-cache-sets = <128>;
31 timebase-frequency = <2faf080>; 33 timebase-frequency = <50000000>;
32 clock-frequency = <23c34600>; 34 clock-frequency = <600000000>;
33 bus-frequency = <bebc200>; 35 bus-frequency = <200000000>;
34 }; 36 };
35 }; 37 };
36 38
37 memory@0 { 39 memory@0 {
38 device_type = "memory"; 40 device_type = "memory";
39 reg = <00000000 20000000>; 41 reg = <0x00000000 0x20000000>;
40 }; 42 };
41 43
42 tsi109@c0000000 { 44 tsi109@c0000000 {
@@ -44,33 +46,33 @@
44 compatible = "tsi109-bridge", "tsi108-bridge"; 46 compatible = "tsi109-bridge", "tsi108-bridge";
45 #address-cells = <1>; 47 #address-cells = <1>;
46 #size-cells = <1>; 48 #size-cells = <1>;
47 ranges = <00000000 c0000000 00010000>; 49 ranges = <0x00000000 0xc0000000 0x00010000>;
48 reg = <c0000000 00010000>; 50 reg = <0xc0000000 0x00010000>;
49 51
50 i2c@7000 { 52 i2c@7000 {
51 device_type = "i2c"; 53 device_type = "i2c";
52 compatible = "tsi109-i2c", "tsi108-i2c"; 54 compatible = "tsi109-i2c", "tsi108-i2c";
53 interrupt-parent = <&MPIC>; 55 interrupt-parent = <&MPIC>;
54 interrupts = <e 2>; 56 interrupts = <0xe 0x2>;
55 reg = <7000 400>; 57 reg = <0x00007000 0x00000400>;
56 }; 58 };
57 59
58 MDIO: mdio@6000 { 60 MDIO: mdio@6000 {
59 device_type = "mdio"; 61 device_type = "mdio";
60 compatible = "tsi109-mdio", "tsi108-mdio"; 62 compatible = "tsi109-mdio", "tsi108-mdio";
61 reg = <6000 50>; 63 reg = <0x00006000 0x00000050>;
62 #address-cells = <1>; 64 #address-cells = <1>;
63 #size-cells = <0>; 65 #size-cells = <0>;
64 66
65 PHY1: ethernet-phy@1 { 67 PHY1: ethernet-phy@1 {
66 compatible = "bcm5461a"; 68 compatible = "bcm5461a";
67 reg = <1>; 69 reg = <0x00000001>;
68 txc-rxc-delay-disable; 70 txc-rxc-delay-disable;
69 }; 71 };
70 72
71 PHY2: ethernet-phy@2 { 73 PHY2: ethernet-phy@2 {
72 compatible = "bcm5461a"; 74 compatible = "bcm5461a";
73 reg = <2>; 75 reg = <0x00000002>;
74 txc-rxc-delay-disable; 76 txc-rxc-delay-disable;
75 }; 77 };
76 }; 78 };
@@ -80,10 +82,10 @@
80 compatible = "tsi109-ethernet", "tsi108-ethernet"; 82 compatible = "tsi109-ethernet", "tsi108-ethernet";
81 #address-cells = <1>; 83 #address-cells = <1>;
82 #size-cells = <0>; 84 #size-cells = <0>;
83 reg = <6000 200>; 85 reg = <0x00006000 0x00000200>;
84 local-mac-address = [ 00 00 00 00 00 00 ]; 86 local-mac-address = [ 00 00 00 00 00 00 ];
85 interrupt-parent = <&MPIC>; 87 interrupt-parent = <&MPIC>;
86 interrupts = <10 2>; 88 interrupts = <0x10 0x2>;
87 mdio-handle = <&MDIO>; 89 mdio-handle = <&MDIO>;
88 phy-handle = <&PHY1>; 90 phy-handle = <&PHY1>;
89 }; 91 };
@@ -93,10 +95,10 @@
93 compatible = "tsi109-ethernet", "tsi108-ethernet"; 95 compatible = "tsi109-ethernet", "tsi108-ethernet";
94 #address-cells = <1>; 96 #address-cells = <1>;
95 #size-cells = <0>; 97 #size-cells = <0>;
96 reg = <6400 200>; 98 reg = <0x00006400 0x00000200>;
97 local-mac-address = [ 00 00 00 00 00 00 ]; 99 local-mac-address = [ 00 00 00 00 00 00 ];
98 interrupt-parent = <&MPIC>; 100 interrupt-parent = <&MPIC>;
99 interrupts = <11 2>; 101 interrupts = <0x11 0x2>;
100 mdio-handle = <&MDIO>; 102 mdio-handle = <&MDIO>;
101 phy-handle = <&PHY2>; 103 phy-handle = <&PHY2>;
102 }; 104 };
@@ -104,23 +106,23 @@
104 serial@7808 { 106 serial@7808 {
105 device_type = "serial"; 107 device_type = "serial";
106 compatible = "ns16550"; 108 compatible = "ns16550";
107 reg = <7808 200>; 109 reg = <0x00007808 0x00000200>;
108 virtual-reg = <c0007808>; 110 virtual-reg = <0xc0007808>;
109 clock-frequency = <3F9C6000>; 111 clock-frequency = <1067212800>;
110 current-speed = <1c200>; 112 current-speed = <115200>;
111 interrupt-parent = <&MPIC>; 113 interrupt-parent = <&MPIC>;
112 interrupts = <c 2>; 114 interrupts = <0xc 0x2>;
113 }; 115 };
114 116
115 serial@7c08 { 117 serial@7c08 {
116 device_type = "serial"; 118 device_type = "serial";
117 compatible = "ns16550"; 119 compatible = "ns16550";
118 reg = <7c08 200>; 120 reg = <0x00007c08 0x00000200>;
119 virtual-reg = <c0007c08>; 121 virtual-reg = <0xc0007c08>;
120 clock-frequency = <3F9C6000>; 122 clock-frequency = <1067212800>;
121 current-speed = <1c200>; 123 current-speed = <115200>;
122 interrupt-parent = <&MPIC>; 124 interrupt-parent = <&MPIC>;
123 interrupts = <d 2>; 125 interrupts = <0xd 0x2>;
124 }; 126 };
125 127
126 MPIC: pic@7400 { 128 MPIC: pic@7400 {
@@ -128,7 +130,7 @@
128 compatible = "chrp,open-pic"; 130 compatible = "chrp,open-pic";
129 interrupt-controller; 131 interrupt-controller;
130 #interrupt-cells = <2>; 132 #interrupt-cells = <2>;
131 reg = <7400 400>; 133 reg = <0x00007400 0x00000400>;
132 big-endian; 134 big-endian;
133 }; 135 };
134 136
@@ -138,42 +140,42 @@
138 #interrupt-cells = <1>; 140 #interrupt-cells = <1>;
139 #size-cells = <2>; 141 #size-cells = <2>;
140 #address-cells = <3>; 142 #address-cells = <3>;
141 reg = <1000 1000>; 143 reg = <0x00001000 0x00001000>;
142 bus-range = <0 0>; 144 bus-range = <0x0 0x0>;
143 /*----------------------------------------------------+ 145 /*----------------------------------------------------+
144 | PCI memory range. 146 | PCI memory range.
145 | 01 denotes I/O space 147 | 01 denotes I/O space
146 | 02 denotes 32-bit memory space 148 | 02 denotes 32-bit memory space
147 +----------------------------------------------------*/ 149 +----------------------------------------------------*/
148 ranges = <02000000 0 40000000 40000000 0 10000000 150 ranges = <0x02000000 0x00000000 0x40000000 0x40000000 0x00000000 0x10000000
149 01000000 0 00000000 7e000000 0 00010000>; 151 0x01000000 0x00000000 0x00000000 0x7e000000 0x00000000 0x00010000>;
150 clock-frequency = <7f28154>; 152 clock-frequency = <133333332>;
151 interrupt-parent = <&MPIC>; 153 interrupt-parent = <&MPIC>;
152 interrupts = <17 2>; 154 interrupts = <0x17 0x2>;
153 interrupt-map-mask = <f800 0 0 7>; 155 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
154 /*----------------------------------------------------+ 156 /*----------------------------------------------------+
155 | The INTA, INTB, INTC, INTD are shared. 157 | The INTA, INTB, INTC, INTD are shared.
156 +----------------------------------------------------*/ 158 +----------------------------------------------------*/
157 interrupt-map = < 159 interrupt-map = <
158 0800 0 0 1 &RT0 24 0 160 0x800 0x0 0x0 0x1 &RT0 0x24 0x0
159 0800 0 0 2 &RT0 25 0 161 0x800 0x0 0x0 0x2 &RT0 0x25 0x0
160 0800 0 0 3 &RT0 26 0 162 0x800 0x0 0x0 0x3 &RT0 0x26 0x0
161 0800 0 0 4 &RT0 27 0 163 0x800 0x0 0x0 0x4 &RT0 0x27 0x0
162 164
163 1000 0 0 1 &RT0 25 0 165 0x1000 0x0 0x0 0x1 &RT0 0x25 0x0
164 1000 0 0 2 &RT0 26 0 166 0x1000 0x0 0x0 0x2 &RT0 0x26 0x0
165 1000 0 0 3 &RT0 27 0 167 0x1000 0x0 0x0 0x3 &RT0 0x27 0x0
166 1000 0 0 4 &RT0 24 0 168 0x1000 0x0 0x0 0x4 &RT0 0x24 0x0
167 169
168 1800 0 0 1 &RT0 26 0 170 0x1800 0x0 0x0 0x1 &RT0 0x26 0x0
169 1800 0 0 2 &RT0 27 0 171 0x1800 0x0 0x0 0x2 &RT0 0x27 0x0
170 1800 0 0 3 &RT0 24 0 172 0x1800 0x0 0x0 0x3 &RT0 0x24 0x0
171 1800 0 0 4 &RT0 25 0 173 0x1800 0x0 0x0 0x4 &RT0 0x25 0x0
172 174
173 2000 0 0 1 &RT0 27 0 175 0x2000 0x0 0x0 0x1 &RT0 0x27 0x0
174 2000 0 0 2 &RT0 24 0 176 0x2000 0x0 0x0 0x2 &RT0 0x24 0x0
175 2000 0 0 3 &RT0 25 0 177 0x2000 0x0 0x0 0x3 &RT0 0x25 0x0
176 2000 0 0 4 &RT0 26 0 178 0x2000 0x0 0x0 0x4 &RT0 0x26 0x0
177 >; 179 >;
178 180
179 RT0: router@1180 { 181 RT0: router@1180 {
@@ -183,7 +185,7 @@
183 clock-frequency = <0>; 185 clock-frequency = <0>;
184 #address-cells = <0>; 186 #address-cells = <0>;
185 #interrupt-cells = <2>; 187 #interrupt-cells = <2>;
186 interrupts = <17 2>; 188 interrupts = <0x17 0x2>;
187 interrupt-parent = <&MPIC>; 189 interrupt-parent = <&MPIC>;
188 }; 190 };
189 }; 191 };
diff --git a/arch/powerpc/boot/dts/katmai.dts b/arch/powerpc/boot/dts/katmai.dts
index cc2873a531d2..077819bc3cbd 100644
--- a/arch/powerpc/boot/dts/katmai.dts
+++ b/arch/powerpc/boot/dts/katmai.dts
@@ -12,12 +12,14 @@
12 * any warranty of any kind, whether express or implied. 12 * any warranty of any kind, whether express or implied.
13 */ 13 */
14 14
15/dts-v1/;
16
15/ { 17/ {
16 #address-cells = <2>; 18 #address-cells = <2>;
17 #size-cells = <1>; 19 #size-cells = <1>;
18 model = "amcc,katmai"; 20 model = "amcc,katmai";
19 compatible = "amcc,katmai"; 21 compatible = "amcc,katmai";
20 dcr-parent = <&/cpus/cpu@0>; 22 dcr-parent = <&{/cpus/cpu@0}>;
21 23
22 aliases { 24 aliases {
23 ethernet0 = &EMAC0; 25 ethernet0 = &EMAC0;
@@ -33,13 +35,13 @@
33 cpu@0 { 35 cpu@0 {
34 device_type = "cpu"; 36 device_type = "cpu";
35 model = "PowerPC,440SPe"; 37 model = "PowerPC,440SPe";
36 reg = <0>; 38 reg = <0x00000000>;
37 clock-frequency = <0>; /* Filled in by zImage */ 39 clock-frequency = <0>; /* Filled in by zImage */
38 timebase-frequency = <0>; /* Filled in by zImage */ 40 timebase-frequency = <0>; /* Filled in by zImage */
39 i-cache-line-size = <20>; 41 i-cache-line-size = <32>;
40 d-cache-line-size = <20>; 42 d-cache-line-size = <32>;
41 i-cache-size = <8000>; 43 i-cache-size = <32768>;
42 d-cache-size = <8000>; 44 d-cache-size = <32768>;
43 dcr-controller; 45 dcr-controller;
44 dcr-access-method = "native"; 46 dcr-access-method = "native";
45 }; 47 };
@@ -47,14 +49,14 @@
47 49
48 memory { 50 memory {
49 device_type = "memory"; 51 device_type = "memory";
50 reg = <0 0 0>; /* Filled in by zImage */ 52 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by zImage */
51 }; 53 };
52 54
53 UIC0: interrupt-controller0 { 55 UIC0: interrupt-controller0 {
54 compatible = "ibm,uic-440spe","ibm,uic"; 56 compatible = "ibm,uic-440spe","ibm,uic";
55 interrupt-controller; 57 interrupt-controller;
56 cell-index = <0>; 58 cell-index = <0>;
57 dcr-reg = <0c0 009>; 59 dcr-reg = <0x0c0 0x009>;
58 #address-cells = <0>; 60 #address-cells = <0>;
59 #size-cells = <0>; 61 #size-cells = <0>;
60 #interrupt-cells = <2>; 62 #interrupt-cells = <2>;
@@ -64,11 +66,11 @@
64 compatible = "ibm,uic-440spe","ibm,uic"; 66 compatible = "ibm,uic-440spe","ibm,uic";
65 interrupt-controller; 67 interrupt-controller;
66 cell-index = <1>; 68 cell-index = <1>;
67 dcr-reg = <0d0 009>; 69 dcr-reg = <0x0d0 0x009>;
68 #address-cells = <0>; 70 #address-cells = <0>;
69 #size-cells = <0>; 71 #size-cells = <0>;
70 #interrupt-cells = <2>; 72 #interrupt-cells = <2>;
71 interrupts = <1e 4 1f 4>; /* cascade */ 73 interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
72 interrupt-parent = <&UIC0>; 74 interrupt-parent = <&UIC0>;
73 }; 75 };
74 76
@@ -76,11 +78,11 @@
76 compatible = "ibm,uic-440spe","ibm,uic"; 78 compatible = "ibm,uic-440spe","ibm,uic";
77 interrupt-controller; 79 interrupt-controller;
78 cell-index = <2>; 80 cell-index = <2>;
79 dcr-reg = <0e0 009>; 81 dcr-reg = <0x0e0 0x009>;
80 #address-cells = <0>; 82 #address-cells = <0>;
81 #size-cells = <0>; 83 #size-cells = <0>;
82 #interrupt-cells = <2>; 84 #interrupt-cells = <2>;
83 interrupts = <a 4 b 4>; /* cascade */ 85 interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
84 interrupt-parent = <&UIC0>; 86 interrupt-parent = <&UIC0>;
85 }; 87 };
86 88
@@ -88,22 +90,22 @@
88 compatible = "ibm,uic-440spe","ibm,uic"; 90 compatible = "ibm,uic-440spe","ibm,uic";
89 interrupt-controller; 91 interrupt-controller;
90 cell-index = <3>; 92 cell-index = <3>;
91 dcr-reg = <0f0 009>; 93 dcr-reg = <0x0f0 0x009>;
92 #address-cells = <0>; 94 #address-cells = <0>;
93 #size-cells = <0>; 95 #size-cells = <0>;
94 #interrupt-cells = <2>; 96 #interrupt-cells = <2>;
95 interrupts = <10 4 11 4>; /* cascade */ 97 interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
96 interrupt-parent = <&UIC0>; 98 interrupt-parent = <&UIC0>;
97 }; 99 };
98 100
99 SDR0: sdr { 101 SDR0: sdr {
100 compatible = "ibm,sdr-440spe"; 102 compatible = "ibm,sdr-440spe";
101 dcr-reg = <00e 002>; 103 dcr-reg = <0x00e 0x002>;
102 }; 104 };
103 105
104 CPR0: cpr { 106 CPR0: cpr {
105 compatible = "ibm,cpr-440spe"; 107 compatible = "ibm,cpr-440spe";
106 dcr-reg = <00c 002>; 108 dcr-reg = <0x00c 0x002>;
107 }; 109 };
108 110
109 plb { 111 plb {
@@ -115,108 +117,108 @@
115 117
116 SDRAM0: sdram { 118 SDRAM0: sdram {
117 compatible = "ibm,sdram-440spe", "ibm,sdram-405gp"; 119 compatible = "ibm,sdram-440spe", "ibm,sdram-405gp";
118 dcr-reg = <010 2>; 120 dcr-reg = <0x010 0x002>;
119 }; 121 };
120 122
121 MAL0: mcmal { 123 MAL0: mcmal {
122 compatible = "ibm,mcmal-440spe", "ibm,mcmal2"; 124 compatible = "ibm,mcmal-440spe", "ibm,mcmal2";
123 dcr-reg = <180 62>; 125 dcr-reg = <0x180 0x062>;
124 num-tx-chans = <2>; 126 num-tx-chans = <2>;
125 num-rx-chans = <1>; 127 num-rx-chans = <1>;
126 interrupt-parent = <&MAL0>; 128 interrupt-parent = <&MAL0>;
127 interrupts = <0 1 2 3 4>; 129 interrupts = <0x0 0x1 0x2 0x3 0x4>;
128 #interrupt-cells = <1>; 130 #interrupt-cells = <1>;
129 #address-cells = <0>; 131 #address-cells = <0>;
130 #size-cells = <0>; 132 #size-cells = <0>;
131 interrupt-map = </*TXEOB*/ 0 &UIC1 6 4 133 interrupt-map = </*TXEOB*/ 0x0 &UIC1 0x6 0x4
132 /*RXEOB*/ 1 &UIC1 7 4 134 /*RXEOB*/ 0x1 &UIC1 0x7 0x4
133 /*SERR*/ 2 &UIC1 1 4 135 /*SERR*/ 0x2 &UIC1 0x1 0x4
134 /*TXDE*/ 3 &UIC1 2 4 136 /*TXDE*/ 0x3 &UIC1 0x2 0x4
135 /*RXDE*/ 4 &UIC1 3 4>; 137 /*RXDE*/ 0x4 &UIC1 0x3 0x4>;
136 }; 138 };
137 139
138 POB0: opb { 140 POB0: opb {
139 compatible = "ibm,opb-440spe", "ibm,opb-440gp", "ibm,opb"; 141 compatible = "ibm,opb-440spe", "ibm,opb-440gp", "ibm,opb";
140 #address-cells = <1>; 142 #address-cells = <1>;
141 #size-cells = <1>; 143 #size-cells = <1>;
142 ranges = <00000000 4 e0000000 20000000>; 144 ranges = <0x00000000 0x00000004 0xe0000000 0x20000000>;
143 clock-frequency = <0>; /* Filled in by zImage */ 145 clock-frequency = <0>; /* Filled in by zImage */
144 146
145 EBC0: ebc { 147 EBC0: ebc {
146 compatible = "ibm,ebc-440spe", "ibm,ebc-440gp", "ibm,ebc"; 148 compatible = "ibm,ebc-440spe", "ibm,ebc-440gp", "ibm,ebc";
147 dcr-reg = <012 2>; 149 dcr-reg = <0x012 0x002>;
148 #address-cells = <2>; 150 #address-cells = <2>;
149 #size-cells = <1>; 151 #size-cells = <1>;
150 clock-frequency = <0>; /* Filled in by zImage */ 152 clock-frequency = <0>; /* Filled in by zImage */
151 interrupts = <5 1>; 153 interrupts = <0x5 0x1>;
152 interrupt-parent = <&UIC1>; 154 interrupt-parent = <&UIC1>;
153 }; 155 };
154 156
155 UART0: serial@10000200 { 157 UART0: serial@10000200 {
156 device_type = "serial"; 158 device_type = "serial";
157 compatible = "ns16550"; 159 compatible = "ns16550";
158 reg = <10000200 8>; 160 reg = <0x10000200 0x00000008>;
159 virtual-reg = <a0000200>; 161 virtual-reg = <0xa0000200>;
160 clock-frequency = <0>; /* Filled in by zImage */ 162 clock-frequency = <0>; /* Filled in by zImage */
161 current-speed = <1c200>; 163 current-speed = <115200>;
162 interrupt-parent = <&UIC0>; 164 interrupt-parent = <&UIC0>;
163 interrupts = <0 4>; 165 interrupts = <0x0 0x4>;
164 }; 166 };
165 167
166 UART1: serial@10000300 { 168 UART1: serial@10000300 {
167 device_type = "serial"; 169 device_type = "serial";
168 compatible = "ns16550"; 170 compatible = "ns16550";
169 reg = <10000300 8>; 171 reg = <0x10000300 0x00000008>;
170 virtual-reg = <a0000300>; 172 virtual-reg = <0xa0000300>;
171 clock-frequency = <0>; 173 clock-frequency = <0>;
172 current-speed = <0>; 174 current-speed = <0>;
173 interrupt-parent = <&UIC0>; 175 interrupt-parent = <&UIC0>;
174 interrupts = <1 4>; 176 interrupts = <0x1 0x4>;
175 }; 177 };
176 178
177 179
178 UART2: serial@10000600 { 180 UART2: serial@10000600 {
179 device_type = "serial"; 181 device_type = "serial";
180 compatible = "ns16550"; 182 compatible = "ns16550";
181 reg = <10000600 8>; 183 reg = <0x10000600 0x00000008>;
182 virtual-reg = <a0000600>; 184 virtual-reg = <0xa0000600>;
183 clock-frequency = <0>; 185 clock-frequency = <0>;
184 current-speed = <0>; 186 current-speed = <0>;
185 interrupt-parent = <&UIC1>; 187 interrupt-parent = <&UIC1>;
186 interrupts = <5 4>; 188 interrupts = <0x5 0x4>;
187 }; 189 };
188 190
189 IIC0: i2c@10000400 { 191 IIC0: i2c@10000400 {
190 compatible = "ibm,iic-440spe", "ibm,iic-440gp", "ibm,iic"; 192 compatible = "ibm,iic-440spe", "ibm,iic-440gp", "ibm,iic";
191 reg = <10000400 14>; 193 reg = <0x10000400 0x00000014>;
192 interrupt-parent = <&UIC0>; 194 interrupt-parent = <&UIC0>;
193 interrupts = <2 4>; 195 interrupts = <0x2 0x4>;
194 }; 196 };
195 197
196 IIC1: i2c@10000500 { 198 IIC1: i2c@10000500 {
197 compatible = "ibm,iic-440spe", "ibm,iic-440gp", "ibm,iic"; 199 compatible = "ibm,iic-440spe", "ibm,iic-440gp", "ibm,iic";
198 reg = <10000500 14>; 200 reg = <0x10000500 0x00000014>;
199 interrupt-parent = <&UIC0>; 201 interrupt-parent = <&UIC0>;
200 interrupts = <3 4>; 202 interrupts = <0x3 0x4>;
201 }; 203 };
202 204
203 EMAC0: ethernet@10000800 { 205 EMAC0: ethernet@10000800 {
204 linux,network-index = <0>; 206 linux,network-index = <0x0>;
205 device_type = "network"; 207 device_type = "network";
206 compatible = "ibm,emac-440spe", "ibm,emac4"; 208 compatible = "ibm,emac-440spe", "ibm,emac4";
207 interrupt-parent = <&UIC1>; 209 interrupt-parent = <&UIC1>;
208 interrupts = <1c 4 1d 4>; 210 interrupts = <0x1c 0x4 0x1d 0x4>;
209 reg = <10000800 70>; 211 reg = <0x10000800 0x00000074>;
210 local-mac-address = [000000000000]; 212 local-mac-address = [000000000000];
211 mal-device = <&MAL0>; 213 mal-device = <&MAL0>;
212 mal-tx-channel = <0>; 214 mal-tx-channel = <0>;
213 mal-rx-channel = <0>; 215 mal-rx-channel = <0>;
214 cell-index = <0>; 216 cell-index = <0>;
215 max-frame-size = <2328>; 217 max-frame-size = <9000>;
216 rx-fifo-size = <1000>; 218 rx-fifo-size = <4096>;
217 tx-fifo-size = <800>; 219 tx-fifo-size = <2048>;
218 phy-mode = "gmii"; 220 phy-mode = "gmii";
219 phy-map = <00000000>; 221 phy-map = <0x00000000>;
220 has-inverted-stacr-oc; 222 has-inverted-stacr-oc;
221 has-new-stacr-staopc; 223 has-new-stacr-staopc;
222 }; 224 };
@@ -231,23 +233,23 @@
231 primary; 233 primary;
232 large-inbound-windows; 234 large-inbound-windows;
233 enable-msi-hole; 235 enable-msi-hole;
234 reg = <c 0ec00000 8 /* Config space access */ 236 reg = <0x0000000c 0x0ec00000 0x00000008 /* Config space access */
235 0 0 0 /* no IACK cycles */ 237 0x00000000 0x00000000 0x00000000 /* no IACK cycles */
236 c 0ed00000 4 /* Special cycles */ 238 0x0000000c 0x0ed00000 0x00000004 /* Special cycles */
237 c 0ec80000 100 /* Internal registers */ 239 0x0000000c 0x0ec80000 0x00000100 /* Internal registers */
238 c 0ec80100 fc>; /* Internal messaging registers */ 240 0x0000000c 0x0ec80100 0x000000fc>; /* Internal messaging registers */
239 241
240 /* Outbound ranges, one memory and one IO, 242 /* Outbound ranges, one memory and one IO,
241 * later cannot be changed 243 * later cannot be changed
242 */ 244 */
243 ranges = <02000000 0 80000000 0000000d 80000000 0 80000000 245 ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000
244 01000000 0 00000000 0000000c 08000000 0 00010000>; 246 0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>;
245 247
246 /* Inbound 2GB range starting at 0 */ 248 /* Inbound 2GB range starting at 0 */
247 dma-ranges = <42000000 0 0 0 0 0 80000000>; 249 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
248 250
249 /* This drives busses 0 to 0xf */ 251 /* This drives busses 0 to 0xf */
250 bus-range = <0 f>; 252 bus-range = <0x0 0xf>;
251 253
252 /* 254 /*
253 * On Katmai, the following PCI-X interrupts signals 255 * On Katmai, the following PCI-X interrupts signals
@@ -258,13 +260,13 @@
258 * INTC: J2: 1-2 260 * INTC: J2: 1-2
259 * INTD: J1: 1-2 261 * INTD: J1: 1-2
260 */ 262 */
261 interrupt-map-mask = <f800 0 0 7>; 263 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
262 interrupt-map = < 264 interrupt-map = <
263 /* IDSEL 1 */ 265 /* IDSEL 1 */
264 0800 0 0 1 &UIC1 14 8 266 0x800 0x0 0x0 0x1 &UIC1 0x14 0x8
265 0800 0 0 2 &UIC1 13 8 267 0x800 0x0 0x0 0x2 &UIC1 0x13 0x8
266 0800 0 0 3 &UIC1 12 8 268 0x800 0x0 0x0 0x3 &UIC1 0x12 0x8
267 0800 0 0 4 &UIC1 11 8 269 0x800 0x0 0x0 0x4 &UIC1 0x11 0x8
268 >; 270 >;
269 }; 271 };
270 272
@@ -275,23 +277,23 @@
275 #address-cells = <3>; 277 #address-cells = <3>;
276 compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex"; 278 compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex";
277 primary; 279 primary;
278 port = <0>; /* port number */ 280 port = <0x0>; /* port number */
279 reg = <d 00000000 20000000 /* Config space access */ 281 reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */
280 c 10000000 00001000>; /* Registers */ 282 0x0000000c 0x10000000 0x00001000>; /* Registers */
281 dcr-reg = <100 020>; 283 dcr-reg = <0x100 0x020>;
282 sdr-base = <300>; 284 sdr-base = <0x300>;
283 285
284 /* Outbound ranges, one memory and one IO, 286 /* Outbound ranges, one memory and one IO,
285 * later cannot be changed 287 * later cannot be changed
286 */ 288 */
287 ranges = <02000000 0 80000000 0000000e 00000000 0 80000000 289 ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000
288 01000000 0 00000000 0000000f 80000000 0 00010000>; 290 0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;
289 291
290 /* Inbound 2GB range starting at 0 */ 292 /* Inbound 2GB range starting at 0 */
291 dma-ranges = <42000000 0 0 0 0 0 80000000>; 293 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
292 294
293 /* This drives busses 10 to 0x1f */ 295 /* This drives busses 10 to 0x1f */
294 bus-range = <10 1f>; 296 bus-range = <0x10 0x1f>;
295 297
296 /* Legacy interrupts (note the weird polarity, the bridge seems 298 /* Legacy interrupts (note the weird polarity, the bridge seems
297 * to invert PCIe legacy interrupts). 299 * to invert PCIe legacy interrupts).
@@ -301,12 +303,12 @@
301 * below are basically de-swizzled numbers. 303 * below are basically de-swizzled numbers.
302 * The real slot is on idsel 0, so the swizzling is 1:1 304 * The real slot is on idsel 0, so the swizzling is 1:1
303 */ 305 */
304 interrupt-map-mask = <0000 0 0 7>; 306 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
305 interrupt-map = < 307 interrupt-map = <
306 0000 0 0 1 &UIC3 0 4 /* swizzled int A */ 308 0x0 0x0 0x0 0x1 &UIC3 0x0 0x4 /* swizzled int A */
307 0000 0 0 2 &UIC3 1 4 /* swizzled int B */ 309 0x0 0x0 0x0 0x2 &UIC3 0x1 0x4 /* swizzled int B */
308 0000 0 0 3 &UIC3 2 4 /* swizzled int C */ 310 0x0 0x0 0x0 0x3 &UIC3 0x2 0x4 /* swizzled int C */
309 0000 0 0 4 &UIC3 3 4 /* swizzled int D */>; 311 0x0 0x0 0x0 0x4 &UIC3 0x3 0x4 /* swizzled int D */>;
310 }; 312 };
311 313
312 PCIE1: pciex@d20000000 { 314 PCIE1: pciex@d20000000 {
@@ -316,23 +318,23 @@
316 #address-cells = <3>; 318 #address-cells = <3>;
317 compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex"; 319 compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex";
318 primary; 320 primary;
319 port = <1>; /* port number */ 321 port = <0x1>; /* port number */
320 reg = <d 20000000 20000000 /* Config space access */ 322 reg = <0x0000000d 0x20000000 0x20000000 /* Config space access */
321 c 10001000 00001000>; /* Registers */ 323 0x0000000c 0x10001000 0x00001000>; /* Registers */
322 dcr-reg = <120 020>; 324 dcr-reg = <0x120 0x020>;
323 sdr-base = <340>; 325 sdr-base = <0x340>;
324 326
325 /* Outbound ranges, one memory and one IO, 327 /* Outbound ranges, one memory and one IO,
326 * later cannot be changed 328 * later cannot be changed
327 */ 329 */
328 ranges = <02000000 0 80000000 0000000e 80000000 0 80000000 330 ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000
329 01000000 0 00000000 0000000f 80010000 0 00010000>; 331 0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>;
330 332
331 /* Inbound 2GB range starting at 0 */ 333 /* Inbound 2GB range starting at 0 */
332 dma-ranges = <42000000 0 0 0 0 0 80000000>; 334 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
333 335
334 /* This drives busses 10 to 0x1f */ 336 /* This drives busses 10 to 0x1f */
335 bus-range = <20 2f>; 337 bus-range = <0x20 0x2f>;
336 338
337 /* Legacy interrupts (note the weird polarity, the bridge seems 339 /* Legacy interrupts (note the weird polarity, the bridge seems
338 * to invert PCIe legacy interrupts). 340 * to invert PCIe legacy interrupts).
@@ -342,12 +344,12 @@
342 * below are basically de-swizzled numbers. 344 * below are basically de-swizzled numbers.
343 * The real slot is on idsel 0, so the swizzling is 1:1 345 * The real slot is on idsel 0, so the swizzling is 1:1
344 */ 346 */
345 interrupt-map-mask = <0000 0 0 7>; 347 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
346 interrupt-map = < 348 interrupt-map = <
347 0000 0 0 1 &UIC3 4 4 /* swizzled int A */ 349 0x0 0x0 0x0 0x1 &UIC3 0x4 0x4 /* swizzled int A */
348 0000 0 0 2 &UIC3 5 4 /* swizzled int B */ 350 0x0 0x0 0x0 0x2 &UIC3 0x5 0x4 /* swizzled int B */
349 0000 0 0 3 &UIC3 6 4 /* swizzled int C */ 351 0x0 0x0 0x0 0x3 &UIC3 0x6 0x4 /* swizzled int C */
350 0000 0 0 4 &UIC3 7 4 /* swizzled int D */>; 352 0x0 0x0 0x0 0x4 &UIC3 0x7 0x4 /* swizzled int D */>;
351 }; 353 };
352 354
353 PCIE2: pciex@d40000000 { 355 PCIE2: pciex@d40000000 {
@@ -357,23 +359,23 @@
357 #address-cells = <3>; 359 #address-cells = <3>;
358 compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex"; 360 compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex";
359 primary; 361 primary;
360 port = <2>; /* port number */ 362 port = <0x2>; /* port number */
361 reg = <d 40000000 20000000 /* Config space access */ 363 reg = <0x0000000d 0x40000000 0x20000000 /* Config space access */
362 c 10002000 00001000>; /* Registers */ 364 0x0000000c 0x10002000 0x00001000>; /* Registers */
363 dcr-reg = <140 020>; 365 dcr-reg = <0x140 0x020>;
364 sdr-base = <370>; 366 sdr-base = <0x370>;
365 367
366 /* Outbound ranges, one memory and one IO, 368 /* Outbound ranges, one memory and one IO,
367 * later cannot be changed 369 * later cannot be changed
368 */ 370 */
369 ranges = <02000000 0 80000000 0000000f 00000000 0 80000000 371 ranges = <0x02000000 0x00000000 0x80000000 0x0000000f 0x00000000 0x00000000 0x80000000
370 01000000 0 00000000 0000000f 80020000 0 00010000>; 372 0x01000000 0x00000000 0x00000000 0x0000000f 0x80020000 0x00000000 0x00010000>;
371 373
372 /* Inbound 2GB range starting at 0 */ 374 /* Inbound 2GB range starting at 0 */
373 dma-ranges = <42000000 0 0 0 0 0 80000000>; 375 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
374 376
375 /* This drives busses 10 to 0x1f */ 377 /* This drives busses 10 to 0x1f */
376 bus-range = <30 3f>; 378 bus-range = <0x30 0x3f>;
377 379
378 /* Legacy interrupts (note the weird polarity, the bridge seems 380 /* Legacy interrupts (note the weird polarity, the bridge seems
379 * to invert PCIe legacy interrupts). 381 * to invert PCIe legacy interrupts).
@@ -383,12 +385,12 @@
383 * below are basically de-swizzled numbers. 385 * below are basically de-swizzled numbers.
384 * The real slot is on idsel 0, so the swizzling is 1:1 386 * The real slot is on idsel 0, so the swizzling is 1:1
385 */ 387 */
386 interrupt-map-mask = <0000 0 0 7>; 388 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
387 interrupt-map = < 389 interrupt-map = <
388 0000 0 0 1 &UIC3 8 4 /* swizzled int A */ 390 0x0 0x0 0x0 0x1 &UIC3 0x8 0x4 /* swizzled int A */
389 0000 0 0 2 &UIC3 9 4 /* swizzled int B */ 391 0x0 0x0 0x0 0x2 &UIC3 0x9 0x4 /* swizzled int B */
390 0000 0 0 3 &UIC3 a 4 /* swizzled int C */ 392 0x0 0x0 0x0 0x3 &UIC3 0xa 0x4 /* swizzled int C */
391 0000 0 0 4 &UIC3 b 4 /* swizzled int D */>; 393 0x0 0x0 0x0 0x4 &UIC3 0xb 0x4 /* swizzled int D */>;
392 }; 394 };
393 }; 395 };
394 396
diff --git a/arch/powerpc/boot/dts/kilauea.dts b/arch/powerpc/boot/dts/kilauea.dts
index 48c9a6e71f1a..dececc4b5ff2 100644
--- a/arch/powerpc/boot/dts/kilauea.dts
+++ b/arch/powerpc/boot/dts/kilauea.dts
@@ -8,12 +8,14 @@
8 * any warranty of any kind, whether express or implied. 8 * any warranty of any kind, whether express or implied.
9 */ 9 */
10 10
11/dts-v1/;
12
11/ { 13/ {
12 #address-cells = <1>; 14 #address-cells = <1>;
13 #size-cells = <1>; 15 #size-cells = <1>;
14 model = "amcc,kilauea"; 16 model = "amcc,kilauea";
15 compatible = "amcc,kilauea"; 17 compatible = "amcc,kilauea";
16 dcr-parent = <&/cpus/cpu@0>; 18 dcr-parent = <&{/cpus/cpu@0}>;
17 19
18 aliases { 20 aliases {
19 ethernet0 = &EMAC0; 21 ethernet0 = &EMAC0;
@@ -29,13 +31,13 @@
29 cpu@0 { 31 cpu@0 {
30 device_type = "cpu"; 32 device_type = "cpu";
31 model = "PowerPC,405EX"; 33 model = "PowerPC,405EX";
32 reg = <0>; 34 reg = <0x00000000>;
33 clock-frequency = <0>; /* Filled in by U-Boot */ 35 clock-frequency = <0>; /* Filled in by U-Boot */
34 timebase-frequency = <0>; /* Filled in by U-Boot */ 36 timebase-frequency = <0>; /* Filled in by U-Boot */
35 i-cache-line-size = <20>; 37 i-cache-line-size = <32>;
36 d-cache-line-size = <20>; 38 d-cache-line-size = <32>;
37 i-cache-size = <4000>; /* 16 kB */ 39 i-cache-size = <16384>; /* 16 kB */
38 d-cache-size = <4000>; /* 16 kB */ 40 d-cache-size = <16384>; /* 16 kB */
39 dcr-controller; 41 dcr-controller;
40 dcr-access-method = "native"; 42 dcr-access-method = "native";
41 }; 43 };
@@ -43,14 +45,14 @@
43 45
44 memory { 46 memory {
45 device_type = "memory"; 47 device_type = "memory";
46 reg = <0 0>; /* Filled in by U-Boot */ 48 reg = <0x00000000 0x00000000>; /* Filled in by U-Boot */
47 }; 49 };
48 50
49 UIC0: interrupt-controller { 51 UIC0: interrupt-controller {
50 compatible = "ibm,uic-405ex", "ibm,uic"; 52 compatible = "ibm,uic-405ex", "ibm,uic";
51 interrupt-controller; 53 interrupt-controller;
52 cell-index = <0>; 54 cell-index = <0>;
53 dcr-reg = <0c0 009>; 55 dcr-reg = <0x0c0 0x009>;
54 #address-cells = <0>; 56 #address-cells = <0>;
55 #size-cells = <0>; 57 #size-cells = <0>;
56 #interrupt-cells = <2>; 58 #interrupt-cells = <2>;
@@ -60,11 +62,11 @@
60 compatible = "ibm,uic-405ex","ibm,uic"; 62 compatible = "ibm,uic-405ex","ibm,uic";
61 interrupt-controller; 63 interrupt-controller;
62 cell-index = <1>; 64 cell-index = <1>;
63 dcr-reg = <0d0 009>; 65 dcr-reg = <0x0d0 0x009>;
64 #address-cells = <0>; 66 #address-cells = <0>;
65 #size-cells = <0>; 67 #size-cells = <0>;
66 #interrupt-cells = <2>; 68 #interrupt-cells = <2>;
67 interrupts = <1e 4 1f 4>; /* cascade */ 69 interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
68 interrupt-parent = <&UIC0>; 70 interrupt-parent = <&UIC0>;
69 }; 71 };
70 72
@@ -72,11 +74,11 @@
72 compatible = "ibm,uic-405ex","ibm,uic"; 74 compatible = "ibm,uic-405ex","ibm,uic";
73 interrupt-controller; 75 interrupt-controller;
74 cell-index = <2>; 76 cell-index = <2>;
75 dcr-reg = <0e0 009>; 77 dcr-reg = <0x0e0 0x009>;
76 #address-cells = <0>; 78 #address-cells = <0>;
77 #size-cells = <0>; 79 #size-cells = <0>;
78 #interrupt-cells = <2>; 80 #interrupt-cells = <2>;
79 interrupts = <1c 4 1d 4>; /* cascade */ 81 interrupts = <0x1c 0x4 0x1d 0x4>; /* cascade */
80 interrupt-parent = <&UIC0>; 82 interrupt-parent = <&UIC0>;
81 }; 83 };
82 84
@@ -89,72 +91,72 @@
89 91
90 SDRAM0: memory-controller { 92 SDRAM0: memory-controller {
91 compatible = "ibm,sdram-405ex"; 93 compatible = "ibm,sdram-405ex";
92 dcr-reg = <010 2>; 94 dcr-reg = <0x010 0x002>;
93 }; 95 };
94 96
95 MAL0: mcmal { 97 MAL0: mcmal {
96 compatible = "ibm,mcmal-405ex", "ibm,mcmal2"; 98 compatible = "ibm,mcmal-405ex", "ibm,mcmal2";
97 dcr-reg = <180 62>; 99 dcr-reg = <0x180 0x062>;
98 num-tx-chans = <2>; 100 num-tx-chans = <2>;
99 num-rx-chans = <2>; 101 num-rx-chans = <2>;
100 interrupt-parent = <&MAL0>; 102 interrupt-parent = <&MAL0>;
101 interrupts = <0 1 2 3 4>; 103 interrupts = <0x0 0x1 0x2 0x3 0x4>;
102 #interrupt-cells = <1>; 104 #interrupt-cells = <1>;
103 #address-cells = <0>; 105 #address-cells = <0>;
104 #size-cells = <0>; 106 #size-cells = <0>;
105 interrupt-map = </*TXEOB*/ 0 &UIC0 a 4 107 interrupt-map = </*TXEOB*/ 0x0 &UIC0 0xa 0x4
106 /*RXEOB*/ 1 &UIC0 b 4 108 /*RXEOB*/ 0x1 &UIC0 0xb 0x4
107 /*SERR*/ 2 &UIC1 0 4 109 /*SERR*/ 0x2 &UIC1 0x0 0x4
108 /*TXDE*/ 3 &UIC1 1 4 110 /*TXDE*/ 0x3 &UIC1 0x1 0x4
109 /*RXDE*/ 4 &UIC1 2 4>; 111 /*RXDE*/ 0x4 &UIC1 0x2 0x4>;
110 interrupt-map-mask = <ffffffff>; 112 interrupt-map-mask = <0xffffffff>;
111 }; 113 };
112 114
113 POB0: opb { 115 POB0: opb {
114 compatible = "ibm,opb-405ex", "ibm,opb"; 116 compatible = "ibm,opb-405ex", "ibm,opb";
115 #address-cells = <1>; 117 #address-cells = <1>;
116 #size-cells = <1>; 118 #size-cells = <1>;
117 ranges = <80000000 80000000 10000000 119 ranges = <0x80000000 0x80000000 0x10000000
118 ef600000 ef600000 a00000 120 0xef600000 0xef600000 0x00a00000
119 f0000000 f0000000 10000000>; 121 0xf0000000 0xf0000000 0x10000000>;
120 dcr-reg = <0a0 5>; 122 dcr-reg = <0x0a0 0x005>;
121 clock-frequency = <0>; /* Filled in by U-Boot */ 123 clock-frequency = <0>; /* Filled in by U-Boot */
122 124
123 EBC0: ebc { 125 EBC0: ebc {
124 compatible = "ibm,ebc-405ex", "ibm,ebc"; 126 compatible = "ibm,ebc-405ex", "ibm,ebc";
125 dcr-reg = <012 2>; 127 dcr-reg = <0x012 0x002>;
126 #address-cells = <2>; 128 #address-cells = <2>;
127 #size-cells = <1>; 129 #size-cells = <1>;
128 clock-frequency = <0>; /* Filled in by U-Boot */ 130 clock-frequency = <0>; /* Filled in by U-Boot */
129 /* ranges property is supplied by U-Boot */ 131 /* ranges property is supplied by U-Boot */
130 interrupts = <5 1>; 132 interrupts = <0x5 0x1>;
131 interrupt-parent = <&UIC1>; 133 interrupt-parent = <&UIC1>;
132 134
133 nor_flash@0,0 { 135 nor_flash@0,0 {
134 compatible = "amd,s29gl512n", "cfi-flash"; 136 compatible = "amd,s29gl512n", "cfi-flash";
135 bank-width = <2>; 137 bank-width = <2>;
136 reg = <0 000000 4000000>; 138 reg = <0x00000000 0x00000000 0x04000000>;
137 #address-cells = <1>; 139 #address-cells = <1>;
138 #size-cells = <1>; 140 #size-cells = <1>;
139 partition@0 { 141 partition@0 {
140 label = "kernel"; 142 label = "kernel";
141 reg = <0 200000>; 143 reg = <0x00000000 0x00200000>;
142 }; 144 };
143 partition@200000 { 145 partition@200000 {
144 label = "root"; 146 label = "root";
145 reg = <200000 200000>; 147 reg = <0x00200000 0x00200000>;
146 }; 148 };
147 partition@400000 { 149 partition@400000 {
148 label = "user"; 150 label = "user";
149 reg = <400000 3b60000>; 151 reg = <0x00400000 0x03b60000>;
150 }; 152 };
151 partition@3f60000 { 153 partition@3f60000 {
152 label = "env"; 154 label = "env";
153 reg = <3f60000 40000>; 155 reg = <0x03f60000 0x00040000>;
154 }; 156 };
155 partition@3fa0000 { 157 partition@3fa0000 {
156 label = "u-boot"; 158 label = "u-boot";
157 reg = <3fa0000 60000>; 159 reg = <0x03fa0000 0x00060000>;
158 }; 160 };
159 }; 161 };
160 }; 162 };
@@ -162,68 +164,68 @@
162 UART0: serial@ef600200 { 164 UART0: serial@ef600200 {
163 device_type = "serial"; 165 device_type = "serial";
164 compatible = "ns16550"; 166 compatible = "ns16550";
165 reg = <ef600200 8>; 167 reg = <0xef600200 0x00000008>;
166 virtual-reg = <ef600200>; 168 virtual-reg = <0xef600200>;
167 clock-frequency = <0>; /* Filled in by U-Boot */ 169 clock-frequency = <0>; /* Filled in by U-Boot */
168 current-speed = <0>; 170 current-speed = <0>;
169 interrupt-parent = <&UIC0>; 171 interrupt-parent = <&UIC0>;
170 interrupts = <1a 4>; 172 interrupts = <0x1a 0x4>;
171 }; 173 };
172 174
173 UART1: serial@ef600300 { 175 UART1: serial@ef600300 {
174 device_type = "serial"; 176 device_type = "serial";
175 compatible = "ns16550"; 177 compatible = "ns16550";
176 reg = <ef600300 8>; 178 reg = <0xef600300 0x00000008>;
177 virtual-reg = <ef600300>; 179 virtual-reg = <0xef600300>;
178 clock-frequency = <0>; /* Filled in by U-Boot */ 180 clock-frequency = <0>; /* Filled in by U-Boot */
179 current-speed = <0>; 181 current-speed = <0>;
180 interrupt-parent = <&UIC0>; 182 interrupt-parent = <&UIC0>;
181 interrupts = <1 4>; 183 interrupts = <0x1 0x4>;
182 }; 184 };
183 185
184 IIC0: i2c@ef600400 { 186 IIC0: i2c@ef600400 {
185 compatible = "ibm,iic-405ex", "ibm,iic"; 187 compatible = "ibm,iic-405ex", "ibm,iic";
186 reg = <ef600400 14>; 188 reg = <0xef600400 0x00000014>;
187 interrupt-parent = <&UIC0>; 189 interrupt-parent = <&UIC0>;
188 interrupts = <2 4>; 190 interrupts = <0x2 0x4>;
189 }; 191 };
190 192
191 IIC1: i2c@ef600500 { 193 IIC1: i2c@ef600500 {
192 compatible = "ibm,iic-405ex", "ibm,iic"; 194 compatible = "ibm,iic-405ex", "ibm,iic";
193 reg = <ef600500 14>; 195 reg = <0xef600500 0x00000014>;
194 interrupt-parent = <&UIC0>; 196 interrupt-parent = <&UIC0>;
195 interrupts = <7 4>; 197 interrupts = <0x7 0x4>;
196 }; 198 };
197 199
198 200
199 RGMII0: emac-rgmii@ef600b00 { 201 RGMII0: emac-rgmii@ef600b00 {
200 compatible = "ibm,rgmii-405ex", "ibm,rgmii"; 202 compatible = "ibm,rgmii-405ex", "ibm,rgmii";
201 reg = <ef600b00 104>; 203 reg = <0xef600b00 0x00000104>;
202 has-mdio; 204 has-mdio;
203 }; 205 };
204 206
205 EMAC0: ethernet@ef600900 { 207 EMAC0: ethernet@ef600900 {
206 linux,network-index = <0>; 208 linux,network-index = <0x0>;
207 device_type = "network"; 209 device_type = "network";
208 compatible = "ibm,emac-405ex", "ibm,emac4"; 210 compatible = "ibm,emac-405ex", "ibm,emac4sync";
209 interrupt-parent = <&EMAC0>; 211 interrupt-parent = <&EMAC0>;
210 interrupts = <0 1>; 212 interrupts = <0x0 0x1>;
211 #interrupt-cells = <1>; 213 #interrupt-cells = <1>;
212 #address-cells = <0>; 214 #address-cells = <0>;
213 #size-cells = <0>; 215 #size-cells = <0>;
214 interrupt-map = </*Status*/ 0 &UIC0 18 4 216 interrupt-map = </*Status*/ 0x0 &UIC0 0x18 0x4
215 /*Wake*/ 1 &UIC1 1d 4>; 217 /*Wake*/ 0x1 &UIC1 0x1d 0x4>;
216 reg = <ef600900 70>; 218 reg = <0xef600900 0x000000c4>;
217 local-mac-address = [000000000000]; /* Filled in by U-Boot */ 219 local-mac-address = [000000000000]; /* Filled in by U-Boot */
218 mal-device = <&MAL0>; 220 mal-device = <&MAL0>;
219 mal-tx-channel = <0>; 221 mal-tx-channel = <0>;
220 mal-rx-channel = <0>; 222 mal-rx-channel = <0>;
221 cell-index = <0>; 223 cell-index = <0>;
222 max-frame-size = <2328>; 224 max-frame-size = <9000>;
223 rx-fifo-size = <1000>; 225 rx-fifo-size = <4096>;
224 tx-fifo-size = <800>; 226 tx-fifo-size = <2048>;
225 phy-mode = "rgmii"; 227 phy-mode = "rgmii";
226 phy-map = <00000000>; 228 phy-map = <0x00000000>;
227 rgmii-device = <&RGMII0>; 229 rgmii-device = <&RGMII0>;
228 rgmii-channel = <0>; 230 rgmii-channel = <0>;
229 has-inverted-stacr-oc; 231 has-inverted-stacr-oc;
@@ -231,27 +233,27 @@
231 }; 233 };
232 234
233 EMAC1: ethernet@ef600a00 { 235 EMAC1: ethernet@ef600a00 {
234 linux,network-index = <1>; 236 linux,network-index = <0x1>;
235 device_type = "network"; 237 device_type = "network";
236 compatible = "ibm,emac-405ex", "ibm,emac4"; 238 compatible = "ibm,emac-405ex", "ibm,emac4sync";
237 interrupt-parent = <&EMAC1>; 239 interrupt-parent = <&EMAC1>;
238 interrupts = <0 1>; 240 interrupts = <0x0 0x1>;
239 #interrupt-cells = <1>; 241 #interrupt-cells = <1>;
240 #address-cells = <0>; 242 #address-cells = <0>;
241 #size-cells = <0>; 243 #size-cells = <0>;
242 interrupt-map = </*Status*/ 0 &UIC0 19 4 244 interrupt-map = </*Status*/ 0x0 &UIC0 0x19 0x4
243 /*Wake*/ 1 &UIC1 1f 4>; 245 /*Wake*/ 0x1 &UIC1 0x1f 0x4>;
244 reg = <ef600a00 70>; 246 reg = <0xef600a00 0x000000c4>;
245 local-mac-address = [000000000000]; /* Filled in by U-Boot */ 247 local-mac-address = [000000000000]; /* Filled in by U-Boot */
246 mal-device = <&MAL0>; 248 mal-device = <&MAL0>;
247 mal-tx-channel = <1>; 249 mal-tx-channel = <1>;
248 mal-rx-channel = <1>; 250 mal-rx-channel = <1>;
249 cell-index = <1>; 251 cell-index = <1>;
250 max-frame-size = <2328>; 252 max-frame-size = <9000>;
251 rx-fifo-size = <1000>; 253 rx-fifo-size = <4096>;
252 tx-fifo-size = <800>; 254 tx-fifo-size = <2048>;
253 phy-mode = "rgmii"; 255 phy-mode = "rgmii";
254 phy-map = <00000000>; 256 phy-map = <0x00000000>;
255 rgmii-device = <&RGMII0>; 257 rgmii-device = <&RGMII0>;
256 rgmii-channel = <1>; 258 rgmii-channel = <1>;
257 has-inverted-stacr-oc; 259 has-inverted-stacr-oc;
@@ -266,23 +268,23 @@
266 #address-cells = <3>; 268 #address-cells = <3>;
267 compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex"; 269 compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex";
268 primary; 270 primary;
269 port = <0>; /* port number */ 271 port = <0x0>; /* port number */
270 reg = <a0000000 20000000 /* Config space access */ 272 reg = <0xa0000000 0x20000000 /* Config space access */
271 ef000000 00001000>; /* Registers */ 273 0xef000000 0x00001000>; /* Registers */
272 dcr-reg = <040 020>; 274 dcr-reg = <0x040 0x020>;
273 sdr-base = <400>; 275 sdr-base = <0x400>;
274 276
275 /* Outbound ranges, one memory and one IO, 277 /* Outbound ranges, one memory and one IO,
276 * later cannot be changed 278 * later cannot be changed
277 */ 279 */
278 ranges = <02000000 0 80000000 90000000 0 08000000 280 ranges = <0x02000000 0x00000000 0x80000000 0x90000000 0x00000000 0x08000000
279 01000000 0 00000000 e0000000 0 00010000>; 281 0x01000000 0x00000000 0x00000000 0xe0000000 0x00000000 0x00010000>;
280 282
281 /* Inbound 2GB range starting at 0 */ 283 /* Inbound 2GB range starting at 0 */
282 dma-ranges = <42000000 0 0 0 0 80000000>; 284 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>;
283 285
284 /* This drives busses 0x00 to 0x3f */ 286 /* This drives busses 0x00 to 0x3f */
285 bus-range = <00 3f>; 287 bus-range = <0x0 0x3f>;
286 288
287 /* Legacy interrupts (note the weird polarity, the bridge seems 289 /* Legacy interrupts (note the weird polarity, the bridge seems
288 * to invert PCIe legacy interrupts). 290 * to invert PCIe legacy interrupts).
@@ -292,12 +294,12 @@
292 * below are basically de-swizzled numbers. 294 * below are basically de-swizzled numbers.
293 * The real slot is on idsel 0, so the swizzling is 1:1 295 * The real slot is on idsel 0, so the swizzling is 1:1
294 */ 296 */
295 interrupt-map-mask = <0000 0 0 7>; 297 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
296 interrupt-map = < 298 interrupt-map = <
297 0000 0 0 1 &UIC2 0 4 /* swizzled int A */ 299 0x0 0x0 0x0 0x1 &UIC2 0x0 0x4 /* swizzled int A */
298 0000 0 0 2 &UIC2 1 4 /* swizzled int B */ 300 0x0 0x0 0x0 0x2 &UIC2 0x1 0x4 /* swizzled int B */
299 0000 0 0 3 &UIC2 2 4 /* swizzled int C */ 301 0x0 0x0 0x0 0x3 &UIC2 0x2 0x4 /* swizzled int C */
300 0000 0 0 4 &UIC2 3 4 /* swizzled int D */>; 302 0x0 0x0 0x0 0x4 &UIC2 0x3 0x4 /* swizzled int D */>;
301 }; 303 };
302 304
303 PCIE1: pciex@0c0000000 { 305 PCIE1: pciex@0c0000000 {
@@ -307,23 +309,23 @@
307 #address-cells = <3>; 309 #address-cells = <3>;
308 compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex"; 310 compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex";
309 primary; 311 primary;
310 port = <1>; /* port number */ 312 port = <0x1>; /* port number */
311 reg = <c0000000 20000000 /* Config space access */ 313 reg = <0xc0000000 0x20000000 /* Config space access */
312 ef001000 00001000>; /* Registers */ 314 0xef001000 0x00001000>; /* Registers */
313 dcr-reg = <060 020>; 315 dcr-reg = <0x060 0x020>;
314 sdr-base = <440>; 316 sdr-base = <0x440>;
315 317
316 /* Outbound ranges, one memory and one IO, 318 /* Outbound ranges, one memory and one IO,
317 * later cannot be changed 319 * later cannot be changed
318 */ 320 */
319 ranges = <02000000 0 80000000 98000000 0 08000000 321 ranges = <0x02000000 0x00000000 0x80000000 0x98000000 0x00000000 0x08000000
320 01000000 0 00000000 e0010000 0 00010000>; 322 0x01000000 0x00000000 0x00000000 0xe0010000 0x00000000 0x00010000>;
321 323
322 /* Inbound 2GB range starting at 0 */ 324 /* Inbound 2GB range starting at 0 */
323 dma-ranges = <42000000 0 0 0 0 80000000>; 325 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>;
324 326
325 /* This drives busses 0x40 to 0x7f */ 327 /* This drives busses 0x40 to 0x7f */
326 bus-range = <40 7f>; 328 bus-range = <0x40 0x7f>;
327 329
328 /* Legacy interrupts (note the weird polarity, the bridge seems 330 /* Legacy interrupts (note the weird polarity, the bridge seems
329 * to invert PCIe legacy interrupts). 331 * to invert PCIe legacy interrupts).
@@ -333,12 +335,12 @@
333 * below are basically de-swizzled numbers. 335 * below are basically de-swizzled numbers.
334 * The real slot is on idsel 0, so the swizzling is 1:1 336 * The real slot is on idsel 0, so the swizzling is 1:1
335 */ 337 */
336 interrupt-map-mask = <0000 0 0 7>; 338 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
337 interrupt-map = < 339 interrupt-map = <
338 0000 0 0 1 &UIC2 b 4 /* swizzled int A */ 340 0x0 0x0 0x0 0x1 &UIC2 0xb 0x4 /* swizzled int A */
339 0000 0 0 2 &UIC2 c 4 /* swizzled int B */ 341 0x0 0x0 0x0 0x2 &UIC2 0xc 0x4 /* swizzled int B */
340 0000 0 0 3 &UIC2 d 4 /* swizzled int C */ 342 0x0 0x0 0x0 0x3 &UIC2 0xd 0x4 /* swizzled int C */
341 0000 0 0 4 &UIC2 e 4 /* swizzled int D */>; 343 0x0 0x0 0x0 0x4 &UIC2 0xe 0x4 /* swizzled int D */>;
342 }; 344 };
343 }; 345 };
344}; 346};
diff --git a/arch/powerpc/boot/dts/ksi8560.dts b/arch/powerpc/boot/dts/ksi8560.dts
index f869ce3ca0b7..49737589ffc8 100644
--- a/arch/powerpc/boot/dts/ksi8560.dts
+++ b/arch/powerpc/boot/dts/ksi8560.dts
@@ -40,6 +40,7 @@
40 timebase-frequency = <0>; /* From U-boot */ 40 timebase-frequency = <0>; /* From U-boot */
41 bus-frequency = <0>; /* From U-boot */ 41 bus-frequency = <0>; /* From U-boot */
42 clock-frequency = <0>; /* From U-boot */ 42 clock-frequency = <0>; /* From U-boot */
43 next-level-cache = <&L2>;
43 }; 44 };
44 }; 45 };
45 46
@@ -58,16 +59,16 @@
58 memory-controller@2000 { 59 memory-controller@2000 {
59 compatible = "fsl,8540-memory-controller"; 60 compatible = "fsl,8540-memory-controller";
60 reg = <0x2000 0x1000>; 61 reg = <0x2000 0x1000>;
61 interrupt-parent = <&MPIC>; 62 interrupt-parent = <&mpic>;
62 interrupts = <0x12 0x2>; 63 interrupts = <0x12 0x2>;
63 }; 64 };
64 65
65 l2-cache-controller@20000 { 66 L2: l2-cache-controller@20000 {
66 compatible = "fsl,8540-l2-cache-controller"; 67 compatible = "fsl,8540-l2-cache-controller";
67 reg = <0x20000 0x1000>; 68 reg = <0x20000 0x1000>;
68 cache-line-size = <0x20>; /* 32 bytes */ 69 cache-line-size = <0x20>; /* 32 bytes */
69 cache-size = <0x40000>; /* L2, 256K */ 70 cache-size = <0x40000>; /* L2, 256K */
70 interrupt-parent = <&MPIC>; 71 interrupt-parent = <&mpic>;
71 interrupts = <0x10 0x2>; 72 interrupts = <0x10 0x2>;
72 }; 73 };
73 74
@@ -78,10 +79,51 @@
78 compatible = "fsl-i2c"; 79 compatible = "fsl-i2c";
79 reg = <0x3000 0x100>; 80 reg = <0x3000 0x100>;
80 interrupts = <0x2b 0x2>; 81 interrupts = <0x2b 0x2>;
81 interrupt-parent = <&MPIC>; 82 interrupt-parent = <&mpic>;
82 dfsrr; 83 dfsrr;
83 }; 84 };
84 85
86 dma@21300 {
87 #address-cells = <1>;
88 #size-cells = <1>;
89 compatible = "fsl,mpc8560-dma", "fsl,eloplus-dma";
90 reg = <0x21300 0x4>;
91 ranges = <0x0 0x21100 0x200>;
92 cell-index = <0>;
93 dma-channel@0 {
94 compatible = "fsl,mpc8560-dma-channel",
95 "fsl,eloplus-dma-channel";
96 reg = <0x0 0x80>;
97 cell-index = <0>;
98 interrupt-parent = <&mpic>;
99 interrupts = <20 2>;
100 };
101 dma-channel@80 {
102 compatible = "fsl,mpc8560-dma-channel",
103 "fsl,eloplus-dma-channel";
104 reg = <0x80 0x80>;
105 cell-index = <1>;
106 interrupt-parent = <&mpic>;
107 interrupts = <21 2>;
108 };
109 dma-channel@100 {
110 compatible = "fsl,mpc8560-dma-channel",
111 "fsl,eloplus-dma-channel";
112 reg = <0x100 0x80>;
113 cell-index = <2>;
114 interrupt-parent = <&mpic>;
115 interrupts = <22 2>;
116 };
117 dma-channel@180 {
118 compatible = "fsl,mpc8560-dma-channel",
119 "fsl,eloplus-dma-channel";
120 reg = <0x180 0x80>;
121 cell-index = <3>;
122 interrupt-parent = <&mpic>;
123 interrupts = <23 2>;
124 };
125 };
126
85 mdio@24520 { /* For TSECs */ 127 mdio@24520 { /* For TSECs */
86 #address-cells = <1>; 128 #address-cells = <1>;
87 #size-cells = <0>; 129 #size-cells = <0>;
@@ -89,13 +131,13 @@
89 reg = <0x24520 0x20>; 131 reg = <0x24520 0x20>;
90 132
91 PHY1: ethernet-phy@1 { 133 PHY1: ethernet-phy@1 {
92 interrupt-parent = <&MPIC>; 134 interrupt-parent = <&mpic>;
93 reg = <0x1>; 135 reg = <0x1>;
94 device_type = "ethernet-phy"; 136 device_type = "ethernet-phy";
95 }; 137 };
96 138
97 PHY2: ethernet-phy@2 { 139 PHY2: ethernet-phy@2 {
98 interrupt-parent = <&MPIC>; 140 interrupt-parent = <&mpic>;
99 reg = <0x2>; 141 reg = <0x2>;
100 device_type = "ethernet-phy"; 142 device_type = "ethernet-phy";
101 }; 143 };
@@ -109,7 +151,7 @@
109 /* Mac address filled in by bootwrapper */ 151 /* Mac address filled in by bootwrapper */
110 local-mac-address = [ 00 00 00 00 00 00 ]; 152 local-mac-address = [ 00 00 00 00 00 00 ];
111 interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>; 153 interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>;
112 interrupt-parent = <&MPIC>; 154 interrupt-parent = <&mpic>;
113 phy-handle = <&PHY1>; 155 phy-handle = <&PHY1>;
114 }; 156 };
115 157
@@ -121,11 +163,11 @@
121 /* Mac address filled in by bootwrapper */ 163 /* Mac address filled in by bootwrapper */
122 local-mac-address = [ 00 00 00 00 00 00 ]; 164 local-mac-address = [ 00 00 00 00 00 00 ];
123 interrupts = <0x23 0x2 0x24 0x2 0x28 0x2>; 165 interrupts = <0x23 0x2 0x24 0x2 0x28 0x2>;
124 interrupt-parent = <&MPIC>; 166 interrupt-parent = <&mpic>;
125 phy-handle = <&PHY2>; 167 phy-handle = <&PHY2>;
126 }; 168 };
127 169
128 MPIC: pic@40000 { 170 mpic: pic@40000 {
129 #address-cells = <0>; 171 #address-cells = <0>;
130 #interrupt-cells = <2>; 172 #interrupt-cells = <2>;
131 interrupt-controller; 173 interrupt-controller;
@@ -164,7 +206,7 @@
164 #interrupt-cells = <2>; 206 #interrupt-cells = <2>;
165 interrupt-controller; 207 interrupt-controller;
166 interrupts = <0x2e 0x2>; 208 interrupts = <0x2e 0x2>;
167 interrupt-parent = <&MPIC>; 209 interrupt-parent = <&mpic>;
168 reg = <0x90c00 0x80>; 210 reg = <0x90c00 0x80>;
169 compatible = "fsl,mpc8560-cpm-pic", "fsl,cpm2-pic"; 211 compatible = "fsl,mpc8560-cpm-pic", "fsl,cpm2-pic";
170 }; 212 };
@@ -202,7 +244,7 @@
202 fsl,mdc-pin = <25>; 244 fsl,mdc-pin = <25>;
203 245
204 PHY0: ethernet-phy@0 { 246 PHY0: ethernet-phy@0 {
205 interrupt-parent = <&MPIC>; 247 interrupt-parent = <&mpic>;
206 reg = <0x0>; 248 reg = <0x0>;
207 device_type = "ethernet-phy"; 249 device_type = "ethernet-phy";
208 }; 250 };
diff --git a/arch/powerpc/boot/dts/makalu.dts b/arch/powerpc/boot/dts/makalu.dts
index 84cc5e72ddd8..945508c7e7d8 100644
--- a/arch/powerpc/boot/dts/makalu.dts
+++ b/arch/powerpc/boot/dts/makalu.dts
@@ -8,12 +8,14 @@
8 * any warranty of any kind, whether express or implied. 8 * any warranty of any kind, whether express or implied.
9 */ 9 */
10 10
11/dts-v1/;
12
11/ { 13/ {
12 #address-cells = <1>; 14 #address-cells = <1>;
13 #size-cells = <1>; 15 #size-cells = <1>;
14 model = "amcc,makalu"; 16 model = "amcc,makalu";
15 compatible = "amcc,makalu"; 17 compatible = "amcc,makalu";
16 dcr-parent = <&/cpus/cpu@0>; 18 dcr-parent = <&{/cpus/cpu@0}>;
17 19
18 aliases { 20 aliases {
19 ethernet0 = &EMAC0; 21 ethernet0 = &EMAC0;
@@ -29,13 +31,13 @@
29 cpu@0 { 31 cpu@0 {
30 device_type = "cpu"; 32 device_type = "cpu";
31 model = "PowerPC,405EX"; 33 model = "PowerPC,405EX";
32 reg = <0>; 34 reg = <0x00000000>;
33 clock-frequency = <0>; /* Filled in by U-Boot */ 35 clock-frequency = <0>; /* Filled in by U-Boot */
34 timebase-frequency = <0>; /* Filled in by U-Boot */ 36 timebase-frequency = <0>; /* Filled in by U-Boot */
35 i-cache-line-size = <20>; 37 i-cache-line-size = <32>;
36 d-cache-line-size = <20>; 38 d-cache-line-size = <32>;
37 i-cache-size = <4000>; /* 16 kB */ 39 i-cache-size = <16384>; /* 16 kB */
38 d-cache-size = <4000>; /* 16 kB */ 40 d-cache-size = <16384>; /* 16 kB */
39 dcr-controller; 41 dcr-controller;
40 dcr-access-method = "native"; 42 dcr-access-method = "native";
41 }; 43 };
@@ -43,14 +45,14 @@
43 45
44 memory { 46 memory {
45 device_type = "memory"; 47 device_type = "memory";
46 reg = <0 0>; /* Filled in by U-Boot */ 48 reg = <0x00000000 0x00000000>; /* Filled in by U-Boot */
47 }; 49 };
48 50
49 UIC0: interrupt-controller { 51 UIC0: interrupt-controller {
50 compatible = "ibm,uic-405ex", "ibm,uic"; 52 compatible = "ibm,uic-405ex", "ibm,uic";
51 interrupt-controller; 53 interrupt-controller;
52 cell-index = <0>; 54 cell-index = <0>;
53 dcr-reg = <0c0 009>; 55 dcr-reg = <0x0c0 0x009>;
54 #address-cells = <0>; 56 #address-cells = <0>;
55 #size-cells = <0>; 57 #size-cells = <0>;
56 #interrupt-cells = <2>; 58 #interrupt-cells = <2>;
@@ -60,11 +62,11 @@
60 compatible = "ibm,uic-405ex","ibm,uic"; 62 compatible = "ibm,uic-405ex","ibm,uic";
61 interrupt-controller; 63 interrupt-controller;
62 cell-index = <1>; 64 cell-index = <1>;
63 dcr-reg = <0d0 009>; 65 dcr-reg = <0x0d0 0x009>;
64 #address-cells = <0>; 66 #address-cells = <0>;
65 #size-cells = <0>; 67 #size-cells = <0>;
66 #interrupt-cells = <2>; 68 #interrupt-cells = <2>;
67 interrupts = <1e 4 1f 4>; /* cascade */ 69 interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
68 interrupt-parent = <&UIC0>; 70 interrupt-parent = <&UIC0>;
69 }; 71 };
70 72
@@ -72,11 +74,11 @@
72 compatible = "ibm,uic-405ex","ibm,uic"; 74 compatible = "ibm,uic-405ex","ibm,uic";
73 interrupt-controller; 75 interrupt-controller;
74 cell-index = <2>; 76 cell-index = <2>;
75 dcr-reg = <0e0 009>; 77 dcr-reg = <0x0e0 0x009>;
76 #address-cells = <0>; 78 #address-cells = <0>;
77 #size-cells = <0>; 79 #size-cells = <0>;
78 #interrupt-cells = <2>; 80 #interrupt-cells = <2>;
79 interrupts = <1c 4 1d 4>; /* cascade */ 81 interrupts = <0x1c 0x4 0x1d 0x4>; /* cascade */
80 interrupt-parent = <&UIC0>; 82 interrupt-parent = <&UIC0>;
81 }; 83 };
82 84
@@ -89,72 +91,72 @@
89 91
90 SDRAM0: memory-controller { 92 SDRAM0: memory-controller {
91 compatible = "ibm,sdram-405ex"; 93 compatible = "ibm,sdram-405ex";
92 dcr-reg = <010 2>; 94 dcr-reg = <0x010 0x002>;
93 }; 95 };
94 96
95 MAL0: mcmal { 97 MAL0: mcmal {
96 compatible = "ibm,mcmal-405ex", "ibm,mcmal2"; 98 compatible = "ibm,mcmal-405ex", "ibm,mcmal2";
97 dcr-reg = <180 62>; 99 dcr-reg = <0x180 0x062>;
98 num-tx-chans = <2>; 100 num-tx-chans = <2>;
99 num-rx-chans = <2>; 101 num-rx-chans = <2>;
100 interrupt-parent = <&MAL0>; 102 interrupt-parent = <&MAL0>;
101 interrupts = <0 1 2 3 4>; 103 interrupts = <0x0 0x1 0x2 0x3 0x4>;
102 #interrupt-cells = <1>; 104 #interrupt-cells = <1>;
103 #address-cells = <0>; 105 #address-cells = <0>;
104 #size-cells = <0>; 106 #size-cells = <0>;
105 interrupt-map = </*TXEOB*/ 0 &UIC0 a 4 107 interrupt-map = </*TXEOB*/ 0x0 &UIC0 0xa 0x4
106 /*RXEOB*/ 1 &UIC0 b 4 108 /*RXEOB*/ 0x1 &UIC0 0xb 0x4
107 /*SERR*/ 2 &UIC1 0 4 109 /*SERR*/ 0x2 &UIC1 0x0 0x4
108 /*TXDE*/ 3 &UIC1 1 4 110 /*TXDE*/ 0x3 &UIC1 0x1 0x4
109 /*RXDE*/ 4 &UIC1 2 4>; 111 /*RXDE*/ 0x4 &UIC1 0x2 0x4>;
110 interrupt-map-mask = <ffffffff>; 112 interrupt-map-mask = <0xffffffff>;
111 }; 113 };
112 114
113 POB0: opb { 115 POB0: opb {
114 compatible = "ibm,opb-405ex", "ibm,opb"; 116 compatible = "ibm,opb-405ex", "ibm,opb";
115 #address-cells = <1>; 117 #address-cells = <1>;
116 #size-cells = <1>; 118 #size-cells = <1>;
117 ranges = <80000000 80000000 10000000 119 ranges = <0x80000000 0x80000000 0x10000000
118 ef600000 ef600000 a00000 120 0xef600000 0xef600000 0x00a00000
119 f0000000 f0000000 10000000>; 121 0xf0000000 0xf0000000 0x10000000>;
120 dcr-reg = <0a0 5>; 122 dcr-reg = <0x0a0 0x005>;
121 clock-frequency = <0>; /* Filled in by U-Boot */ 123 clock-frequency = <0>; /* Filled in by U-Boot */
122 124
123 EBC0: ebc { 125 EBC0: ebc {
124 compatible = "ibm,ebc-405ex", "ibm,ebc"; 126 compatible = "ibm,ebc-405ex", "ibm,ebc";
125 dcr-reg = <012 2>; 127 dcr-reg = <0x012 0x002>;
126 #address-cells = <2>; 128 #address-cells = <2>;
127 #size-cells = <1>; 129 #size-cells = <1>;
128 clock-frequency = <0>; /* Filled in by U-Boot */ 130 clock-frequency = <0>; /* Filled in by U-Boot */
129 /* ranges property is supplied by U-Boot */ 131 /* ranges property is supplied by U-Boot */
130 interrupts = <5 1>; 132 interrupts = <0x5 0x1>;
131 interrupt-parent = <&UIC1>; 133 interrupt-parent = <&UIC1>;
132 134
133 nor_flash@0,0 { 135 nor_flash@0,0 {
134 compatible = "amd,s29gl512n", "cfi-flash"; 136 compatible = "amd,s29gl512n", "cfi-flash";
135 bank-width = <2>; 137 bank-width = <2>;
136 reg = <0 000000 4000000>; 138 reg = <0x00000000 0x00000000 0x04000000>;
137 #address-cells = <1>; 139 #address-cells = <1>;
138 #size-cells = <1>; 140 #size-cells = <1>;
139 partition@0 { 141 partition@0 {
140 label = "kernel"; 142 label = "kernel";
141 reg = <0 200000>; 143 reg = <0x00000000 0x00200000>;
142 }; 144 };
143 partition@200000 { 145 partition@200000 {
144 label = "root"; 146 label = "root";
145 reg = <200000 200000>; 147 reg = <0x00200000 0x00200000>;
146 }; 148 };
147 partition@400000 { 149 partition@400000 {
148 label = "user"; 150 label = "user";
149 reg = <400000 3b60000>; 151 reg = <0x00400000 0x03b60000>;
150 }; 152 };
151 partition@3f60000 { 153 partition@3f60000 {
152 label = "env"; 154 label = "env";
153 reg = <3f60000 40000>; 155 reg = <0x03f60000 0x00040000>;
154 }; 156 };
155 partition@3fa0000 { 157 partition@3fa0000 {
156 label = "u-boot"; 158 label = "u-boot";
157 reg = <3fa0000 60000>; 159 reg = <0x03fa0000 0x00060000>;
158 }; 160 };
159 }; 161 };
160 }; 162 };
@@ -162,68 +164,68 @@
162 UART0: serial@ef600200 { 164 UART0: serial@ef600200 {
163 device_type = "serial"; 165 device_type = "serial";
164 compatible = "ns16550"; 166 compatible = "ns16550";
165 reg = <ef600200 8>; 167 reg = <0xef600200 0x00000008>;
166 virtual-reg = <ef600200>; 168 virtual-reg = <0xef600200>;
167 clock-frequency = <0>; /* Filled in by U-Boot */ 169 clock-frequency = <0>; /* Filled in by U-Boot */
168 current-speed = <0>; 170 current-speed = <0>;
169 interrupt-parent = <&UIC0>; 171 interrupt-parent = <&UIC0>;
170 interrupts = <1a 4>; 172 interrupts = <0x1a 0x4>;
171 }; 173 };
172 174
173 UART1: serial@ef600300 { 175 UART1: serial@ef600300 {
174 device_type = "serial"; 176 device_type = "serial";
175 compatible = "ns16550"; 177 compatible = "ns16550";
176 reg = <ef600300 8>; 178 reg = <0xef600300 0x00000008>;
177 virtual-reg = <ef600300>; 179 virtual-reg = <0xef600300>;
178 clock-frequency = <0>; /* Filled in by U-Boot */ 180 clock-frequency = <0>; /* Filled in by U-Boot */
179 current-speed = <0>; 181 current-speed = <0>;
180 interrupt-parent = <&UIC0>; 182 interrupt-parent = <&UIC0>;
181 interrupts = <1 4>; 183 interrupts = <0x1 0x4>;
182 }; 184 };
183 185
184 IIC0: i2c@ef600400 { 186 IIC0: i2c@ef600400 {
185 compatible = "ibm,iic-405ex", "ibm,iic"; 187 compatible = "ibm,iic-405ex", "ibm,iic";
186 reg = <ef600400 14>; 188 reg = <0xef600400 0x00000014>;
187 interrupt-parent = <&UIC0>; 189 interrupt-parent = <&UIC0>;
188 interrupts = <2 4>; 190 interrupts = <0x2 0x4>;
189 }; 191 };
190 192
191 IIC1: i2c@ef600500 { 193 IIC1: i2c@ef600500 {
192 compatible = "ibm,iic-405ex", "ibm,iic"; 194 compatible = "ibm,iic-405ex", "ibm,iic";
193 reg = <ef600500 14>; 195 reg = <0xef600500 0x00000014>;
194 interrupt-parent = <&UIC0>; 196 interrupt-parent = <&UIC0>;
195 interrupts = <7 4>; 197 interrupts = <0x7 0x4>;
196 }; 198 };
197 199
198 200
199 RGMII0: emac-rgmii@ef600b00 { 201 RGMII0: emac-rgmii@ef600b00 {
200 compatible = "ibm,rgmii-405ex", "ibm,rgmii"; 202 compatible = "ibm,rgmii-405ex", "ibm,rgmii";
201 reg = <ef600b00 104>; 203 reg = <0xef600b00 0x00000104>;
202 has-mdio; 204 has-mdio;
203 }; 205 };
204 206
205 EMAC0: ethernet@ef600900 { 207 EMAC0: ethernet@ef600900 {
206 linux,network-index = <0>; 208 linux,network-index = <0x0>;
207 device_type = "network"; 209 device_type = "network";
208 compatible = "ibm,emac-405ex", "ibm,emac4"; 210 compatible = "ibm,emac-405ex", "ibm,emac4sync";
209 interrupt-parent = <&EMAC0>; 211 interrupt-parent = <&EMAC0>;
210 interrupts = <0 1>; 212 interrupts = <0x0 0x1>;
211 #interrupt-cells = <1>; 213 #interrupt-cells = <1>;
212 #address-cells = <0>; 214 #address-cells = <0>;
213 #size-cells = <0>; 215 #size-cells = <0>;
214 interrupt-map = </*Status*/ 0 &UIC0 18 4 216 interrupt-map = </*Status*/ 0x0 &UIC0 0x18 0x4
215 /*Wake*/ 1 &UIC1 1d 4>; 217 /*Wake*/ 0x1 &UIC1 0x1d 0x4>;
216 reg = <ef600900 70>; 218 reg = <0xef600900 0x000000c4>;
217 local-mac-address = [000000000000]; /* Filled in by U-Boot */ 219 local-mac-address = [000000000000]; /* Filled in by U-Boot */
218 mal-device = <&MAL0>; 220 mal-device = <&MAL0>;
219 mal-tx-channel = <0>; 221 mal-tx-channel = <0>;
220 mal-rx-channel = <0>; 222 mal-rx-channel = <0>;
221 cell-index = <0>; 223 cell-index = <0>;
222 max-frame-size = <2328>; 224 max-frame-size = <9000>;
223 rx-fifo-size = <1000>; 225 rx-fifo-size = <4096>;
224 tx-fifo-size = <800>; 226 tx-fifo-size = <2048>;
225 phy-mode = "rgmii"; 227 phy-mode = "rgmii";
226 phy-map = <0000003f>; /* Start at 6 */ 228 phy-map = <0x0000003f>; /* Start at 6 */
227 rgmii-device = <&RGMII0>; 229 rgmii-device = <&RGMII0>;
228 rgmii-channel = <0>; 230 rgmii-channel = <0>;
229 has-inverted-stacr-oc; 231 has-inverted-stacr-oc;
@@ -231,27 +233,27 @@
231 }; 233 };
232 234
233 EMAC1: ethernet@ef600a00 { 235 EMAC1: ethernet@ef600a00 {
234 linux,network-index = <1>; 236 linux,network-index = <0x1>;
235 device_type = "network"; 237 device_type = "network";
236 compatible = "ibm,emac-405ex", "ibm,emac4"; 238 compatible = "ibm,emac-405ex", "ibm,emac4sync";
237 interrupt-parent = <&EMAC1>; 239 interrupt-parent = <&EMAC1>;
238 interrupts = <0 1>; 240 interrupts = <0x0 0x1>;
239 #interrupt-cells = <1>; 241 #interrupt-cells = <1>;
240 #address-cells = <0>; 242 #address-cells = <0>;
241 #size-cells = <0>; 243 #size-cells = <0>;
242 interrupt-map = </*Status*/ 0 &UIC0 19 4 244 interrupt-map = </*Status*/ 0x0 &UIC0 0x19 0x4
243 /*Wake*/ 1 &UIC1 1f 4>; 245 /*Wake*/ 0x1 &UIC1 0x1f 0x4>;
244 reg = <ef600a00 70>; 246 reg = <0xef600a00 0x000000c4>;
245 local-mac-address = [000000000000]; /* Filled in by U-Boot */ 247 local-mac-address = [000000000000]; /* Filled in by U-Boot */
246 mal-device = <&MAL0>; 248 mal-device = <&MAL0>;
247 mal-tx-channel = <1>; 249 mal-tx-channel = <1>;
248 mal-rx-channel = <1>; 250 mal-rx-channel = <1>;
249 cell-index = <1>; 251 cell-index = <1>;
250 max-frame-size = <2328>; 252 max-frame-size = <9000>;
251 rx-fifo-size = <1000>; 253 rx-fifo-size = <4096>;
252 tx-fifo-size = <800>; 254 tx-fifo-size = <2048>;
253 phy-mode = "rgmii"; 255 phy-mode = "rgmii";
254 phy-map = <00000000>; 256 phy-map = <0x00000000>;
255 rgmii-device = <&RGMII0>; 257 rgmii-device = <&RGMII0>;
256 rgmii-channel = <1>; 258 rgmii-channel = <1>;
257 has-inverted-stacr-oc; 259 has-inverted-stacr-oc;
@@ -266,23 +268,23 @@
266 #address-cells = <3>; 268 #address-cells = <3>;
267 compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex"; 269 compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex";
268 primary; 270 primary;
269 port = <0>; /* port number */ 271 port = <0x0>; /* port number */
270 reg = <a0000000 20000000 /* Config space access */ 272 reg = <0xa0000000 0x20000000 /* Config space access */
271 ef000000 00001000>; /* Registers */ 273 0xef000000 0x00001000>; /* Registers */
272 dcr-reg = <040 020>; 274 dcr-reg = <0x040 0x020>;
273 sdr-base = <400>; 275 sdr-base = <0x400>;
274 276
275 /* Outbound ranges, one memory and one IO, 277 /* Outbound ranges, one memory and one IO,
276 * later cannot be changed 278 * later cannot be changed
277 */ 279 */
278 ranges = <02000000 0 80000000 90000000 0 08000000 280 ranges = <0x02000000 0x00000000 0x80000000 0x90000000 0x00000000 0x08000000
279 01000000 0 00000000 e0000000 0 00010000>; 281 0x01000000 0x00000000 0x00000000 0xe0000000 0x00000000 0x00010000>;
280 282
281 /* Inbound 2GB range starting at 0 */ 283 /* Inbound 2GB range starting at 0 */
282 dma-ranges = <42000000 0 0 0 0 80000000>; 284 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>;
283 285
284 /* This drives busses 0x00 to 0x3f */ 286 /* This drives busses 0x00 to 0x3f */
285 bus-range = <00 3f>; 287 bus-range = <0x0 0x3f>;
286 288
287 /* Legacy interrupts (note the weird polarity, the bridge seems 289 /* Legacy interrupts (note the weird polarity, the bridge seems
288 * to invert PCIe legacy interrupts). 290 * to invert PCIe legacy interrupts).
@@ -292,12 +294,12 @@
292 * below are basically de-swizzled numbers. 294 * below are basically de-swizzled numbers.
293 * The real slot is on idsel 0, so the swizzling is 1:1 295 * The real slot is on idsel 0, so the swizzling is 1:1
294 */ 296 */
295 interrupt-map-mask = <0000 0 0 7>; 297 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
296 interrupt-map = < 298 interrupt-map = <
297 0000 0 0 1 &UIC2 0 4 /* swizzled int A */ 299 0x0 0x0 0x0 0x1 &UIC2 0x0 0x4 /* swizzled int A */
298 0000 0 0 2 &UIC2 1 4 /* swizzled int B */ 300 0x0 0x0 0x0 0x2 &UIC2 0x1 0x4 /* swizzled int B */
299 0000 0 0 3 &UIC2 2 4 /* swizzled int C */ 301 0x0 0x0 0x0 0x3 &UIC2 0x2 0x4 /* swizzled int C */
300 0000 0 0 4 &UIC2 3 4 /* swizzled int D */>; 302 0x0 0x0 0x0 0x4 &UIC2 0x3 0x4 /* swizzled int D */>;
301 }; 303 };
302 304
303 PCIE1: pciex@0c0000000 { 305 PCIE1: pciex@0c0000000 {
@@ -307,23 +309,23 @@
307 #address-cells = <3>; 309 #address-cells = <3>;
308 compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex"; 310 compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex";
309 primary; 311 primary;
310 port = <1>; /* port number */ 312 port = <0x1>; /* port number */
311 reg = <c0000000 20000000 /* Config space access */ 313 reg = <0xc0000000 0x20000000 /* Config space access */
312 ef001000 00001000>; /* Registers */ 314 0xef001000 0x00001000>; /* Registers */
313 dcr-reg = <060 020>; 315 dcr-reg = <0x060 0x020>;
314 sdr-base = <440>; 316 sdr-base = <0x440>;
315 317
316 /* Outbound ranges, one memory and one IO, 318 /* Outbound ranges, one memory and one IO,
317 * later cannot be changed 319 * later cannot be changed
318 */ 320 */
319 ranges = <02000000 0 80000000 98000000 0 08000000 321 ranges = <0x02000000 0x00000000 0x80000000 0x98000000 0x00000000 0x08000000
320 01000000 0 00000000 e0010000 0 00010000>; 322 0x01000000 0x00000000 0x00000000 0xe0010000 0x00000000 0x00010000>;
321 323
322 /* Inbound 2GB range starting at 0 */ 324 /* Inbound 2GB range starting at 0 */
323 dma-ranges = <42000000 0 0 0 0 80000000>; 325 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>;
324 326
325 /* This drives busses 0x40 to 0x7f */ 327 /* This drives busses 0x40 to 0x7f */
326 bus-range = <40 7f>; 328 bus-range = <0x40 0x7f>;
327 329
328 /* Legacy interrupts (note the weird polarity, the bridge seems 330 /* Legacy interrupts (note the weird polarity, the bridge seems
329 * to invert PCIe legacy interrupts). 331 * to invert PCIe legacy interrupts).
@@ -333,12 +335,12 @@
333 * below are basically de-swizzled numbers. 335 * below are basically de-swizzled numbers.
334 * The real slot is on idsel 0, so the swizzling is 1:1 336 * The real slot is on idsel 0, so the swizzling is 1:1
335 */ 337 */
336 interrupt-map-mask = <0000 0 0 7>; 338 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
337 interrupt-map = < 339 interrupt-map = <
338 0000 0 0 1 &UIC2 b 4 /* swizzled int A */ 340 0x0 0x0 0x0 0x1 &UIC2 0xb 0x4 /* swizzled int A */
339 0000 0 0 2 &UIC2 c 4 /* swizzled int B */ 341 0x0 0x0 0x0 0x2 &UIC2 0xc 0x4 /* swizzled int B */
340 0000 0 0 3 &UIC2 d 4 /* swizzled int C */ 342 0x0 0x0 0x0 0x3 &UIC2 0xd 0x4 /* swizzled int C */
341 0000 0 0 4 &UIC2 e 4 /* swizzled int D */>; 343 0x0 0x0 0x0 0x4 &UIC2 0xe 0x4 /* swizzled int D */>;
342 }; 344 };
343 }; 345 };
344}; 346};
diff --git a/arch/powerpc/boot/dts/mpc5121ads.dts b/arch/powerpc/boot/dts/mpc5121ads.dts
index 94ad7b2b241e..1f9036c317b4 100644
--- a/arch/powerpc/boot/dts/mpc5121ads.dts
+++ b/arch/powerpc/boot/dts/mpc5121ads.dts
@@ -1,7 +1,7 @@
1/* 1/*
2 * MPC5121E MDS Device Tree Source 2 * MPC5121E ADS Device Tree Source
3 * 3 *
4 * Copyright 2007 Freescale Semiconductor Inc. 4 * Copyright 2007,2008 Freescale Semiconductor Inc.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the 7 * under the terms of the GNU General Public License as published by the
@@ -17,6 +17,10 @@
17 #address-cells = <1>; 17 #address-cells = <1>;
18 #size-cells = <1>; 18 #size-cells = <1>;
19 19
20 aliases {
21 pci = &pci;
22 };
23
20 cpus { 24 cpus {
21 #address-cells = <1>; 25 #address-cells = <1>;
22 #size-cells = <0>; 26 #size-cells = <0>;
@@ -39,8 +43,41 @@
39 reg = <0x00000000 0x10000000>; // 256MB at 0 43 reg = <0x00000000 0x10000000>; // 256MB at 0
40 }; 44 };
41 45
46 mbx@20000000 {
47 compatible = "fsl,mpc5121-mbx";
48 reg = <0x20000000 0x4000>;
49 interrupts = <66 0x8>;
50 interrupt-parent = < &ipic >;
51 };
52
53 sram@30000000 {
54 compatible = "fsl,mpc5121-sram";
55 reg = <0x30000000 0x20000>; // 128K at 0x30000000
56 };
57
58 nfc@40000000 {
59 compatible = "fsl,mpc5121-nfc";
60 reg = <0x40000000 0x100000>; // 1M at 0x40000000
61 interrupts = <6 8>;
62 interrupt-parent = < &ipic >;
63 #address-cells = <1>;
64 #size-cells = <1>;
65 bank-width = <1>;
66 // ADS has two Hynix 512MB Nand flash chips in a single
67 // stacked package .
68 chips = <2>;
69 nand0@0 {
70 label = "nand0";
71 reg = <0x00000000 0x02000000>; // first 32 MB of chip 0
72 };
73 nand1@20000000 {
74 label = "nand1";
75 reg = <0x20000000 0x02000000>; // first 32 MB of chip 1
76 };
77 };
78
42 localbus@80000020 { 79 localbus@80000020 {
43 compatible = "fsl,mpc5121ads-localbus"; 80 compatible = "fsl,mpc5121-localbus";
44 #address-cells = <2>; 81 #address-cells = <2>;
45 #size-cells = <1>; 82 #size-cells = <1>;
46 reg = <0x80000020 0x40>; 83 reg = <0x80000020 0x40>;
@@ -51,14 +88,51 @@
51 flash@0,0 { 88 flash@0,0 {
52 compatible = "cfi-flash"; 89 compatible = "cfi-flash";
53 reg = <0 0x0 0x4000000>; 90 reg = <0 0x0 0x4000000>;
91 #address-cells = <1>;
92 #size-cells = <1>;
54 bank-width = <4>; 93 bank-width = <4>;
55 device-width = <1>; 94 device-width = <2>;
95 protected@0 {
96 label = "protected";
97 reg = <0x00000000 0x00040000>; // first sector is protected
98 read-only;
99 };
100 filesystem@40000 {
101 label = "filesystem";
102 reg = <0x00040000 0x03c00000>; // 60M for filesystem
103 };
104 kernel@3c40000 {
105 label = "kernel";
106 reg = <0x03c40000 0x00280000>; // 2.5M for kernel
107 };
108 device-tree@3ec0000 {
109 label = "device-tree";
110 reg = <0x03ec0000 0x00040000>; // one sector for device tree
111 };
112 u-boot@3f00000 {
113 label = "u-boot";
114 reg = <0x03f00000 0x00100000>; // 1M for u-boot
115 read-only;
116 };
56 }; 117 };
57 118
58 board-control@2,0 { 119 board-control@2,0 {
59 compatible = "fsl,mpc5121ads-cpld"; 120 compatible = "fsl,mpc5121ads-cpld";
60 reg = <0x2 0x0 0x8000>; 121 reg = <0x2 0x0 0x8000>;
61 }; 122 };
123
124 cpld_pic: pic@2,a {
125 compatible = "fsl,mpc5121ads-cpld-pic";
126 interrupt-controller;
127 #interrupt-cells = <2>;
128 reg = <0x2 0xa 0x5>;
129 interrupt-parent = < &ipic >;
130 // irq routing
131 // all irqs but touch screen are routed to irq0 (ipic 48)
132 // touch screen is statically routed to irq1 (ipic 17)
133 // so don't use it here
134 interrupts = <48 0x8>;
135 };
62 }; 136 };
63 137
64 soc@80000000 { 138 soc@80000000 {
@@ -85,38 +159,252 @@
85 reg = <0xc00 0x100>; 159 reg = <0xc00 0x100>;
86 }; 160 };
87 161
88 // 512x PSCs are not 52xx PSCs compatible 162 rtc@a00 { // Real time clock
163 compatible = "fsl,mpc5121-rtc";
164 reg = <0xa00 0x100>;
165 interrupts = <79 0x8 80 0x8>;
166 interrupt-parent = < &ipic >;
167 };
168
169 clock@f00 { // Clock control
170 compatible = "fsl,mpc5121-clock";
171 reg = <0xf00 0x100>;
172 };
173
174 pmc@1000{ //Power Management Controller
175 compatible = "fsl,mpc5121-pmc";
176 reg = <0x1000 0x100>;
177 interrupts = <83 0x2>;
178 interrupt-parent = < &ipic >;
179 };
180
181 gpio@1100 {
182 compatible = "fsl,mpc5121-gpio";
183 reg = <0x1100 0x100>;
184 interrupts = <78 0x8>;
185 interrupt-parent = < &ipic >;
186 };
187
188 mscan@1300 {
189 compatible = "fsl,mpc5121-mscan";
190 cell-index = <0>;
191 interrupts = <12 0x8>;
192 interrupt-parent = < &ipic >;
193 reg = <0x1300 0x80>;
194 };
195
196 mscan@1380 {
197 compatible = "fsl,mpc5121-mscan";
198 cell-index = <1>;
199 interrupts = <13 0x8>;
200 interrupt-parent = < &ipic >;
201 reg = <0x1380 0x80>;
202 };
203
204 i2c@1700 {
205 #address-cells = <1>;
206 #size-cells = <0>;
207 compatible = "fsl,mpc5121-i2c", "fsl-i2c";
208 cell-index = <0>;
209 reg = <0x1700 0x20>;
210 interrupts = <9 0x8>;
211 interrupt-parent = < &ipic >;
212 fsl5200-clocking;
213 };
214
215 i2c@1720 {
216 #address-cells = <1>;
217 #size-cells = <0>;
218 compatible = "fsl,mpc5121-i2c", "fsl-i2c";
219 cell-index = <1>;
220 reg = <0x1720 0x20>;
221 interrupts = <10 0x8>;
222 interrupt-parent = < &ipic >;
223 fsl5200-clocking;
224 };
225
226 i2c@1740 {
227 #address-cells = <1>;
228 #size-cells = <0>;
229 compatible = "fsl,mpc5121-i2c", "fsl-i2c";
230 cell-index = <2>;
231 reg = <0x1740 0x20>;
232 interrupts = <11 0x8>;
233 interrupt-parent = < &ipic >;
234 fsl5200-clocking;
235 };
236
237 i2ccontrol@1760 {
238 compatible = "fsl,mpc5121-i2c-ctrl";
239 reg = <0x1760 0x8>;
240 };
241
242 axe@2000 {
243 compatible = "fsl,mpc5121-axe";
244 reg = <0x2000 0x100>;
245 interrupts = <42 0x8>;
246 interrupt-parent = < &ipic >;
247 };
248
249 display@2100 {
250 compatible = "fsl,mpc5121-diu", "fsl-diu";
251 reg = <0x2100 0x100>;
252 interrupts = <64 0x8>;
253 interrupt-parent = < &ipic >;
254 };
255
256 mdio@2800 {
257 compatible = "fsl,mpc5121-fec-mdio";
258 reg = <0x2800 0x800>;
259 #address-cells = <1>;
260 #size-cells = <0>;
261 phy: ethernet-phy@0 {
262 reg = <1>;
263 device_type = "ethernet-phy";
264 };
265 };
266
267 ethernet@2800 {
268 device_type = "network";
269 compatible = "fsl,mpc5121-fec";
270 reg = <0x2800 0x800>;
271 local-mac-address = [ 00 00 00 00 00 00 ];
272 interrupts = <4 0x8>;
273 interrupt-parent = < &ipic >;
274 phy-handle = < &phy >;
275 fsl,align-tx-packets = <4>;
276 };
277
278 // 5121e has two dr usb modules
279 // mpc5121_ads only uses USB0
280
281 // USB1 using external ULPI PHY
282 //usb@3000 {
283 // compatible = "fsl,mpc5121-usb2-dr", "fsl-usb2-dr";
284 // reg = <0x3000 0x1000>;
285 // #address-cells = <1>;
286 // #size-cells = <0>;
287 // interrupt-parent = < &ipic >;
288 // interrupts = <43 0x8>;
289 // dr_mode = "otg";
290 // phy_type = "ulpi";
291 // port1;
292 //};
293
294 // USB0 using internal UTMI PHY
295 usb@4000 {
296 compatible = "fsl,mpc5121-usb2-dr", "fsl-usb2-dr";
297 reg = <0x4000 0x1000>;
298 #address-cells = <1>;
299 #size-cells = <0>;
300 interrupt-parent = < &ipic >;
301 interrupts = <44 0x8>;
302 dr_mode = "otg";
303 phy_type = "utmi_wide";
304 port0;
305 };
306
307 // IO control
308 ioctl@a000 {
309 compatible = "fsl,mpc5121-ioctl";
310 reg = <0xA000 0x1000>;
311 };
312
313 pata@10200 {
314 compatible = "fsl,mpc5121-pata";
315 reg = <0x10200 0x100>;
316 interrupts = <5 0x8>;
317 interrupt-parent = < &ipic >;
318 };
319
320 // 512x PSCs are not 52xx PSC compatible
89 // PSC3 serial port A aka ttyPSC0 321 // PSC3 serial port A aka ttyPSC0
90 serial@11300 { 322 serial@11300 {
91 device_type = "serial"; 323 device_type = "serial";
92 compatible = "fsl,mpc5121-psc-uart"; 324 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
93 // Logical port assignment needed until driver 325 // Logical port assignment needed until driver
94 // learns to use aliases 326 // learns to use aliases
95 port-number = <0>; 327 port-number = <0>;
96 cell-index = <3>; 328 cell-index = <3>;
97 reg = <0x11300 0x100>; 329 reg = <0x11300 0x100>;
98 interrupts = <0x28 0x8>; // actually the fifo irq 330 interrupts = <40 0x8>;
99 interrupt-parent = < &ipic >; 331 interrupt-parent = < &ipic >;
332 rx-fifo-size = <16>;
333 tx-fifo-size = <16>;
100 }; 334 };
101 335
102 // PSC4 serial port B aka ttyPSC1 336 // PSC4 serial port B aka ttyPSC1
103 serial@11400 { 337 serial@11400 {
104 device_type = "serial"; 338 device_type = "serial";
105 compatible = "fsl,mpc5121-psc-uart"; 339 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
106 // Logical port assignment needed until driver 340 // Logical port assignment needed until driver
107 // learns to use aliases 341 // learns to use aliases
108 port-number = <1>; 342 port-number = <1>;
109 cell-index = <4>; 343 cell-index = <4>;
110 reg = <0x11400 0x100>; 344 reg = <0x11400 0x100>;
111 interrupts = <0x28 0x8>; // actually the fifo irq 345 interrupts = <40 0x8>;
112 interrupt-parent = < &ipic >; 346 interrupt-parent = < &ipic >;
347 rx-fifo-size = <16>;
348 tx-fifo-size = <16>;
113 }; 349 };
114 350
115 pscsfifo@11f00 { 351 // PSC5 in ac97 mode
352 ac97@11500 {
353 compatible = "fsl,mpc5121-psc-ac97", "fsl,mpc5121-psc";
354 cell-index = <5>;
355 reg = <0x11500 0x100>;
356 interrupts = <40 0x8>;
357 interrupt-parent = < &ipic >;
358 fsl,mode = "ac97-slave";
359 rx-fifo-size = <384>;
360 tx-fifo-size = <384>;
361 };
362
363 pscfifo@11f00 {
116 compatible = "fsl,mpc5121-psc-fifo"; 364 compatible = "fsl,mpc5121-psc-fifo";
117 reg = <0x11f00 0x100>; 365 reg = <0x11f00 0x100>;
118 interrupts = <0x28 0x8>; 366 interrupts = <40 0x8>;
119 interrupt-parent = < &ipic >; 367 interrupt-parent = < &ipic >;
120 }; 368 };
369
370 dma@14000 {
371 compatible = "fsl,mpc5121-dma2";
372 reg = <0x14000 0x1800>;
373 interrupts = <65 0x8>;
374 interrupt-parent = < &ipic >;
375 };
376
377 };
378
379 pci: pci@80008500 {
380 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
381 interrupt-map = <
382 // IDSEL 0x15 - Slot 1 PCI
383 0xa800 0x0 0x0 0x1 &cpld_pic 0x0 0x8
384 0xa800 0x0 0x0 0x2 &cpld_pic 0x1 0x8
385 0xa800 0x0 0x0 0x3 &cpld_pic 0x2 0x8
386 0xa800 0x0 0x0 0x4 &cpld_pic 0x3 0x8
387
388 // IDSEL 0x16 - Slot 2 MiniPCI
389 0xb000 0x0 0x0 0x1 &cpld_pic 0x4 0x8
390 0xb000 0x0 0x0 0x2 &cpld_pic 0x5 0x8
391
392 // IDSEL 0x17 - Slot 3 MiniPCI
393 0xb800 0x0 0x0 0x1 &cpld_pic 0x6 0x8
394 0xb800 0x0 0x0 0x2 &cpld_pic 0x7 0x8
395 >;
396 interrupt-parent = < &ipic >;
397 interrupts = <1 0x8>;
398 bus-range = <0 0>;
399 ranges = <0x42000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
400 0x02000000 0x0 0xb0000000 0xb0000000 0x0 0x10000000
401 0x01000000 0x0 0x00000000 0x84000000 0x0 0x01000000>;
402 clock-frequency = <0>;
403 #interrupt-cells = <1>;
404 #size-cells = <2>;
405 #address-cells = <3>;
406 reg = <0x80008500 0x100>;
407 compatible = "fsl,mpc5121-pci";
408 device_type = "pci";
121 }; 409 };
122}; 410};
diff --git a/arch/powerpc/boot/dts/mpc7448hpc2.dts b/arch/powerpc/boot/dts/mpc7448hpc2.dts
index 4936349b87cd..705c23c14f32 100644
--- a/arch/powerpc/boot/dts/mpc7448hpc2.dts
+++ b/arch/powerpc/boot/dts/mpc7448hpc2.dts
@@ -124,14 +124,12 @@
124 }; 124 };
125 125
126 mpic: pic@7400 { 126 mpic: pic@7400 {
127 clock-frequency = <0>;
128 interrupt-controller; 127 interrupt-controller;
129 #address-cells = <0>; 128 #address-cells = <0>;
130 #interrupt-cells = <2>; 129 #interrupt-cells = <2>;
131 reg = <0x7400 0x400>; 130 reg = <0x7400 0x400>;
132 compatible = "chrp,open-pic"; 131 compatible = "chrp,open-pic";
133 device_type = "open-pic"; 132 device_type = "open-pic";
134 big-endian;
135 }; 133 };
136 pci@1000 { 134 pci@1000 {
137 compatible = "tsi108-pci"; 135 compatible = "tsi108-pci";
diff --git a/arch/powerpc/boot/dts/mpc8272ads.dts b/arch/powerpc/boot/dts/mpc8272ads.dts
index 46e2da30c3dd..2a1929acaabd 100644
--- a/arch/powerpc/boot/dts/mpc8272ads.dts
+++ b/arch/powerpc/boot/dts/mpc8272ads.dts
@@ -217,6 +217,17 @@
217 linux,network-index = <1>; 217 linux,network-index = <1>;
218 fsl,cpm-command = <0x16200300>; 218 fsl,cpm-command = <0x16200300>;
219 }; 219 };
220
221 i2c@11860 {
222 compatible = "fsl,mpc8272-i2c",
223 "fsl,cpm2-i2c";
224 reg = <0x11860 0x20 0x8afc 0x2>;
225 interrupts = <1 8>;
226 interrupt-parent = <&PIC>;
227 fsl,cpm-command = <0x29600000>;
228 #address-cells = <1>;
229 #size-cells = <0>;
230 };
220 }; 231 };
221 232
222 PIC: interrupt-controller@10c00 { 233 PIC: interrupt-controller@10c00 {
@@ -226,22 +237,15 @@
226 compatible = "fsl,mpc8272-pic", "fsl,cpm2-pic"; 237 compatible = "fsl,mpc8272-pic", "fsl,cpm2-pic";
227 }; 238 };
228 239
229/* May need to remove if on a part without crypto engine */
230 crypto@30000 { 240 crypto@30000 {
231 device_type = "crypto"; 241 compatible = "fsl,sec1.0";
232 model = "SEC2"; 242 reg = <0x40000 0x13000>;
233 compatible = "fsl,mpc8272-talitos-sec2", 243 interrupts = <47 0x8>;
234 "fsl,talitos-sec2",
235 "fsl,talitos",
236 "talitos";
237 reg = <0x30000 0x10000>;
238 interrupts = <11 8>;
239 interrupt-parent = <&PIC>; 244 interrupt-parent = <&PIC>;
240 num-channels = <4>; 245 fsl,num-channels = <4>;
241 channel-fifo-len = <24>; 246 fsl,channel-fifo-len = <24>;
242 exec-units-mask = <0x7e>; 247 fsl,exec-units-mask = <0x7e>;
243/* desc mask is for rev1.x, we need runtime fixup for >=2.x */ 248 fsl,descriptor-types-mask = <0x1010415>;
244 descriptor-types-mask = <0x1010ebf>;
245 }; 249 };
246 }; 250 };
247 251
diff --git a/arch/powerpc/boot/dts/mpc8313erdb.dts b/arch/powerpc/boot/dts/mpc8313erdb.dts
index e1f0dca8ac39..3664fb584026 100644
--- a/arch/powerpc/boot/dts/mpc8313erdb.dts
+++ b/arch/powerpc/boot/dts/mpc8313erdb.dts
@@ -144,6 +144,41 @@
144 mode = "cpu"; 144 mode = "cpu";
145 }; 145 };
146 146
147 dma@82a8 {
148 #address-cells = <1>;
149 #size-cells = <1>;
150 compatible = "fsl,mpc8313-dma", "fsl,elo-dma";
151 reg = <0x82a8 4>;
152 ranges = <0 0x8100 0x1a8>;
153 interrupt-parent = <&ipic>;
154 interrupts = <71 8>;
155 cell-index = <0>;
156 dma-channel@0 {
157 compatible = "fsl,mpc8313-dma-channel", "fsl,elo-dma-channel";
158 reg = <0 0x80>;
159 interrupt-parent = <&ipic>;
160 interrupts = <71 8>;
161 };
162 dma-channel@80 {
163 compatible = "fsl,mpc8313-dma-channel", "fsl,elo-dma-channel";
164 reg = <0x80 0x80>;
165 interrupt-parent = <&ipic>;
166 interrupts = <71 8>;
167 };
168 dma-channel@100 {
169 compatible = "fsl,mpc8313-dma-channel", "fsl,elo-dma-channel";
170 reg = <0x100 0x80>;
171 interrupt-parent = <&ipic>;
172 interrupts = <71 8>;
173 };
174 dma-channel@180 {
175 compatible = "fsl,mpc8313-dma-channel", "fsl,elo-dma-channel";
176 reg = <0x180 0x28>;
177 interrupt-parent = <&ipic>;
178 interrupts = <71 8>;
179 };
180 };
181
147 /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */ 182 /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
148 usb@23000 { 183 usb@23000 {
149 compatible = "fsl-usb2-dr"; 184 compatible = "fsl-usb2-dr";
@@ -219,17 +254,14 @@
219 }; 254 };
220 255
221 crypto@30000 { 256 crypto@30000 {
222 device_type = "crypto"; 257 compatible = "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
223 model = "SEC2"; 258 reg = <0x30000 0x10000>;
224 compatible = "talitos";
225 reg = <0x30000 0x7000>;
226 interrupts = <11 0x8>; 259 interrupts = <11 0x8>;
227 interrupt-parent = <&ipic>; 260 interrupt-parent = <&ipic>;
228 /* Rev. 2.2 */ 261 fsl,num-channels = <1>;
229 num-channels = <1>; 262 fsl,channel-fifo-len = <24>;
230 channel-fifo-len = <24>; 263 fsl,exec-units-mask = <0x4c>;
231 exec-units-mask = <0x0000004c>; 264 fsl,descriptor-types-mask = <0x0122003f>;
232 descriptor-types-mask = <0x0122003f>;
233 }; 265 };
234 266
235 /* IPIC 267 /* IPIC
diff --git a/arch/powerpc/boot/dts/mpc8315erdb.dts b/arch/powerpc/boot/dts/mpc8315erdb.dts
index d7a1ececa30f..f704513fb930 100644
--- a/arch/powerpc/boot/dts/mpc8315erdb.dts
+++ b/arch/powerpc/boot/dts/mpc8315erdb.dts
@@ -132,6 +132,41 @@
132 mode = "cpu"; 132 mode = "cpu";
133 }; 133 };
134 134
135 dma@82a8 {
136 #address-cells = <1>;
137 #size-cells = <1>;
138 compatible = "fsl,mpc8315-dma", "fsl,elo-dma";
139 reg = <0x82a8 4>;
140 ranges = <0 0x8100 0x1a8>;
141 interrupt-parent = <&ipic>;
142 interrupts = <71 8>;
143 cell-index = <0>;
144 dma-channel@0 {
145 compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
146 reg = <0 0x80>;
147 interrupt-parent = <&ipic>;
148 interrupts = <71 8>;
149 };
150 dma-channel@80 {
151 compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
152 reg = <0x80 0x80>;
153 interrupt-parent = <&ipic>;
154 interrupts = <71 8>;
155 };
156 dma-channel@100 {
157 compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
158 reg = <0x100 0x80>;
159 interrupt-parent = <&ipic>;
160 interrupts = <71 8>;
161 };
162 dma-channel@180 {
163 compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
164 reg = <0x180 0x28>;
165 interrupt-parent = <&ipic>;
166 interrupts = <71 8>;
167 };
168 };
169
135 usb@23000 { 170 usb@23000 {
136 compatible = "fsl-usb2-dr"; 171 compatible = "fsl-usb2-dr";
137 reg = <0x23000 0x1000>; 172 reg = <0x23000 0x1000>;
@@ -206,17 +241,16 @@
206 }; 241 };
207 242
208 crypto@30000 { 243 crypto@30000 {
209 model = "SEC3"; 244 compatible = "fsl,sec3.3", "fsl,sec3.1", "fsl,sec3.0",
210 device_type = "crypto"; 245 "fsl,sec2.4", "fsl,sec2.2", "fsl,sec2.1",
211 compatible = "talitos"; 246 "fsl,sec2.0";
212 reg = <0x30000 0x10000>; 247 reg = <0x30000 0x10000>;
213 interrupts = <11 0x8>; 248 interrupts = <11 0x8>;
214 interrupt-parent = <&ipic>; 249 interrupt-parent = <&ipic>;
215 /* Rev. 3.0 geometry */ 250 fsl,num-channels = <4>;
216 num-channels = <4>; 251 fsl,channel-fifo-len = <24>;
217 channel-fifo-len = <24>; 252 fsl,exec-units-mask = <0x97c>;
218 exec-units-mask = <0x000001fe>; 253 fsl,descriptor-types-mask = <0x3ab0abf>;
219 descriptor-types-mask = <0x03ab0ebf>;
220 }; 254 };
221 255
222 sata@18000 { 256 sata@18000 {
diff --git a/arch/powerpc/boot/dts/mpc832x_mds.dts b/arch/powerpc/boot/dts/mpc832x_mds.dts
index 539e02fb3526..7345743d3d96 100644
--- a/arch/powerpc/boot/dts/mpc832x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc832x_mds.dts
@@ -114,18 +114,50 @@
114 interrupt-parent = <&ipic>; 114 interrupt-parent = <&ipic>;
115 }; 115 };
116 116
117 dma@82a8 {
118 #address-cells = <1>;
119 #size-cells = <1>;
120 compatible = "fsl,mpc8323-dma", "fsl,elo-dma";
121 reg = <0x82a8 4>;
122 ranges = <0 0x8100 0x1a8>;
123 interrupt-parent = <&ipic>;
124 interrupts = <71 8>;
125 cell-index = <0>;
126 dma-channel@0 {
127 compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
128 reg = <0 0x80>;
129 interrupt-parent = <&ipic>;
130 interrupts = <71 8>;
131 };
132 dma-channel@80 {
133 compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
134 reg = <0x80 0x80>;
135 interrupt-parent = <&ipic>;
136 interrupts = <71 8>;
137 };
138 dma-channel@100 {
139 compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
140 reg = <0x100 0x80>;
141 interrupt-parent = <&ipic>;
142 interrupts = <71 8>;
143 };
144 dma-channel@180 {
145 compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
146 reg = <0x180 0x28>;
147 interrupt-parent = <&ipic>;
148 interrupts = <71 8>;
149 };
150 };
151
117 crypto@30000 { 152 crypto@30000 {
118 device_type = "crypto"; 153 compatible = "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
119 model = "SEC2"; 154 reg = <0x30000 0x10000>;
120 compatible = "talitos";
121 reg = <0x30000 0x7000>;
122 interrupts = <11 0x8>; 155 interrupts = <11 0x8>;
123 interrupt-parent = <&ipic>; 156 interrupt-parent = <&ipic>;
124 /* Rev. 2.2 */ 157 fsl,num-channels = <1>;
125 num-channels = <1>; 158 fsl,channel-fifo-len = <24>;
126 channel-fifo-len = <24>; 159 fsl,exec-units-mask = <0x4c>;
127 exec-units-mask = <0x0000004c>; 160 fsl,descriptor-types-mask = <0x0122003f>;
128 descriptor-types-mask = <0x0122003f>;
129 }; 161 };
130 162
131 ipic: pic@700 { 163 ipic: pic@700 {
diff --git a/arch/powerpc/boot/dts/mpc832x_rdb.dts b/arch/powerpc/boot/dts/mpc832x_rdb.dts
index 179c81c6a7ac..e74c045a0f8c 100644
--- a/arch/powerpc/boot/dts/mpc832x_rdb.dts
+++ b/arch/powerpc/boot/dts/mpc832x_rdb.dts
@@ -68,7 +68,7 @@
68 compatible = "fsl-i2c"; 68 compatible = "fsl-i2c";
69 reg = <0x3000 0x100>; 69 reg = <0x3000 0x100>;
70 interrupts = <14 0x8>; 70 interrupts = <14 0x8>;
71 interrupt-parent = <&pic>; 71 interrupt-parent = <&ipic>;
72 dfsrr; 72 dfsrr;
73 }; 73 };
74 74
@@ -79,7 +79,7 @@
79 reg = <0x4500 0x100>; 79 reg = <0x4500 0x100>;
80 clock-frequency = <0>; 80 clock-frequency = <0>;
81 interrupts = <9 0x8>; 81 interrupts = <9 0x8>;
82 interrupt-parent = <&pic>; 82 interrupt-parent = <&ipic>;
83 }; 83 };
84 84
85 serial1: serial@4600 { 85 serial1: serial@4600 {
@@ -89,24 +89,56 @@
89 reg = <0x4600 0x100>; 89 reg = <0x4600 0x100>;
90 clock-frequency = <0>; 90 clock-frequency = <0>;
91 interrupts = <10 0x8>; 91 interrupts = <10 0x8>;
92 interrupt-parent = <&pic>; 92 interrupt-parent = <&ipic>;
93 };
94
95 dma@82a8 {
96 #address-cells = <1>;
97 #size-cells = <1>;
98 compatible = "fsl,mpc8323-dma", "fsl,elo-dma";
99 reg = <0x82a8 4>;
100 ranges = <0 0x8100 0x1a8>;
101 interrupt-parent = <&ipic>;
102 interrupts = <71 8>;
103 cell-index = <0>;
104 dma-channel@0 {
105 compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
106 reg = <0 0x80>;
107 interrupt-parent = <&ipic>;
108 interrupts = <71 8>;
109 };
110 dma-channel@80 {
111 compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
112 reg = <0x80 0x80>;
113 interrupt-parent = <&ipic>;
114 interrupts = <71 8>;
115 };
116 dma-channel@100 {
117 compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
118 reg = <0x100 0x80>;
119 interrupt-parent = <&ipic>;
120 interrupts = <71 8>;
121 };
122 dma-channel@180 {
123 compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
124 reg = <0x180 0x28>;
125 interrupt-parent = <&ipic>;
126 interrupts = <71 8>;
127 };
93 }; 128 };
94 129
95 crypto@30000 { 130 crypto@30000 {
96 device_type = "crypto"; 131 compatible = "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
97 model = "SEC2"; 132 reg = <0x30000 0x10000>;
98 compatible = "talitos";
99 reg = <0x30000 0x7000>;
100 interrupts = <11 0x8>; 133 interrupts = <11 0x8>;
101 interrupt-parent = <&pic>; 134 interrupt-parent = <&ipic>;
102 /* Rev. 2.2 */ 135 fsl,num-channels = <1>;
103 num-channels = <1>; 136 fsl,channel-fifo-len = <24>;
104 channel-fifo-len = <24>; 137 fsl,exec-units-mask = <0x4c>;
105 exec-units-mask = <0x0000004c>; 138 fsl,descriptor-types-mask = <0x0122003f>;
106 descriptor-types-mask = <0x0122003f>;
107 }; 139 };
108 140
109 pic:pic@700 { 141 ipic:pic@700 {
110 interrupt-controller; 142 interrupt-controller;
111 #address-cells = <0>; 143 #address-cells = <0>;
112 #interrupt-cells = <2>; 144 #interrupt-cells = <2>;
@@ -240,13 +272,13 @@
240 compatible = "fsl,ucc-mdio"; 272 compatible = "fsl,ucc-mdio";
241 273
242 phy00:ethernet-phy@00 { 274 phy00:ethernet-phy@00 {
243 interrupt-parent = <&pic>; 275 interrupt-parent = <&ipic>;
244 interrupts = <0>; 276 interrupts = <0>;
245 reg = <0x0>; 277 reg = <0x0>;
246 device_type = "ethernet-phy"; 278 device_type = "ethernet-phy";
247 }; 279 };
248 phy04:ethernet-phy@04 { 280 phy04:ethernet-phy@04 {
249 interrupt-parent = <&pic>; 281 interrupt-parent = <&ipic>;
250 interrupts = <0>; 282 interrupts = <0>;
251 reg = <0x4>; 283 reg = <0x4>;
252 device_type = "ethernet-phy"; 284 device_type = "ethernet-phy";
@@ -261,7 +293,7 @@
261 reg = <0x80 0x80>; 293 reg = <0x80 0x80>;
262 big-endian; 294 big-endian;
263 interrupts = <32 0x8 33 0x8>; //high:32 low:33 295 interrupts = <32 0x8 33 0x8>; //high:32 low:33
264 interrupt-parent = <&pic>; 296 interrupt-parent = <&ipic>;
265 }; 297 };
266 }; 298 };
267 299
@@ -270,21 +302,21 @@
270 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 302 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
271 interrupt-map = < 303 interrupt-map = <
272 /* IDSEL 0x10 AD16 (USB) */ 304 /* IDSEL 0x10 AD16 (USB) */
273 0x8000 0x0 0x0 0x1 &pic 17 0x8 305 0x8000 0x0 0x0 0x1 &ipic 17 0x8
274 306
275 /* IDSEL 0x11 AD17 (Mini1)*/ 307 /* IDSEL 0x11 AD17 (Mini1)*/
276 0x8800 0x0 0x0 0x1 &pic 18 0x8 308 0x8800 0x0 0x0 0x1 &ipic 18 0x8
277 0x8800 0x0 0x0 0x2 &pic 19 0x8 309 0x8800 0x0 0x0 0x2 &ipic 19 0x8
278 0x8800 0x0 0x0 0x3 &pic 20 0x8 310 0x8800 0x0 0x0 0x3 &ipic 20 0x8
279 0x8800 0x0 0x0 0x4 &pic 48 0x8 311 0x8800 0x0 0x0 0x4 &ipic 48 0x8
280 312
281 /* IDSEL 0x12 AD18 (PCI/Mini2) */ 313 /* IDSEL 0x12 AD18 (PCI/Mini2) */
282 0x9000 0x0 0x0 0x1 &pic 19 0x8 314 0x9000 0x0 0x0 0x1 &ipic 19 0x8
283 0x9000 0x0 0x0 0x2 &pic 20 0x8 315 0x9000 0x0 0x0 0x2 &ipic 20 0x8
284 0x9000 0x0 0x0 0x3 &pic 48 0x8 316 0x9000 0x0 0x0 0x3 &ipic 48 0x8
285 0x9000 0x0 0x0 0x4 &pic 17 0x8>; 317 0x9000 0x0 0x0 0x4 &ipic 17 0x8>;
286 318
287 interrupt-parent = <&pic>; 319 interrupt-parent = <&ipic>;
288 interrupts = <66 0x8>; 320 interrupts = <66 0x8>;
289 bus-range = <0x0 0x0>; 321 bus-range = <0x0 0x0>;
290 ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000 322 ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
diff --git a/arch/powerpc/boot/dts/mpc8349emitx.dts b/arch/powerpc/boot/dts/mpc8349emitx.dts
index 9426676b0b7d..8dfab5662585 100644
--- a/arch/powerpc/boot/dts/mpc8349emitx.dts
+++ b/arch/powerpc/boot/dts/mpc8349emitx.dts
@@ -93,6 +93,41 @@
93 mode = "cpu"; 93 mode = "cpu";
94 }; 94 };
95 95
96 dma@82a8 {
97 #address-cells = <1>;
98 #size-cells = <1>;
99 compatible = "fsl,mpc8349-dma", "fsl,elo-dma";
100 reg = <0x82a8 4>;
101 ranges = <0 0x8100 0x1a8>;
102 interrupt-parent = <&ipic>;
103 interrupts = <71 8>;
104 cell-index = <0>;
105 dma-channel@0 {
106 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
107 reg = <0 0x80>;
108 interrupt-parent = <&ipic>;
109 interrupts = <71 8>;
110 };
111 dma-channel@80 {
112 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
113 reg = <0x80 0x80>;
114 interrupt-parent = <&ipic>;
115 interrupts = <71 8>;
116 };
117 dma-channel@100 {
118 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
119 reg = <0x100 0x80>;
120 interrupt-parent = <&ipic>;
121 interrupts = <71 8>;
122 };
123 dma-channel@180 {
124 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
125 reg = <0x180 0x28>;
126 interrupt-parent = <&ipic>;
127 interrupts = <71 8>;
128 };
129 };
130
96 usb@22000 { 131 usb@22000 {
97 compatible = "fsl-usb2-mph"; 132 compatible = "fsl-usb2-mph";
98 reg = <0x22000 0x1000>; 133 reg = <0x22000 0x1000>;
@@ -178,16 +213,14 @@
178 }; 213 };
179 214
180 crypto@30000 { 215 crypto@30000 {
181 device_type = "crypto"; 216 compatible = "fsl,sec2.0";
182 model = "SEC2";
183 compatible = "talitos";
184 reg = <0x30000 0x10000>; 217 reg = <0x30000 0x10000>;
185 interrupts = <11 0x8>; 218 interrupts = <11 0x8>;
186 interrupt-parent = <&ipic>; 219 interrupt-parent = <&ipic>;
187 num-channels = <4>; 220 fsl,num-channels = <4>;
188 channel-fifo-len = <24>; 221 fsl,channel-fifo-len = <24>;
189 exec-units-mask = <0x0000007e>; 222 fsl,exec-units-mask = <0x7e>;
190 descriptor-types-mask = <0x01010ebf>; 223 fsl,descriptor-types-mask = <0x01010ebf>;
191 }; 224 };
192 225
193 ipic: pic@700 { 226 ipic: pic@700 {
diff --git a/arch/powerpc/boot/dts/mpc8349emitxgp.dts b/arch/powerpc/boot/dts/mpc8349emitxgp.dts
index f81d735e6e72..49ca3497eefb 100644
--- a/arch/powerpc/boot/dts/mpc8349emitxgp.dts
+++ b/arch/powerpc/boot/dts/mpc8349emitxgp.dts
@@ -91,6 +91,41 @@
91 mode = "cpu"; 91 mode = "cpu";
92 }; 92 };
93 93
94 dma@82a8 {
95 #address-cells = <1>;
96 #size-cells = <1>;
97 compatible = "fsl,mpc8349-dma", "fsl,elo-dma";
98 reg = <0x82a8 4>;
99 ranges = <0 0x8100 0x1a8>;
100 interrupt-parent = <&ipic>;
101 interrupts = <71 8>;
102 cell-index = <0>;
103 dma-channel@0 {
104 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
105 reg = <0 0x80>;
106 interrupt-parent = <&ipic>;
107 interrupts = <71 8>;
108 };
109 dma-channel@80 {
110 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
111 reg = <0x80 0x80>;
112 interrupt-parent = <&ipic>;
113 interrupts = <71 8>;
114 };
115 dma-channel@100 {
116 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
117 reg = <0x100 0x80>;
118 interrupt-parent = <&ipic>;
119 interrupts = <71 8>;
120 };
121 dma-channel@180 {
122 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
123 reg = <0x180 0x28>;
124 interrupt-parent = <&ipic>;
125 interrupts = <71 8>;
126 };
127 };
128
94 usb@23000 { 129 usb@23000 {
95 compatible = "fsl-usb2-dr"; 130 compatible = "fsl-usb2-dr";
96 reg = <0x23000 0x1000>; 131 reg = <0x23000 0x1000>;
@@ -151,16 +186,14 @@
151 }; 186 };
152 187
153 crypto@30000 { 188 crypto@30000 {
154 device_type = "crypto"; 189 compatible = "fsl,sec2.0";
155 model = "SEC2";
156 compatible = "talitos";
157 reg = <0x30000 0x10000>; 190 reg = <0x30000 0x10000>;
158 interrupts = <11 0x8>; 191 interrupts = <11 0x8>;
159 interrupt-parent = <&ipic>; 192 interrupt-parent = <&ipic>;
160 num-channels = <4>; 193 fsl,num-channels = <4>;
161 channel-fifo-len = <24>; 194 fsl,channel-fifo-len = <24>;
162 exec-units-mask = <0x0000007e>; 195 fsl,exec-units-mask = <0x7e>;
163 descriptor-types-mask = <0x01010ebf>; 196 fsl,descriptor-types-mask = <0x01010ebf>;
164 }; 197 };
165 198
166 ipic: pic@700 { 199 ipic: pic@700 {
diff --git a/arch/powerpc/boot/dts/mpc834x_mds.dts b/arch/powerpc/boot/dts/mpc834x_mds.dts
index 0199c5c548d8..ba586cb7afbb 100644
--- a/arch/powerpc/boot/dts/mpc834x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc834x_mds.dts
@@ -103,6 +103,41 @@
103 mode = "cpu"; 103 mode = "cpu";
104 }; 104 };
105 105
106 dma@82a8 {
107 #address-cells = <1>;
108 #size-cells = <1>;
109 compatible = "fsl,mpc8349-dma", "fsl,elo-dma";
110 reg = <0x82a8 4>;
111 ranges = <0 0x8100 0x1a8>;
112 interrupt-parent = <&ipic>;
113 interrupts = <71 8>;
114 cell-index = <0>;
115 dma-channel@0 {
116 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
117 reg = <0 0x80>;
118 interrupt-parent = <&ipic>;
119 interrupts = <71 8>;
120 };
121 dma-channel@80 {
122 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
123 reg = <0x80 0x80>;
124 interrupt-parent = <&ipic>;
125 interrupts = <71 8>;
126 };
127 dma-channel@100 {
128 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
129 reg = <0x100 0x80>;
130 interrupt-parent = <&ipic>;
131 interrupts = <71 8>;
132 };
133 dma-channel@180 {
134 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
135 reg = <0x180 0x28>;
136 interrupt-parent = <&ipic>;
137 interrupts = <71 8>;
138 };
139 };
140
106 /* phy type (ULPI or SERIAL) are only types supported for MPH */ 141 /* phy type (ULPI or SERIAL) are only types supported for MPH */
107 /* port = 0 or 1 */ 142 /* port = 0 or 1 */
108 usb@22000 { 143 usb@22000 {
@@ -193,20 +228,15 @@
193 interrupt-parent = <&ipic>; 228 interrupt-parent = <&ipic>;
194 }; 229 };
195 230
196 /* May need to remove if on a part without crypto engine */
197 crypto@30000 { 231 crypto@30000 {
198 device_type = "crypto"; 232 compatible = "fsl,sec2.0";
199 model = "SEC2";
200 compatible = "talitos";
201 reg = <0x30000 0x10000>; 233 reg = <0x30000 0x10000>;
202 interrupts = <11 0x8>; 234 interrupts = <11 0x8>;
203 interrupt-parent = <&ipic>; 235 interrupt-parent = <&ipic>;
204 num-channels = <4>; 236 fsl,num-channels = <4>;
205 channel-fifo-len = <24>; 237 fsl,channel-fifo-len = <24>;
206 exec-units-mask = <0x0000007e>; 238 fsl,exec-units-mask = <0x7e>;
207 /* desc mask is for rev2.0, 239 fsl,descriptor-types-mask = <0x01010ebf>;
208 * we need runtime fixup for >2.0 */
209 descriptor-types-mask = <0x01010ebf>;
210 }; 240 };
211 241
212 /* IPIC 242 /* IPIC
diff --git a/arch/powerpc/boot/dts/mpc836x_mds.dts b/arch/powerpc/boot/dts/mpc836x_mds.dts
index 8160ff24e87e..3701dae1ee02 100644
--- a/arch/powerpc/boot/dts/mpc836x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc836x_mds.dts
@@ -118,18 +118,50 @@
118 interrupt-parent = <&ipic>; 118 interrupt-parent = <&ipic>;
119 }; 119 };
120 120
121 dma@82a8 {
122 #address-cells = <1>;
123 #size-cells = <1>;
124 compatible = "fsl,mpc8360-dma", "fsl,elo-dma";
125 reg = <0x82a8 4>;
126 ranges = <0 0x8100 0x1a8>;
127 interrupt-parent = <&ipic>;
128 interrupts = <71 8>;
129 cell-index = <0>;
130 dma-channel@0 {
131 compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
132 reg = <0 0x80>;
133 interrupt-parent = <&ipic>;
134 interrupts = <71 8>;
135 };
136 dma-channel@80 {
137 compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
138 reg = <0x80 0x80>;
139 interrupt-parent = <&ipic>;
140 interrupts = <71 8>;
141 };
142 dma-channel@100 {
143 compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
144 reg = <0x100 0x80>;
145 interrupt-parent = <&ipic>;
146 interrupts = <71 8>;
147 };
148 dma-channel@180 {
149 compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
150 reg = <0x180 0x28>;
151 interrupt-parent = <&ipic>;
152 interrupts = <71 8>;
153 };
154 };
155
121 crypto@30000 { 156 crypto@30000 {
122 device_type = "crypto"; 157 compatible = "fsl,sec2.0";
123 model = "SEC2";
124 compatible = "talitos";
125 reg = <0x30000 0x10000>; 158 reg = <0x30000 0x10000>;
126 interrupts = <11 0x8>; 159 interrupts = <11 0x8>;
127 interrupt-parent = <&ipic>; 160 interrupt-parent = <&ipic>;
128 num-channels = <4>; 161 fsl,num-channels = <4>;
129 channel-fifo-len = <24>; 162 fsl,channel-fifo-len = <24>;
130 exec-units-mask = <0x0000007e>; 163 fsl,exec-units-mask = <0x7e>;
131 /* desc mask is for rev1.x, we need runtime fixup for >=2.x */ 164 fsl,descriptor-types-mask = <0x01010ebf>;
132 descriptor-types-mask = <0x01010ebf>;
133 }; 165 };
134 166
135 ipic: pic@700 { 167 ipic: pic@700 {
diff --git a/arch/powerpc/boot/dts/mpc836x_rdk.dts b/arch/powerpc/boot/dts/mpc836x_rdk.dts
new file mode 100644
index 000000000000..8acd1d6577f2
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc836x_rdk.dts
@@ -0,0 +1,432 @@
1/*
2 * MPC8360E RDK Device Tree Source
3 *
4 * Copyright 2006 Freescale Semiconductor Inc.
5 * Copyright 2007-2008 MontaVista Software, Inc.
6 *
7 * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14
15/dts-v1/;
16
17/ {
18 #address-cells = <1>;
19 #size-cells = <1>;
20 compatible = "fsl,mpc8360rdk";
21
22 aliases {
23 serial0 = &serial0;
24 serial1 = &serial1;
25 serial2 = &serial2;
26 serial3 = &serial3;
27 ethernet0 = &enet0;
28 ethernet1 = &enet1;
29 ethernet2 = &enet2;
30 ethernet3 = &enet3;
31 pci0 = &pci0;
32 };
33
34 cpus {
35 #address-cells = <1>;
36 #size-cells = <0>;
37
38 PowerPC,8360@0 {
39 device_type = "cpu";
40 reg = <0>;
41 d-cache-line-size = <32>;
42 i-cache-line-size = <32>;
43 d-cache-size = <32768>;
44 i-cache-size = <32768>;
45 /* filled by u-boot */
46 timebase-frequency = <0>;
47 bus-frequency = <0>;
48 clock-frequency = <0>;
49 };
50 };
51
52 memory {
53 device_type = "memory";
54 /* filled by u-boot */
55 reg = <0 0>;
56 };
57
58 soc@e0000000 {
59 #address-cells = <1>;
60 #size-cells = <1>;
61 device_type = "soc";
62 compatible = "fsl,mpc8360-immr", "fsl,immr", "fsl,soc",
63 "simple-bus";
64 ranges = <0 0xe0000000 0x200000>;
65 reg = <0xe0000000 0x200>;
66 /* filled by u-boot */
67 bus-frequency = <0>;
68
69 wdt@200 {
70 compatible = "mpc83xx_wdt";
71 reg = <0x200 0x100>;
72 };
73
74 i2c@3000 {
75 #address-cells = <1>;
76 #size-cells = <0>;
77 cell-index = <0>;
78 compatible = "fsl-i2c";
79 reg = <0x3000 0x100>;
80 interrupts = <14 8>;
81 interrupt-parent = <&ipic>;
82 dfsrr;
83 };
84
85 i2c@3100 {
86 #address-cells = <1>;
87 #size-cells = <0>;
88 cell-index = <1>;
89 compatible = "fsl-i2c";
90 reg = <0x3100 0x100>;
91 interrupts = <16 8>;
92 interrupt-parent = <&ipic>;
93 dfsrr;
94 };
95
96 serial0: serial@4500 {
97 device_type = "serial";
98 compatible = "ns16550";
99 reg = <0x4500 0x100>;
100 interrupts = <9 8>;
101 interrupt-parent = <&ipic>;
102 /* filled by u-boot */
103 clock-frequency = <0>;
104 };
105
106 serial1: serial@4600 {
107 device_type = "serial";
108 compatible = "ns16550";
109 reg = <0x4600 0x100>;
110 interrupts = <10 8>;
111 interrupt-parent = <&ipic>;
112 /* filled by u-boot */
113 clock-frequency = <0>;
114 };
115
116 dma@82a8 {
117 #address-cells = <1>;
118 #size-cells = <1>;
119 compatible = "fsl,mpc8360-dma", "fsl,elo-dma";
120 reg = <0x82a8 4>;
121 ranges = <0 0x8100 0x1a8>;
122 interrupt-parent = <&ipic>;
123 interrupts = <71 8>;
124 cell-index = <0>;
125 dma-channel@0 {
126 compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
127 reg = <0 0x80>;
128 interrupt-parent = <&ipic>;
129 interrupts = <71 8>;
130 };
131 dma-channel@80 {
132 compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
133 reg = <0x80 0x80>;
134 interrupt-parent = <&ipic>;
135 interrupts = <71 8>;
136 };
137 dma-channel@100 {
138 compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
139 reg = <0x100 0x80>;
140 interrupt-parent = <&ipic>;
141 interrupts = <71 8>;
142 };
143 dma-channel@180 {
144 compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
145 reg = <0x180 0x28>;
146 interrupt-parent = <&ipic>;
147 interrupts = <71 8>;
148 };
149 };
150
151 crypto@30000 {
152 compatible = "fsl,sec2-crypto";
153 reg = <0x30000 0x10000>;
154 interrupts = <11 8>;
155 interrupt-parent = <&ipic>;
156 num-channels = <4>;
157 channel-fifo-len = <24>;
158 exec-units-mask = <0x7e>;
159 /*
160 * desc mask is for rev1.x, we need runtime fixup
161 * for >=2.x
162 */
163 descriptor-types-mask = <0x1010ebf>;
164 };
165
166 ipic: interrupt-controller@700 {
167 #address-cells = <0>;
168 #interrupt-cells = <2>;
169 compatible = "fsl,pq2pro-pic", "fsl,ipic";
170 interrupt-controller;
171 reg = <0x700 0x100>;
172 };
173
174 qe_pio_b: gpio-controller@1418 {
175 #gpio-cells = <2>;
176 compatible = "fsl,mpc8360-qe-pario-bank",
177 "fsl,mpc8323-qe-pario-bank";
178 reg = <0x1418 0x18>;
179 gpio-controller;
180 };
181
182 qe_pio_e: gpio-controller@1460 {
183 #gpio-cells = <2>;
184 compatible = "fsl,mpc8360-qe-pario-bank",
185 "fsl,mpc8323-qe-pario-bank";
186 reg = <0x1460 0x18>;
187 gpio-controller;
188 };
189
190 qe@100000 {
191 #address-cells = <1>;
192 #size-cells = <1>;
193 device_type = "qe";
194 compatible = "fsl,qe", "simple-bus";
195 ranges = <0 0x100000 0x100000>;
196 reg = <0x100000 0x480>;
197 /* filled by u-boot */
198 clock-frequency = <0>;
199 bus-frequency = <0>;
200 brg-frequency = <0>;
201
202 muram@10000 {
203 #address-cells = <1>;
204 #size-cells = <1>;
205 compatible = "fsl,qe-muram", "fsl,cpm-muram";
206 ranges = <0 0x10000 0xc000>;
207
208 data-only@0 {
209 compatible = "fsl,qe-muram-data",
210 "fsl,cpm-muram-data";
211 reg = <0 0xc000>;
212 };
213 };
214
215 timer@440 {
216 compatible = "fsl,mpc8360-qe-gtm",
217 "fsl,qe-gtm", "fsl,gtm";
218 reg = <0x440 0x40>;
219 interrupts = <12 13 14 15>;
220 interrupt-parent = <&qeic>;
221 /* filled by u-boot */
222 clock-frequency = <0>;
223 };
224
225 spi@4c0 {
226 cell-index = <0>;
227 compatible = "fsl,spi";
228 reg = <0x4c0 0x40>;
229 interrupts = <2>;
230 interrupt-parent = <&qeic>;
231 mode = "cpu-qe";
232 };
233
234 spi@500 {
235 cell-index = <1>;
236 compatible = "fsl,spi";
237 reg = <0x500 0x40>;
238 interrupts = <1>;
239 interrupt-parent = <&qeic>;
240 mode = "cpu-qe";
241 };
242
243 enet0: ucc@2000 {
244 device_type = "network";
245 compatible = "ucc_geth";
246 cell-index = <1>;
247 reg = <0x2000 0x200>;
248 interrupts = <32>;
249 interrupt-parent = <&qeic>;
250 rx-clock-name = "none";
251 tx-clock-name = "clk9";
252 phy-handle = <&phy2>;
253 phy-connection-type = "rgmii-rxid";
254 /* filled by u-boot */
255 local-mac-address = [ 00 00 00 00 00 00 ];
256 };
257
258 enet1: ucc@3000 {
259 device_type = "network";
260 compatible = "ucc_geth";
261 cell-index = <2>;
262 reg = <0x3000 0x200>;
263 interrupts = <33>;
264 interrupt-parent = <&qeic>;
265 rx-clock-name = "none";
266 tx-clock-name = "clk4";
267 phy-handle = <&phy4>;
268 phy-connection-type = "rgmii-rxid";
269 /* filled by u-boot */
270 local-mac-address = [ 00 00 00 00 00 00 ];
271 };
272
273 enet2: ucc@2600 {
274 device_type = "network";
275 compatible = "ucc_geth";
276 cell-index = <7>;
277 reg = <0x2600 0x200>;
278 interrupts = <42>;
279 interrupt-parent = <&qeic>;
280 rx-clock-name = "clk20";
281 tx-clock-name = "clk19";
282 phy-handle = <&phy1>;
283 phy-connection-type = "mii";
284 /* filled by u-boot */
285 local-mac-address = [ 00 00 00 00 00 00 ];
286 };
287
288 enet3: ucc@3200 {
289 device_type = "network";
290 compatible = "ucc_geth";
291 cell-index = <4>;
292 reg = <0x3200 0x200>;
293 interrupts = <35>;
294 interrupt-parent = <&qeic>;
295 rx-clock-name = "clk8";
296 tx-clock-name = "clk7";
297 phy-handle = <&phy3>;
298 phy-connection-type = "mii";
299 /* filled by u-boot */
300 local-mac-address = [ 00 00 00 00 00 00 ];
301 };
302
303 mdio@2120 {
304 #address-cells = <1>;
305 #size-cells = <0>;
306 compatible = "fsl,ucc-mdio";
307 reg = <0x2120 0x18>;
308
309 phy1: ethernet-phy@1 {
310 device_type = "ethernet-phy";
311 compatible = "national,DP83848VV";
312 reg = <1>;
313 };
314
315 phy2: ethernet-phy@2 {
316 device_type = "ethernet-phy";
317 compatible = "broadcom,BCM5481UA2KMLG";
318 reg = <2>;
319 };
320
321 phy3: ethernet-phy@3 {
322 device_type = "ethernet-phy";
323 compatible = "national,DP83848VV";
324 reg = <3>;
325 };
326
327 phy4: ethernet-phy@4 {
328 device_type = "ethernet-phy";
329 compatible = "broadcom,BCM5481UA2KMLG";
330 reg = <4>;
331 };
332 };
333
334 serial2: ucc@2400 {
335 device_type = "serial";
336 compatible = "ucc_uart";
337 reg = <0x2400 0x200>;
338 cell-index = <5>;
339 port-number = <0>;
340 rx-clock-name = "brg7";
341 tx-clock-name = "brg8";
342 interrupts = <40>;
343 interrupt-parent = <&qeic>;
344 soft-uart;
345 };
346
347 serial3: ucc@3400 {
348 device_type = "serial";
349 compatible = "ucc_uart";
350 reg = <0x3400 0x200>;
351 cell-index = <6>;
352 port-number = <1>;
353 rx-clock-name = "brg13";
354 tx-clock-name = "brg14";
355 interrupts = <41>;
356 interrupt-parent = <&qeic>;
357 soft-uart;
358 };
359
360 qeic: interrupt-controller@80 {
361 #address-cells = <0>;
362 #interrupt-cells = <1>;
363 compatible = "fsl,qe-ic";
364 interrupt-controller;
365 reg = <0x80 0x80>;
366 big-endian;
367 interrupts = <32 8 33 8>;
368 interrupt-parent = <&ipic>;
369 };
370 };
371 };
372
373 localbus@e0005000 {
374 #address-cells = <2>;
375 #size-cells = <1>;
376 compatible = "fsl,mpc8360-localbus", "fsl,pq2pro-localbus",
377 "simple-bus";
378 reg = <0xe0005000 0xd8>;
379 ranges = <0 0 0xff800000 0x0800000
380 1 0 0x60000000 0x0001000
381 2 0 0x70000000 0x4000000>;
382
383 flash@0,0 {
384 compatible = "intel,PC28F640P30T85", "cfi-flash";
385 reg = <0 0 0x800000>;
386 bank-width = <2>;
387 device-width = <1>;
388 };
389
390 display@2,0 {
391 device_type = "display";
392 compatible = "fujitsu,MB86277", "fujitsu,mint";
393 reg = <2 0 0x4000000>;
394 fujitsu,sh3;
395 little-endian;
396 /* filled by u-boot */
397 address = <0>;
398 depth = <0>;
399 width = <0>;
400 height = <0>;
401 linebytes = <0>;
402 /* linux,opened; - added by uboot */
403 };
404 };
405
406 pci0: pci@e0008500 {
407 #address-cells = <3>;
408 #size-cells = <2>;
409 #interrupt-cells = <1>;
410 device_type = "pci";
411 compatible = "fsl,mpc8360-pci", "fsl,mpc8349-pci";
412 reg = <0xe0008500 0x100>;
413 ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000
414 0x42000000 0 0x80000000 0x80000000 0 0x10000000
415 0x01000000 0 0xe0300000 0xe0300000 0 0x00100000>;
416 interrupts = <66 8>;
417 interrupt-parent = <&ipic>;
418 interrupt-map-mask = <0xf800 0 0 7>;
419 interrupt-map = </* miniPCI0 IDSEL 0x14 AD20 */
420 0xa000 0 0 1 &ipic 18 8
421 0xa000 0 0 2 &ipic 19 8
422
423 /* PCI1 IDSEL 0x15 AD21 */
424 0xa800 0 0 1 &ipic 19 8
425 0xa800 0 0 2 &ipic 20 8
426 0xa800 0 0 3 &ipic 21 8
427 0xa800 0 0 4 &ipic 18 8>;
428 /* filled by u-boot */
429 bus-range = <0 0>;
430 clock-frequency = <0>;
431 };
432};
diff --git a/arch/powerpc/boot/dts/mpc8377_mds.dts b/arch/powerpc/boot/dts/mpc8377_mds.dts
index fea592574004..0a700cb5f611 100644
--- a/arch/powerpc/boot/dts/mpc8377_mds.dts
+++ b/arch/powerpc/boot/dts/mpc8377_mds.dts
@@ -233,41 +233,6 @@
233 interrupt-parent = <&ipic>; 233 interrupt-parent = <&ipic>;
234 }; 234 };
235 235
236 crypto@30000 {
237 model = "SEC3";
238 compatible = "talitos";
239 reg = <0x30000 0x10000>;
240 interrupts = <11 0x8>;
241 interrupt-parent = <&ipic>;
242 /* Rev. 3.0 geometry */
243 num-channels = <4>;
244 channel-fifo-len = <24>;
245 exec-units-mask = <0x000001fe>;
246 descriptor-types-mask = <0x03ab0ebf>;
247 };
248
249 sdhc@2e000 {
250 model = "eSDHC";
251 compatible = "fsl,esdhc";
252 reg = <0x2e000 0x1000>;
253 interrupts = <42 0x8>;
254 interrupt-parent = <&ipic>;
255 };
256
257 sata@18000 {
258 compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
259 reg = <0x18000 0x1000>;
260 interrupts = <44 0x8>;
261 interrupt-parent = <&ipic>;
262 };
263
264 sata@19000 {
265 compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
266 reg = <0x19000 0x1000>;
267 interrupts = <45 0x8>;
268 interrupt-parent = <&ipic>;
269 };
270
271 dma@82a8 { 236 dma@82a8 {
272 #address-cells = <1>; 237 #address-cells = <1>;
273 #size-cells = <1>; 238 #size-cells = <1>;
@@ -303,6 +268,40 @@
303 }; 268 };
304 }; 269 };
305 270
271 crypto@30000 {
272 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
273 "fsl,sec2.1", "fsl,sec2.0";
274 reg = <0x30000 0x10000>;
275 interrupts = <11 0x8>;
276 interrupt-parent = <&ipic>;
277 fsl,num-channels = <4>;
278 fsl,channel-fifo-len = <24>;
279 fsl,exec-units-mask = <0x9fe>;
280 fsl,descriptor-types-mask = <0x3ab0ebf>;
281 };
282
283 sdhc@2e000 {
284 model = "eSDHC";
285 compatible = "fsl,esdhc";
286 reg = <0x2e000 0x1000>;
287 interrupts = <42 0x8>;
288 interrupt-parent = <&ipic>;
289 };
290
291 sata@18000 {
292 compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
293 reg = <0x18000 0x1000>;
294 interrupts = <44 0x8>;
295 interrupt-parent = <&ipic>;
296 };
297
298 sata@19000 {
299 compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
300 reg = <0x19000 0x1000>;
301 interrupts = <45 0x8>;
302 interrupt-parent = <&ipic>;
303 };
304
306 /* IPIC 305 /* IPIC
307 * interrupts cell = <intr #, sense> 306 * interrupts cell = <intr #, sense>
308 * sense values match linux IORESOURCE_IRQ_* defines: 307 * sense values match linux IORESOURCE_IRQ_* defines:
diff --git a/arch/powerpc/boot/dts/mpc8377_rdb.dts b/arch/powerpc/boot/dts/mpc8377_rdb.dts
index f3083c779b66..ed137aa83d5f 100644
--- a/arch/powerpc/boot/dts/mpc8377_rdb.dts
+++ b/arch/powerpc/boot/dts/mpc8377_rdb.dts
@@ -143,6 +143,41 @@
143 mode = "cpu"; 143 mode = "cpu";
144 }; 144 };
145 145
146 dma@82a8 {
147 #address-cells = <1>;
148 #size-cells = <1>;
149 compatible = "fsl,mpc8377-dma", "fsl,elo-dma";
150 reg = <0x82a8 4>;
151 ranges = <0 0x8100 0x1a8>;
152 interrupt-parent = <&ipic>;
153 interrupts = <71 8>;
154 cell-index = <0>;
155 dma-channel@0 {
156 compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
157 reg = <0 0x80>;
158 interrupt-parent = <&ipic>;
159 interrupts = <71 8>;
160 };
161 dma-channel@80 {
162 compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
163 reg = <0x80 0x80>;
164 interrupt-parent = <&ipic>;
165 interrupts = <71 8>;
166 };
167 dma-channel@100 {
168 compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
169 reg = <0x100 0x80>;
170 interrupt-parent = <&ipic>;
171 interrupts = <71 8>;
172 };
173 dma-channel@180 {
174 compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
175 reg = <0x180 0x28>;
176 interrupt-parent = <&ipic>;
177 interrupts = <71 8>;
178 };
179 };
180
146 usb@23000 { 181 usb@23000 {
147 compatible = "fsl-usb2-dr"; 182 compatible = "fsl-usb2-dr";
148 reg = <0x23000 0x1000>; 183 reg = <0x23000 0x1000>;
@@ -213,17 +248,15 @@
213 }; 248 };
214 249
215 crypto@30000 { 250 crypto@30000 {
216 model = "SEC3"; 251 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
217 device_type = "crypto"; 252 "fsl,sec2.1", "fsl,sec2.0";
218 compatible = "talitos";
219 reg = <0x30000 0x10000>; 253 reg = <0x30000 0x10000>;
220 interrupts = <11 0x8>; 254 interrupts = <11 0x8>;
221 interrupt-parent = <&ipic>; 255 interrupt-parent = <&ipic>;
222 /* Rev. 3.0 geometry */ 256 fsl,num-channels = <4>;
223 num-channels = <4>; 257 fsl,channel-fifo-len = <24>;
224 channel-fifo-len = <24>; 258 fsl,exec-units-mask = <0x9fe>;
225 exec-units-mask = <0x000001fe>; 259 fsl,descriptor-types-mask = <0x3ab0ebf>;
226 descriptor-types-mask = <0x03ab0ebf>;
227 }; 260 };
228 261
229 sata@18000 { 262 sata@18000 {
diff --git a/arch/powerpc/boot/dts/mpc8378_mds.dts b/arch/powerpc/boot/dts/mpc8378_mds.dts
index 1d6ea080ad73..29c8c76a58f7 100644
--- a/arch/powerpc/boot/dts/mpc8378_mds.dts
+++ b/arch/powerpc/boot/dts/mpc8378_mds.dts
@@ -157,6 +157,41 @@
157 mode = "cpu"; 157 mode = "cpu";
158 }; 158 };
159 159
160 dma@82a8 {
161 #address-cells = <1>;
162 #size-cells = <1>;
163 compatible = "fsl,mpc8378-dma", "fsl,elo-dma";
164 reg = <0x82a8 4>;
165 ranges = <0 0x8100 0x1a8>;
166 interrupt-parent = <&ipic>;
167 interrupts = <71 8>;
168 cell-index = <0>;
169 dma-channel@0 {
170 compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
171 reg = <0 0x80>;
172 interrupt-parent = <&ipic>;
173 interrupts = <71 8>;
174 };
175 dma-channel@80 {
176 compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
177 reg = <0x80 0x80>;
178 interrupt-parent = <&ipic>;
179 interrupts = <71 8>;
180 };
181 dma-channel@100 {
182 compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
183 reg = <0x100 0x80>;
184 interrupt-parent = <&ipic>;
185 interrupts = <71 8>;
186 };
187 dma-channel@180 {
188 compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
189 reg = <0x180 0x28>;
190 interrupt-parent = <&ipic>;
191 interrupts = <71 8>;
192 };
193 };
194
160 usb@23000 { 195 usb@23000 {
161 compatible = "fsl-usb2-dr"; 196 compatible = "fsl-usb2-dr";
162 reg = <0x23000 0x1000>; 197 reg = <0x23000 0x1000>;
@@ -234,16 +269,15 @@
234 }; 269 };
235 270
236 crypto@30000 { 271 crypto@30000 {
237 model = "SEC3"; 272 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
238 compatible = "talitos"; 273 "fsl,sec2.1", "fsl,sec2.0";
239 reg = <0x30000 0x10000>; 274 reg = <0x30000 0x10000>;
240 interrupts = <11 0x8>; 275 interrupts = <11 0x8>;
241 interrupt-parent = <&ipic>; 276 interrupt-parent = <&ipic>;
242 /* Rev. 3.0 geometry */ 277 fsl,num-channels = <4>;
243 num-channels = <4>; 278 fsl,channel-fifo-len = <24>;
244 channel-fifo-len = <24>; 279 fsl,exec-units-mask = <0x9fe>;
245 exec-units-mask = <0x000001fe>; 280 fsl,descriptor-types-mask = <0x3ab0ebf>;
246 descriptor-types-mask = <0x03ab0ebf>;
247 }; 281 };
248 282
249 sdhc@2e000 { 283 sdhc@2e000 {
diff --git a/arch/powerpc/boot/dts/mpc8378_rdb.dts b/arch/powerpc/boot/dts/mpc8378_rdb.dts
index 0e872a60e091..34a7f2f935e1 100644
--- a/arch/powerpc/boot/dts/mpc8378_rdb.dts
+++ b/arch/powerpc/boot/dts/mpc8378_rdb.dts
@@ -143,6 +143,41 @@
143 mode = "cpu"; 143 mode = "cpu";
144 }; 144 };
145 145
146 dma@82a8 {
147 #address-cells = <1>;
148 #size-cells = <1>;
149 compatible = "fsl,mpc8378-dma", "fsl,elo-dma";
150 reg = <0x82a8 4>;
151 ranges = <0 0x8100 0x1a8>;
152 interrupt-parent = <&ipic>;
153 interrupts = <71 8>;
154 cell-index = <0>;
155 dma-channel@0 {
156 compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
157 reg = <0 0x80>;
158 interrupt-parent = <&ipic>;
159 interrupts = <71 8>;
160 };
161 dma-channel@80 {
162 compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
163 reg = <0x80 0x80>;
164 interrupt-parent = <&ipic>;
165 interrupts = <71 8>;
166 };
167 dma-channel@100 {
168 compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
169 reg = <0x100 0x80>;
170 interrupt-parent = <&ipic>;
171 interrupts = <71 8>;
172 };
173 dma-channel@180 {
174 compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
175 reg = <0x180 0x28>;
176 interrupt-parent = <&ipic>;
177 interrupts = <71 8>;
178 };
179 };
180
146 usb@23000 { 181 usb@23000 {
147 compatible = "fsl-usb2-dr"; 182 compatible = "fsl-usb2-dr";
148 reg = <0x23000 0x1000>; 183 reg = <0x23000 0x1000>;
@@ -213,17 +248,15 @@
213 }; 248 };
214 249
215 crypto@30000 { 250 crypto@30000 {
216 model = "SEC3"; 251 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
217 device_type = "crypto"; 252 "fsl,sec2.1", "fsl,sec2.0";
218 compatible = "talitos";
219 reg = <0x30000 0x10000>; 253 reg = <0x30000 0x10000>;
220 interrupts = <11 0x8>; 254 interrupts = <11 0x8>;
221 interrupt-parent = <&ipic>; 255 interrupt-parent = <&ipic>;
222 /* Rev. 3.0 geometry */ 256 fsl,num-channels = <4>;
223 num-channels = <4>; 257 fsl,channel-fifo-len = <24>;
224 channel-fifo-len = <24>; 258 fsl,exec-units-mask = <0x9fe>;
225 exec-units-mask = <0x000001fe>; 259 fsl,descriptor-types-mask = <0x3ab0ebf>;
226 descriptor-types-mask = <0x03ab0ebf>;
227 }; 260 };
228 261
229 /* IPIC 262 /* IPIC
diff --git a/arch/powerpc/boot/dts/mpc8379_mds.dts b/arch/powerpc/boot/dts/mpc8379_mds.dts
index 6f78a9fd9826..d641a8985ea3 100644
--- a/arch/powerpc/boot/dts/mpc8379_mds.dts
+++ b/arch/powerpc/boot/dts/mpc8379_mds.dts
@@ -157,6 +157,41 @@
157 mode = "cpu"; 157 mode = "cpu";
158 }; 158 };
159 159
160 dma@82a8 {
161 #address-cells = <1>;
162 #size-cells = <1>;
163 compatible = "fsl,mpc8379-dma", "fsl,elo-dma";
164 reg = <0x82a8 4>;
165 ranges = <0 0x8100 0x1a8>;
166 interrupt-parent = <&ipic>;
167 interrupts = <71 8>;
168 cell-index = <0>;
169 dma-channel@0 {
170 compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel";
171 reg = <0 0x80>;
172 interrupt-parent = <&ipic>;
173 interrupts = <71 8>;
174 };
175 dma-channel@80 {
176 compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel";
177 reg = <0x80 0x80>;
178 interrupt-parent = <&ipic>;
179 interrupts = <71 8>;
180 };
181 dma-channel@100 {
182 compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel";
183 reg = <0x100 0x80>;
184 interrupt-parent = <&ipic>;
185 interrupts = <71 8>;
186 };
187 dma-channel@180 {
188 compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel";
189 reg = <0x180 0x28>;
190 interrupt-parent = <&ipic>;
191 interrupts = <71 8>;
192 };
193 };
194
160 usb@23000 { 195 usb@23000 {
161 compatible = "fsl-usb2-dr"; 196 compatible = "fsl-usb2-dr";
162 reg = <0x23000 0x1000>; 197 reg = <0x23000 0x1000>;
@@ -234,16 +269,15 @@
234 }; 269 };
235 270
236 crypto@30000 { 271 crypto@30000 {
237 model = "SEC3"; 272 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
238 compatible = "talitos"; 273 "fsl,sec2.1", "fsl,sec2.0";
239 reg = <0x30000 0x10000>; 274 reg = <0x30000 0x10000>;
240 interrupts = <11 0x8>; 275 interrupts = <11 0x8>;
241 interrupt-parent = <&ipic>; 276 interrupt-parent = <&ipic>;
242 /* Rev. 3.0 geometry */ 277 fsl,num-channels = <4>;
243 num-channels = <4>; 278 fsl,channel-fifo-len = <24>;
244 channel-fifo-len = <24>; 279 fsl,exec-units-mask = <0x9fe>;
245 exec-units-mask = <0x000001fe>; 280 fsl,descriptor-types-mask = <0x3ab0ebf>;
246 descriptor-types-mask = <0x03ab0ebf>;
247 }; 281 };
248 282
249 sdhc@2e000 { 283 sdhc@2e000 {
diff --git a/arch/powerpc/boot/dts/mpc8379_rdb.dts b/arch/powerpc/boot/dts/mpc8379_rdb.dts
index 1eb8defaff6f..e4d7030d50e5 100644
--- a/arch/powerpc/boot/dts/mpc8379_rdb.dts
+++ b/arch/powerpc/boot/dts/mpc8379_rdb.dts
@@ -143,6 +143,41 @@
143 mode = "cpu"; 143 mode = "cpu";
144 }; 144 };
145 145
146 dma@82a8 {
147 #address-cells = <1>;
148 #size-cells = <1>;
149 compatible = "fsl,mpc8379-dma", "fsl,elo-dma";
150 reg = <0x82a8 4>;
151 ranges = <0 0x8100 0x1a8>;
152 interrupt-parent = <&ipic>;
153 interrupts = <71 8>;
154 cell-index = <0>;
155 dma-channel@0 {
156 compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel";
157 reg = <0 0x80>;
158 interrupt-parent = <&ipic>;
159 interrupts = <71 8>;
160 };
161 dma-channel@80 {
162 compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel";
163 reg = <0x80 0x80>;
164 interrupt-parent = <&ipic>;
165 interrupts = <71 8>;
166 };
167 dma-channel@100 {
168 compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel";
169 reg = <0x100 0x80>;
170 interrupt-parent = <&ipic>;
171 interrupts = <71 8>;
172 };
173 dma-channel@180 {
174 compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel";
175 reg = <0x180 0x28>;
176 interrupt-parent = <&ipic>;
177 interrupts = <71 8>;
178 };
179 };
180
146 usb@23000 { 181 usb@23000 {
147 compatible = "fsl-usb2-dr"; 182 compatible = "fsl-usb2-dr";
148 reg = <0x23000 0x1000>; 183 reg = <0x23000 0x1000>;
@@ -213,17 +248,15 @@
213 }; 248 };
214 249
215 crypto@30000 { 250 crypto@30000 {
216 model = "SEC3"; 251 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
217 device_type = "crypto"; 252 "fsl,sec2.1", "fsl,sec2.0";
218 compatible = "talitos";
219 reg = <0x30000 0x10000>; 253 reg = <0x30000 0x10000>;
220 interrupts = <11 0x8>; 254 interrupts = <11 0x8>;
221 interrupt-parent = <&ipic>; 255 interrupt-parent = <&ipic>;
222 /* Rev. 3.0 geometry */ 256 fsl,num-channels = <4>;
223 num-channels = <4>; 257 fsl,channel-fifo-len = <24>;
224 channel-fifo-len = <24>; 258 fsl,exec-units-mask = <0x9fe>;
225 exec-units-mask = <0x000001fe>; 259 fsl,descriptor-types-mask = <0x3ab0ebf>;
226 descriptor-types-mask = <0x03ab0ebf>;
227 }; 260 };
228 261
229 sata@18000 { 262 sata@18000 {
diff --git a/arch/powerpc/boot/dts/mpc8536ds.dts b/arch/powerpc/boot/dts/mpc8536ds.dts
new file mode 100644
index 000000000000..02cfa24a1695
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc8536ds.dts
@@ -0,0 +1,432 @@
1/*
2 * MPC8536 DS Device Tree Source
3 *
4 * Copyright 2008 Freescale Semiconductor, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/dts-v1/;
13
14/ {
15 model = "fsl,mpc8536ds";
16 compatible = "fsl,mpc8536ds";
17 #address-cells = <1>;
18 #size-cells = <1>;
19
20 aliases {
21 ethernet0 = &enet0;
22 ethernet1 = &enet1;
23 serial0 = &serial0;
24 serial1 = &serial1;
25 pci0 = &pci0;
26 pci1 = &pci1;
27 pci2 = &pci2;
28 pci3 = &pci3;
29 };
30
31 cpus {
32 #cpus = <1>;
33 #address-cells = <1>;
34 #size-cells = <0>;
35
36 PowerPC,8536@0 {
37 device_type = "cpu";
38 reg = <0>;
39 next-level-cache = <&L2>;
40 };
41 };
42
43 memory {
44 device_type = "memory";
45 reg = <00000000 00000000>; // Filled by U-Boot
46 };
47
48 soc@ffe00000 {
49 #address-cells = <1>;
50 #size-cells = <1>;
51 device_type = "soc";
52 ranges = <0x0 0xffe00000 0x100000>;
53 reg = <0xffe00000 0x1000>;
54 bus-frequency = <0>; // Filled out by uboot.
55
56 memory-controller@2000 {
57 compatible = "fsl,mpc8536-memory-controller";
58 reg = <0x2000 0x1000>;
59 interrupt-parent = <&mpic>;
60 interrupts = <18 0x2>;
61 };
62
63 L2: l2-cache-controller@20000 {
64 compatible = "fsl,mpc8536-l2-cache-controller";
65 reg = <0x20000 0x1000>;
66 interrupt-parent = <&mpic>;
67 interrupts = <16 0x2>;
68 };
69
70 i2c@3000 {
71 #address-cells = <1>;
72 #size-cells = <0>;
73 cell-index = <0>;
74 compatible = "fsl-i2c";
75 reg = <0x3000 0x100>;
76 interrupts = <43 0x2>;
77 interrupt-parent = <&mpic>;
78 dfsrr;
79 };
80
81 i2c@3100 {
82 #address-cells = <1>;
83 #size-cells = <0>;
84 cell-index = <1>;
85 compatible = "fsl-i2c";
86 reg = <0x3100 0x100>;
87 interrupts = <43 0x2>;
88 interrupt-parent = <&mpic>;
89 dfsrr;
90 rtc@68 {
91 compatible = "dallas,ds3232";
92 reg = <0x68>;
93 };
94 };
95
96 dma@21300 {
97 #address-cells = <1>;
98 #size-cells = <1>;
99 compatible = "fsl,mpc8536-dma", "fsl,eloplus-dma";
100 reg = <0x21300 4>;
101 ranges = <0 0x21100 0x200>;
102 cell-index = <0>;
103 dma-channel@0 {
104 compatible = "fsl,mpc8536-dma-channel",
105 "fsl,eloplus-dma-channel";
106 reg = <0x0 0x80>;
107 cell-index = <0>;
108 interrupt-parent = <&mpic>;
109 interrupts = <14 0x2>;
110 };
111 dma-channel@80 {
112 compatible = "fsl,mpc8536-dma-channel",
113 "fsl,eloplus-dma-channel";
114 reg = <0x80 0x80>;
115 cell-index = <1>;
116 interrupt-parent = <&mpic>;
117 interrupts = <15 0x2>;
118 };
119 dma-channel@100 {
120 compatible = "fsl,mpc8536-dma-channel",
121 "fsl,eloplus-dma-channel";
122 reg = <0x100 0x80>;
123 cell-index = <2>;
124 interrupt-parent = <&mpic>;
125 interrupts = <16 0x2>;
126 };
127 dma-channel@180 {
128 compatible = "fsl,mpc8536-dma-channel",
129 "fsl,eloplus-dma-channel";
130 reg = <0x180 0x80>;
131 cell-index = <3>;
132 interrupt-parent = <&mpic>;
133 interrupts = <17 0x2>;
134 };
135 };
136
137 mdio@24520 {
138 #address-cells = <1>;
139 #size-cells = <0>;
140 compatible = "fsl,gianfar-mdio";
141 reg = <0x24520 0x20>;
142
143 phy0: ethernet-phy@0 {
144 interrupt-parent = <&mpic>;
145 interrupts = <10 0x1>;
146 reg = <0>;
147 device_type = "ethernet-phy";
148 };
149 phy1: ethernet-phy@1 {
150 interrupt-parent = <&mpic>;
151 interrupts = <10 0x1>;
152 reg = <1>;
153 device_type = "ethernet-phy";
154 };
155 };
156
157 usb@22000 {
158 compatible = "fsl,mpc8536-usb2-mph", "fsl-usb2-mph";
159 reg = <0x22000 0x1000>;
160 #address-cells = <1>;
161 #size-cells = <0>;
162 interrupt-parent = <&mpic>;
163 interrupts = <28 0x2>;
164 phy_type = "ulpi";
165 };
166
167 usb@23000 {
168 compatible = "fsl,mpc8536-usb2-mph", "fsl-usb2-mph";
169 reg = <0x23000 0x1000>;
170 #address-cells = <1>;
171 #size-cells = <0>;
172 interrupt-parent = <&mpic>;
173 interrupts = <46 0x2>;
174 phy_type = "ulpi";
175 };
176
177 enet0: ethernet@24000 {
178 cell-index = <0>;
179 device_type = "network";
180 model = "TSEC";
181 compatible = "gianfar";
182 reg = <0x24000 0x1000>;
183 local-mac-address = [ 00 00 00 00 00 00 ];
184 interrupts = <29 2 30 2 34 2>;
185 interrupt-parent = <&mpic>;
186 phy-handle = <&phy1>;
187 phy-connection-type = "rgmii-id";
188 };
189
190 enet1: ethernet@26000 {
191 cell-index = <1>;
192 device_type = "network";
193 model = "TSEC";
194 compatible = "gianfar";
195 reg = <0x26000 0x1000>;
196 local-mac-address = [ 00 00 00 00 00 00 ];
197 interrupts = <31 2 32 2 33 2>;
198 interrupt-parent = <&mpic>;
199 phy-handle = <&phy0>;
200 phy-connection-type = "rgmii-id";
201 };
202
203 usb@2b000 {
204 compatible = "fsl,mpc8536-usb2-dr", "fsl-usb2-dr";
205 reg = <0x2b000 0x1000>;
206 #address-cells = <1>;
207 #size-cells = <0>;
208 interrupt-parent = <&mpic>;
209 interrupts = <60 0x2>;
210 dr_mode = "peripheral";
211 phy_type = "ulpi";
212 };
213
214 serial0: serial@4500 {
215 cell-index = <0>;
216 device_type = "serial";
217 compatible = "ns16550";
218 reg = <0x4500 0x100>;
219 clock-frequency = <0>;
220 interrupts = <42 0x2>;
221 interrupt-parent = <&mpic>;
222 };
223
224 serial1: serial@4600 {
225 cell-index = <1>;
226 device_type = "serial";
227 compatible = "ns16550";
228 reg = <0x4600 0x100>;
229 clock-frequency = <0>;
230 interrupts = <42 0x2>;
231 interrupt-parent = <&mpic>;
232 };
233
234 crypto@30000 {
235 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
236 "fsl,sec2.1", "fsl,sec2.0";
237 reg = <0x30000 0x10000>;
238 interrupts = <45 2 58 2>;
239 interrupt-parent = <&mpic>;
240 fsl,num-channels = <4>;
241 fsl,channel-fifo-len = <24>;
242 fsl,exec-units-mask = <0x9fe>;
243 fsl,descriptor-types-mask = <0x3ab0ebf>;
244 };
245
246 sata@18000 {
247 compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
248 reg = <0x18000 0x1000>;
249 cell-index = <1>;
250 interrupts = <74 0x2>;
251 interrupt-parent = <&mpic>;
252 };
253
254 sata@19000 {
255 compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
256 reg = <0x19000 0x1000>;
257 cell-index = <2>;
258 interrupts = <41 0x2>;
259 interrupt-parent = <&mpic>;
260 };
261
262 global-utilities@e0000 { //global utilities block
263 compatible = "fsl,mpc8548-guts";
264 reg = <0xe0000 0x1000>;
265 fsl,has-rstcr;
266 };
267
268 mpic: pic@40000 {
269 clock-frequency = <0>;
270 interrupt-controller;
271 #address-cells = <0>;
272 #interrupt-cells = <2>;
273 reg = <0x40000 0x40000>;
274 compatible = "chrp,open-pic";
275 device_type = "open-pic";
276 big-endian;
277 };
278
279 msi@41600 {
280 compatible = "fsl,mpc8536-msi", "fsl,mpic-msi";
281 reg = <0x41600 0x80>;
282 msi-available-ranges = <0 0x100>;
283 interrupts = <
284 0xe0 0
285 0xe1 0
286 0xe2 0
287 0xe3 0
288 0xe4 0
289 0xe5 0
290 0xe6 0
291 0xe7 0>;
292 interrupt-parent = <&mpic>;
293 };
294 };
295
296 pci0: pci@ffe08000 {
297 cell-index = <0>;
298 compatible = "fsl,mpc8540-pci";
299 device_type = "pci";
300 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
301 interrupt-map = <
302
303 /* IDSEL 0x11 J17 Slot 1 */
304 0x8800 0 0 1 &mpic 1 1
305 0x8800 0 0 2 &mpic 2 1
306 0x8800 0 0 3 &mpic 3 1
307 0x8800 0 0 4 &mpic 4 1>;
308
309 interrupt-parent = <&mpic>;
310 interrupts = <24 0x2>;
311 bus-range = <0 0xff>;
312 ranges = <0x02000000 0 0x80000000 0x80000000 0 0x10000000
313 0x01000000 0 0x00000000 0xffc00000 0 0x00010000>;
314 clock-frequency = <66666666>;
315 #interrupt-cells = <1>;
316 #size-cells = <2>;
317 #address-cells = <3>;
318 reg = <0xffe08000 0x1000>;
319 };
320
321 pci1: pcie@ffe09000 {
322 cell-index = <1>;
323 compatible = "fsl,mpc8548-pcie";
324 device_type = "pci";
325 #interrupt-cells = <1>;
326 #size-cells = <2>;
327 #address-cells = <3>;
328 reg = <0xffe09000 0x1000>;
329 bus-range = <0 0xff>;
330 ranges = <0x02000000 0 0x98000000 0x98000000 0 0x08000000
331 0x01000000 0 0x00000000 0xffc20000 0 0x00010000>;
332 clock-frequency = <33333333>;
333 interrupt-parent = <&mpic>;
334 interrupts = <25 0x2>;
335 interrupt-map-mask = <0xf800 0 0 7>;
336 interrupt-map = <
337 /* IDSEL 0x0 */
338 0000 0 0 1 &mpic 4 1
339 0000 0 0 2 &mpic 5 1
340 0000 0 0 3 &mpic 6 1
341 0000 0 0 4 &mpic 7 1
342 >;
343 pcie@0 {
344 reg = <0 0 0 0 0>;
345 #size-cells = <2>;
346 #address-cells = <3>;
347 device_type = "pci";
348 ranges = <0x02000000 0 0x98000000
349 0x02000000 0 0x98000000
350 0 0x08000000
351
352 0x01000000 0 0x00000000
353 0x01000000 0 0x00000000
354 0 0x00010000>;
355 };
356 };
357
358 pci2: pcie@ffe0a000 {
359 cell-index = <2>;
360 compatible = "fsl,mpc8548-pcie";
361 device_type = "pci";
362 #interrupt-cells = <1>;
363 #size-cells = <2>;
364 #address-cells = <3>;
365 reg = <0xffe0a000 0x1000>;
366 bus-range = <0 0xff>;
367 ranges = <0x02000000 0 0x90000000 0x90000000 0 0x08000000
368 0x01000000 0 0x00000000 0xffc10000 0 0x00010000>;
369 clock-frequency = <33333333>;
370 interrupt-parent = <&mpic>;
371 interrupts = <26 0x2>;
372 interrupt-map-mask = <0xf800 0 0 7>;
373 interrupt-map = <
374 /* IDSEL 0x0 */
375 0000 0 0 1 &mpic 0 1
376 0000 0 0 2 &mpic 1 1
377 0000 0 0 3 &mpic 2 1
378 0000 0 0 4 &mpic 3 1
379 >;
380 pcie@0 {
381 reg = <0 0 0 0 0>;
382 #size-cells = <2>;
383 #address-cells = <3>;
384 device_type = "pci";
385 ranges = <0x02000000 0 0x90000000
386 0x02000000 0 0x90000000
387 0 0x08000000
388
389 0x01000000 0 0x00000000
390 0x01000000 0 0x00000000
391 0 0x00010000>;
392 };
393 };
394
395 pci3: pcie@ffe0b000 {
396 cell-index = <3>;
397 compatible = "fsl,mpc8548-pcie";
398 device_type = "pci";
399 #interrupt-cells = <1>;
400 #size-cells = <2>;
401 #address-cells = <3>;
402 reg = <0xffe0b000 0x1000>;
403 bus-range = <0 0xff>;
404 ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x20000000
405 0x01000000 0 0x00000000 0xffc30000 0 0x00010000>;
406 clock-frequency = <33333333>;
407 interrupt-parent = <&mpic>;
408 interrupts = <27 0x2>;
409 interrupt-map-mask = <0xf800 0 0 7>;
410 interrupt-map = <
411 /* IDSEL 0x0 */
412 0000 0 0 1 &mpic 8 1
413 0000 0 0 2 &mpic 9 1
414 0000 0 0 3 &mpic 10 1
415 0000 0 0 4 &mpic 11 1
416 >;
417
418 pcie@0 {
419 reg = <0 0 0 0 0>;
420 #size-cells = <2>;
421 #address-cells = <3>;
422 device_type = "pci";
423 ranges = <0x02000000 0 0xa0000000
424 0x02000000 0 0xa0000000
425 0 0x20000000
426
427 0x01000000 0 0x00000000
428 0x01000000 0 0x00000000
429 0 0x00100000>;
430 };
431 };
432};
diff --git a/arch/powerpc/boot/dts/mpc8540ads.dts b/arch/powerpc/boot/dts/mpc8540ads.dts
index 18033ed0b535..f2273a872b11 100644
--- a/arch/powerpc/boot/dts/mpc8540ads.dts
+++ b/arch/powerpc/boot/dts/mpc8540ads.dts
@@ -40,6 +40,7 @@
40 timebase-frequency = <0>; // 33 MHz, from uboot 40 timebase-frequency = <0>; // 33 MHz, from uboot
41 bus-frequency = <0>; // 166 MHz 41 bus-frequency = <0>; // 166 MHz
42 clock-frequency = <0>; // 825 MHz, from uboot 42 clock-frequency = <0>; // 825 MHz, from uboot
43 next-level-cache = <&L2>;
43 }; 44 };
44 }; 45 };
45 46
@@ -63,7 +64,7 @@
63 interrupts = <18 2>; 64 interrupts = <18 2>;
64 }; 65 };
65 66
66 l2-cache-controller@20000 { 67 L2: l2-cache-controller@20000 {
67 compatible = "fsl,8540-l2-cache-controller"; 68 compatible = "fsl,8540-l2-cache-controller";
68 reg = <0x20000 0x1000>; 69 reg = <0x20000 0x1000>;
69 cache-line-size = <32>; // 32 bytes 70 cache-line-size = <32>; // 32 bytes
@@ -83,6 +84,47 @@
83 dfsrr; 84 dfsrr;
84 }; 85 };
85 86
87 dma@21300 {
88 #address-cells = <1>;
89 #size-cells = <1>;
90 compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma";
91 reg = <0x21300 0x4>;
92 ranges = <0x0 0x21100 0x200>;
93 cell-index = <0>;
94 dma-channel@0 {
95 compatible = "fsl,mpc8540-dma-channel",
96 "fsl,eloplus-dma-channel";
97 reg = <0x0 0x80>;
98 cell-index = <0>;
99 interrupt-parent = <&mpic>;
100 interrupts = <20 2>;
101 };
102 dma-channel@80 {
103 compatible = "fsl,mpc8540-dma-channel",
104 "fsl,eloplus-dma-channel";
105 reg = <0x80 0x80>;
106 cell-index = <1>;
107 interrupt-parent = <&mpic>;
108 interrupts = <21 2>;
109 };
110 dma-channel@100 {
111 compatible = "fsl,mpc8540-dma-channel",
112 "fsl,eloplus-dma-channel";
113 reg = <0x100 0x80>;
114 cell-index = <2>;
115 interrupt-parent = <&mpic>;
116 interrupts = <22 2>;
117 };
118 dma-channel@180 {
119 compatible = "fsl,mpc8540-dma-channel",
120 "fsl,eloplus-dma-channel";
121 reg = <0x180 0x80>;
122 cell-index = <3>;
123 interrupt-parent = <&mpic>;
124 interrupts = <23 2>;
125 };
126 };
127
86 mdio@24520 { 128 mdio@24520 {
87 #address-cells = <1>; 129 #address-cells = <1>;
88 #size-cells = <0>; 130 #size-cells = <0>;
@@ -165,14 +207,12 @@
165 interrupt-parent = <&mpic>; 207 interrupt-parent = <&mpic>;
166 }; 208 };
167 mpic: pic@40000 { 209 mpic: pic@40000 {
168 clock-frequency = <0>;
169 interrupt-controller; 210 interrupt-controller;
170 #address-cells = <0>; 211 #address-cells = <0>;
171 #interrupt-cells = <2>; 212 #interrupt-cells = <2>;
172 reg = <0x40000 0x40000>; 213 reg = <0x40000 0x40000>;
173 compatible = "chrp,open-pic"; 214 compatible = "chrp,open-pic";
174 device_type = "open-pic"; 215 device_type = "open-pic";
175 big-endian;
176 }; 216 };
177 }; 217 };
178 218
diff --git a/arch/powerpc/boot/dts/mpc8541cds.dts b/arch/powerpc/boot/dts/mpc8541cds.dts
index 663c7c50ca45..c4469f19ff82 100644
--- a/arch/powerpc/boot/dts/mpc8541cds.dts
+++ b/arch/powerpc/boot/dts/mpc8541cds.dts
@@ -40,6 +40,7 @@
40 timebase-frequency = <0>; // 33 MHz, from uboot 40 timebase-frequency = <0>; // 33 MHz, from uboot
41 bus-frequency = <0>; // 166 MHz 41 bus-frequency = <0>; // 166 MHz
42 clock-frequency = <0>; // 825 MHz, from uboot 42 clock-frequency = <0>; // 825 MHz, from uboot
43 next-level-cache = <&L2>;
43 }; 44 };
44 }; 45 };
45 46
@@ -63,7 +64,7 @@
63 interrupts = <18 2>; 64 interrupts = <18 2>;
64 }; 65 };
65 66
66 l2-cache-controller@20000 { 67 L2: l2-cache-controller@20000 {
67 compatible = "fsl,8541-l2-cache-controller"; 68 compatible = "fsl,8541-l2-cache-controller";
68 reg = <0x20000 0x1000>; 69 reg = <0x20000 0x1000>;
69 cache-line-size = <32>; // 32 bytes 70 cache-line-size = <32>; // 32 bytes
@@ -83,6 +84,47 @@
83 dfsrr; 84 dfsrr;
84 }; 85 };
85 86
87 dma@21300 {
88 #address-cells = <1>;
89 #size-cells = <1>;
90 compatible = "fsl,mpc8541-dma", "fsl,eloplus-dma";
91 reg = <0x21300 0x4>;
92 ranges = <0x0 0x21100 0x200>;
93 cell-index = <0>;
94 dma-channel@0 {
95 compatible = "fsl,mpc8541-dma-channel",
96 "fsl,eloplus-dma-channel";
97 reg = <0x0 0x80>;
98 cell-index = <0>;
99 interrupt-parent = <&mpic>;
100 interrupts = <20 2>;
101 };
102 dma-channel@80 {
103 compatible = "fsl,mpc8541-dma-channel",
104 "fsl,eloplus-dma-channel";
105 reg = <0x80 0x80>;
106 cell-index = <1>;
107 interrupt-parent = <&mpic>;
108 interrupts = <21 2>;
109 };
110 dma-channel@100 {
111 compatible = "fsl,mpc8541-dma-channel",
112 "fsl,eloplus-dma-channel";
113 reg = <0x100 0x80>;
114 cell-index = <2>;
115 interrupt-parent = <&mpic>;
116 interrupts = <22 2>;
117 };
118 dma-channel@180 {
119 compatible = "fsl,mpc8541-dma-channel",
120 "fsl,eloplus-dma-channel";
121 reg = <0x180 0x80>;
122 cell-index = <3>;
123 interrupt-parent = <&mpic>;
124 interrupts = <23 2>;
125 };
126 };
127
86 mdio@24520 { 128 mdio@24520 {
87 #address-cells = <1>; 129 #address-cells = <1>;
88 #size-cells = <0>; 130 #size-cells = <0>;
@@ -147,15 +189,24 @@
147 interrupt-parent = <&mpic>; 189 interrupt-parent = <&mpic>;
148 }; 190 };
149 191
192 crypto@30000 {
193 compatible = "fsl,sec2.0";
194 reg = <0x30000 0x10000>;
195 interrupts = <45 2>;
196 interrupt-parent = <&mpic>;
197 fsl,num-channels = <4>;
198 fsl,channel-fifo-len = <24>;
199 fsl,exec-units-mask = <0x7e>;
200 fsl,descriptor-types-mask = <0x01010ebf>;
201 };
202
150 mpic: pic@40000 { 203 mpic: pic@40000 {
151 clock-frequency = <0>;
152 interrupt-controller; 204 interrupt-controller;
153 #address-cells = <0>; 205 #address-cells = <0>;
154 #interrupt-cells = <2>; 206 #interrupt-cells = <2>;
155 reg = <0x40000 0x40000>; 207 reg = <0x40000 0x40000>;
156 compatible = "chrp,open-pic"; 208 compatible = "chrp,open-pic";
157 device_type = "open-pic"; 209 device_type = "open-pic";
158 big-endian;
159 }; 210 };
160 211
161 cpm@919c0 { 212 cpm@919c0 {
diff --git a/arch/powerpc/boot/dts/mpc8544ds.dts b/arch/powerpc/boot/dts/mpc8544ds.dts
index 6a0d8db96d97..7d3829d3495e 100644
--- a/arch/powerpc/boot/dts/mpc8544ds.dts
+++ b/arch/powerpc/boot/dts/mpc8544ds.dts
@@ -41,6 +41,7 @@
41 timebase-frequency = <0>; 41 timebase-frequency = <0>;
42 bus-frequency = <0>; 42 bus-frequency = <0>;
43 clock-frequency = <0>; 43 clock-frequency = <0>;
44 next-level-cache = <&L2>;
44 }; 45 };
45 }; 46 };
46 47
@@ -65,7 +66,7 @@
65 interrupts = <18 2>; 66 interrupts = <18 2>;
66 }; 67 };
67 68
68 l2-cache-controller@20000 { 69 L2: l2-cache-controller@20000 {
69 compatible = "fsl,8544-l2-cache-controller"; 70 compatible = "fsl,8544-l2-cache-controller";
70 reg = <0x20000 0x1000>; 71 reg = <0x20000 0x1000>;
71 cache-line-size = <32>; // 32 bytes 72 cache-line-size = <32>; // 32 bytes
@@ -209,15 +210,40 @@
209 fsl,has-rstcr; 210 fsl,has-rstcr;
210 }; 211 };
211 212
213 crypto@30000 {
214 compatible = "fsl,sec2.1", "fsl,sec2.0";
215 reg = <0x30000 0x10000>;
216 interrupts = <45 2>;
217 interrupt-parent = <&mpic>;
218 fsl,num-channels = <4>;
219 fsl,channel-fifo-len = <24>;
220 fsl,exec-units-mask = <0xfe>;
221 fsl,descriptor-types-mask = <0x12b0ebf>;
222 };
223
212 mpic: pic@40000 { 224 mpic: pic@40000 {
213 clock-frequency = <0>;
214 interrupt-controller; 225 interrupt-controller;
215 #address-cells = <0>; 226 #address-cells = <0>;
216 #interrupt-cells = <2>; 227 #interrupt-cells = <2>;
217 reg = <0x40000 0x40000>; 228 reg = <0x40000 0x40000>;
218 compatible = "chrp,open-pic"; 229 compatible = "chrp,open-pic";
219 device_type = "open-pic"; 230 device_type = "open-pic";
220 big-endian; 231 };
232
233 msi@41600 {
234 compatible = "fsl,mpc8544-msi", "fsl,mpic-msi";
235 reg = <0x41600 0x80>;
236 msi-available-ranges = <0 0x100>;
237 interrupts = <
238 0xe0 0
239 0xe1 0
240 0xe2 0
241 0xe3 0
242 0xe4 0
243 0xe5 0
244 0xe6 0
245 0xe7 0>;
246 interrupt-parent = <&mpic>;
221 }; 247 };
222 }; 248 };
223 249
diff --git a/arch/powerpc/boot/dts/mpc8548cds.dts b/arch/powerpc/boot/dts/mpc8548cds.dts
index 4811b8107415..d84466bb7eca 100644
--- a/arch/powerpc/boot/dts/mpc8548cds.dts
+++ b/arch/powerpc/boot/dts/mpc8548cds.dts
@@ -45,6 +45,7 @@
45 timebase-frequency = <0>; // 33 MHz, from uboot 45 timebase-frequency = <0>; // 33 MHz, from uboot
46 bus-frequency = <0>; // 166 MHz 46 bus-frequency = <0>; // 166 MHz
47 clock-frequency = <0>; // 825 MHz, from uboot 47 clock-frequency = <0>; // 825 MHz, from uboot
48 next-level-cache = <&L2>;
48 }; 49 };
49 }; 50 };
50 51
@@ -68,7 +69,7 @@
68 interrupts = <18 2>; 69 interrupts = <18 2>;
69 }; 70 };
70 71
71 l2-cache-controller@20000 { 72 L2: l2-cache-controller@20000 {
72 compatible = "fsl,8548-l2-cache-controller"; 73 compatible = "fsl,8548-l2-cache-controller";
73 reg = <0x20000 0x1000>; 74 reg = <0x20000 0x1000>;
74 cache-line-size = <32>; // 32 bytes 75 cache-line-size = <32>; // 32 bytes
@@ -99,6 +100,47 @@
99 dfsrr; 100 dfsrr;
100 }; 101 };
101 102
103 dma@21300 {
104 #address-cells = <1>;
105 #size-cells = <1>;
106 compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma";
107 reg = <0x21300 0x4>;
108 ranges = <0x0 0x21100 0x200>;
109 cell-index = <0>;
110 dma-channel@0 {
111 compatible = "fsl,mpc8548-dma-channel",
112 "fsl,eloplus-dma-channel";
113 reg = <0x0 0x80>;
114 cell-index = <0>;
115 interrupt-parent = <&mpic>;
116 interrupts = <20 2>;
117 };
118 dma-channel@80 {
119 compatible = "fsl,mpc8548-dma-channel",
120 "fsl,eloplus-dma-channel";
121 reg = <0x80 0x80>;
122 cell-index = <1>;
123 interrupt-parent = <&mpic>;
124 interrupts = <21 2>;
125 };
126 dma-channel@100 {
127 compatible = "fsl,mpc8548-dma-channel",
128 "fsl,eloplus-dma-channel";
129 reg = <0x100 0x80>;
130 cell-index = <2>;
131 interrupt-parent = <&mpic>;
132 interrupts = <22 2>;
133 };
134 dma-channel@180 {
135 compatible = "fsl,mpc8548-dma-channel",
136 "fsl,eloplus-dma-channel";
137 reg = <0x180 0x80>;
138 cell-index = <3>;
139 interrupt-parent = <&mpic>;
140 interrupts = <23 2>;
141 };
142 };
143
102 mdio@24520 { 144 mdio@24520 {
103 #address-cells = <1>; 145 #address-cells = <1>;
104 #size-cells = <0>; 146 #size-cells = <0>;
@@ -207,15 +249,24 @@
207 fsl,has-rstcr; 249 fsl,has-rstcr;
208 }; 250 };
209 251
252 crypto@30000 {
253 compatible = "fsl,sec2.1", "fsl,sec2.0";
254 reg = <0x30000 0x10000>;
255 interrupts = <45 2>;
256 interrupt-parent = <&mpic>;
257 fsl,num-channels = <4>;
258 fsl,channel-fifo-len = <24>;
259 fsl,exec-units-mask = <0xfe>;
260 fsl,descriptor-types-mask = <0x12b0ebf>;
261 };
262
210 mpic: pic@40000 { 263 mpic: pic@40000 {
211 clock-frequency = <0>;
212 interrupt-controller; 264 interrupt-controller;
213 #address-cells = <0>; 265 #address-cells = <0>;
214 #interrupt-cells = <2>; 266 #interrupt-cells = <2>;
215 reg = <0x40000 0x40000>; 267 reg = <0x40000 0x40000>;
216 compatible = "chrp,open-pic"; 268 compatible = "chrp,open-pic";
217 device_type = "open-pic"; 269 device_type = "open-pic";
218 big-endian;
219 }; 270 };
220 }; 271 };
221 272
diff --git a/arch/powerpc/boot/dts/mpc8555cds.dts b/arch/powerpc/boot/dts/mpc8555cds.dts
index b025c566c10d..e03a78006283 100644
--- a/arch/powerpc/boot/dts/mpc8555cds.dts
+++ b/arch/powerpc/boot/dts/mpc8555cds.dts
@@ -40,6 +40,7 @@
40 timebase-frequency = <0>; // 33 MHz, from uboot 40 timebase-frequency = <0>; // 33 MHz, from uboot
41 bus-frequency = <0>; // 166 MHz 41 bus-frequency = <0>; // 166 MHz
42 clock-frequency = <0>; // 825 MHz, from uboot 42 clock-frequency = <0>; // 825 MHz, from uboot
43 next-level-cache = <&L2>;
43 }; 44 };
44 }; 45 };
45 46
@@ -63,7 +64,7 @@
63 interrupts = <18 2>; 64 interrupts = <18 2>;
64 }; 65 };
65 66
66 l2-cache-controller@20000 { 67 L2: l2-cache-controller@20000 {
67 compatible = "fsl,8555-l2-cache-controller"; 68 compatible = "fsl,8555-l2-cache-controller";
68 reg = <0x20000 0x1000>; 69 reg = <0x20000 0x1000>;
69 cache-line-size = <32>; // 32 bytes 70 cache-line-size = <32>; // 32 bytes
@@ -83,6 +84,47 @@
83 dfsrr; 84 dfsrr;
84 }; 85 };
85 86
87 dma@21300 {
88 #address-cells = <1>;
89 #size-cells = <1>;
90 compatible = "fsl,mpc8555-dma", "fsl,eloplus-dma";
91 reg = <0x21300 0x4>;
92 ranges = <0x0 0x21100 0x200>;
93 cell-index = <0>;
94 dma-channel@0 {
95 compatible = "fsl,mpc8555-dma-channel",
96 "fsl,eloplus-dma-channel";
97 reg = <0x0 0x80>;
98 cell-index = <0>;
99 interrupt-parent = <&mpic>;
100 interrupts = <20 2>;
101 };
102 dma-channel@80 {
103 compatible = "fsl,mpc8555-dma-channel",
104 "fsl,eloplus-dma-channel";
105 reg = <0x80 0x80>;
106 cell-index = <1>;
107 interrupt-parent = <&mpic>;
108 interrupts = <21 2>;
109 };
110 dma-channel@100 {
111 compatible = "fsl,mpc8555-dma-channel",
112 "fsl,eloplus-dma-channel";
113 reg = <0x100 0x80>;
114 cell-index = <2>;
115 interrupt-parent = <&mpic>;
116 interrupts = <22 2>;
117 };
118 dma-channel@180 {
119 compatible = "fsl,mpc8555-dma-channel",
120 "fsl,eloplus-dma-channel";
121 reg = <0x180 0x80>;
122 cell-index = <3>;
123 interrupt-parent = <&mpic>;
124 interrupts = <23 2>;
125 };
126 };
127
86 mdio@24520 { 128 mdio@24520 {
87 #address-cells = <1>; 129 #address-cells = <1>;
88 #size-cells = <0>; 130 #size-cells = <0>;
@@ -147,15 +189,24 @@
147 interrupt-parent = <&mpic>; 189 interrupt-parent = <&mpic>;
148 }; 190 };
149 191
192 crypto@30000 {
193 compatible = "fsl,sec2.0";
194 reg = <0x30000 0x10000>;
195 interrupts = <45 2>;
196 interrupt-parent = <&mpic>;
197 fsl,num-channels = <4>;
198 fsl,channel-fifo-len = <24>;
199 fsl,exec-units-mask = <0x7e>;
200 fsl,descriptor-types-mask = <0x01010ebf>;
201 };
202
150 mpic: pic@40000 { 203 mpic: pic@40000 {
151 clock-frequency = <0>;
152 interrupt-controller; 204 interrupt-controller;
153 #address-cells = <0>; 205 #address-cells = <0>;
154 #interrupt-cells = <2>; 206 #interrupt-cells = <2>;
155 reg = <0x40000 0x40000>; 207 reg = <0x40000 0x40000>;
156 compatible = "chrp,open-pic"; 208 compatible = "chrp,open-pic";
157 device_type = "open-pic"; 209 device_type = "open-pic";
158 big-endian;
159 }; 210 };
160 211
161 cpm@919c0 { 212 cpm@919c0 {
diff --git a/arch/powerpc/boot/dts/mpc8560ads.dts b/arch/powerpc/boot/dts/mpc8560ads.dts
index 0cc16ab305d1..ba8159de040b 100644
--- a/arch/powerpc/boot/dts/mpc8560ads.dts
+++ b/arch/powerpc/boot/dts/mpc8560ads.dts
@@ -64,7 +64,7 @@
64 interrupts = <18 2>; 64 interrupts = <18 2>;
65 }; 65 };
66 66
67 l2-cache-controller@20000 { 67 L2: l2-cache-controller@20000 {
68 compatible = "fsl,8540-l2-cache-controller"; 68 compatible = "fsl,8540-l2-cache-controller";
69 reg = <0x20000 0x1000>; 69 reg = <0x20000 0x1000>;
70 cache-line-size = <32>; // 32 bytes 70 cache-line-size = <32>; // 32 bytes
@@ -73,6 +73,47 @@
73 interrupts = <16 2>; 73 interrupts = <16 2>;
74 }; 74 };
75 75
76 dma@21300 {
77 #address-cells = <1>;
78 #size-cells = <1>;
79 compatible = "fsl,mpc8560-dma", "fsl,eloplus-dma";
80 reg = <0x21300 0x4>;
81 ranges = <0x0 0x21100 0x200>;
82 cell-index = <0>;
83 dma-channel@0 {
84 compatible = "fsl,mpc8560-dma-channel",
85 "fsl,eloplus-dma-channel";
86 reg = <0x0 0x80>;
87 cell-index = <0>;
88 interrupt-parent = <&mpic>;
89 interrupts = <20 2>;
90 };
91 dma-channel@80 {
92 compatible = "fsl,mpc8560-dma-channel",
93 "fsl,eloplus-dma-channel";
94 reg = <0x80 0x80>;
95 cell-index = <1>;
96 interrupt-parent = <&mpic>;
97 interrupts = <21 2>;
98 };
99 dma-channel@100 {
100 compatible = "fsl,mpc8560-dma-channel",
101 "fsl,eloplus-dma-channel";
102 reg = <0x100 0x80>;
103 cell-index = <2>;
104 interrupt-parent = <&mpic>;
105 interrupts = <22 2>;
106 };
107 dma-channel@180 {
108 compatible = "fsl,mpc8560-dma-channel",
109 "fsl,eloplus-dma-channel";
110 reg = <0x180 0x80>;
111 cell-index = <3>;
112 interrupt-parent = <&mpic>;
113 interrupts = <23 2>;
114 };
115 };
116
76 mdio@24520 { 117 mdio@24520 {
77 #address-cells = <1>; 118 #address-cells = <1>;
78 #size-cells = <0>; 119 #size-cells = <0>;
@@ -134,6 +175,7 @@
134 #address-cells = <0>; 175 #address-cells = <0>;
135 #interrupt-cells = <2>; 176 #interrupt-cells = <2>;
136 reg = <0x40000 0x40000>; 177 reg = <0x40000 0x40000>;
178 compatible = "chrp,open-pic";
137 device_type = "open-pic"; 179 device_type = "open-pic";
138 }; 180 };
139 181
diff --git a/arch/powerpc/boot/dts/mpc8568mds.dts b/arch/powerpc/boot/dts/mpc8568mds.dts
index a025a8ededc5..9c30a34821dc 100644
--- a/arch/powerpc/boot/dts/mpc8568mds.dts
+++ b/arch/powerpc/boot/dts/mpc8568mds.dts
@@ -42,6 +42,7 @@
42 timebase-frequency = <0>; 42 timebase-frequency = <0>;
43 bus-frequency = <0>; 43 bus-frequency = <0>;
44 clock-frequency = <0>; 44 clock-frequency = <0>;
45 next-level-cache = <&L2>;
45 }; 46 };
46 }; 47 };
47 48
@@ -70,7 +71,7 @@
70 interrupts = <18 2>; 71 interrupts = <18 2>;
71 }; 72 };
72 73
73 l2-cache-controller@20000 { 74 L2: l2-cache-controller@20000 {
74 compatible = "fsl,8568-l2-cache-controller"; 75 compatible = "fsl,8568-l2-cache-controller";
75 reg = <0x20000 0x1000>; 76 reg = <0x20000 0x1000>;
76 cache-line-size = <32>; // 32 bytes 77 cache-line-size = <32>; // 32 bytes
@@ -106,6 +107,47 @@
106 dfsrr; 107 dfsrr;
107 }; 108 };
108 109
110 dma@21300 {
111 #address-cells = <1>;
112 #size-cells = <1>;
113 compatible = "fsl,mpc8568-dma", "fsl,eloplus-dma";
114 reg = <0x21300 0x4>;
115 ranges = <0x0 0x21100 0x200>;
116 cell-index = <0>;
117 dma-channel@0 {
118 compatible = "fsl,mpc8568-dma-channel",
119 "fsl,eloplus-dma-channel";
120 reg = <0x0 0x80>;
121 cell-index = <0>;
122 interrupt-parent = <&mpic>;
123 interrupts = <20 2>;
124 };
125 dma-channel@80 {
126 compatible = "fsl,mpc8568-dma-channel",
127 "fsl,eloplus-dma-channel";
128 reg = <0x80 0x80>;
129 cell-index = <1>;
130 interrupt-parent = <&mpic>;
131 interrupts = <21 2>;
132 };
133 dma-channel@100 {
134 compatible = "fsl,mpc8568-dma-channel",
135 "fsl,eloplus-dma-channel";
136 reg = <0x100 0x80>;
137 cell-index = <2>;
138 interrupt-parent = <&mpic>;
139 interrupts = <22 2>;
140 };
141 dma-channel@180 {
142 compatible = "fsl,mpc8568-dma-channel",
143 "fsl,eloplus-dma-channel";
144 reg = <0x180 0x80>;
145 cell-index = <3>;
146 interrupt-parent = <&mpic>;
147 interrupts = <23 2>;
148 };
149 };
150
109 mdio@24520 { 151 mdio@24520 {
110 #address-cells = <1>; 152 #address-cells = <1>;
111 #size-cells = <0>; 153 #size-cells = <0>;
@@ -189,27 +231,23 @@
189 }; 231 };
190 232
191 crypto@30000 { 233 crypto@30000 {
192 device_type = "crypto"; 234 compatible = "fsl,sec2.1", "fsl,sec2.0";
193 model = "SEC2"; 235 reg = <0x30000 0x10000>;
194 compatible = "talitos";
195 reg = <0x30000 0xf000>;
196 interrupts = <45 2>; 236 interrupts = <45 2>;
197 interrupt-parent = <&mpic>; 237 interrupt-parent = <&mpic>;
198 num-channels = <4>; 238 fsl,num-channels = <4>;
199 channel-fifo-len = <24>; 239 fsl,channel-fifo-len = <24>;
200 exec-units-mask = <0xfe>; 240 fsl,exec-units-mask = <0xfe>;
201 descriptor-types-mask = <0x12b0ebf>; 241 fsl,descriptor-types-mask = <0x12b0ebf>;
202 }; 242 };
203 243
204 mpic: pic@40000 { 244 mpic: pic@40000 {
205 clock-frequency = <0>;
206 interrupt-controller; 245 interrupt-controller;
207 #address-cells = <0>; 246 #address-cells = <0>;
208 #interrupt-cells = <2>; 247 #interrupt-cells = <2>;
209 reg = <0x40000 0x40000>; 248 reg = <0x40000 0x40000>;
210 compatible = "chrp,open-pic"; 249 compatible = "chrp,open-pic";
211 device_type = "open-pic"; 250 device_type = "open-pic";
212 big-endian;
213 }; 251 };
214 252
215 par_io@e0100 { 253 par_io@e0100 {
diff --git a/arch/powerpc/boot/dts/mpc8572ds.dts b/arch/powerpc/boot/dts/mpc8572ds.dts
index 66f27ab613a2..08c61e3daecc 100644
--- a/arch/powerpc/boot/dts/mpc8572ds.dts
+++ b/arch/powerpc/boot/dts/mpc8572ds.dts
@@ -42,6 +42,7 @@
42 timebase-frequency = <0>; 42 timebase-frequency = <0>;
43 bus-frequency = <0>; 43 bus-frequency = <0>;
44 clock-frequency = <0>; 44 clock-frequency = <0>;
45 next-level-cache = <&L2>;
45 }; 46 };
46 47
47 PowerPC,8572@1 { 48 PowerPC,8572@1 {
@@ -54,6 +55,7 @@
54 timebase-frequency = <0>; 55 timebase-frequency = <0>;
55 bus-frequency = <0>; 56 bus-frequency = <0>;
56 clock-frequency = <0>; 57 clock-frequency = <0>;
58 next-level-cache = <&L2>;
57 }; 59 };
58 }; 60 };
59 61
@@ -84,7 +86,7 @@
84 interrupts = <18 2>; 86 interrupts = <18 2>;
85 }; 87 };
86 88
87 l2-cache-controller@20000 { 89 L2: l2-cache-controller@20000 {
88 compatible = "fsl,mpc8572-l2-cache-controller"; 90 compatible = "fsl,mpc8572-l2-cache-controller";
89 reg = <0x20000 0x1000>; 91 reg = <0x20000 0x1000>;
90 cache-line-size = <32>; // 32 bytes 92 cache-line-size = <32>; // 32 bytes
@@ -115,6 +117,88 @@
115 dfsrr; 117 dfsrr;
116 }; 118 };
117 119
120 dma@c300 {
121 #address-cells = <1>;
122 #size-cells = <1>;
123 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
124 reg = <0xc300 0x4>;
125 ranges = <0x0 0xc100 0x200>;
126 cell-index = <1>;
127 dma-channel@0 {
128 compatible = "fsl,mpc8572-dma-channel",
129 "fsl,eloplus-dma-channel";
130 reg = <0x0 0x80>;
131 cell-index = <0>;
132 interrupt-parent = <&mpic>;
133 interrupts = <76 2>;
134 };
135 dma-channel@80 {
136 compatible = "fsl,mpc8572-dma-channel",
137 "fsl,eloplus-dma-channel";
138 reg = <0x80 0x80>;
139 cell-index = <1>;
140 interrupt-parent = <&mpic>;
141 interrupts = <77 2>;
142 };
143 dma-channel@100 {
144 compatible = "fsl,mpc8572-dma-channel",
145 "fsl,eloplus-dma-channel";
146 reg = <0x100 0x80>;
147 cell-index = <2>;
148 interrupt-parent = <&mpic>;
149 interrupts = <78 2>;
150 };
151 dma-channel@180 {
152 compatible = "fsl,mpc8572-dma-channel",
153 "fsl,eloplus-dma-channel";
154 reg = <0x180 0x80>;
155 cell-index = <3>;
156 interrupt-parent = <&mpic>;
157 interrupts = <79 2>;
158 };
159 };
160
161 dma@21300 {
162 #address-cells = <1>;
163 #size-cells = <1>;
164 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
165 reg = <0x21300 0x4>;
166 ranges = <0x0 0x21100 0x200>;
167 cell-index = <0>;
168 dma-channel@0 {
169 compatible = "fsl,mpc8572-dma-channel",
170 "fsl,eloplus-dma-channel";
171 reg = <0x0 0x80>;
172 cell-index = <0>;
173 interrupt-parent = <&mpic>;
174 interrupts = <20 2>;
175 };
176 dma-channel@80 {
177 compatible = "fsl,mpc8572-dma-channel",
178 "fsl,eloplus-dma-channel";
179 reg = <0x80 0x80>;
180 cell-index = <1>;
181 interrupt-parent = <&mpic>;
182 interrupts = <21 2>;
183 };
184 dma-channel@100 {
185 compatible = "fsl,mpc8572-dma-channel",
186 "fsl,eloplus-dma-channel";
187 reg = <0x100 0x80>;
188 cell-index = <2>;
189 interrupt-parent = <&mpic>;
190 interrupts = <22 2>;
191 };
192 dma-channel@180 {
193 compatible = "fsl,mpc8572-dma-channel",
194 "fsl,eloplus-dma-channel";
195 reg = <0x180 0x80>;
196 cell-index = <3>;
197 interrupt-parent = <&mpic>;
198 interrupts = <23 2>;
199 };
200 };
201
118 mdio@24520 { 202 mdio@24520 {
119 #address-cells = <1>; 203 #address-cells = <1>;
120 #size-cells = <0>; 204 #size-cells = <0>;
@@ -221,15 +305,41 @@
221 fsl,has-rstcr; 305 fsl,has-rstcr;
222 }; 306 };
223 307
308 msi@41600 {
309 compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
310 reg = <0x41600 0x80>;
311 msi-available-ranges = <0 0x100>;
312 interrupts = <
313 0xe0 0
314 0xe1 0
315 0xe2 0
316 0xe3 0
317 0xe4 0
318 0xe5 0
319 0xe6 0
320 0xe7 0>;
321 interrupt-parent = <&mpic>;
322 };
323
324 crypto@30000 {
325 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
326 "fsl,sec2.1", "fsl,sec2.0";
327 reg = <0x30000 0x10000>;
328 interrupts = <45 2 58 2>;
329 interrupt-parent = <&mpic>;
330 fsl,num-channels = <4>;
331 fsl,channel-fifo-len = <24>;
332 fsl,exec-units-mask = <0x9fe>;
333 fsl,descriptor-types-mask = <0x3ab0ebf>;
334 };
335
224 mpic: pic@40000 { 336 mpic: pic@40000 {
225 clock-frequency = <0>;
226 interrupt-controller; 337 interrupt-controller;
227 #address-cells = <0>; 338 #address-cells = <0>;
228 #interrupt-cells = <2>; 339 #interrupt-cells = <2>;
229 reg = <0x40000 0x40000>; 340 reg = <0x40000 0x40000>;
230 compatible = "chrp,open-pic"; 341 compatible = "chrp,open-pic";
231 device_type = "open-pic"; 342 device_type = "open-pic";
232 big-endian;
233 }; 343 };
234 }; 344 };
235 345
diff --git a/arch/powerpc/boot/dts/mpc8610_hpcd.dts b/arch/powerpc/boot/dts/mpc8610_hpcd.dts
index fa9b6bbeb5af..981941e5d7a5 100644
--- a/arch/powerpc/boot/dts/mpc8610_hpcd.dts
+++ b/arch/powerpc/boot/dts/mpc8610_hpcd.dts
@@ -172,14 +172,28 @@
172 }; 172 };
173 173
174 mpic: interrupt-controller@40000 { 174 mpic: interrupt-controller@40000 {
175 clock-frequency = <0>;
176 interrupt-controller; 175 interrupt-controller;
177 #address-cells = <0>; 176 #address-cells = <0>;
178 #interrupt-cells = <2>; 177 #interrupt-cells = <2>;
179 reg = <0x40000 0x40000>; 178 reg = <0x40000 0x40000>;
180 compatible = "chrp,open-pic"; 179 compatible = "chrp,open-pic";
181 device_type = "open-pic"; 180 device_type = "open-pic";
182 big-endian; 181 };
182
183 msi@41600 {
184 compatible = "fsl,mpc8610-msi", "fsl,mpic-msi";
185 reg = <0x41600 0x80>;
186 msi-available-ranges = <0 0x100>;
187 interrupts = <
188 0xe0 0
189 0xe1 0
190 0xe2 0
191 0xe3 0
192 0xe4 0
193 0xe5 0
194 0xe6 0
195 0xe7 0>;
196 interrupt-parent = <&mpic>;
183 }; 197 };
184 198
185 global-utilities@e0000 { 199 global-utilities@e0000 {
@@ -349,7 +363,7 @@
349 0xe000 0 0 4 &mpic 1 1 363 0xe000 0 0 4 &mpic 1 1
350 364
351 /* IDSEL 0x1f */ 365 /* IDSEL 0x1f */
352 0xf800 0 0 1 &mpic 3 0 366 0xf800 0 0 1 &mpic 3 2
353 0xf800 0 0 2 &mpic 0 1 367 0xf800 0 0 2 &mpic 0 1
354 >; 368 >;
355 369
diff --git a/arch/powerpc/boot/dts/mpc8641_hpcn.dts b/arch/powerpc/boot/dts/mpc8641_hpcn.dts
index 1e4bfe9cadb9..ae08761ffff1 100644
--- a/arch/powerpc/boot/dts/mpc8641_hpcn.dts
+++ b/arch/powerpc/boot/dts/mpc8641_hpcn.dts
@@ -134,6 +134,47 @@
134 dfsrr; 134 dfsrr;
135 }; 135 };
136 136
137 dma@21300 {
138 #address-cells = <1>;
139 #size-cells = <1>;
140 compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma";
141 reg = <0x21300 0x4>;
142 ranges = <0x0 0x21100 0x200>;
143 cell-index = <0>;
144 dma-channel@0 {
145 compatible = "fsl,mpc8641-dma-channel",
146 "fsl,eloplus-dma-channel";
147 reg = <0x0 0x80>;
148 cell-index = <0>;
149 interrupt-parent = <&mpic>;
150 interrupts = <20 2>;
151 };
152 dma-channel@80 {
153 compatible = "fsl,mpc8641-dma-channel",
154 "fsl,eloplus-dma-channel";
155 reg = <0x80 0x80>;
156 cell-index = <1>;
157 interrupt-parent = <&mpic>;
158 interrupts = <21 2>;
159 };
160 dma-channel@100 {
161 compatible = "fsl,mpc8641-dma-channel",
162 "fsl,eloplus-dma-channel";
163 reg = <0x100 0x80>;
164 cell-index = <2>;
165 interrupt-parent = <&mpic>;
166 interrupts = <22 2>;
167 };
168 dma-channel@180 {
169 compatible = "fsl,mpc8641-dma-channel",
170 "fsl,eloplus-dma-channel";
171 reg = <0x180 0x80>;
172 cell-index = <3>;
173 interrupt-parent = <&mpic>;
174 interrupts = <23 2>;
175 };
176 };
177
137 mdio@24520 { 178 mdio@24520 {
138 #address-cells = <1>; 179 #address-cells = <1>;
139 #size-cells = <0>; 180 #size-cells = <0>;
@@ -239,14 +280,12 @@
239 }; 280 };
240 281
241 mpic: pic@40000 { 282 mpic: pic@40000 {
242 clock-frequency = <0>;
243 interrupt-controller; 283 interrupt-controller;
244 #address-cells = <0>; 284 #address-cells = <0>;
245 #interrupt-cells = <2>; 285 #interrupt-cells = <2>;
246 reg = <0x40000 0x40000>; 286 reg = <0x40000 0x40000>;
247 compatible = "chrp,open-pic"; 287 compatible = "chrp,open-pic";
248 device_type = "open-pic"; 288 device_type = "open-pic";
249 big-endian;
250 }; 289 };
251 290
252 global-utilities@e0000 { 291 global-utilities@e0000 {
diff --git a/arch/powerpc/boot/dts/mpc866ads.dts b/arch/powerpc/boot/dts/mpc866ads.dts
index 765e43c997da..bd700651f360 100644
--- a/arch/powerpc/boot/dts/mpc866ads.dts
+++ b/arch/powerpc/boot/dts/mpc866ads.dts
@@ -171,6 +171,17 @@
171 fsl,cpm-command = <0000>; 171 fsl,cpm-command = <0000>;
172 linux,network-index = <1>; 172 linux,network-index = <1>;
173 }; 173 };
174
175 i2c@860 {
176 compatible = "fsl,mpc866-i2c",
177 "fsl,cpm1-i2c";
178 reg = <0x860 0x20 0x3c80 0x30>;
179 interrupts = <16>;
180 interrupt-parent = <&CPM_PIC>;
181 fsl,cpm-command = <0x10>;
182 #address-cells = <1>;
183 #size-cells = <0>;
184 };
174 }; 185 };
175 }; 186 };
176 187
diff --git a/arch/powerpc/boot/dts/mpc885ads.dts b/arch/powerpc/boot/dts/mpc885ads.dts
index 9895043722b9..b123e9f7a5a8 100644
--- a/arch/powerpc/boot/dts/mpc885ads.dts
+++ b/arch/powerpc/boot/dts/mpc885ads.dts
@@ -215,6 +215,17 @@
215 fsl,cpm-command = <0x80>; 215 fsl,cpm-command = <0x80>;
216 linux,network-index = <2>; 216 linux,network-index = <2>;
217 }; 217 };
218
219 i2c@860 {
220 compatible = "fsl,mpc885-i2c",
221 "fsl,cpm1-i2c";
222 reg = <0x860 0x20 0x3c80 0x30>;
223 interrupts = <16>;
224 interrupt-parent = <&CPM_PIC>;
225 fsl,cpm-command = <0x10>;
226 #address-cells = <1>;
227 #size-cells = <0>;
228 };
218 }; 229 };
219 }; 230 };
220 231
diff --git a/arch/powerpc/boot/dts/ps3.dts b/arch/powerpc/boot/dts/ps3.dts
index 379ded282d5e..96ba5b512afe 100644
--- a/arch/powerpc/boot/dts/ps3.dts
+++ b/arch/powerpc/boot/dts/ps3.dts
@@ -18,6 +18,8 @@
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */ 19 */
20 20
21/dts-v1/;
22
21/ { 23/ {
22 model = "SonyPS3"; 24 model = "SonyPS3";
23 compatible = "sony,ps3"; 25 compatible = "sony,ps3";
@@ -34,7 +36,7 @@
34 36
35 memory { 37 memory {
36 device_type = "memory"; 38 device_type = "memory";
37 reg = <0 0 0 0>; 39 reg = <0x00000000 0x00000000 0x00000000 0x00000000>;
38 }; 40 };
39 41
40 /* 42 /*
@@ -55,14 +57,14 @@
55 57
56 cpu@0 { 58 cpu@0 {
57 device_type = "cpu"; 59 device_type = "cpu";
58 reg = <0>; 60 reg = <0x00000000>;
59 ibm,ppc-interrupt-server#s = <0 1>; 61 ibm,ppc-interrupt-server#s = <0x0 0x1>;
60 clock-frequency = <0>; 62 clock-frequency = <0>;
61 timebase-frequency = <0>; 63 timebase-frequency = <0>;
62 i-cache-size = <8000>; 64 i-cache-size = <32768>;
63 d-cache-size = <8000>; 65 d-cache-size = <32768>;
64 i-cache-line-size = <80>; 66 i-cache-line-size = <128>;
65 d-cache-line-size = <80>; 67 d-cache-line-size = <128>;
66 }; 68 };
67 }; 69 };
68}; 70};
diff --git a/arch/powerpc/boot/dts/rainier.dts b/arch/powerpc/boot/dts/rainier.dts
index 6a8fa7089ea2..9684c80e4093 100644
--- a/arch/powerpc/boot/dts/rainier.dts
+++ b/arch/powerpc/boot/dts/rainier.dts
@@ -12,12 +12,14 @@
12 * 12 *
13 */ 13 */
14 14
15/dts-v1/;
16
15/ { 17/ {
16 #address-cells = <2>; 18 #address-cells = <2>;
17 #size-cells = <1>; 19 #size-cells = <1>;
18 model = "amcc,rainier"; 20 model = "amcc,rainier";
19 compatible = "amcc,rainier"; 21 compatible = "amcc,rainier";
20 dcr-parent = <&/cpus/cpu@0>; 22 dcr-parent = <&{/cpus/cpu@0}>;
21 23
22 aliases { 24 aliases {
23 ethernet0 = &EMAC0; 25 ethernet0 = &EMAC0;
@@ -35,13 +37,13 @@
35 cpu@0 { 37 cpu@0 {
36 device_type = "cpu"; 38 device_type = "cpu";
37 model = "PowerPC,440GRx"; 39 model = "PowerPC,440GRx";
38 reg = <0>; 40 reg = <0x00000000>;
39 clock-frequency = <0>; /* Filled in by zImage */ 41 clock-frequency = <0>; /* Filled in by zImage */
40 timebase-frequency = <0>; /* Filled in by zImage */ 42 timebase-frequency = <0>; /* Filled in by zImage */
41 i-cache-line-size = <20>; 43 i-cache-line-size = <32>;
42 d-cache-line-size = <20>; 44 d-cache-line-size = <32>;
43 i-cache-size = <8000>; 45 i-cache-size = <32768>;
44 d-cache-size = <8000>; 46 d-cache-size = <32768>;
45 dcr-controller; 47 dcr-controller;
46 dcr-access-method = "native"; 48 dcr-access-method = "native";
47 }; 49 };
@@ -49,14 +51,14 @@
49 51
50 memory { 52 memory {
51 device_type = "memory"; 53 device_type = "memory";
52 reg = <0 0 0>; /* Filled in by zImage */ 54 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by zImage */
53 }; 55 };
54 56
55 UIC0: interrupt-controller0 { 57 UIC0: interrupt-controller0 {
56 compatible = "ibm,uic-440grx","ibm,uic"; 58 compatible = "ibm,uic-440grx","ibm,uic";
57 interrupt-controller; 59 interrupt-controller;
58 cell-index = <0>; 60 cell-index = <0>;
59 dcr-reg = <0c0 009>; 61 dcr-reg = <0x0c0 0x009>;
60 #address-cells = <0>; 62 #address-cells = <0>;
61 #size-cells = <0>; 63 #size-cells = <0>;
62 #interrupt-cells = <2>; 64 #interrupt-cells = <2>;
@@ -66,11 +68,11 @@
66 compatible = "ibm,uic-440grx","ibm,uic"; 68 compatible = "ibm,uic-440grx","ibm,uic";
67 interrupt-controller; 69 interrupt-controller;
68 cell-index = <1>; 70 cell-index = <1>;
69 dcr-reg = <0d0 009>; 71 dcr-reg = <0x0d0 0x009>;
70 #address-cells = <0>; 72 #address-cells = <0>;
71 #size-cells = <0>; 73 #size-cells = <0>;
72 #interrupt-cells = <2>; 74 #interrupt-cells = <2>;
73 interrupts = <1e 4 1f 4>; /* cascade */ 75 interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
74 interrupt-parent = <&UIC0>; 76 interrupt-parent = <&UIC0>;
75 }; 77 };
76 78
@@ -78,22 +80,22 @@
78 compatible = "ibm,uic-440grx","ibm,uic"; 80 compatible = "ibm,uic-440grx","ibm,uic";
79 interrupt-controller; 81 interrupt-controller;
80 cell-index = <2>; 82 cell-index = <2>;
81 dcr-reg = <0e0 009>; 83 dcr-reg = <0x0e0 0x009>;
82 #address-cells = <0>; 84 #address-cells = <0>;
83 #size-cells = <0>; 85 #size-cells = <0>;
84 #interrupt-cells = <2>; 86 #interrupt-cells = <2>;
85 interrupts = <1c 4 1d 4>; /* cascade */ 87 interrupts = <0x1c 0x4 0x1d 0x4>; /* cascade */
86 interrupt-parent = <&UIC0>; 88 interrupt-parent = <&UIC0>;
87 }; 89 };
88 90
89 SDR0: sdr { 91 SDR0: sdr {
90 compatible = "ibm,sdr-440grx", "ibm,sdr-440ep"; 92 compatible = "ibm,sdr-440grx", "ibm,sdr-440ep";
91 dcr-reg = <00e 002>; 93 dcr-reg = <0x00e 0x002>;
92 }; 94 };
93 95
94 CPR0: cpr { 96 CPR0: cpr {
95 compatible = "ibm,cpr-440grx", "ibm,cpr-440ep"; 97 compatible = "ibm,cpr-440grx", "ibm,cpr-440ep";
96 dcr-reg = <00c 002>; 98 dcr-reg = <0x00c 0x002>;
97 }; 99 };
98 100
99 plb { 101 plb {
@@ -105,80 +107,80 @@
105 107
106 SDRAM0: sdram { 108 SDRAM0: sdram {
107 compatible = "ibm,sdram-440grx", "ibm,sdram-44x-ddr2denali"; 109 compatible = "ibm,sdram-440grx", "ibm,sdram-44x-ddr2denali";
108 dcr-reg = <010 2>; 110 dcr-reg = <0x010 0x002>;
109 }; 111 };
110 112
111 DMA0: dma { 113 DMA0: dma {
112 compatible = "ibm,dma-440grx", "ibm,dma-4xx"; 114 compatible = "ibm,dma-440grx", "ibm,dma-4xx";
113 dcr-reg = <100 027>; 115 dcr-reg = <0x100 0x027>;
114 }; 116 };
115 117
116 MAL0: mcmal { 118 MAL0: mcmal {
117 compatible = "ibm,mcmal-440grx", "ibm,mcmal2"; 119 compatible = "ibm,mcmal-440grx", "ibm,mcmal2";
118 dcr-reg = <180 62>; 120 dcr-reg = <0x180 0x062>;
119 num-tx-chans = <2>; 121 num-tx-chans = <2>;
120 num-rx-chans = <2>; 122 num-rx-chans = <2>;
121 interrupt-parent = <&MAL0>; 123 interrupt-parent = <&MAL0>;
122 interrupts = <0 1 2 3 4>; 124 interrupts = <0x0 0x1 0x2 0x3 0x4>;
123 #interrupt-cells = <1>; 125 #interrupt-cells = <1>;
124 #address-cells = <0>; 126 #address-cells = <0>;
125 #size-cells = <0>; 127 #size-cells = <0>;
126 interrupt-map = </*TXEOB*/ 0 &UIC0 a 4 128 interrupt-map = </*TXEOB*/ 0x0 &UIC0 0xa 0x4
127 /*RXEOB*/ 1 &UIC0 b 4 129 /*RXEOB*/ 0x1 &UIC0 0xb 0x4
128 /*SERR*/ 2 &UIC1 0 4 130 /*SERR*/ 0x2 &UIC1 0x0 0x4
129 /*TXDE*/ 3 &UIC1 1 4 131 /*TXDE*/ 0x3 &UIC1 0x1 0x4
130 /*RXDE*/ 4 &UIC1 2 4>; 132 /*RXDE*/ 0x4 &UIC1 0x2 0x4>;
131 interrupt-map-mask = <ffffffff>; 133 interrupt-map-mask = <0xffffffff>;
132 }; 134 };
133 135
134 POB0: opb { 136 POB0: opb {
135 compatible = "ibm,opb-440grx", "ibm,opb"; 137 compatible = "ibm,opb-440grx", "ibm,opb";
136 #address-cells = <1>; 138 #address-cells = <1>;
137 #size-cells = <1>; 139 #size-cells = <1>;
138 ranges = <00000000 1 00000000 80000000 140 ranges = <0x00000000 0x00000001 0x00000000 0x80000000
139 80000000 1 80000000 80000000>; 141 0x80000000 0x00000001 0x80000000 0x80000000>;
140 interrupt-parent = <&UIC1>; 142 interrupt-parent = <&UIC1>;
141 interrupts = <7 4>; 143 interrupts = <0x7 0x4>;
142 clock-frequency = <0>; /* Filled in by zImage */ 144 clock-frequency = <0>; /* Filled in by zImage */
143 145
144 EBC0: ebc { 146 EBC0: ebc {
145 compatible = "ibm,ebc-440grx", "ibm,ebc"; 147 compatible = "ibm,ebc-440grx", "ibm,ebc";
146 dcr-reg = <012 2>; 148 dcr-reg = <0x012 0x002>;
147 #address-cells = <2>; 149 #address-cells = <2>;
148 #size-cells = <1>; 150 #size-cells = <1>;
149 clock-frequency = <0>; /* Filled in by zImage */ 151 clock-frequency = <0>; /* Filled in by zImage */
150 interrupts = <5 1>; 152 interrupts = <0x5 0x1>;
151 interrupt-parent = <&UIC1>; 153 interrupt-parent = <&UIC1>;
152 154
153 nor_flash@0,0 { 155 nor_flash@0,0 {
154 compatible = "amd,s29gl256n", "cfi-flash"; 156 compatible = "amd,s29gl256n", "cfi-flash";
155 bank-width = <2>; 157 bank-width = <2>;
156 reg = <0 000000 4000000>; 158 reg = <0x00000000 0x00000000 0x04000000>;
157 #address-cells = <1>; 159 #address-cells = <1>;
158 #size-cells = <1>; 160 #size-cells = <1>;
159 partition@0 { 161 partition@0 {
160 label = "Kernel"; 162 label = "Kernel";
161 reg = <0 180000>; 163 reg = <0x00000000 0x00180000>;
162 }; 164 };
163 partition@180000 { 165 partition@180000 {
164 label = "ramdisk"; 166 label = "ramdisk";
165 reg = <180000 200000>; 167 reg = <0x00180000 0x00200000>;
166 }; 168 };
167 partition@380000 { 169 partition@380000 {
168 label = "file system"; 170 label = "file system";
169 reg = <380000 3aa0000>; 171 reg = <0x00380000 0x03aa0000>;
170 }; 172 };
171 partition@3e20000 { 173 partition@3e20000 {
172 label = "kozio"; 174 label = "kozio";
173 reg = <3e20000 140000>; 175 reg = <0x03e20000 0x00140000>;
174 }; 176 };
175 partition@3f60000 { 177 partition@3f60000 {
176 label = "env"; 178 label = "env";
177 reg = <3f60000 40000>; 179 reg = <0x03f60000 0x00040000>;
178 }; 180 };
179 partition@3fa0000 { 181 partition@3fa0000 {
180 label = "u-boot"; 182 label = "u-boot";
181 reg = <3fa0000 60000>; 183 reg = <0x03fa0000 0x00060000>;
182 }; 184 };
183 }; 185 };
184 186
@@ -187,69 +189,69 @@
187 UART0: serial@ef600300 { 189 UART0: serial@ef600300 {
188 device_type = "serial"; 190 device_type = "serial";
189 compatible = "ns16550"; 191 compatible = "ns16550";
190 reg = <ef600300 8>; 192 reg = <0xef600300 0x00000008>;
191 virtual-reg = <ef600300>; 193 virtual-reg = <0xef600300>;
192 clock-frequency = <0>; /* Filled in by zImage */ 194 clock-frequency = <0>; /* Filled in by zImage */
193 current-speed = <1c200>; 195 current-speed = <115200>;
194 interrupt-parent = <&UIC0>; 196 interrupt-parent = <&UIC0>;
195 interrupts = <0 4>; 197 interrupts = <0x0 0x4>;
196 }; 198 };
197 199
198 UART1: serial@ef600400 { 200 UART1: serial@ef600400 {
199 device_type = "serial"; 201 device_type = "serial";
200 compatible = "ns16550"; 202 compatible = "ns16550";
201 reg = <ef600400 8>; 203 reg = <0xef600400 0x00000008>;
202 virtual-reg = <ef600400>; 204 virtual-reg = <0xef600400>;
203 clock-frequency = <0>; 205 clock-frequency = <0>;
204 current-speed = <0>; 206 current-speed = <0>;
205 interrupt-parent = <&UIC0>; 207 interrupt-parent = <&UIC0>;
206 interrupts = <1 4>; 208 interrupts = <0x1 0x4>;
207 }; 209 };
208 210
209 UART2: serial@ef600500 { 211 UART2: serial@ef600500 {
210 device_type = "serial"; 212 device_type = "serial";
211 compatible = "ns16550"; 213 compatible = "ns16550";
212 reg = <ef600500 8>; 214 reg = <0xef600500 0x00000008>;
213 virtual-reg = <ef600500>; 215 virtual-reg = <0xef600500>;
214 clock-frequency = <0>; 216 clock-frequency = <0>;
215 current-speed = <0>; 217 current-speed = <0>;
216 interrupt-parent = <&UIC1>; 218 interrupt-parent = <&UIC1>;
217 interrupts = <3 4>; 219 interrupts = <0x3 0x4>;
218 }; 220 };
219 221
220 UART3: serial@ef600600 { 222 UART3: serial@ef600600 {
221 device_type = "serial"; 223 device_type = "serial";
222 compatible = "ns16550"; 224 compatible = "ns16550";
223 reg = <ef600600 8>; 225 reg = <0xef600600 0x00000008>;
224 virtual-reg = <ef600600>; 226 virtual-reg = <0xef600600>;
225 clock-frequency = <0>; 227 clock-frequency = <0>;
226 current-speed = <0>; 228 current-speed = <0>;
227 interrupt-parent = <&UIC1>; 229 interrupt-parent = <&UIC1>;
228 interrupts = <4 4>; 230 interrupts = <0x4 0x4>;
229 }; 231 };
230 232
231 IIC0: i2c@ef600700 { 233 IIC0: i2c@ef600700 {
232 compatible = "ibm,iic-440grx", "ibm,iic"; 234 compatible = "ibm,iic-440grx", "ibm,iic";
233 reg = <ef600700 14>; 235 reg = <0xef600700 0x00000014>;
234 interrupt-parent = <&UIC0>; 236 interrupt-parent = <&UIC0>;
235 interrupts = <2 4>; 237 interrupts = <0x2 0x4>;
236 }; 238 };
237 239
238 IIC1: i2c@ef600800 { 240 IIC1: i2c@ef600800 {
239 compatible = "ibm,iic-440grx", "ibm,iic"; 241 compatible = "ibm,iic-440grx", "ibm,iic";
240 reg = <ef600800 14>; 242 reg = <0xef600800 0x00000014>;
241 interrupt-parent = <&UIC0>; 243 interrupt-parent = <&UIC0>;
242 interrupts = <7 4>; 244 interrupts = <0x7 0x4>;
243 }; 245 };
244 246
245 ZMII0: emac-zmii@ef600d00 { 247 ZMII0: emac-zmii@ef600d00 {
246 compatible = "ibm,zmii-440grx", "ibm,zmii"; 248 compatible = "ibm,zmii-440grx", "ibm,zmii";
247 reg = <ef600d00 c>; 249 reg = <0xef600d00 0x0000000c>;
248 }; 250 };
249 251
250 RGMII0: emac-rgmii@ef601000 { 252 RGMII0: emac-rgmii@ef601000 {
251 compatible = "ibm,rgmii-440grx", "ibm,rgmii"; 253 compatible = "ibm,rgmii-440grx", "ibm,rgmii";
252 reg = <ef601000 8>; 254 reg = <0xef601000 0x00000008>;
253 has-mdio; 255 has-mdio;
254 }; 256 };
255 257
@@ -257,23 +259,23 @@
257 device_type = "network"; 259 device_type = "network";
258 compatible = "ibm,emac-440grx", "ibm,emac-440epx", "ibm,emac4"; 260 compatible = "ibm,emac-440grx", "ibm,emac-440epx", "ibm,emac4";
259 interrupt-parent = <&EMAC0>; 261 interrupt-parent = <&EMAC0>;
260 interrupts = <0 1>; 262 interrupts = <0x0 0x1>;
261 #interrupt-cells = <1>; 263 #interrupt-cells = <1>;
262 #address-cells = <0>; 264 #address-cells = <0>;
263 #size-cells = <0>; 265 #size-cells = <0>;
264 interrupt-map = </*Status*/ 0 &UIC0 18 4 266 interrupt-map = </*Status*/ 0x0 &UIC0 0x18 0x4
265 /*Wake*/ 1 &UIC1 1d 4>; 267 /*Wake*/ 0x1 &UIC1 0x1d 0x4>;
266 reg = <ef600e00 70>; 268 reg = <0xef600e00 0x00000074>;
267 local-mac-address = [000000000000]; 269 local-mac-address = [000000000000];
268 mal-device = <&MAL0>; 270 mal-device = <&MAL0>;
269 mal-tx-channel = <0>; 271 mal-tx-channel = <0>;
270 mal-rx-channel = <0>; 272 mal-rx-channel = <0>;
271 cell-index = <0>; 273 cell-index = <0>;
272 max-frame-size = <2328>; 274 max-frame-size = <9000>;
273 rx-fifo-size = <1000>; 275 rx-fifo-size = <4096>;
274 tx-fifo-size = <800>; 276 tx-fifo-size = <2048>;
275 phy-mode = "rgmii"; 277 phy-mode = "rgmii";
276 phy-map = <00000000>; 278 phy-map = <0x00000000>;
277 zmii-device = <&ZMII0>; 279 zmii-device = <&ZMII0>;
278 zmii-channel = <0>; 280 zmii-channel = <0>;
279 rgmii-device = <&RGMII0>; 281 rgmii-device = <&RGMII0>;
@@ -286,23 +288,23 @@
286 device_type = "network"; 288 device_type = "network";
287 compatible = "ibm,emac-440grx", "ibm,emac-440epx", "ibm,emac4"; 289 compatible = "ibm,emac-440grx", "ibm,emac-440epx", "ibm,emac4";
288 interrupt-parent = <&EMAC1>; 290 interrupt-parent = <&EMAC1>;
289 interrupts = <0 1>; 291 interrupts = <0x0 0x1>;
290 #interrupt-cells = <1>; 292 #interrupt-cells = <1>;
291 #address-cells = <0>; 293 #address-cells = <0>;
292 #size-cells = <0>; 294 #size-cells = <0>;
293 interrupt-map = </*Status*/ 0 &UIC0 19 4 295 interrupt-map = </*Status*/ 0x0 &UIC0 0x19 0x4
294 /*Wake*/ 1 &UIC1 1f 4>; 296 /*Wake*/ 0x1 &UIC1 0x1f 0x4>;
295 reg = <ef600f00 70>; 297 reg = <0xef600f00 0x00000074>;
296 local-mac-address = [000000000000]; 298 local-mac-address = [000000000000];
297 mal-device = <&MAL0>; 299 mal-device = <&MAL0>;
298 mal-tx-channel = <1>; 300 mal-tx-channel = <1>;
299 mal-rx-channel = <1>; 301 mal-rx-channel = <1>;
300 cell-index = <1>; 302 cell-index = <1>;
301 max-frame-size = <2328>; 303 max-frame-size = <9000>;
302 rx-fifo-size = <1000>; 304 rx-fifo-size = <4096>;
303 tx-fifo-size = <800>; 305 tx-fifo-size = <2048>;
304 phy-mode = "rgmii"; 306 phy-mode = "rgmii";
305 phy-map = <00000000>; 307 phy-map = <0x00000000>;
306 zmii-device = <&ZMII0>; 308 zmii-device = <&ZMII0>;
307 zmii-channel = <1>; 309 zmii-channel = <1>;
308 rgmii-device = <&RGMII0>; 310 rgmii-device = <&RGMII0>;
@@ -319,24 +321,25 @@
319 #address-cells = <3>; 321 #address-cells = <3>;
320 compatible = "ibm,plb440grx-pci", "ibm,plb-pci"; 322 compatible = "ibm,plb440grx-pci", "ibm,plb-pci";
321 primary; 323 primary;
322 reg = <1 eec00000 8 /* Config space access */ 324 reg = <0x00000001 0xeec00000 0x00000008 /* Config space access */
323 1 eed00000 4 /* IACK */ 325 0x00000001 0xeed00000 0x00000004 /* IACK */
324 1 eed00000 4 /* Special cycle */ 326 0x00000001 0xeed00000 0x00000004 /* Special cycle */
325 1 ef400000 40>; /* Internal registers */ 327 0x00000001 0xef400000 0x00000040>; /* Internal registers */
326 328
327 /* Outbound ranges, one memory and one IO, 329 /* Outbound ranges, one memory and one IO,
328 * later cannot be changed. Chip supports a second 330 * later cannot be changed. Chip supports a second
329 * IO range but we don't use it for now 331 * IO range but we don't use it for now
330 */ 332 */
331 ranges = <02000000 0 80000000 1 80000000 0 10000000 333 ranges = <0x02000000 0x0 0x80000000 0x1 0x80000000 0x0 0x40000000
332 01000000 0 00000000 1 e8000000 0 00100000>; 334 0x01000000 0x0 0x00000000 0x1 0xe8000000 0x0 0x00010000
335 0x01000000 0x0 0x00000000 0x1 0xe8800000 0x0 0x03800000>;
333 336
334 /* Inbound 2GB range starting at 0 */ 337 /* Inbound 2GB range starting at 0 */
335 dma-ranges = <42000000 0 0 0 0 0 80000000>; 338 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
336 339
337 /* All PCI interrupts are routed to IRQ 67 */ 340 /* All PCI interrupts are routed to IRQ 67 */
338 interrupt-map-mask = <0000 0 0 0>; 341 interrupt-map-mask = <0x0 0x0 0x0 0x0>;
339 interrupt-map = < 0000 0 0 0 &UIC2 3 8 >; 342 interrupt-map = < 0x0 0x0 0x0 0x0 &UIC2 0x3 0x8 >;
340 }; 343 };
341 }; 344 };
342 345
diff --git a/arch/powerpc/boot/dts/sam440ep.dts b/arch/powerpc/boot/dts/sam440ep.dts
new file mode 100644
index 000000000000..f0663be10421
--- /dev/null
+++ b/arch/powerpc/boot/dts/sam440ep.dts
@@ -0,0 +1,293 @@
1/*
2 * Device Tree Source for ACube Sam440ep based off bamboo.dts code
3 * original copyrights below
4 *
5 * Copyright (c) 2006, 2007 IBM Corp.
6 * Josh Boyer <jwboyer@linux.vnet.ibm.com>
7 *
8 * Modified from bamboo.dts for sam440ep:
9 * Copyright 2008 Giuseppe Coviello <gicoviello@gmail.com>
10 *
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without
13 * any warranty of any kind, whether express or implied.
14 */
15
16/dts-v1/;
17
18/ {
19 #address-cells = <2>;
20 #size-cells = <1>;
21 model = "acube,sam440ep";
22 compatible = "acube,sam440ep";
23
24 aliases {
25 ethernet0 = &EMAC0;
26 ethernet1 = &EMAC1;
27 serial0 = &UART0;
28 serial1 = &UART1;
29 serial2 = &UART2;
30 serial3 = &UART3;
31 };
32
33 cpus {
34 #address-cells = <1>;
35 #size-cells = <0>;
36
37 cpu@0 {
38 device_type = "cpu";
39 model = "PowerPC,440EP";
40 reg = <0>;
41 clock-frequency = <0>; /* Filled in by zImage */
42 timebase-frequency = <0>; /* Filled in by zImage */
43 i-cache-line-size = <32>;
44 d-cache-line-size = <32>;
45 i-cache-size = <32768>;
46 d-cache-size = <32768>;
47 dcr-controller;
48 dcr-access-method = "native";
49 };
50 };
51
52 memory {
53 device_type = "memory";
54 reg = <0 0 0>; /* Filled in by zImage */
55 };
56
57 UIC0: interrupt-controller0 {
58 compatible = "ibm,uic-440ep","ibm,uic";
59 interrupt-controller;
60 cell-index = <0>;
61 dcr-reg = <0x0c0 9>;
62 #address-cells = <0>;
63 #size-cells = <0>;
64 #interrupt-cells = <2>;
65 };
66
67 UIC1: interrupt-controller1 {
68 compatible = "ibm,uic-440ep","ibm,uic";
69 interrupt-controller;
70 cell-index = <1>;
71 dcr-reg = <0x0d0 9>;
72 #address-cells = <0>;
73 #size-cells = <0>;
74 #interrupt-cells = <2>;
75 interrupts = <0x1e 4 0x1f 4>; /* cascade */
76 interrupt-parent = <&UIC0>;
77 };
78
79 SDR0: sdr {
80 compatible = "ibm,sdr-440ep";
81 dcr-reg = <0x00e 2>;
82 };
83
84 CPR0: cpr {
85 compatible = "ibm,cpr-440ep";
86 dcr-reg = <0x00c 2>;
87 };
88
89 plb {
90 compatible = "ibm,plb-440ep", "ibm,plb-440gp", "ibm,plb4";
91 #address-cells = <2>;
92 #size-cells = <1>;
93 ranges;
94 clock-frequency = <0>; /* Filled in by zImage */
95
96 SDRAM0: sdram {
97 compatible = "ibm,sdram-440ep", "ibm,sdram-405gp";
98 dcr-reg = <0x010 2>;
99 };
100
101 DMA0: dma {
102 compatible = "ibm,dma-440ep", "ibm,dma-440gp";
103 dcr-reg = <0x100 0x027>;
104 };
105
106 MAL0: mcmal {
107 compatible = "ibm,mcmal-440ep", "ibm,mcmal-440gp", "ibm,mcmal";
108 dcr-reg = <0x180 0x062>;
109 num-tx-chans = <4>;
110 num-rx-chans = <2>;
111 interrupt-parent = <&MAL0>;
112 interrupts = <0 1 2 3 4>;
113 #interrupt-cells = <1>;
114 #address-cells = <0>;
115 #size-cells = <0>;
116 interrupt-map = </*TXEOB*/ 0 &UIC0 10 4
117 /*RXEOB*/ 1 &UIC0 11 4
118 /*SERR*/ 2 &UIC1 0 4
119 /*TXDE*/ 3 &UIC1 1 4
120 /*RXDE*/ 4 &UIC1 2 4>;
121 };
122
123 POB0: opb {
124 compatible = "ibm,opb-440ep", "ibm,opb-440gp", "ibm,opb";
125 #address-cells = <1>;
126 #size-cells = <1>;
127 /* Bamboo is oddball in the 44x world and doesn't use the ERPN
128 * bits.
129 */
130 ranges = <0x00000000 0 0x00000000 0x80000000
131 0x80000000 0 0x80000000 0x80000000>;
132 interrupt-parent = <&UIC1>;
133 interrupts = <7 4>;
134 clock-frequency = <0>; /* Filled in by zImage */
135
136 EBC0: ebc {
137 compatible = "ibm,ebc-440ep", "ibm,ebc-440gp", "ibm,ebc";
138 dcr-reg = <0x012 2>;
139 #address-cells = <2>;
140 #size-cells = <1>;
141 clock-frequency = <0>; /* Filled in by zImage */
142 interrupts = <5 1>;
143 interrupt-parent = <&UIC1>;
144 };
145
146 UART0: serial@ef600300 {
147 device_type = "serial";
148 compatible = "ns16550";
149 reg = <0xef600300 8>;
150 virtual-reg = <0xef600300>;
151 clock-frequency = <0>; /* Filled in by zImage */
152 current-speed = <0x1c200>;
153 interrupt-parent = <&UIC0>;
154 interrupts = <0 4>;
155 };
156
157 UART1: serial@ef600400 {
158 device_type = "serial";
159 compatible = "ns16550";
160 reg = <0xef600400 8>;
161 virtual-reg = <0xef600400>;
162 clock-frequency = <0>;
163 current-speed = <0>;
164 interrupt-parent = <&UIC0>;
165 interrupts = <1 4>;
166 };
167
168 UART2: serial@ef600500 {
169 device_type = "serial";
170 compatible = "ns16550";
171 reg = <0xef600500 8>;
172 virtual-reg = <0xef600500>;
173 clock-frequency = <0>;
174 current-speed = <0>;
175 interrupt-parent = <&UIC0>;
176 interrupts = <3 4>;
177 };
178
179 UART3: serial@ef600600 {
180 device_type = "serial";
181 compatible = "ns16550";
182 reg = <0xef600600 8>;
183 virtual-reg = <0xef600600>;
184 clock-frequency = <0>;
185 current-speed = <0>;
186 interrupt-parent = <&UIC0>;
187 interrupts = <4 4>;
188 };
189
190 IIC0: i2c@ef600700 {
191 #address-cells = <1>;
192 #size-cells = <0>;
193 compatible = "ibm,iic-440ep", "ibm,iic-440gp", "ibm,iic";
194 index = <0>;
195 reg = <0xef600700 0x14>;
196 interrupt-parent = <&UIC0>;
197 interrupts = <2 4>;
198 rtc@68 {
199 compatible = "stm,m41t80";
200 reg = <0x68>;
201 };
202 };
203
204 IIC1: i2c@ef600800 {
205 compatible = "ibm,iic-440ep", "ibm,iic-440gp", "ibm,iic";
206 index = <5>;
207 reg = <0xef600800 0x14>;
208 interrupt-parent = <&UIC0>;
209 interrupts = <7 4>;
210 };
211
212 ZMII0: emac-zmii@ef600d00 {
213 compatible = "ibm,zmii-440ep", "ibm,zmii-440gp", "ibm,zmii";
214 reg = <0xef600d00 0xc>;
215 };
216
217 EMAC0: ethernet@ef600e00 {
218 linux,network-index = <0>;
219 device_type = "network";
220 compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac";
221 interrupt-parent = <&UIC1>;
222 interrupts = <0x1c 4 0x1d 4>;
223 reg = <0xef600e00 0x70>;
224 local-mac-address = [000000000000];
225 mal-device = <&MAL0>;
226 mal-tx-channel = <0 1>;
227 mal-rx-channel = <0>;
228 cell-index = <0>;
229 max-frame-size = <0x5dc>;
230 rx-fifo-size = <0x1000>;
231 tx-fifo-size = <0x800>;
232 phy-mode = "rmii";
233 phy-map = <00000000>;
234 zmii-device = <&ZMII0>;
235 zmii-channel = <0>;
236 };
237
238 EMAC1: ethernet@ef600f00 {
239 linux,network-index = <1>;
240 device_type = "network";
241 compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac";
242 interrupt-parent = <&UIC1>;
243 interrupts = <0x1e 4 0x1f 4>;
244 reg = <0xef600f00 0x70>;
245 local-mac-address = [000000000000];
246 mal-device = <&MAL0>;
247 mal-tx-channel = <2 3>;
248 mal-rx-channel = <1>;
249 cell-index = <1>;
250 max-frame-size = <0x5dc>;
251 rx-fifo-size = <0x1000>;
252 tx-fifo-size = <0x800>;
253 phy-mode = "rmii";
254 phy-map = <00000000>;
255 zmii-device = <&ZMII0>;
256 zmii-channel = <1>;
257 };
258 usb@ef601000 {
259 compatible = "ohci-be";
260 reg = <0xef601000 0x80>;
261 interrupts = <8 4 9 4>;
262 interrupt-parent = <&UIC1>;
263 };
264 };
265
266 PCI0: pci@ec000000 {
267 device_type = "pci";
268 #interrupt-cells = <1>;
269 #size-cells = <2>;
270 #address-cells = <3>;
271 compatible = "ibm,plb440ep-pci", "ibm,plb-pci";
272 primary;
273 reg = <0 0xeec00000 8 /* Config space access */
274 0 0xeed00000 4 /* IACK */
275 0 0xeed00000 4 /* Special cycle */
276 0 0xef400000 0x40>; /* Internal registers */
277
278 /* Outbound ranges, one memory and one IO,
279 * later cannot be changed. Chip supports a second
280 * IO range but we don't use it for now
281 */
282 ranges = <0x02000000 0 0xa0000000 0 0xa0000000 0 0x20000000
283 0x01000000 0 0x00000000 0 0xe8000000 0 0x00010000>;
284
285 /* Inbound 2GB range starting at 0 */
286 dma-ranges = <0x42000000 0 0 0 0 0 0x80000000>;
287 };
288 };
289
290 chosen {
291 linux,stdout-path = "/plb/opb/serial@ef600300";
292 };
293};
diff --git a/arch/powerpc/boot/dts/sbc8349.dts b/arch/powerpc/boot/dts/sbc8349.dts
index 3839d4b7d6a7..45f789b56709 100644
--- a/arch/powerpc/boot/dts/sbc8349.dts
+++ b/arch/powerpc/boot/dts/sbc8349.dts
@@ -95,6 +95,41 @@
95 mode = "cpu"; 95 mode = "cpu";
96 }; 96 };
97 97
98 dma@82a8 {
99 #address-cells = <1>;
100 #size-cells = <1>;
101 compatible = "fsl,mpc8349-dma", "fsl,elo-dma";
102 reg = <0x82a8 4>;
103 ranges = <0 0x8100 0x1a8>;
104 interrupt-parent = <&ipic>;
105 interrupts = <71 8>;
106 cell-index = <0>;
107 dma-channel@0 {
108 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
109 reg = <0 0x80>;
110 interrupt-parent = <&ipic>;
111 interrupts = <71 8>;
112 };
113 dma-channel@80 {
114 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
115 reg = <0x80 0x80>;
116 interrupt-parent = <&ipic>;
117 interrupts = <71 8>;
118 };
119 dma-channel@100 {
120 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
121 reg = <0x100 0x80>;
122 interrupt-parent = <&ipic>;
123 interrupts = <71 8>;
124 };
125 dma-channel@180 {
126 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
127 reg = <0x180 0x28>;
128 interrupt-parent = <&ipic>;
129 interrupts = <71 8>;
130 };
131 };
132
98 /* phy type (ULPI or SERIAL) are only types supported for MPH */ 133 /* phy type (ULPI or SERIAL) are only types supported for MPH */
99 /* port = 0 or 1 */ 134 /* port = 0 or 1 */
100 usb@22000 { 135 usb@22000 {
@@ -186,19 +221,15 @@
186 interrupt-parent = <&ipic>; 221 interrupt-parent = <&ipic>;
187 }; 222 };
188 223
189 /* May need to remove if on a part without crypto engine */
190 crypto@30000 { 224 crypto@30000 {
191 model = "SEC2"; 225 compatible = "fsl,sec2.0";
192 compatible = "talitos";
193 reg = <0x30000 0x10000>; 226 reg = <0x30000 0x10000>;
194 interrupts = <11 0x8>; 227 interrupts = <11 0x8>;
195 interrupt-parent = <&ipic>; 228 interrupt-parent = <&ipic>;
196 num-channels = <4>; 229 fsl,num-channels = <4>;
197 channel-fifo-len = <24>; 230 fsl,channel-fifo-len = <24>;
198 exec-units-mask = <0x0000007e>; 231 fsl,exec-units-mask = <0x7e>;
199 /* desc mask is for rev2.0, 232 fsl,descriptor-types-mask = <0x01010ebf>;
200 * we need runtime fixup for >2.0 */
201 descriptor-types-mask = <0x01010ebf>;
202 }; 233 };
203 234
204 /* IPIC 235 /* IPIC
diff --git a/arch/powerpc/boot/dts/sbc8548.dts b/arch/powerpc/boot/dts/sbc8548.dts
index 22d967178fe9..333552b4e90d 100644
--- a/arch/powerpc/boot/dts/sbc8548.dts
+++ b/arch/powerpc/boot/dts/sbc8548.dts
@@ -44,6 +44,7 @@
44 timebase-frequency = <0>; // From uboot 44 timebase-frequency = <0>; // From uboot
45 bus-frequency = <0>; 45 bus-frequency = <0>;
46 clock-frequency = <0>; 46 clock-frequency = <0>;
47 next-level-cache = <&L2>;
47 }; 48 };
48 }; 49 };
49 50
@@ -161,7 +162,7 @@
161 interrupts = <0x12 0x2>; 162 interrupts = <0x12 0x2>;
162 }; 163 };
163 164
164 l2-cache-controller@20000 { 165 L2: l2-cache-controller@20000 {
165 compatible = "fsl,8548-l2-cache-controller"; 166 compatible = "fsl,8548-l2-cache-controller";
166 reg = <0x20000 0x1000>; 167 reg = <0x20000 0x1000>;
167 cache-line-size = <0x20>; // 32 bytes 168 cache-line-size = <0x20>; // 32 bytes
@@ -192,6 +193,47 @@
192 dfsrr; 193 dfsrr;
193 }; 194 };
194 195
196 dma@21300 {
197 #address-cells = <1>;
198 #size-cells = <1>;
199 compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma";
200 reg = <0x21300 0x4>;
201 ranges = <0x0 0x21100 0x200>;
202 cell-index = <0>;
203 dma-channel@0 {
204 compatible = "fsl,mpc8548-dma-channel",
205 "fsl,eloplus-dma-channel";
206 reg = <0x0 0x80>;
207 cell-index = <0>;
208 interrupt-parent = <&mpic>;
209 interrupts = <20 2>;
210 };
211 dma-channel@80 {
212 compatible = "fsl,mpc8548-dma-channel",
213 "fsl,eloplus-dma-channel";
214 reg = <0x80 0x80>;
215 cell-index = <1>;
216 interrupt-parent = <&mpic>;
217 interrupts = <21 2>;
218 };
219 dma-channel@100 {
220 compatible = "fsl,mpc8548-dma-channel",
221 "fsl,eloplus-dma-channel";
222 reg = <0x100 0x80>;
223 cell-index = <2>;
224 interrupt-parent = <&mpic>;
225 interrupts = <22 2>;
226 };
227 dma-channel@180 {
228 compatible = "fsl,mpc8548-dma-channel",
229 "fsl,eloplus-dma-channel";
230 reg = <0x180 0x80>;
231 cell-index = <3>;
232 interrupt-parent = <&mpic>;
233 interrupts = <23 2>;
234 };
235 };
236
195 mdio@24520 { 237 mdio@24520 {
196 #address-cells = <1>; 238 #address-cells = <1>;
197 #size-cells = <0>; 239 #size-cells = <0>;
@@ -262,15 +304,24 @@
262 fsl,has-rstcr; 304 fsl,has-rstcr;
263 }; 305 };
264 306
307 crypto@30000 {
308 compatible = "fsl,sec2.1", "fsl,sec2.0";
309 reg = <0x30000 0x10000>;
310 interrupts = <45 2>;
311 interrupt-parent = <&mpic>;
312 fsl,num-channels = <4>;
313 fsl,channel-fifo-len = <24>;
314 fsl,exec-units-mask = <0xfe>;
315 fsl,descriptor-types-mask = <0x12b0ebf>;
316 };
317
265 mpic: pic@40000 { 318 mpic: pic@40000 {
266 interrupt-controller; 319 interrupt-controller;
267 #address-cells = <0>; 320 #address-cells = <0>;
268 #size-cells = <0>;
269 #interrupt-cells = <2>; 321 #interrupt-cells = <2>;
270 reg = <0x40000 0x40000>; 322 reg = <0x40000 0x40000>;
271 compatible = "chrp,open-pic"; 323 compatible = "chrp,open-pic";
272 device_type = "open-pic"; 324 device_type = "open-pic";
273 big-endian;
274 }; 325 };
275 }; 326 };
276 327
diff --git a/arch/powerpc/boot/dts/sbc8560.dts b/arch/powerpc/boot/dts/sbc8560.dts
index 0476802fba60..db3632ef9888 100644
--- a/arch/powerpc/boot/dts/sbc8560.dts
+++ b/arch/powerpc/boot/dts/sbc8560.dts
@@ -43,6 +43,7 @@
43 timebase-frequency = <0>; // From uboot 43 timebase-frequency = <0>; // From uboot
44 bus-frequency = <0>; 44 bus-frequency = <0>;
45 clock-frequency = <0>; 45 clock-frequency = <0>;
46 next-level-cache = <&L2>;
46 }; 47 };
47 }; 48 };
48 49
@@ -66,7 +67,7 @@
66 interrupts = <0x12 0x2>; 67 interrupts = <0x12 0x2>;
67 }; 68 };
68 69
69 l2-cache-controller@20000 { 70 L2: l2-cache-controller@20000 {
70 compatible = "fsl,8560-l2-cache-controller"; 71 compatible = "fsl,8560-l2-cache-controller";
71 reg = <0x20000 0x1000>; 72 reg = <0x20000 0x1000>;
72 cache-line-size = <0x20>; // 32 bytes 73 cache-line-size = <0x20>; // 32 bytes
@@ -97,6 +98,47 @@
97 dfsrr; 98 dfsrr;
98 }; 99 };
99 100
101 dma@21300 {
102 #address-cells = <1>;
103 #size-cells = <1>;
104 compatible = "fsl,mpc8560-dma", "fsl,eloplus-dma";
105 reg = <0x21300 0x4>;
106 ranges = <0x0 0x21100 0x200>;
107 cell-index = <0>;
108 dma-channel@0 {
109 compatible = "fsl,mpc8560-dma-channel",
110 "fsl,eloplus-dma-channel";
111 reg = <0x0 0x80>;
112 cell-index = <0>;
113 interrupt-parent = <&mpic>;
114 interrupts = <20 2>;
115 };
116 dma-channel@80 {
117 compatible = "fsl,mpc8560-dma-channel",
118 "fsl,eloplus-dma-channel";
119 reg = <0x80 0x80>;
120 cell-index = <1>;
121 interrupt-parent = <&mpic>;
122 interrupts = <21 2>;
123 };
124 dma-channel@100 {
125 compatible = "fsl,mpc8560-dma-channel",
126 "fsl,eloplus-dma-channel";
127 reg = <0x100 0x80>;
128 cell-index = <2>;
129 interrupt-parent = <&mpic>;
130 interrupts = <22 2>;
131 };
132 dma-channel@180 {
133 compatible = "fsl,mpc8560-dma-channel",
134 "fsl,eloplus-dma-channel";
135 reg = <0x180 0x80>;
136 cell-index = <3>;
137 interrupt-parent = <&mpic>;
138 interrupts = <23 2>;
139 };
140 };
141
100 mdio@24520 { 142 mdio@24520 {
101 #address-cells = <1>; 143 #address-cells = <1>;
102 #size-cells = <0>; 144 #size-cells = <0>;
@@ -155,8 +197,8 @@
155 mpic: pic@40000 { 197 mpic: pic@40000 {
156 interrupt-controller; 198 interrupt-controller;
157 #address-cells = <0>; 199 #address-cells = <0>;
158 #size-cells = <0>;
159 #interrupt-cells = <2>; 200 #interrupt-cells = <2>;
201 compatible = "chrp,open-pic";
160 reg = <0x40000 0x40000>; 202 reg = <0x40000 0x40000>;
161 device_type = "open-pic"; 203 device_type = "open-pic";
162 }; 204 };
diff --git a/arch/powerpc/boot/dts/sbc8641d.dts b/arch/powerpc/boot/dts/sbc8641d.dts
index 3eebeec157b3..9652456158fb 100644
--- a/arch/powerpc/boot/dts/sbc8641d.dts
+++ b/arch/powerpc/boot/dts/sbc8641d.dts
@@ -151,6 +151,47 @@
151 dfsrr; 151 dfsrr;
152 }; 152 };
153 153
154 dma@21300 {
155 #address-cells = <1>;
156 #size-cells = <1>;
157 compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma";
158 reg = <0x21300 0x4>;
159 ranges = <0x0 0x21100 0x200>;
160 cell-index = <0>;
161 dma-channel@0 {
162 compatible = "fsl,mpc8641-dma-channel",
163 "fsl,eloplus-dma-channel";
164 reg = <0x0 0x80>;
165 cell-index = <0>;
166 interrupt-parent = <&mpic>;
167 interrupts = <20 2>;
168 };
169 dma-channel@80 {
170 compatible = "fsl,mpc8641-dma-channel",
171 "fsl,eloplus-dma-channel";
172 reg = <0x80 0x80>;
173 cell-index = <1>;
174 interrupt-parent = <&mpic>;
175 interrupts = <21 2>;
176 };
177 dma-channel@100 {
178 compatible = "fsl,mpc8641-dma-channel",
179 "fsl,eloplus-dma-channel";
180 reg = <0x100 0x80>;
181 cell-index = <2>;
182 interrupt-parent = <&mpic>;
183 interrupts = <22 2>;
184 };
185 dma-channel@180 {
186 compatible = "fsl,mpc8641-dma-channel",
187 "fsl,eloplus-dma-channel";
188 reg = <0x180 0x80>;
189 cell-index = <3>;
190 interrupt-parent = <&mpic>;
191 interrupts = <23 2>;
192 };
193 };
194
154 mdio@24520 { 195 mdio@24520 {
155 #address-cells = <1>; 196 #address-cells = <1>;
156 #size-cells = <0>; 197 #size-cells = <0>;
diff --git a/arch/powerpc/boot/dts/sequoia.dts b/arch/powerpc/boot/dts/sequoia.dts
index 72d67564bdfc..72d15f075d34 100644
--- a/arch/powerpc/boot/dts/sequoia.dts
+++ b/arch/powerpc/boot/dts/sequoia.dts
@@ -12,12 +12,14 @@
12 * 12 *
13 */ 13 */
14 14
15/dts-v1/;
16
15/ { 17/ {
16 #address-cells = <2>; 18 #address-cells = <2>;
17 #size-cells = <1>; 19 #size-cells = <1>;
18 model = "amcc,sequoia"; 20 model = "amcc,sequoia";
19 compatible = "amcc,sequoia"; 21 compatible = "amcc,sequoia";
20 dcr-parent = <&/cpus/cpu@0>; 22 dcr-parent = <&{/cpus/cpu@0}>;
21 23
22 aliases { 24 aliases {
23 ethernet0 = &EMAC0; 25 ethernet0 = &EMAC0;
@@ -35,13 +37,13 @@
35 cpu@0 { 37 cpu@0 {
36 device_type = "cpu"; 38 device_type = "cpu";
37 model = "PowerPC,440EPx"; 39 model = "PowerPC,440EPx";
38 reg = <0>; 40 reg = <0x00000000>;
39 clock-frequency = <0>; /* Filled in by zImage */ 41 clock-frequency = <0>; /* Filled in by zImage */
40 timebase-frequency = <0>; /* Filled in by zImage */ 42 timebase-frequency = <0>; /* Filled in by zImage */
41 i-cache-line-size = <20>; 43 i-cache-line-size = <32>;
42 d-cache-line-size = <20>; 44 d-cache-line-size = <32>;
43 i-cache-size = <8000>; 45 i-cache-size = <32768>;
44 d-cache-size = <8000>; 46 d-cache-size = <32768>;
45 dcr-controller; 47 dcr-controller;
46 dcr-access-method = "native"; 48 dcr-access-method = "native";
47 }; 49 };
@@ -49,14 +51,14 @@
49 51
50 memory { 52 memory {
51 device_type = "memory"; 53 device_type = "memory";
52 reg = <0 0 0>; /* Filled in by zImage */ 54 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by zImage */
53 }; 55 };
54 56
55 UIC0: interrupt-controller0 { 57 UIC0: interrupt-controller0 {
56 compatible = "ibm,uic-440epx","ibm,uic"; 58 compatible = "ibm,uic-440epx","ibm,uic";
57 interrupt-controller; 59 interrupt-controller;
58 cell-index = <0>; 60 cell-index = <0>;
59 dcr-reg = <0c0 009>; 61 dcr-reg = <0x0c0 0x009>;
60 #address-cells = <0>; 62 #address-cells = <0>;
61 #size-cells = <0>; 63 #size-cells = <0>;
62 #interrupt-cells = <2>; 64 #interrupt-cells = <2>;
@@ -66,11 +68,11 @@
66 compatible = "ibm,uic-440epx","ibm,uic"; 68 compatible = "ibm,uic-440epx","ibm,uic";
67 interrupt-controller; 69 interrupt-controller;
68 cell-index = <1>; 70 cell-index = <1>;
69 dcr-reg = <0d0 009>; 71 dcr-reg = <0x0d0 0x009>;
70 #address-cells = <0>; 72 #address-cells = <0>;
71 #size-cells = <0>; 73 #size-cells = <0>;
72 #interrupt-cells = <2>; 74 #interrupt-cells = <2>;
73 interrupts = <1e 4 1f 4>; /* cascade */ 75 interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
74 interrupt-parent = <&UIC0>; 76 interrupt-parent = <&UIC0>;
75 }; 77 };
76 78
@@ -78,22 +80,22 @@
78 compatible = "ibm,uic-440epx","ibm,uic"; 80 compatible = "ibm,uic-440epx","ibm,uic";
79 interrupt-controller; 81 interrupt-controller;
80 cell-index = <2>; 82 cell-index = <2>;
81 dcr-reg = <0e0 009>; 83 dcr-reg = <0x0e0 0x009>;
82 #address-cells = <0>; 84 #address-cells = <0>;
83 #size-cells = <0>; 85 #size-cells = <0>;
84 #interrupt-cells = <2>; 86 #interrupt-cells = <2>;
85 interrupts = <1c 4 1d 4>; /* cascade */ 87 interrupts = <0x1c 0x4 0x1d 0x4>; /* cascade */
86 interrupt-parent = <&UIC0>; 88 interrupt-parent = <&UIC0>;
87 }; 89 };
88 90
89 SDR0: sdr { 91 SDR0: sdr {
90 compatible = "ibm,sdr-440epx", "ibm,sdr-440ep"; 92 compatible = "ibm,sdr-440epx", "ibm,sdr-440ep";
91 dcr-reg = <00e 002>; 93 dcr-reg = <0x00e 0x002>;
92 }; 94 };
93 95
94 CPR0: cpr { 96 CPR0: cpr {
95 compatible = "ibm,cpr-440epx", "ibm,cpr-440ep"; 97 compatible = "ibm,cpr-440epx", "ibm,cpr-440ep";
96 dcr-reg = <00c 002>; 98 dcr-reg = <0x00c 0x002>;
97 }; 99 };
98 100
99 plb { 101 plb {
@@ -105,44 +107,44 @@
105 107
106 SDRAM0: sdram { 108 SDRAM0: sdram {
107 compatible = "ibm,sdram-440epx", "ibm,sdram-44x-ddr2denali"; 109 compatible = "ibm,sdram-440epx", "ibm,sdram-44x-ddr2denali";
108 dcr-reg = <010 2>; 110 dcr-reg = <0x010 0x002>;
109 }; 111 };
110 112
111 DMA0: dma { 113 DMA0: dma {
112 compatible = "ibm,dma-440epx", "ibm,dma-4xx"; 114 compatible = "ibm,dma-440epx", "ibm,dma-4xx";
113 dcr-reg = <100 027>; 115 dcr-reg = <0x100 0x027>;
114 }; 116 };
115 117
116 MAL0: mcmal { 118 MAL0: mcmal {
117 compatible = "ibm,mcmal-440epx", "ibm,mcmal2"; 119 compatible = "ibm,mcmal-440epx", "ibm,mcmal2";
118 dcr-reg = <180 62>; 120 dcr-reg = <0x180 0x062>;
119 num-tx-chans = <2>; 121 num-tx-chans = <2>;
120 num-rx-chans = <2>; 122 num-rx-chans = <2>;
121 interrupt-parent = <&MAL0>; 123 interrupt-parent = <&MAL0>;
122 interrupts = <0 1 2 3 4>; 124 interrupts = <0x0 0x1 0x2 0x3 0x4>;
123 #interrupt-cells = <1>; 125 #interrupt-cells = <1>;
124 #address-cells = <0>; 126 #address-cells = <0>;
125 #size-cells = <0>; 127 #size-cells = <0>;
126 interrupt-map = </*TXEOB*/ 0 &UIC0 a 4 128 interrupt-map = </*TXEOB*/ 0x0 &UIC0 0xa 0x4
127 /*RXEOB*/ 1 &UIC0 b 4 129 /*RXEOB*/ 0x1 &UIC0 0xb 0x4
128 /*SERR*/ 2 &UIC1 0 4 130 /*SERR*/ 0x2 &UIC1 0x0 0x4
129 /*TXDE*/ 3 &UIC1 1 4 131 /*TXDE*/ 0x3 &UIC1 0x1 0x4
130 /*RXDE*/ 4 &UIC1 2 4>; 132 /*RXDE*/ 0x4 &UIC1 0x2 0x4>;
131 interrupt-map-mask = <ffffffff>; 133 interrupt-map-mask = <0xffffffff>;
132 }; 134 };
133 135
134 USB1: usb@e0000400 { 136 USB1: usb@e0000400 {
135 compatible = "ohci-be"; 137 compatible = "ohci-be";
136 reg = <0 e0000400 60>; 138 reg = <0x00000000 0xe0000400 0x00000060>;
137 interrupt-parent = <&UIC0>; 139 interrupt-parent = <&UIC0>;
138 interrupts = <15 8>; 140 interrupts = <0x15 0x8>;
139 }; 141 };
140 142
141 USB0: ehci@e0000300 { 143 USB0: ehci@e0000300 {
142 compatible = "ibm,usb-ehci-440epx", "usb-ehci"; 144 compatible = "ibm,usb-ehci-440epx", "usb-ehci";
143 interrupt-parent = <&UIC0>; 145 interrupt-parent = <&UIC0>;
144 interrupts = <1a 4>; 146 interrupts = <0x1a 0x4>;
145 reg = <0 e0000300 90 0 e0000390 70>; 147 reg = <0x00000000 0xe0000300 0x00000090 0x00000000 0xe0000390 0x00000070>;
146 big-endian; 148 big-endian;
147 }; 149 };
148 150
@@ -150,50 +152,50 @@
150 compatible = "ibm,opb-440epx", "ibm,opb"; 152 compatible = "ibm,opb-440epx", "ibm,opb";
151 #address-cells = <1>; 153 #address-cells = <1>;
152 #size-cells = <1>; 154 #size-cells = <1>;
153 ranges = <00000000 1 00000000 80000000 155 ranges = <0x00000000 0x00000001 0x00000000 0x80000000
154 80000000 1 80000000 80000000>; 156 0x80000000 0x00000001 0x80000000 0x80000000>;
155 interrupt-parent = <&UIC1>; 157 interrupt-parent = <&UIC1>;
156 interrupts = <7 4>; 158 interrupts = <0x7 0x4>;
157 clock-frequency = <0>; /* Filled in by zImage */ 159 clock-frequency = <0>; /* Filled in by zImage */
158 160
159 EBC0: ebc { 161 EBC0: ebc {
160 compatible = "ibm,ebc-440epx", "ibm,ebc"; 162 compatible = "ibm,ebc-440epx", "ibm,ebc";
161 dcr-reg = <012 2>; 163 dcr-reg = <0x012 0x002>;
162 #address-cells = <2>; 164 #address-cells = <2>;
163 #size-cells = <1>; 165 #size-cells = <1>;
164 clock-frequency = <0>; /* Filled in by zImage */ 166 clock-frequency = <0>; /* Filled in by zImage */
165 interrupts = <5 1>; 167 interrupts = <0x5 0x1>;
166 interrupt-parent = <&UIC1>; 168 interrupt-parent = <&UIC1>;
167 169
168 nor_flash@0,0 { 170 nor_flash@0,0 {
169 compatible = "amd,s29gl256n", "cfi-flash"; 171 compatible = "amd,s29gl256n", "cfi-flash";
170 bank-width = <2>; 172 bank-width = <2>;
171 reg = <0 000000 4000000>; 173 reg = <0x00000000 0x00000000 0x04000000>;
172 #address-cells = <1>; 174 #address-cells = <1>;
173 #size-cells = <1>; 175 #size-cells = <1>;
174 partition@0 { 176 partition@0 {
175 label = "Kernel"; 177 label = "Kernel";
176 reg = <0 180000>; 178 reg = <0x00000000 0x00180000>;
177 }; 179 };
178 partition@180000 { 180 partition@180000 {
179 label = "ramdisk"; 181 label = "ramdisk";
180 reg = <180000 200000>; 182 reg = <0x00180000 0x00200000>;
181 }; 183 };
182 partition@380000 { 184 partition@380000 {
183 label = "file system"; 185 label = "file system";
184 reg = <380000 3aa0000>; 186 reg = <0x00380000 0x03aa0000>;
185 }; 187 };
186 partition@3e20000 { 188 partition@3e20000 {
187 label = "kozio"; 189 label = "kozio";
188 reg = <3e20000 140000>; 190 reg = <0x03e20000 0x00140000>;
189 }; 191 };
190 partition@3f60000 { 192 partition@3f60000 {
191 label = "env"; 193 label = "env";
192 reg = <3f60000 40000>; 194 reg = <0x03f60000 0x00040000>;
193 }; 195 };
194 partition@3fa0000 { 196 partition@3fa0000 {
195 label = "u-boot"; 197 label = "u-boot";
196 reg = <3fa0000 60000>; 198 reg = <0x03fa0000 0x00060000>;
197 }; 199 };
198 }; 200 };
199 201
@@ -202,69 +204,69 @@
202 UART0: serial@ef600300 { 204 UART0: serial@ef600300 {
203 device_type = "serial"; 205 device_type = "serial";
204 compatible = "ns16550"; 206 compatible = "ns16550";
205 reg = <ef600300 8>; 207 reg = <0xef600300 0x00000008>;
206 virtual-reg = <ef600300>; 208 virtual-reg = <0xef600300>;
207 clock-frequency = <0>; /* Filled in by zImage */ 209 clock-frequency = <0>; /* Filled in by zImage */
208 current-speed = <1c200>; 210 current-speed = <115200>;
209 interrupt-parent = <&UIC0>; 211 interrupt-parent = <&UIC0>;
210 interrupts = <0 4>; 212 interrupts = <0x0 0x4>;
211 }; 213 };
212 214
213 UART1: serial@ef600400 { 215 UART1: serial@ef600400 {
214 device_type = "serial"; 216 device_type = "serial";
215 compatible = "ns16550"; 217 compatible = "ns16550";
216 reg = <ef600400 8>; 218 reg = <0xef600400 0x00000008>;
217 virtual-reg = <ef600400>; 219 virtual-reg = <0xef600400>;
218 clock-frequency = <0>; 220 clock-frequency = <0>;
219 current-speed = <0>; 221 current-speed = <0>;
220 interrupt-parent = <&UIC0>; 222 interrupt-parent = <&UIC0>;
221 interrupts = <1 4>; 223 interrupts = <0x1 0x4>;
222 }; 224 };
223 225
224 UART2: serial@ef600500 { 226 UART2: serial@ef600500 {
225 device_type = "serial"; 227 device_type = "serial";
226 compatible = "ns16550"; 228 compatible = "ns16550";
227 reg = <ef600500 8>; 229 reg = <0xef600500 0x00000008>;
228 virtual-reg = <ef600500>; 230 virtual-reg = <0xef600500>;
229 clock-frequency = <0>; 231 clock-frequency = <0>;
230 current-speed = <0>; 232 current-speed = <0>;
231 interrupt-parent = <&UIC1>; 233 interrupt-parent = <&UIC1>;
232 interrupts = <3 4>; 234 interrupts = <0x3 0x4>;
233 }; 235 };
234 236
235 UART3: serial@ef600600 { 237 UART3: serial@ef600600 {
236 device_type = "serial"; 238 device_type = "serial";
237 compatible = "ns16550"; 239 compatible = "ns16550";
238 reg = <ef600600 8>; 240 reg = <0xef600600 0x00000008>;
239 virtual-reg = <ef600600>; 241 virtual-reg = <0xef600600>;
240 clock-frequency = <0>; 242 clock-frequency = <0>;
241 current-speed = <0>; 243 current-speed = <0>;
242 interrupt-parent = <&UIC1>; 244 interrupt-parent = <&UIC1>;
243 interrupts = <4 4>; 245 interrupts = <0x4 0x4>;
244 }; 246 };
245 247
246 IIC0: i2c@ef600700 { 248 IIC0: i2c@ef600700 {
247 compatible = "ibm,iic-440epx", "ibm,iic"; 249 compatible = "ibm,iic-440epx", "ibm,iic";
248 reg = <ef600700 14>; 250 reg = <0xef600700 0x00000014>;
249 interrupt-parent = <&UIC0>; 251 interrupt-parent = <&UIC0>;
250 interrupts = <2 4>; 252 interrupts = <0x2 0x4>;
251 }; 253 };
252 254
253 IIC1: i2c@ef600800 { 255 IIC1: i2c@ef600800 {
254 compatible = "ibm,iic-440epx", "ibm,iic"; 256 compatible = "ibm,iic-440epx", "ibm,iic";
255 reg = <ef600800 14>; 257 reg = <0xef600800 0x00000014>;
256 interrupt-parent = <&UIC0>; 258 interrupt-parent = <&UIC0>;
257 interrupts = <7 4>; 259 interrupts = <0x7 0x4>;
258 }; 260 };
259 261
260 ZMII0: emac-zmii@ef600d00 { 262 ZMII0: emac-zmii@ef600d00 {
261 compatible = "ibm,zmii-440epx", "ibm,zmii"; 263 compatible = "ibm,zmii-440epx", "ibm,zmii";
262 reg = <ef600d00 c>; 264 reg = <0xef600d00 0x0000000c>;
263 }; 265 };
264 266
265 RGMII0: emac-rgmii@ef601000 { 267 RGMII0: emac-rgmii@ef601000 {
266 compatible = "ibm,rgmii-440epx", "ibm,rgmii"; 268 compatible = "ibm,rgmii-440epx", "ibm,rgmii";
267 reg = <ef601000 8>; 269 reg = <0xef601000 0x00000008>;
268 has-mdio; 270 has-mdio;
269 }; 271 };
270 272
@@ -272,23 +274,23 @@
272 device_type = "network"; 274 device_type = "network";
273 compatible = "ibm,emac-440epx", "ibm,emac4"; 275 compatible = "ibm,emac-440epx", "ibm,emac4";
274 interrupt-parent = <&EMAC0>; 276 interrupt-parent = <&EMAC0>;
275 interrupts = <0 1>; 277 interrupts = <0x0 0x1>;
276 #interrupt-cells = <1>; 278 #interrupt-cells = <1>;
277 #address-cells = <0>; 279 #address-cells = <0>;
278 #size-cells = <0>; 280 #size-cells = <0>;
279 interrupt-map = </*Status*/ 0 &UIC0 18 4 281 interrupt-map = </*Status*/ 0x0 &UIC0 0x18 0x4
280 /*Wake*/ 1 &UIC1 1d 4>; 282 /*Wake*/ 0x1 &UIC1 0x1d 0x4>;
281 reg = <ef600e00 70>; 283 reg = <0xef600e00 0x00000074>;
282 local-mac-address = [000000000000]; 284 local-mac-address = [000000000000];
283 mal-device = <&MAL0>; 285 mal-device = <&MAL0>;
284 mal-tx-channel = <0>; 286 mal-tx-channel = <0>;
285 mal-rx-channel = <0>; 287 mal-rx-channel = <0>;
286 cell-index = <0>; 288 cell-index = <0>;
287 max-frame-size = <2328>; 289 max-frame-size = <9000>;
288 rx-fifo-size = <1000>; 290 rx-fifo-size = <4096>;
289 tx-fifo-size = <800>; 291 tx-fifo-size = <2048>;
290 phy-mode = "rgmii"; 292 phy-mode = "rgmii";
291 phy-map = <00000000>; 293 phy-map = <0x00000000>;
292 zmii-device = <&ZMII0>; 294 zmii-device = <&ZMII0>;
293 zmii-channel = <0>; 295 zmii-channel = <0>;
294 rgmii-device = <&RGMII0>; 296 rgmii-device = <&RGMII0>;
@@ -301,23 +303,23 @@
301 device_type = "network"; 303 device_type = "network";
302 compatible = "ibm,emac-440epx", "ibm,emac4"; 304 compatible = "ibm,emac-440epx", "ibm,emac4";
303 interrupt-parent = <&EMAC1>; 305 interrupt-parent = <&EMAC1>;
304 interrupts = <0 1>; 306 interrupts = <0x0 0x1>;
305 #interrupt-cells = <1>; 307 #interrupt-cells = <1>;
306 #address-cells = <0>; 308 #address-cells = <0>;
307 #size-cells = <0>; 309 #size-cells = <0>;
308 interrupt-map = </*Status*/ 0 &UIC0 19 4 310 interrupt-map = </*Status*/ 0x0 &UIC0 0x19 0x4
309 /*Wake*/ 1 &UIC1 1f 4>; 311 /*Wake*/ 0x1 &UIC1 0x1f 0x4>;
310 reg = <ef600f00 70>; 312 reg = <0xef600f00 0x00000074>;
311 local-mac-address = [000000000000]; 313 local-mac-address = [000000000000];
312 mal-device = <&MAL0>; 314 mal-device = <&MAL0>;
313 mal-tx-channel = <1>; 315 mal-tx-channel = <1>;
314 mal-rx-channel = <1>; 316 mal-rx-channel = <1>;
315 cell-index = <1>; 317 cell-index = <1>;
316 max-frame-size = <2328>; 318 max-frame-size = <9000>;
317 rx-fifo-size = <1000>; 319 rx-fifo-size = <4096>;
318 tx-fifo-size = <800>; 320 tx-fifo-size = <2048>;
319 phy-mode = "rgmii"; 321 phy-mode = "rgmii";
320 phy-map = <00000000>; 322 phy-map = <0x00000000>;
321 zmii-device = <&ZMII0>; 323 zmii-device = <&ZMII0>;
322 zmii-channel = <1>; 324 zmii-channel = <1>;
323 rgmii-device = <&RGMII0>; 325 rgmii-device = <&RGMII0>;
@@ -334,10 +336,10 @@
334 #address-cells = <3>; 336 #address-cells = <3>;
335 compatible = "ibm,plb440epx-pci", "ibm,plb-pci"; 337 compatible = "ibm,plb440epx-pci", "ibm,plb-pci";
336 primary; 338 primary;
337 reg = <1 eec00000 8 /* Config space access */ 339 reg = <0x00000001 0xeec00000 0x00000008 /* Config space access */
338 1 eed00000 4 /* IACK */ 340 0x00000001 0xeed00000 0x00000004 /* IACK */
339 1 eed00000 4 /* Special cycle */ 341 0x00000001 0xeed00000 0x00000004 /* Special cycle */
340 1 ef400000 40>; /* Internal registers */ 342 0x00000001 0xef400000 0x00000040>; /* Internal registers */
341 343
342 /* Outbound ranges, one memory and one IO, 344 /* Outbound ranges, one memory and one IO,
343 * later cannot be changed. Chip supports a second 345 * later cannot be changed. Chip supports a second
@@ -347,16 +349,16 @@
347 * I/O 1 E800 0000 1 E800 FFFF 64KB 349 * I/O 1 E800 0000 1 E800 FFFF 64KB
348 * I/O 1 E880 0000 1 EBFF FFFF 56MB 350 * I/O 1 E880 0000 1 EBFF FFFF 56MB
349 */ 351 */
350 ranges = <02000000 0 80000000 1 80000000 0 40000000 352 ranges = <0x02000000 0x00000000 0x80000000 0x00000001 0x80000000 0x00000000 0x40000000
351 01000000 0 00000000 1 e8000000 0 00010000 353 0x01000000 0x00000000 0x00000000 0x00000001 0xe8000000 0x00000000 0x00010000
352 01000000 0 00000000 1 e8800000 0 03800000>; 354 0x01000000 0x00000000 0x00000000 0x00000001 0xe8800000 0x00000000 0x03800000>;
353 355
354 /* Inbound 2GB range starting at 0 */ 356 /* Inbound 2GB range starting at 0 */
355 dma-ranges = <42000000 0 0 0 0 0 80000000>; 357 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
356 358
357 /* All PCI interrupts are routed to IRQ 67 */ 359 /* All PCI interrupts are routed to IRQ 67 */
358 interrupt-map-mask = <0000 0 0 0>; 360 interrupt-map-mask = <0x0 0x0 0x0 0x0>;
359 interrupt-map = < 0000 0 0 0 &UIC2 3 8 >; 361 interrupt-map = < 0x0 0x0 0x0 0x0 &UIC2 0x3 0x8 >;
360 }; 362 };
361 }; 363 };
362 364
diff --git a/arch/powerpc/boot/dts/storcenter.dts b/arch/powerpc/boot/dts/storcenter.dts
index 5893816c0bce..eab680ce10da 100644
--- a/arch/powerpc/boot/dts/storcenter.dts
+++ b/arch/powerpc/boot/dts/storcenter.dts
@@ -95,6 +95,7 @@
95 95
96 mpic: interrupt-controller@40000 { 96 mpic: interrupt-controller@40000 {
97 #interrupt-cells = <2>; 97 #interrupt-cells = <2>;
98 #address-cells = <0>;
98 device_type = "open-pic"; 99 device_type = "open-pic";
99 compatible = "chrp,open-pic"; 100 compatible = "chrp,open-pic";
100 interrupt-controller; 101 interrupt-controller;
diff --git a/arch/powerpc/boot/dts/stx_gp3_8560.dts b/arch/powerpc/boot/dts/stx_gp3_8560.dts
index f81fd7fdb29e..fcd1db6ca0a8 100644
--- a/arch/powerpc/boot/dts/stx_gp3_8560.dts
+++ b/arch/powerpc/boot/dts/stx_gp3_8560.dts
@@ -38,6 +38,7 @@
38 timebase-frequency = <0>; 38 timebase-frequency = <0>;
39 bus-frequency = <0>; 39 bus-frequency = <0>;
40 clock-frequency = <0>; 40 clock-frequency = <0>;
41 next-level-cache = <&L2>;
41 }; 42 };
42 }; 43 };
43 44
@@ -62,7 +63,7 @@
62 interrupts = <18 2>; 63 interrupts = <18 2>;
63 }; 64 };
64 65
65 l2-cache-controller@20000 { 66 L2: l2-cache-controller@20000 {
66 compatible = "fsl,8540-l2-cache-controller"; 67 compatible = "fsl,8540-l2-cache-controller";
67 reg = <0x20000 0x1000>; 68 reg = <0x20000 0x1000>;
68 cache-line-size = <32>; 69 cache-line-size = <32>;
@@ -82,6 +83,47 @@
82 dfsrr; 83 dfsrr;
83 }; 84 };
84 85
86 dma@21300 {
87 #address-cells = <1>;
88 #size-cells = <1>;
89 compatible = "fsl,mpc8560-dma", "fsl,eloplus-dma";
90 reg = <0x21300 0x4>;
91 ranges = <0x0 0x21100 0x200>;
92 cell-index = <0>;
93 dma-channel@0 {
94 compatible = "fsl,mpc8560-dma-channel",
95 "fsl,eloplus-dma-channel";
96 reg = <0x0 0x80>;
97 cell-index = <0>;
98 interrupt-parent = <&mpic>;
99 interrupts = <20 2>;
100 };
101 dma-channel@80 {
102 compatible = "fsl,mpc8560-dma-channel",
103 "fsl,eloplus-dma-channel";
104 reg = <0x80 0x80>;
105 cell-index = <1>;
106 interrupt-parent = <&mpic>;
107 interrupts = <21 2>;
108 };
109 dma-channel@100 {
110 compatible = "fsl,mpc8560-dma-channel",
111 "fsl,eloplus-dma-channel";
112 reg = <0x100 0x80>;
113 cell-index = <2>;
114 interrupt-parent = <&mpic>;
115 interrupts = <22 2>;
116 };
117 dma-channel@180 {
118 compatible = "fsl,mpc8560-dma-channel",
119 "fsl,eloplus-dma-channel";
120 reg = <0x180 0x80>;
121 cell-index = <3>;
122 interrupt-parent = <&mpic>;
123 interrupts = <23 2>;
124 };
125 };
126
85 mdio@24520 { 127 mdio@24520 {
86 #address-cells = <1>; 128 #address-cells = <1>;
87 #size-cells = <0>; 129 #size-cells = <0>;
@@ -131,6 +173,7 @@
131 #address-cells = <0>; 173 #address-cells = <0>;
132 #interrupt-cells = <2>; 174 #interrupt-cells = <2>;
133 reg = <0x40000 0x40000>; 175 reg = <0x40000 0x40000>;
176 compatible = "chrp,open-pic";
134 device_type = "open-pic"; 177 device_type = "open-pic";
135 }; 178 };
136 179
diff --git a/arch/powerpc/boot/dts/taishan.dts b/arch/powerpc/boot/dts/taishan.dts
index e808e1c5593a..058438f9629b 100644
--- a/arch/powerpc/boot/dts/taishan.dts
+++ b/arch/powerpc/boot/dts/taishan.dts
@@ -10,12 +10,14 @@
10 * any warranty of any kind, whether express or implied. 10 * any warranty of any kind, whether express or implied.
11 */ 11 */
12 12
13/dts-v1/;
14
13/ { 15/ {
14 #address-cells = <2>; 16 #address-cells = <2>;
15 #size-cells = <1>; 17 #size-cells = <1>;
16 model = "amcc,taishan"; 18 model = "amcc,taishan";
17 compatible = "amcc,taishan"; 19 compatible = "amcc,taishan";
18 dcr-parent = <&/cpus/cpu@0>; 20 dcr-parent = <&{/cpus/cpu@0}>;
19 21
20 aliases { 22 aliases {
21 ethernet0 = &EMAC2; 23 ethernet0 = &EMAC2;
@@ -31,13 +33,13 @@
31 cpu@0 { 33 cpu@0 {
32 device_type = "cpu"; 34 device_type = "cpu";
33 model = "PowerPC,440GX"; 35 model = "PowerPC,440GX";
34 reg = <0>; 36 reg = <0x00000000>;
35 clock-frequency = <2FAF0800>; // 800MHz 37 clock-frequency = <800000000>; // 800MHz
36 timebase-frequency = <0>; // Filled in by zImage 38 timebase-frequency = <0>; // Filled in by zImage
37 i-cache-line-size = <32>; 39 i-cache-line-size = <50>;
38 d-cache-line-size = <32>; 40 d-cache-line-size = <50>;
39 i-cache-size = <8000>; /* 32 kB */ 41 i-cache-size = <32768>; /* 32 kB */
40 d-cache-size = <8000>; /* 32 kB */ 42 d-cache-size = <32768>; /* 32 kB */
41 dcr-controller; 43 dcr-controller;
42 dcr-access-method = "native"; 44 dcr-access-method = "native";
43 }; 45 };
@@ -45,7 +47,7 @@
45 47
46 memory { 48 memory {
47 device_type = "memory"; 49 device_type = "memory";
48 reg = <0 0 0>; // Filled in by zImage 50 reg = <0x00000000 0x00000000 0x00000000>; // Filled in by zImage
49 }; 51 };
50 52
51 53
@@ -53,7 +55,7 @@
53 compatible = "ibm,uic-440gx", "ibm,uic"; 55 compatible = "ibm,uic-440gx", "ibm,uic";
54 interrupt-controller; 56 interrupt-controller;
55 cell-index = <3>; 57 cell-index = <3>;
56 dcr-reg = <200 009>; 58 dcr-reg = <0x200 0x009>;
57 #address-cells = <0>; 59 #address-cells = <0>;
58 #size-cells = <0>; 60 #size-cells = <0>;
59 #interrupt-cells = <2>; 61 #interrupt-cells = <2>;
@@ -64,11 +66,11 @@
64 compatible = "ibm,uic-440gx", "ibm,uic"; 66 compatible = "ibm,uic-440gx", "ibm,uic";
65 interrupt-controller; 67 interrupt-controller;
66 cell-index = <0>; 68 cell-index = <0>;
67 dcr-reg = <0c0 009>; 69 dcr-reg = <0x0c0 0x009>;
68 #address-cells = <0>; 70 #address-cells = <0>;
69 #size-cells = <0>; 71 #size-cells = <0>;
70 #interrupt-cells = <2>; 72 #interrupt-cells = <2>;
71 interrupts = <01 4 00 4>; /* cascade - first non-critical */ 73 interrupts = <0x1 0x4 0x0 0x4>; /* cascade - first non-critical */
72 interrupt-parent = <&UICB0>; 74 interrupt-parent = <&UICB0>;
73 75
74 }; 76 };
@@ -77,11 +79,11 @@
77 compatible = "ibm,uic-440gx", "ibm,uic"; 79 compatible = "ibm,uic-440gx", "ibm,uic";
78 interrupt-controller; 80 interrupt-controller;
79 cell-index = <1>; 81 cell-index = <1>;
80 dcr-reg = <0d0 009>; 82 dcr-reg = <0x0d0 0x009>;
81 #address-cells = <0>; 83 #address-cells = <0>;
82 #size-cells = <0>; 84 #size-cells = <0>;
83 #interrupt-cells = <2>; 85 #interrupt-cells = <2>;
84 interrupts = <03 4 02 4>; /* cascade */ 86 interrupts = <0x3 0x4 0x2 0x4>; /* cascade */
85 interrupt-parent = <&UICB0>; 87 interrupt-parent = <&UICB0>;
86 }; 88 };
87 89
@@ -89,29 +91,29 @@
89 compatible = "ibm,uic-440gx", "ibm,uic"; 91 compatible = "ibm,uic-440gx", "ibm,uic";
90 interrupt-controller; 92 interrupt-controller;
91 cell-index = <2>; /* was 1 */ 93 cell-index = <2>; /* was 1 */
92 dcr-reg = <210 009>; 94 dcr-reg = <0x210 0x009>;
93 #address-cells = <0>; 95 #address-cells = <0>;
94 #size-cells = <0>; 96 #size-cells = <0>;
95 #interrupt-cells = <2>; 97 #interrupt-cells = <2>;
96 interrupts = <05 4 04 4>; /* cascade */ 98 interrupts = <0x5 0x4 0x4 0x4>; /* cascade */
97 interrupt-parent = <&UICB0>; 99 interrupt-parent = <&UICB0>;
98 }; 100 };
99 101
100 102
101 CPC0: cpc { 103 CPC0: cpc {
102 compatible = "ibm,cpc-440gp"; 104 compatible = "ibm,cpc-440gp";
103 dcr-reg = <0b0 003 0e0 010>; 105 dcr-reg = <0x0b0 0x003 0x0e0 0x010>;
104 // FIXME: anything else? 106 // FIXME: anything else?
105 }; 107 };
106 108
107 L2C0: l2c { 109 L2C0: l2c {
108 compatible = "ibm,l2-cache-440gx", "ibm,l2-cache"; 110 compatible = "ibm,l2-cache-440gx", "ibm,l2-cache";
109 dcr-reg = <20 8 /* Internal SRAM DCR's */ 111 dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */
110 30 8>; /* L2 cache DCR's */ 112 0x030 0x008>; /* L2 cache DCR's */
111 cache-line-size = <20>; /* 32 bytes */ 113 cache-line-size = <32>; /* 32 bytes */
112 cache-size = <40000>; /* L2, 256K */ 114 cache-size = <262144>; /* L2, 256K */
113 interrupt-parent = <&UIC2>; 115 interrupt-parent = <&UIC2>;
114 interrupts = <17 1>; 116 interrupts = <0x17 0x1>;
115 }; 117 };
116 118
117 plb { 119 plb {
@@ -119,41 +121,41 @@
119 #address-cells = <2>; 121 #address-cells = <2>;
120 #size-cells = <1>; 122 #size-cells = <1>;
121 ranges; 123 ranges;
122 clock-frequency = <9896800>; // 160MHz 124 clock-frequency = <160000000>; // 160MHz
123 125
124 SDRAM0: memory-controller { 126 SDRAM0: memory-controller {
125 compatible = "ibm,sdram-440gp"; 127 compatible = "ibm,sdram-440gp";
126 dcr-reg = <010 2>; 128 dcr-reg = <0x010 0x002>;
127 // FIXME: anything else? 129 // FIXME: anything else?
128 }; 130 };
129 131
130 SRAM0: sram { 132 SRAM0: sram {
131 compatible = "ibm,sram-440gp"; 133 compatible = "ibm,sram-440gp";
132 dcr-reg = <020 8 00a 1>; 134 dcr-reg = <0x020 0x008 0x00a 0x001>;
133 }; 135 };
134 136
135 DMA0: dma { 137 DMA0: dma {
136 // FIXME: ??? 138 // FIXME: ???
137 compatible = "ibm,dma-440gp"; 139 compatible = "ibm,dma-440gp";
138 dcr-reg = <100 027>; 140 dcr-reg = <0x100 0x027>;
139 }; 141 };
140 142
141 MAL0: mcmal { 143 MAL0: mcmal {
142 compatible = "ibm,mcmal-440gx", "ibm,mcmal2"; 144 compatible = "ibm,mcmal-440gx", "ibm,mcmal2";
143 dcr-reg = <180 62>; 145 dcr-reg = <0x180 0x062>;
144 num-tx-chans = <4>; 146 num-tx-chans = <4>;
145 num-rx-chans = <4>; 147 num-rx-chans = <4>;
146 interrupt-parent = <&MAL0>; 148 interrupt-parent = <&MAL0>;
147 interrupts = <0 1 2 3 4>; 149 interrupts = <0x0 0x1 0x2 0x3 0x4>;
148 #interrupt-cells = <1>; 150 #interrupt-cells = <1>;
149 #address-cells = <0>; 151 #address-cells = <0>;
150 #size-cells = <0>; 152 #size-cells = <0>;
151 interrupt-map = </*TXEOB*/ 0 &UIC0 a 4 153 interrupt-map = </*TXEOB*/ 0x0 &UIC0 0xa 0x4
152 /*RXEOB*/ 1 &UIC0 b 4 154 /*RXEOB*/ 0x1 &UIC0 0xb 0x4
153 /*SERR*/ 2 &UIC1 0 4 155 /*SERR*/ 0x2 &UIC1 0x0 0x4
154 /*TXDE*/ 3 &UIC1 1 4 156 /*TXDE*/ 0x3 &UIC1 0x1 0x4
155 /*RXDE*/ 4 &UIC1 2 4>; 157 /*RXDE*/ 0x4 &UIC1 0x2 0x4>;
156 interrupt-map-mask = <ffffffff>; 158 interrupt-map-mask = <0xffffffff>;
157 }; 159 };
158 160
159 POB0: opb { 161 POB0: opb {
@@ -162,29 +164,56 @@
162 #size-cells = <1>; 164 #size-cells = <1>;
163 /* Wish there was a nicer way of specifying a full 32-bit 165 /* Wish there was a nicer way of specifying a full 32-bit
164 range */ 166 range */
165 ranges = <00000000 1 00000000 80000000 167 ranges = <0x00000000 0x00000001 0x00000000 0x80000000
166 80000000 1 80000000 80000000>; 168 0x80000000 0x00000001 0x80000000 0x80000000>;
167 dcr-reg = <090 00b>; 169 dcr-reg = <0x090 0x00b>;
168 interrupt-parent = <&UIC1>; 170 interrupt-parent = <&UIC1>;
169 interrupts = <7 4>; 171 interrupts = <0x7 0x4>;
170 clock-frequency = <4C4B400>; // 80MHz 172 clock-frequency = <80000000>; // 80MHz
171 173
172 174
173 EBC0: ebc { 175 EBC0: ebc {
174 compatible = "ibm,ebc-440gx", "ibm,ebc"; 176 compatible = "ibm,ebc-440gx", "ibm,ebc";
175 dcr-reg = <012 2>; 177 dcr-reg = <0x012 0x002>;
176 #address-cells = <2>; 178 #address-cells = <2>;
177 #size-cells = <1>; 179 #size-cells = <1>;
178 clock-frequency = <4C4B400>; // 80MHz 180 clock-frequency = <80000000>; // 80MHz
179 181
180 /* ranges property is supplied by zImage 182 /* ranges property is supplied by zImage
181 * based on firmware's configuration of the 183 * based on firmware's configuration of the
182 * EBC bridge */ 184 * EBC bridge */
183 185
184 interrupts = <5 4>; 186 interrupts = <0x5 0x4>;
185 interrupt-parent = <&UIC1>; 187 interrupt-parent = <&UIC1>;
186 188
187 /* TODO: Add other EBC devices */ 189 nor_flash@0,0 {
190 compatible = "cfi-flash";
191 bank-width = <4>;
192 device-width = <2>;
193 reg = <0x0 0x0 0x4000000>;
194 #address-cells = <1>;
195 #size-cells = <1>;
196 partition@0 {
197 label = "kernel";
198 reg = <0x0 0x180000>;
199 };
200 partition@180000 {
201 label = "root";
202 reg = <0x180000 0x200000>;
203 };
204 partition@380000 {
205 label = "user";
206 reg = <0x380000 0x3bc0000>;
207 };
208 partition@3f40000 {
209 label = "env";
210 reg = <0x3f40000 0x80000>;
211 };
212 partition@3fc0000 {
213 label = "u-boot";
214 reg = <0x3fc0000 0x40000>;
215 };
216 };
188 }; 217 };
189 218
190 219
@@ -192,103 +221,103 @@
192 UART0: serial@40000200 { 221 UART0: serial@40000200 {
193 device_type = "serial"; 222 device_type = "serial";
194 compatible = "ns16550"; 223 compatible = "ns16550";
195 reg = <40000200 8>; 224 reg = <0x40000200 0x00000008>;
196 virtual-reg = <e0000200>; 225 virtual-reg = <0xe0000200>;
197 clock-frequency = <A8C000>; 226 clock-frequency = <11059200>;
198 current-speed = <1C200>; /* 115200 */ 227 current-speed = <115200>; /* 115200 */
199 interrupt-parent = <&UIC0>; 228 interrupt-parent = <&UIC0>;
200 interrupts = <0 4>; 229 interrupts = <0x0 0x4>;
201 }; 230 };
202 231
203 UART1: serial@40000300 { 232 UART1: serial@40000300 {
204 device_type = "serial"; 233 device_type = "serial";
205 compatible = "ns16550"; 234 compatible = "ns16550";
206 reg = <40000300 8>; 235 reg = <0x40000300 0x00000008>;
207 virtual-reg = <e0000300>; 236 virtual-reg = <0xe0000300>;
208 clock-frequency = <A8C000>; 237 clock-frequency = <11059200>;
209 current-speed = <1C200>; /* 115200 */ 238 current-speed = <115200>; /* 115200 */
210 interrupt-parent = <&UIC0>; 239 interrupt-parent = <&UIC0>;
211 interrupts = <1 4>; 240 interrupts = <0x1 0x4>;
212 }; 241 };
213 242
214 IIC0: i2c@40000400 { 243 IIC0: i2c@40000400 {
215 /* FIXME */ 244 /* FIXME */
216 compatible = "ibm,iic-440gp", "ibm,iic"; 245 compatible = "ibm,iic-440gp", "ibm,iic";
217 reg = <40000400 14>; 246 reg = <0x40000400 0x00000014>;
218 interrupt-parent = <&UIC0>; 247 interrupt-parent = <&UIC0>;
219 interrupts = <2 4>; 248 interrupts = <0x2 0x4>;
220 }; 249 };
221 IIC1: i2c@40000500 { 250 IIC1: i2c@40000500 {
222 /* FIXME */ 251 /* FIXME */
223 compatible = "ibm,iic-440gp", "ibm,iic"; 252 compatible = "ibm,iic-440gp", "ibm,iic";
224 reg = <40000500 14>; 253 reg = <0x40000500 0x00000014>;
225 interrupt-parent = <&UIC0>; 254 interrupt-parent = <&UIC0>;
226 interrupts = <3 4>; 255 interrupts = <0x3 0x4>;
227 }; 256 };
228 257
229 GPIO0: gpio@40000700 { 258 GPIO0: gpio@40000700 {
230 /* FIXME */ 259 /* FIXME */
231 compatible = "ibm,gpio-440gp"; 260 compatible = "ibm,gpio-440gp";
232 reg = <40000700 20>; 261 reg = <0x40000700 0x00000020>;
233 }; 262 };
234 263
235 ZMII0: emac-zmii@40000780 { 264 ZMII0: emac-zmii@40000780 {
236 compatible = "ibm,zmii-440gx", "ibm,zmii"; 265 compatible = "ibm,zmii-440gx", "ibm,zmii";
237 reg = <40000780 c>; 266 reg = <0x40000780 0x0000000c>;
238 }; 267 };
239 268
240 RGMII0: emac-rgmii@40000790 { 269 RGMII0: emac-rgmii@40000790 {
241 compatible = "ibm,rgmii"; 270 compatible = "ibm,rgmii";
242 reg = <40000790 8>; 271 reg = <0x40000790 0x00000008>;
243 }; 272 };
244 273
245 TAH0: emac-tah@40000b50 { 274 TAH0: emac-tah@40000b50 {
246 compatible = "ibm,tah-440gx", "ibm,tah"; 275 compatible = "ibm,tah-440gx", "ibm,tah";
247 reg = <40000b50 30>; 276 reg = <0x40000b50 0x00000030>;
248 }; 277 };
249 278
250 TAH1: emac-tah@40000d50 { 279 TAH1: emac-tah@40000d50 {
251 compatible = "ibm,tah-440gx", "ibm,tah"; 280 compatible = "ibm,tah-440gx", "ibm,tah";
252 reg = <40000d50 30>; 281 reg = <0x40000d50 0x00000030>;
253 }; 282 };
254 283
255 EMAC0: ethernet@40000800 { 284 EMAC0: ethernet@40000800 {
256 unused = <1>; 285 unused = <0x1>;
257 device_type = "network"; 286 device_type = "network";
258 compatible = "ibm,emac-440gx", "ibm,emac4"; 287 compatible = "ibm,emac-440gx", "ibm,emac4";
259 interrupt-parent = <&UIC1>; 288 interrupt-parent = <&UIC1>;
260 interrupts = <1c 4 1d 4>; 289 interrupts = <0x1c 0x4 0x1d 0x4>;
261 reg = <40000800 70>; 290 reg = <0x40000800 0x00000074>;
262 local-mac-address = [000000000000]; // Filled in by zImage 291 local-mac-address = [000000000000]; // Filled in by zImage
263 mal-device = <&MAL0>; 292 mal-device = <&MAL0>;
264 mal-tx-channel = <0>; 293 mal-tx-channel = <0>;
265 mal-rx-channel = <0>; 294 mal-rx-channel = <0>;
266 cell-index = <0>; 295 cell-index = <0>;
267 max-frame-size = <5dc>; 296 max-frame-size = <1500>;
268 rx-fifo-size = <1000>; 297 rx-fifo-size = <4096>;
269 tx-fifo-size = <800>; 298 tx-fifo-size = <2048>;
270 phy-mode = "rmii"; 299 phy-mode = "rmii";
271 phy-map = <00000001>; 300 phy-map = <0x00000001>;
272 zmii-device = <&ZMII0>; 301 zmii-device = <&ZMII0>;
273 zmii-channel = <0>; 302 zmii-channel = <0>;
274 }; 303 };
275 EMAC1: ethernet@40000900 { 304 EMAC1: ethernet@40000900 {
276 unused = <1>; 305 unused = <0x1>;
277 device_type = "network"; 306 device_type = "network";
278 compatible = "ibm,emac-440gx", "ibm,emac4"; 307 compatible = "ibm,emac-440gx", "ibm,emac4";
279 interrupt-parent = <&UIC1>; 308 interrupt-parent = <&UIC1>;
280 interrupts = <1e 4 1f 4>; 309 interrupts = <0x1e 0x4 0x1f 0x4>;
281 reg = <40000900 70>; 310 reg = <0x40000900 0x00000074>;
282 local-mac-address = [000000000000]; // Filled in by zImage 311 local-mac-address = [000000000000]; // Filled in by zImage
283 mal-device = <&MAL0>; 312 mal-device = <&MAL0>;
284 mal-tx-channel = <1>; 313 mal-tx-channel = <1>;
285 mal-rx-channel = <1>; 314 mal-rx-channel = <1>;
286 cell-index = <1>; 315 cell-index = <1>;
287 max-frame-size = <5dc>; 316 max-frame-size = <1500>;
288 rx-fifo-size = <1000>; 317 rx-fifo-size = <4096>;
289 tx-fifo-size = <800>; 318 tx-fifo-size = <2048>;
290 phy-mode = "rmii"; 319 phy-mode = "rmii";
291 phy-map = <00000001>; 320 phy-map = <0x00000001>;
292 zmii-device = <&ZMII0>; 321 zmii-device = <&ZMII0>;
293 zmii-channel = <1>; 322 zmii-channel = <1>;
294 }; 323 };
@@ -297,18 +326,18 @@
297 device_type = "network"; 326 device_type = "network";
298 compatible = "ibm,emac-440gx", "ibm,emac4"; 327 compatible = "ibm,emac-440gx", "ibm,emac4";
299 interrupt-parent = <&UIC2>; 328 interrupt-parent = <&UIC2>;
300 interrupts = <0 4 1 4>; 329 interrupts = <0x0 0x4 0x1 0x4>;
301 reg = <40000c00 70>; 330 reg = <0x40000c00 0x00000074>;
302 local-mac-address = [000000000000]; // Filled in by zImage 331 local-mac-address = [000000000000]; // Filled in by zImage
303 mal-device = <&MAL0>; 332 mal-device = <&MAL0>;
304 mal-tx-channel = <2>; 333 mal-tx-channel = <2>;
305 mal-rx-channel = <2>; 334 mal-rx-channel = <2>;
306 cell-index = <2>; 335 cell-index = <2>;
307 max-frame-size = <2328>; 336 max-frame-size = <9000>;
308 rx-fifo-size = <1000>; 337 rx-fifo-size = <4096>;
309 tx-fifo-size = <800>; 338 tx-fifo-size = <2048>;
310 phy-mode = "rgmii"; 339 phy-mode = "rgmii";
311 phy-map = <00000001>; 340 phy-map = <0x00000001>;
312 rgmii-device = <&RGMII0>; 341 rgmii-device = <&RGMII0>;
313 rgmii-channel = <0>; 342 rgmii-channel = <0>;
314 zmii-device = <&ZMII0>; 343 zmii-device = <&ZMII0>;
@@ -321,18 +350,18 @@
321 device_type = "network"; 350 device_type = "network";
322 compatible = "ibm,emac-440gx", "ibm,emac4"; 351 compatible = "ibm,emac-440gx", "ibm,emac4";
323 interrupt-parent = <&UIC2>; 352 interrupt-parent = <&UIC2>;
324 interrupts = <2 4 3 4>; 353 interrupts = <0x2 0x4 0x3 0x4>;
325 reg = <40000e00 70>; 354 reg = <0x40000e00 0x00000074>;
326 local-mac-address = [000000000000]; // Filled in by zImage 355 local-mac-address = [000000000000]; // Filled in by zImage
327 mal-device = <&MAL0>; 356 mal-device = <&MAL0>;
328 mal-tx-channel = <3>; 357 mal-tx-channel = <3>;
329 mal-rx-channel = <3>; 358 mal-rx-channel = <3>;
330 cell-index = <3>; 359 cell-index = <3>;
331 max-frame-size = <2328>; 360 max-frame-size = <9000>;
332 rx-fifo-size = <1000>; 361 rx-fifo-size = <4096>;
333 tx-fifo-size = <800>; 362 tx-fifo-size = <2048>;
334 phy-mode = "rgmii"; 363 phy-mode = "rgmii";
335 phy-map = <00000003>; 364 phy-map = <0x00000003>;
336 rgmii-device = <&RGMII0>; 365 rgmii-device = <&RGMII0>;
337 rgmii-channel = <1>; 366 rgmii-channel = <1>;
338 zmii-device = <&ZMII0>; 367 zmii-device = <&ZMII0>;
@@ -344,9 +373,9 @@
344 373
345 GPT0: gpt@40000a00 { 374 GPT0: gpt@40000a00 {
346 /* FIXME */ 375 /* FIXME */
347 reg = <40000a00 d4>; 376 reg = <0x40000a00 0x000000d4>;
348 interrupt-parent = <&UIC0>; 377 interrupt-parent = <&UIC0>;
349 interrupts = <12 4 13 4 14 4 15 4 16 4>; 378 interrupts = <0x12 0x4 0x13 0x4 0x14 0x4 0x15 0x4 0x16 0x4>;
350 }; 379 };
351 380
352 }; 381 };
@@ -360,34 +389,34 @@
360 primary; 389 primary;
361 large-inbound-windows; 390 large-inbound-windows;
362 enable-msi-hole; 391 enable-msi-hole;
363 reg = <2 0ec00000 8 /* Config space access */ 392 reg = <0x00000002 0x0ec00000 0x00000008 /* Config space access */
364 0 0 0 /* no IACK cycles */ 393 0x00000000 0x00000000 0x00000000 /* no IACK cycles */
365 2 0ed00000 4 /* Special cycles */ 394 0x00000002 0x0ed00000 0x00000004 /* Special cycles */
366 2 0ec80000 100 /* Internal registers */ 395 0x00000002 0x0ec80000 0x00000100 /* Internal registers */
367 2 0ec80100 fc>; /* Internal messaging registers */ 396 0x00000002 0x0ec80100 0x000000fc>; /* Internal messaging registers */
368 397
369 /* Outbound ranges, one memory and one IO, 398 /* Outbound ranges, one memory and one IO,
370 * later cannot be changed 399 * later cannot be changed
371 */ 400 */
372 ranges = <02000000 0 80000000 00000003 80000000 0 80000000 401 ranges = <0x02000000 0x00000000 0x80000000 0x00000003 0x80000000 0x00000000 0x80000000
373 01000000 0 00000000 00000002 08000000 0 00010000>; 402 0x01000000 0x00000000 0x00000000 0x00000002 0x08000000 0x00000000 0x00010000>;
374 403
375 /* Inbound 2GB range starting at 0 */ 404 /* Inbound 2GB range starting at 0 */
376 dma-ranges = <42000000 0 0 0 0 0 80000000>; 405 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
377 406
378 interrupt-map-mask = <f800 0 0 7>; 407 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
379 interrupt-map = < 408 interrupt-map = <
380 /* IDSEL 1 */ 409 /* IDSEL 1 */
381 0800 0 0 1 &UIC0 17 8 410 0x800 0x0 0x0 0x1 &UIC0 0x17 0x8
382 0800 0 0 2 &UIC0 18 8 411 0x800 0x0 0x0 0x2 &UIC0 0x18 0x8
383 0800 0 0 3 &UIC0 19 8 412 0x800 0x0 0x0 0x3 &UIC0 0x19 0x8
384 0800 0 0 4 &UIC0 1a 8 413 0x800 0x0 0x0 0x4 &UIC0 0x1a 0x8
385 414
386 /* IDSEL 2 */ 415 /* IDSEL 2 */
387 1000 0 0 1 &UIC0 18 8 416 0x1000 0x0 0x0 0x1 &UIC0 0x18 0x8
388 1000 0 0 2 &UIC0 19 8 417 0x1000 0x0 0x0 0x2 &UIC0 0x19 0x8
389 1000 0 0 3 &UIC0 1a 8 418 0x1000 0x0 0x0 0x3 &UIC0 0x1a 0x8
390 1000 0 0 4 &UIC0 17 8 419 0x1000 0x0 0x0 0x4 &UIC0 0x17 0x8
391 >; 420 >;
392 }; 421 };
393 }; 422 };
diff --git a/arch/powerpc/boot/dts/tqm5200.dts b/arch/powerpc/boot/dts/tqm5200.dts
index 773a68e00058..3008bf8830c1 100644
--- a/arch/powerpc/boot/dts/tqm5200.dts
+++ b/arch/powerpc/boot/dts/tqm5200.dts
@@ -70,6 +70,20 @@
70 fsl,has-wdt; 70 fsl,has-wdt;
71 }; 71 };
72 72
73 can@900 {
74 compatible = "fsl,mpc5200-mscan";
75 interrupts = <2 17 0>;
76 interrupt-parent = <&mpc5200_pic>;
77 reg = <0x900 0x80>;
78 };
79
80 can@980 {
81 compatible = "fsl,mpc5200-mscan";
82 interrupts = <2 18 0>;
83 interrupt-parent = <&mpc5200_pic>;
84 reg = <0x980 0x80>;
85 };
86
73 gpio@b00 { 87 gpio@b00 {
74 compatible = "fsl,mpc5200-gpio"; 88 compatible = "fsl,mpc5200-gpio";
75 reg = <0xb00 0x40>; 89 reg = <0xb00 0x40>;
diff --git a/arch/powerpc/boot/dts/tqm8540.dts b/arch/powerpc/boot/dts/tqm8540.dts
index 1addb3ae719e..e1d260b9085e 100644
--- a/arch/powerpc/boot/dts/tqm8540.dts
+++ b/arch/powerpc/boot/dts/tqm8540.dts
@@ -12,8 +12,8 @@
12/dts-v1/; 12/dts-v1/;
13 13
14/ { 14/ {
15 model = "tqm,8540"; 15 model = "tqc,tqm8540";
16 compatible = "tqm,8540", "tqm,85xx"; 16 compatible = "tqc,tqm8540";
17 #address-cells = <1>; 17 #address-cells = <1>;
18 #size-cells = <1>; 18 #size-cells = <1>;
19 19
@@ -40,6 +40,7 @@
40 timebase-frequency = <0>; 40 timebase-frequency = <0>;
41 bus-frequency = <0>; 41 bus-frequency = <0>;
42 clock-frequency = <0>; 42 clock-frequency = <0>;
43 next-level-cache = <&L2>;
43 }; 44 };
44 }; 45 };
45 46
@@ -64,7 +65,7 @@
64 interrupts = <18 2>; 65 interrupts = <18 2>;
65 }; 66 };
66 67
67 l2-cache-controller@20000 { 68 L2: l2-cache-controller@20000 {
68 compatible = "fsl,8540-l2-cache-controller"; 69 compatible = "fsl,8540-l2-cache-controller";
69 reg = <0x20000 0x1000>; 70 reg = <0x20000 0x1000>;
70 cache-line-size = <32>; 71 cache-line-size = <32>;
@@ -89,6 +90,47 @@
89 }; 90 };
90 }; 91 };
91 92
93 dma@21300 {
94 #address-cells = <1>;
95 #size-cells = <1>;
96 compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma";
97 reg = <0x21300 0x4>;
98 ranges = <0x0 0x21100 0x200>;
99 cell-index = <0>;
100 dma-channel@0 {
101 compatible = "fsl,mpc8540-dma-channel",
102 "fsl,eloplus-dma-channel";
103 reg = <0x0 0x80>;
104 cell-index = <0>;
105 interrupt-parent = <&mpic>;
106 interrupts = <20 2>;
107 };
108 dma-channel@80 {
109 compatible = "fsl,mpc8540-dma-channel",
110 "fsl,eloplus-dma-channel";
111 reg = <0x80 0x80>;
112 cell-index = <1>;
113 interrupt-parent = <&mpic>;
114 interrupts = <21 2>;
115 };
116 dma-channel@100 {
117 compatible = "fsl,mpc8540-dma-channel",
118 "fsl,eloplus-dma-channel";
119 reg = <0x100 0x80>;
120 cell-index = <2>;
121 interrupt-parent = <&mpic>;
122 interrupts = <22 2>;
123 };
124 dma-channel@180 {
125 compatible = "fsl,mpc8540-dma-channel",
126 "fsl,eloplus-dma-channel";
127 reg = <0x180 0x80>;
128 cell-index = <3>;
129 interrupt-parent = <&mpic>;
130 interrupts = <23 2>;
131 };
132 };
133
92 mdio@24520 { 134 mdio@24520 {
93 #address-cells = <1>; 135 #address-cells = <1>;
94 #size-cells = <0>; 136 #size-cells = <0>;
@@ -177,6 +219,7 @@
177 #interrupt-cells = <2>; 219 #interrupt-cells = <2>;
178 reg = <0x40000 0x40000>; 220 reg = <0x40000 0x40000>;
179 device_type = "open-pic"; 221 device_type = "open-pic";
222 compatible = "chrp,open-pic";
180 }; 223 };
181 }; 224 };
182 225
diff --git a/arch/powerpc/boot/dts/tqm8541.dts b/arch/powerpc/boot/dts/tqm8541.dts
index 9e01093f496e..d76441ec5dc7 100644
--- a/arch/powerpc/boot/dts/tqm8541.dts
+++ b/arch/powerpc/boot/dts/tqm8541.dts
@@ -12,8 +12,8 @@
12/dts-v1/; 12/dts-v1/;
13 13
14/ { 14/ {
15 model = "tqm,8541"; 15 model = "tqc,tqm8541";
16 compatible = "tqm,8541", "tqm,85xx"; 16 compatible = "tqc,tqm8541";
17 #address-cells = <1>; 17 #address-cells = <1>;
18 #size-cells = <1>; 18 #size-cells = <1>;
19 19
@@ -39,6 +39,7 @@
39 timebase-frequency = <0>; 39 timebase-frequency = <0>;
40 bus-frequency = <0>; 40 bus-frequency = <0>;
41 clock-frequency = <0>; 41 clock-frequency = <0>;
42 next-level-cache = <&L2>;
42 }; 43 };
43 }; 44 };
44 45
@@ -63,7 +64,7 @@
63 interrupts = <18 2>; 64 interrupts = <18 2>;
64 }; 65 };
65 66
66 l2-cache-controller@20000 { 67 L2: l2-cache-controller@20000 {
67 compatible = "fsl,8540-l2-cache-controller"; 68 compatible = "fsl,8540-l2-cache-controller";
68 reg = <0x20000 0x1000>; 69 reg = <0x20000 0x1000>;
69 cache-line-size = <32>; 70 cache-line-size = <32>;
@@ -88,6 +89,47 @@
88 }; 89 };
89 }; 90 };
90 91
92 dma@21300 {
93 #address-cells = <1>;
94 #size-cells = <1>;
95 compatible = "fsl,mpc8541-dma", "fsl,eloplus-dma";
96 reg = <0x21300 0x4>;
97 ranges = <0x0 0x21100 0x200>;
98 cell-index = <0>;
99 dma-channel@0 {
100 compatible = "fsl,mpc8541-dma-channel",
101 "fsl,eloplus-dma-channel";
102 reg = <0x0 0x80>;
103 cell-index = <0>;
104 interrupt-parent = <&mpic>;
105 interrupts = <20 2>;
106 };
107 dma-channel@80 {
108 compatible = "fsl,mpc8541-dma-channel",
109 "fsl,eloplus-dma-channel";
110 reg = <0x80 0x80>;
111 cell-index = <1>;
112 interrupt-parent = <&mpic>;
113 interrupts = <21 2>;
114 };
115 dma-channel@100 {
116 compatible = "fsl,mpc8541-dma-channel",
117 "fsl,eloplus-dma-channel";
118 reg = <0x100 0x80>;
119 cell-index = <2>;
120 interrupt-parent = <&mpic>;
121 interrupts = <22 2>;
122 };
123 dma-channel@180 {
124 compatible = "fsl,mpc8541-dma-channel",
125 "fsl,eloplus-dma-channel";
126 reg = <0x180 0x80>;
127 cell-index = <3>;
128 interrupt-parent = <&mpic>;
129 interrupts = <23 2>;
130 };
131 };
132
91 mdio@24520 { 133 mdio@24520 {
92 #address-cells = <1>; 134 #address-cells = <1>;
93 #size-cells = <0>; 135 #size-cells = <0>;
@@ -158,12 +200,24 @@
158 interrupt-parent = <&mpic>; 200 interrupt-parent = <&mpic>;
159 }; 201 };
160 202
203 crypto@30000 {
204 compatible = "fsl,sec2.0";
205 reg = <0x30000 0x10000>;
206 interrupts = <45 2>;
207 interrupt-parent = <&mpic>;
208 fsl,num-channels = <4>;
209 fsl,channel-fifo-len = <24>;
210 fsl,exec-units-mask = <0x7e>;
211 fsl,descriptor-types-mask = <0x01010ebf>;
212 };
213
161 mpic: pic@40000 { 214 mpic: pic@40000 {
162 interrupt-controller; 215 interrupt-controller;
163 #address-cells = <0>; 216 #address-cells = <0>;
164 #interrupt-cells = <2>; 217 #interrupt-cells = <2>;
165 reg = <0x40000 0x40000>; 218 reg = <0x40000 0x40000>;
166 device_type = "open-pic"; 219 device_type = "open-pic";
220 compatible = "chrp,open-pic";
167 }; 221 };
168 222
169 cpm@919c0 { 223 cpm@919c0 {
diff --git a/arch/powerpc/boot/dts/tqm8548-bigflash.dts b/arch/powerpc/boot/dts/tqm8548-bigflash.dts
new file mode 100644
index 000000000000..64d2d5bbcdf1
--- /dev/null
+++ b/arch/powerpc/boot/dts/tqm8548-bigflash.dts
@@ -0,0 +1,406 @@
1/*
2 * TQM8548 Device Tree Source
3 *
4 * Copyright 2006 Freescale Semiconductor Inc.
5 * Copyright 2008 Wolfgang Grandegger <wg@denx.de>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13/dts-v1/;
14
15/ {
16 model = "tqc,tqm8548";
17 compatible = "tqc,tqm8548";
18 #address-cells = <1>;
19 #size-cells = <1>;
20
21 aliases {
22 ethernet0 = &enet0;
23 ethernet1 = &enet1;
24 ethernet2 = &enet2;
25 ethernet3 = &enet3;
26
27 serial0 = &serial0;
28 serial1 = &serial1;
29 pci0 = &pci0;
30 pci1 = &pci1;
31 };
32
33 cpus {
34 #address-cells = <1>;
35 #size-cells = <0>;
36
37 PowerPC,8548@0 {
38 device_type = "cpu";
39 reg = <0>;
40 d-cache-line-size = <32>; // 32 bytes
41 i-cache-line-size = <32>; // 32 bytes
42 d-cache-size = <0x8000>; // L1, 32K
43 i-cache-size = <0x8000>; // L1, 32K
44 next-level-cache = <&L2>;
45 };
46 };
47
48 memory {
49 device_type = "memory";
50 reg = <0x00000000 0x00000000>; // Filled in by U-Boot
51 };
52
53 soc8548@a0000000 {
54 #address-cells = <1>;
55 #size-cells = <1>;
56 device_type = "soc";
57 ranges = <0x0 0xa0000000 0x100000>;
58 reg = <0xa0000000 0x1000>; // CCSRBAR
59 bus-frequency = <0>;
60
61 memory-controller@2000 {
62 compatible = "fsl,mpc8548-memory-controller";
63 reg = <0x2000 0x1000>;
64 interrupt-parent = <&mpic>;
65 interrupts = <18 2>;
66 };
67
68 L2: l2-cache-controller@20000 {
69 compatible = "fsl,mpc8548-l2-cache-controller";
70 reg = <0x20000 0x1000>;
71 cache-line-size = <32>; // 32 bytes
72 cache-size = <0x80000>; // L2, 512K
73 interrupt-parent = <&mpic>;
74 interrupts = <16 2>;
75 };
76
77 i2c@3000 {
78 #address-cells = <1>;
79 #size-cells = <0>;
80 cell-index = <0>;
81 compatible = "fsl-i2c";
82 reg = <0x3000 0x100>;
83 interrupts = <43 2>;
84 interrupt-parent = <&mpic>;
85 dfsrr;
86 };
87
88 i2c@3100 {
89 #address-cells = <1>;
90 #size-cells = <0>;
91 cell-index = <1>;
92 compatible = "fsl-i2c";
93 reg = <0x3100 0x100>;
94 interrupts = <43 2>;
95 interrupt-parent = <&mpic>;
96 dfsrr;
97 };
98
99 dma@21300 {
100 #address-cells = <1>;
101 #size-cells = <1>;
102 compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma";
103 reg = <0x21300 0x4>;
104 ranges = <0x0 0x21100 0x200>;
105 cell-index = <0>;
106 dma-channel@0 {
107 compatible = "fsl,mpc8548-dma-channel",
108 "fsl,eloplus-dma-channel";
109 reg = <0x0 0x80>;
110 cell-index = <0>;
111 interrupt-parent = <&mpic>;
112 interrupts = <20 2>;
113 };
114 dma-channel@80 {
115 compatible = "fsl,mpc8548-dma-channel",
116 "fsl,eloplus-dma-channel";
117 reg = <0x80 0x80>;
118 cell-index = <1>;
119 interrupt-parent = <&mpic>;
120 interrupts = <21 2>;
121 };
122 dma-channel@100 {
123 compatible = "fsl,mpc8548-dma-channel",
124 "fsl,eloplus-dma-channel";
125 reg = <0x100 0x80>;
126 cell-index = <2>;
127 interrupt-parent = <&mpic>;
128 interrupts = <22 2>;
129 };
130 dma-channel@180 {
131 compatible = "fsl,mpc8548-dma-channel",
132 "fsl,eloplus-dma-channel";
133 reg = <0x180 0x80>;
134 cell-index = <3>;
135 interrupt-parent = <&mpic>;
136 interrupts = <23 2>;
137 };
138 };
139
140 mdio@24520 {
141 #address-cells = <1>;
142 #size-cells = <0>;
143 compatible = "fsl,gianfar-mdio";
144 reg = <0x24520 0x20>;
145
146 phy1: ethernet-phy@0 {
147 interrupt-parent = <&mpic>;
148 interrupts = <8 1>;
149 reg = <1>;
150 device_type = "ethernet-phy";
151 };
152 phy2: ethernet-phy@1 {
153 interrupt-parent = <&mpic>;
154 interrupts = <8 1>;
155 reg = <2>;
156 device_type = "ethernet-phy";
157 };
158 phy3: ethernet-phy@3 {
159 interrupt-parent = <&mpic>;
160 interrupts = <8 1>;
161 reg = <3>;
162 device_type = "ethernet-phy";
163 };
164 phy4: ethernet-phy@4 {
165 interrupt-parent = <&mpic>;
166 interrupts = <8 1>;
167 reg = <4>;
168 device_type = "ethernet-phy";
169 };
170 phy5: ethernet-phy@5 {
171 interrupt-parent = <&mpic>;
172 interrupts = <8 1>;
173 reg = <5>;
174 device_type = "ethernet-phy";
175 };
176 };
177
178 enet0: ethernet@24000 {
179 cell-index = <0>;
180 device_type = "network";
181 model = "eTSEC";
182 compatible = "gianfar";
183 reg = <0x24000 0x1000>;
184 local-mac-address = [ 00 00 00 00 00 00 ];
185 interrupts = <29 2 30 2 34 2>;
186 interrupt-parent = <&mpic>;
187 phy-handle = <&phy2>;
188 };
189
190 enet1: ethernet@25000 {
191 cell-index = <1>;
192 device_type = "network";
193 model = "eTSEC";
194 compatible = "gianfar";
195 reg = <0x25000 0x1000>;
196 local-mac-address = [ 00 00 00 00 00 00 ];
197 interrupts = <35 2 36 2 40 2>;
198 interrupt-parent = <&mpic>;
199 phy-handle = <&phy1>;
200 };
201
202 enet2: ethernet@26000 {
203 cell-index = <2>;
204 device_type = "network";
205 model = "eTSEC";
206 compatible = "gianfar";
207 reg = <0x26000 0x1000>;
208 local-mac-address = [ 00 00 00 00 00 00 ];
209 interrupts = <31 2 32 2 33 2>;
210 interrupt-parent = <&mpic>;
211 phy-handle = <&phy3>;
212 };
213
214 enet3: ethernet@27000 {
215 cell-index = <3>;
216 device_type = "network";
217 model = "eTSEC";
218 compatible = "gianfar";
219 reg = <0x27000 0x1000>;
220 local-mac-address = [ 00 00 00 00 00 00 ];
221 interrupts = <37 2 38 2 39 2>;
222 interrupt-parent = <&mpic>;
223 phy-handle = <&phy4>;
224 };
225
226 serial0: serial@4500 {
227 cell-index = <0>;
228 device_type = "serial";
229 compatible = "ns16550";
230 reg = <0x4500 0x100>; // reg base, size
231 clock-frequency = <0>; // should we fill in in uboot?
232 current-speed = <115200>;
233 interrupts = <42 2>;
234 interrupt-parent = <&mpic>;
235 };
236
237 serial1: serial@4600 {
238 cell-index = <1>;
239 device_type = "serial";
240 compatible = "ns16550";
241 reg = <0x4600 0x100>; // reg base, size
242 clock-frequency = <0>; // should we fill in in uboot?
243 current-speed = <115200>;
244 interrupts = <42 2>;
245 interrupt-parent = <&mpic>;
246 };
247
248 global-utilities@e0000 { // global utilities reg
249 compatible = "fsl,mpc8548-guts";
250 reg = <0xe0000 0x1000>;
251 fsl,has-rstcr;
252 };
253
254 mpic: pic@40000 {
255 interrupt-controller;
256 #address-cells = <0>;
257 #interrupt-cells = <2>;
258 reg = <0x40000 0x40000>;
259 compatible = "chrp,open-pic";
260 device_type = "open-pic";
261 };
262 };
263
264 localbus@a0005000 {
265 compatible = "fsl,mpc8548-localbus", "fsl,pq3-localbus",
266 "simple-bus";
267 #address-cells = <2>;
268 #size-cells = <1>;
269 reg = <0xa0005000 0x100>; // BRx, ORx, etc.
270
271 ranges = <
272 0 0x0 0xfc000000 0x04000000 // NOR FLASH bank 1
273 1 0x0 0xf8000000 0x08000000 // NOR FLASH bank 0
274 2 0x0 0xa3000000 0x00008000 // CAN (2 x i82527)
275 3 0x0 0xa3010000 0x00008000 // NAND FLASH
276
277 >;
278
279 flash@1,0 {
280 #address-cells = <1>;
281 #size-cells = <1>;
282 compatible = "cfi-flash";
283 reg = <1 0x0 0x8000000>;
284 bank-width = <4>;
285 device-width = <1>;
286
287 partition@0 {
288 label = "kernel";
289 reg = <0x00000000 0x00200000>;
290 };
291 partition@200000 {
292 label = "root";
293 reg = <0x00200000 0x00300000>;
294 };
295 partition@500000 {
296 label = "user";
297 reg = <0x00500000 0x07a00000>;
298 };
299 partition@7f00000 {
300 label = "env1";
301 reg = <0x07f00000 0x00040000>;
302 };
303 partition@7f40000 {
304 label = "env2";
305 reg = <0x07f40000 0x00040000>;
306 };
307 partition@7f80000 {
308 label = "u-boot";
309 reg = <0x07f80000 0x00080000>;
310 read-only;
311 };
312 };
313
314 /* Note: CAN support needs be enabled in U-Boot */
315 can0@2,0 {
316 compatible = "intel,82527"; // Bosch CC770
317 reg = <2 0x0 0x100>;
318 interrupts = <4 0>;
319 interrupt-parent = <&mpic>;
320 };
321
322 can1@2,100 {
323 compatible = "intel,82527"; // Bosch CC770
324 reg = <2 0x100 0x100>;
325 interrupts = <4 0>;
326 interrupt-parent = <&mpic>;
327 };
328
329 /* Note: NAND support needs to be enabled in U-Boot */
330 upm@3,0 {
331 #address-cells = <0>;
332 #size-cells = <0>;
333 compatible = "fsl,upm-nand";
334 reg = <3 0x0 0x800>;
335 fsl,upm-addr-offset = <0x10>;
336 fsl,upm-cmd-offset = <0x08>;
337 chip-delay = <25>; // in micro-seconds
338
339 nand@0 {
340 #address-cells = <1>;
341 #size-cells = <1>;
342
343 partition@0 {
344 label = "fs";
345 reg = <0x00000000 0x01000000>;
346 };
347 };
348 };
349 };
350
351 pci0: pci@a0008000 {
352 cell-index = <0>;
353 #interrupt-cells = <1>;
354 #size-cells = <2>;
355 #address-cells = <3>;
356 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
357 device_type = "pci";
358 reg = <0xa0008000 0x1000>;
359 clock-frequency = <33333333>;
360 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
361 interrupt-map = <
362 /* IDSEL 28 */
363 0xe000 0 0 1 &mpic 2 1
364 0xe000 0 0 2 &mpic 3 1>;
365
366 interrupt-parent = <&mpic>;
367 interrupts = <24 2>;
368 bus-range = <0 0>;
369 ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000
370 0x01000000 0 0x00000000 0xa2000000 0 0x01000000>;
371 };
372
373 pci1: pcie@a000a000 {
374 cell-index = <2>;
375 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
376 interrupt-map = <
377 /* IDSEL 0x0 (PEX) */
378 0x00000 0 0 1 &mpic 0 1
379 0x00000 0 0 2 &mpic 1 1
380 0x00000 0 0 3 &mpic 2 1
381 0x00000 0 0 4 &mpic 3 1>;
382
383 interrupt-parent = <&mpic>;
384 interrupts = <26 2>;
385 bus-range = <0 0xff>;
386 ranges = <0x02000000 0 0xb0000000 0xb0000000 0 0x10000000
387 0x01000000 0 0x00000000 0xaf000000 0 0x08000000>;
388 clock-frequency = <33333333>;
389 #interrupt-cells = <1>;
390 #size-cells = <2>;
391 #address-cells = <3>;
392 reg = <0xa000a000 0x1000>;
393 compatible = "fsl,mpc8548-pcie";
394 device_type = "pci";
395 pcie@0 {
396 reg = <0 0 0 0 0>;
397 #size-cells = <2>;
398 #address-cells = <3>;
399 device_type = "pci";
400 ranges = <0x02000000 0 0xb0000000 0x02000000 0
401 0xb0000000 0 0x10000000
402 0x01000000 0 0x00000000 0x01000000 0
403 0x00000000 0 0x08000000>;
404 };
405 };
406};
diff --git a/arch/powerpc/boot/dts/tqm8548.dts b/arch/powerpc/boot/dts/tqm8548.dts
new file mode 100644
index 000000000000..2563112cabd3
--- /dev/null
+++ b/arch/powerpc/boot/dts/tqm8548.dts
@@ -0,0 +1,411 @@
1/*
2 * TQM8548 Device Tree Source
3 *
4 * Copyright 2006 Freescale Semiconductor Inc.
5 * Copyright 2008 Wolfgang Grandegger <wg@denx.de>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13/dts-v1/;
14
15/ {
16 model = "tqc,tqm8548";
17 compatible = "tqc,tqm8548";
18 #address-cells = <1>;
19 #size-cells = <1>;
20
21 aliases {
22 ethernet0 = &enet0;
23 ethernet1 = &enet1;
24 ethernet2 = &enet2;
25 ethernet3 = &enet3;
26
27 serial0 = &serial0;
28 serial1 = &serial1;
29 pci0 = &pci0;
30 pci1 = &pci1;
31 };
32
33 cpus {
34 #address-cells = <1>;
35 #size-cells = <0>;
36
37 PowerPC,8548@0 {
38 device_type = "cpu";
39 reg = <0>;
40 d-cache-line-size = <32>; // 32 bytes
41 i-cache-line-size = <32>; // 32 bytes
42 d-cache-size = <0x8000>; // L1, 32K
43 i-cache-size = <0x8000>; // L1, 32K
44 next-level-cache = <&L2>;
45 };
46 };
47
48 memory {
49 device_type = "memory";
50 reg = <0x00000000 0x00000000>; // Filled in by U-Boot
51 };
52
53 soc8548@e0000000 {
54 #address-cells = <1>;
55 #size-cells = <1>;
56 device_type = "soc";
57 ranges = <0x0 0xe0000000 0x100000>;
58 reg = <0xe0000000 0x1000>; // CCSRBAR
59 bus-frequency = <0>;
60
61 memory-controller@2000 {
62 compatible = "fsl,mpc8548-memory-controller";
63 reg = <0x2000 0x1000>;
64 interrupt-parent = <&mpic>;
65 interrupts = <18 2>;
66 };
67
68 L2: l2-cache-controller@20000 {
69 compatible = "fsl,mpc8548-l2-cache-controller";
70 reg = <0x20000 0x1000>;
71 cache-line-size = <32>; // 32 bytes
72 cache-size = <0x80000>; // L2, 512K
73 interrupt-parent = <&mpic>;
74 interrupts = <16 2>;
75 };
76
77 i2c@3000 {
78 #address-cells = <1>;
79 #size-cells = <0>;
80 cell-index = <0>;
81 compatible = "fsl-i2c";
82 reg = <0x3000 0x100>;
83 interrupts = <43 2>;
84 interrupt-parent = <&mpic>;
85 dfsrr;
86
87 rtc@68 {
88 compatible = "dallas,ds1337";
89 reg = <0x68>;
90 };
91 };
92
93 i2c@3100 {
94 #address-cells = <1>;
95 #size-cells = <0>;
96 cell-index = <1>;
97 compatible = "fsl-i2c";
98 reg = <0x3100 0x100>;
99 interrupts = <43 2>;
100 interrupt-parent = <&mpic>;
101 dfsrr;
102 };
103
104 dma@21300 {
105 #address-cells = <1>;
106 #size-cells = <1>;
107 compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma";
108 reg = <0x21300 0x4>;
109 ranges = <0x0 0x21100 0x200>;
110 cell-index = <0>;
111 dma-channel@0 {
112 compatible = "fsl,mpc8548-dma-channel",
113 "fsl,eloplus-dma-channel";
114 reg = <0x0 0x80>;
115 cell-index = <0>;
116 interrupt-parent = <&mpic>;
117 interrupts = <20 2>;
118 };
119 dma-channel@80 {
120 compatible = "fsl,mpc8548-dma-channel",
121 "fsl,eloplus-dma-channel";
122 reg = <0x80 0x80>;
123 cell-index = <1>;
124 interrupt-parent = <&mpic>;
125 interrupts = <21 2>;
126 };
127 dma-channel@100 {
128 compatible = "fsl,mpc8548-dma-channel",
129 "fsl,eloplus-dma-channel";
130 reg = <0x100 0x80>;
131 cell-index = <2>;
132 interrupt-parent = <&mpic>;
133 interrupts = <22 2>;
134 };
135 dma-channel@180 {
136 compatible = "fsl,mpc8548-dma-channel",
137 "fsl,eloplus-dma-channel";
138 reg = <0x180 0x80>;
139 cell-index = <3>;
140 interrupt-parent = <&mpic>;
141 interrupts = <23 2>;
142 };
143 };
144
145 mdio@24520 {
146 #address-cells = <1>;
147 #size-cells = <0>;
148 compatible = "fsl,gianfar-mdio";
149 reg = <0x24520 0x20>;
150
151 phy1: ethernet-phy@0 {
152 interrupt-parent = <&mpic>;
153 interrupts = <8 1>;
154 reg = <1>;
155 device_type = "ethernet-phy";
156 };
157 phy2: ethernet-phy@1 {
158 interrupt-parent = <&mpic>;
159 interrupts = <8 1>;
160 reg = <2>;
161 device_type = "ethernet-phy";
162 };
163 phy3: ethernet-phy@3 {
164 interrupt-parent = <&mpic>;
165 interrupts = <8 1>;
166 reg = <3>;
167 device_type = "ethernet-phy";
168 };
169 phy4: ethernet-phy@4 {
170 interrupt-parent = <&mpic>;
171 interrupts = <8 1>;
172 reg = <4>;
173 device_type = "ethernet-phy";
174 };
175 phy5: ethernet-phy@5 {
176 interrupt-parent = <&mpic>;
177 interrupts = <8 1>;
178 reg = <5>;
179 device_type = "ethernet-phy";
180 };
181 };
182
183 enet0: ethernet@24000 {
184 cell-index = <0>;
185 device_type = "network";
186 model = "eTSEC";
187 compatible = "gianfar";
188 reg = <0x24000 0x1000>;
189 local-mac-address = [ 00 00 00 00 00 00 ];
190 interrupts = <29 2 30 2 34 2>;
191 interrupt-parent = <&mpic>;
192 phy-handle = <&phy2>;
193 };
194
195 enet1: ethernet@25000 {
196 cell-index = <1>;
197 device_type = "network";
198 model = "eTSEC";
199 compatible = "gianfar";
200 reg = <0x25000 0x1000>;
201 local-mac-address = [ 00 00 00 00 00 00 ];
202 interrupts = <35 2 36 2 40 2>;
203 interrupt-parent = <&mpic>;
204 phy-handle = <&phy1>;
205 };
206
207 enet2: ethernet@26000 {
208 cell-index = <2>;
209 device_type = "network";
210 model = "eTSEC";
211 compatible = "gianfar";
212 reg = <0x26000 0x1000>;
213 local-mac-address = [ 00 00 00 00 00 00 ];
214 interrupts = <31 2 32 2 33 2>;
215 interrupt-parent = <&mpic>;
216 phy-handle = <&phy3>;
217 };
218
219 enet3: ethernet@27000 {
220 cell-index = <3>;
221 device_type = "network";
222 model = "eTSEC";
223 compatible = "gianfar";
224 reg = <0x27000 0x1000>;
225 local-mac-address = [ 00 00 00 00 00 00 ];
226 interrupts = <37 2 38 2 39 2>;
227 interrupt-parent = <&mpic>;
228 phy-handle = <&phy4>;
229 };
230
231 serial0: serial@4500 {
232 cell-index = <0>;
233 device_type = "serial";
234 compatible = "ns16550";
235 reg = <0x4500 0x100>; // reg base, size
236 clock-frequency = <0>; // should we fill in in uboot?
237 current-speed = <115200>;
238 interrupts = <42 2>;
239 interrupt-parent = <&mpic>;
240 };
241
242 serial1: serial@4600 {
243 cell-index = <1>;
244 device_type = "serial";
245 compatible = "ns16550";
246 reg = <0x4600 0x100>; // reg base, size
247 clock-frequency = <0>; // should we fill in in uboot?
248 current-speed = <115200>;
249 interrupts = <42 2>;
250 interrupt-parent = <&mpic>;
251 };
252
253 global-utilities@e0000 { // global utilities reg
254 compatible = "fsl,mpc8548-guts";
255 reg = <0xe0000 0x1000>;
256 fsl,has-rstcr;
257 };
258
259 mpic: pic@40000 {
260 interrupt-controller;
261 #address-cells = <0>;
262 #interrupt-cells = <2>;
263 reg = <0x40000 0x40000>;
264 compatible = "chrp,open-pic";
265 device_type = "open-pic";
266 };
267 };
268
269 localbus@e0005000 {
270 compatible = "fsl,mpc8548-localbus", "fsl,pq3-localbus",
271 "simple-bus";
272 #address-cells = <2>;
273 #size-cells = <1>;
274 reg = <0xe0005000 0x100>; // BRx, ORx, etc.
275
276 ranges = <
277 0 0x0 0xfc000000 0x04000000 // NOR FLASH bank 1
278 1 0x0 0xf8000000 0x08000000 // NOR FLASH bank 0
279 2 0x0 0xe3000000 0x00008000 // CAN (2 x i82527)
280 3 0x0 0xe3010000 0x00008000 // NAND FLASH
281
282 >;
283
284 flash@1,0 {
285 #address-cells = <1>;
286 #size-cells = <1>;
287 compatible = "cfi-flash";
288 reg = <1 0x0 0x8000000>;
289 bank-width = <4>;
290 device-width = <1>;
291
292 partition@0 {
293 label = "kernel";
294 reg = <0x00000000 0x00200000>;
295 };
296 partition@200000 {
297 label = "root";
298 reg = <0x00200000 0x00300000>;
299 };
300 partition@500000 {
301 label = "user";
302 reg = <0x00500000 0x07a00000>;
303 };
304 partition@7f00000 {
305 label = "env1";
306 reg = <0x07f00000 0x00040000>;
307 };
308 partition@7f40000 {
309 label = "env2";
310 reg = <0x07f40000 0x00040000>;
311 };
312 partition@7f80000 {
313 label = "u-boot";
314 reg = <0x07f80000 0x00080000>;
315 read-only;
316 };
317 };
318
319 /* Note: CAN support needs be enabled in U-Boot */
320 can0@2,0 {
321 compatible = "intel,82527"; // Bosch CC770
322 reg = <2 0x0 0x100>;
323 interrupts = <4 0>;
324 interrupt-parent = <&mpic>;
325 };
326
327 can1@2,100 {
328 compatible = "intel,82527"; // Bosch CC770
329 reg = <2 0x100 0x100>;
330 interrupts = <4 0>;
331 interrupt-parent = <&mpic>;
332 };
333
334 /* Note: NAND support needs to be enabled in U-Boot */
335 upm@3,0 {
336 #address-cells = <0>;
337 #size-cells = <0>;
338 compatible = "fsl,upm-nand";
339 reg = <3 0x0 0x800>;
340 fsl,upm-addr-offset = <0x10>;
341 fsl,upm-cmd-offset = <0x08>;
342 chip-delay = <25>; // in micro-seconds
343
344 nand@0 {
345 #address-cells = <1>;
346 #size-cells = <1>;
347
348 partition@0 {
349 label = "fs";
350 reg = <0x00000000 0x01000000>;
351 };
352 };
353 };
354 };
355
356 pci0: pci@e0008000 {
357 cell-index = <0>;
358 #interrupt-cells = <1>;
359 #size-cells = <2>;
360 #address-cells = <3>;
361 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
362 device_type = "pci";
363 reg = <0xe0008000 0x1000>;
364 clock-frequency = <33333333>;
365 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
366 interrupt-map = <
367 /* IDSEL 28 */
368 0xe000 0 0 1 &mpic 2 1
369 0xe000 0 0 2 &mpic 3 1>;
370
371 interrupt-parent = <&mpic>;
372 interrupts = <24 2>;
373 bus-range = <0 0>;
374 ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000
375 0x01000000 0 0x00000000 0xe2000000 0 0x01000000>;
376 };
377
378 pci1: pcie@e000a000 {
379 cell-index = <2>;
380 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
381 interrupt-map = <
382 /* IDSEL 0x0 (PEX) */
383 0x00000 0 0 1 &mpic 0 1
384 0x00000 0 0 2 &mpic 1 1
385 0x00000 0 0 3 &mpic 2 1
386 0x00000 0 0 4 &mpic 3 1>;
387
388 interrupt-parent = <&mpic>;
389 interrupts = <26 2>;
390 bus-range = <0 0xff>;
391 ranges = <0x02000000 0 0xc0000000 0xc0000000 0 0x20000000
392 0x01000000 0 0x00000000 0xef000000 0 0x08000000>;
393 clock-frequency = <33333333>;
394 #interrupt-cells = <1>;
395 #size-cells = <2>;
396 #address-cells = <3>;
397 reg = <0xe000a000 0x1000>;
398 compatible = "fsl,mpc8548-pcie";
399 device_type = "pci";
400 pcie@0 {
401 reg = <0 0 0 0 0>;
402 #size-cells = <2>;
403 #address-cells = <3>;
404 device_type = "pci";
405 ranges = <0x02000000 0 0xc0000000 0x02000000 0
406 0xc0000000 0 0x20000000
407 0x01000000 0 0x00000000 0x01000000 0
408 0x00000000 0 0x08000000>;
409 };
410 };
411};
diff --git a/arch/powerpc/boot/dts/tqm8555.dts b/arch/powerpc/boot/dts/tqm8555.dts
index a20eb06c482f..6f7ea59c4846 100644
--- a/arch/powerpc/boot/dts/tqm8555.dts
+++ b/arch/powerpc/boot/dts/tqm8555.dts
@@ -12,8 +12,8 @@
12/dts-v1/; 12/dts-v1/;
13 13
14/ { 14/ {
15 model = "tqm,8555"; 15 model = "tqc,tqm8555";
16 compatible = "tqm,8555", "tqm,85xx"; 16 compatible = "tqc,tqm8555";
17 #address-cells = <1>; 17 #address-cells = <1>;
18 #size-cells = <1>; 18 #size-cells = <1>;
19 19
@@ -39,6 +39,7 @@
39 timebase-frequency = <0>; 39 timebase-frequency = <0>;
40 bus-frequency = <0>; 40 bus-frequency = <0>;
41 clock-frequency = <0>; 41 clock-frequency = <0>;
42 next-level-cache = <&L2>;
42 }; 43 };
43 }; 44 };
44 45
@@ -63,7 +64,7 @@
63 interrupts = <18 2>; 64 interrupts = <18 2>;
64 }; 65 };
65 66
66 l2-cache-controller@20000 { 67 L2: l2-cache-controller@20000 {
67 compatible = "fsl,8540-l2-cache-controller"; 68 compatible = "fsl,8540-l2-cache-controller";
68 reg = <0x20000 0x1000>; 69 reg = <0x20000 0x1000>;
69 cache-line-size = <32>; 70 cache-line-size = <32>;
@@ -88,6 +89,47 @@
88 }; 89 };
89 }; 90 };
90 91
92 dma@21300 {
93 #address-cells = <1>;
94 #size-cells = <1>;
95 compatible = "fsl,mpc8555-dma", "fsl,eloplus-dma";
96 reg = <0x21300 0x4>;
97 ranges = <0x0 0x21100 0x200>;
98 cell-index = <0>;
99 dma-channel@0 {
100 compatible = "fsl,mpc8555-dma-channel",
101 "fsl,eloplus-dma-channel";
102 reg = <0x0 0x80>;
103 cell-index = <0>;
104 interrupt-parent = <&mpic>;
105 interrupts = <20 2>;
106 };
107 dma-channel@80 {
108 compatible = "fsl,mpc8555-dma-channel",
109 "fsl,eloplus-dma-channel";
110 reg = <0x80 0x80>;
111 cell-index = <1>;
112 interrupt-parent = <&mpic>;
113 interrupts = <21 2>;
114 };
115 dma-channel@100 {
116 compatible = "fsl,mpc8555-dma-channel",
117 "fsl,eloplus-dma-channel";
118 reg = <0x100 0x80>;
119 cell-index = <2>;
120 interrupt-parent = <&mpic>;
121 interrupts = <22 2>;
122 };
123 dma-channel@180 {
124 compatible = "fsl,mpc8555-dma-channel",
125 "fsl,eloplus-dma-channel";
126 reg = <0x180 0x80>;
127 cell-index = <3>;
128 interrupt-parent = <&mpic>;
129 interrupts = <23 2>;
130 };
131 };
132
91 mdio@24520 { 133 mdio@24520 {
92 #address-cells = <1>; 134 #address-cells = <1>;
93 #size-cells = <0>; 135 #size-cells = <0>;
@@ -158,12 +200,24 @@
158 interrupt-parent = <&mpic>; 200 interrupt-parent = <&mpic>;
159 }; 201 };
160 202
203 crypto@30000 {
204 compatible = "fsl,sec2.0";
205 reg = <0x30000 0x10000>;
206 interrupts = <45 2>;
207 interrupt-parent = <&mpic>;
208 fsl,num-channels = <4>;
209 fsl,channel-fifo-len = <24>;
210 fsl,exec-units-mask = <0x7e>;
211 fsl,descriptor-types-mask = <0x01010ebf>;
212 };
213
161 mpic: pic@40000 { 214 mpic: pic@40000 {
162 interrupt-controller; 215 interrupt-controller;
163 #address-cells = <0>; 216 #address-cells = <0>;
164 #interrupt-cells = <2>; 217 #interrupt-cells = <2>;
165 reg = <0x40000 0x40000>; 218 reg = <0x40000 0x40000>;
166 device_type = "open-pic"; 219 device_type = "open-pic";
220 compatible = "chrp,open-pic";
167 }; 221 };
168 222
169 cpm@919c0 { 223 cpm@919c0 {
diff --git a/arch/powerpc/boot/dts/tqm8560.dts b/arch/powerpc/boot/dts/tqm8560.dts
index b9ac6c943b89..3fe35208907b 100644
--- a/arch/powerpc/boot/dts/tqm8560.dts
+++ b/arch/powerpc/boot/dts/tqm8560.dts
@@ -2,6 +2,7 @@
2 * TQM 8560 Device Tree Source 2 * TQM 8560 Device Tree Source
3 * 3 *
4 * Copyright 2008 Freescale Semiconductor Inc. 4 * Copyright 2008 Freescale Semiconductor Inc.
5 * Copyright 2008 Wolfgang Grandegger <wg@grandegger.com>
5 * 6 *
6 * This program is free software; you can redistribute it and/or modify it 7 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the 8 * under the terms of the GNU General Public License as published by the
@@ -12,8 +13,8 @@
12/dts-v1/; 13/dts-v1/;
13 14
14/ { 15/ {
15 model = "tqm,8560"; 16 model = "tqc,tqm8560";
16 compatible = "tqm,8560", "tqm,85xx"; 17 compatible = "tqc,tqm8560";
17 #address-cells = <1>; 18 #address-cells = <1>;
18 #size-cells = <1>; 19 #size-cells = <1>;
19 20
@@ -40,6 +41,7 @@
40 timebase-frequency = <0>; 41 timebase-frequency = <0>;
41 bus-frequency = <0>; 42 bus-frequency = <0>;
42 clock-frequency = <0>; 43 clock-frequency = <0>;
44 next-level-cache = <&L2>;
43 }; 45 };
44 }; 46 };
45 47
@@ -64,7 +66,7 @@
64 interrupts = <18 2>; 66 interrupts = <18 2>;
65 }; 67 };
66 68
67 l2-cache-controller@20000 { 69 L2: l2-cache-controller@20000 {
68 compatible = "fsl,8540-l2-cache-controller"; 70 compatible = "fsl,8540-l2-cache-controller";
69 reg = <0x20000 0x1000>; 71 reg = <0x20000 0x1000>;
70 cache-line-size = <32>; 72 cache-line-size = <32>;
@@ -89,6 +91,47 @@
89 }; 91 };
90 }; 92 };
91 93
94 dma@21300 {
95 #address-cells = <1>;
96 #size-cells = <1>;
97 compatible = "fsl,mpc8560-dma", "fsl,eloplus-dma";
98 reg = <0x21300 0x4>;
99 ranges = <0x0 0x21100 0x200>;
100 cell-index = <0>;
101 dma-channel@0 {
102 compatible = "fsl,mpc8560-dma-channel",
103 "fsl,eloplus-dma-channel";
104 reg = <0x0 0x80>;
105 cell-index = <0>;
106 interrupt-parent = <&mpic>;
107 interrupts = <20 2>;
108 };
109 dma-channel@80 {
110 compatible = "fsl,mpc8560-dma-channel",
111 "fsl,eloplus-dma-channel";
112 reg = <0x80 0x80>;
113 cell-index = <1>;
114 interrupt-parent = <&mpic>;
115 interrupts = <21 2>;
116 };
117 dma-channel@100 {
118 compatible = "fsl,mpc8560-dma-channel",
119 "fsl,eloplus-dma-channel";
120 reg = <0x100 0x80>;
121 cell-index = <2>;
122 interrupt-parent = <&mpic>;
123 interrupts = <22 2>;
124 };
125 dma-channel@180 {
126 compatible = "fsl,mpc8560-dma-channel",
127 "fsl,eloplus-dma-channel";
128 reg = <0x180 0x80>;
129 cell-index = <3>;
130 interrupt-parent = <&mpic>;
131 interrupts = <23 2>;
132 };
133 };
134
92 mdio@24520 { 135 mdio@24520 {
93 #address-cells = <1>; 136 #address-cells = <1>;
94 #size-cells = <0>; 137 #size-cells = <0>;
@@ -145,6 +188,7 @@
145 #interrupt-cells = <2>; 188 #interrupt-cells = <2>;
146 reg = <0x40000 0x40000>; 189 reg = <0x40000 0x40000>;
147 device_type = "open-pic"; 190 device_type = "open-pic";
191 compatible = "chrp,open-pic";
148 }; 192 };
149 193
150 cpm@919c0 { 194 cpm@919c0 {
@@ -221,6 +265,70 @@
221 }; 265 };
222 }; 266 };
223 267
268 localbus@e0005000 {
269 compatible = "fsl,mpc8560-localbus", "fsl,pq3-localbus",
270 "simple-bus";
271 #address-cells = <2>;
272 #size-cells = <1>;
273 reg = <0xe0005000 0x100>; // BRx, ORx, etc.
274
275 ranges = <
276 0 0x0 0xfc000000 0x04000000 // NOR FLASH bank 1
277 1 0x0 0xf8000000 0x08000000 // NOR FLASH bank 0
278 2 0x0 0xe3000000 0x00008000 // CAN (2 x i82527)
279 >;
280
281 flash@1,0 {
282 #address-cells = <1>;
283 #size-cells = <1>;
284 compatible = "cfi-flash";
285 reg = <1 0x0 0x8000000>;
286 bank-width = <4>;
287 device-width = <1>;
288
289 partition@0 {
290 label = "kernel";
291 reg = <0x00000000 0x00200000>;
292 };
293 partition@200000 {
294 label = "root";
295 reg = <0x00200000 0x00300000>;
296 };
297 partition@500000 {
298 label = "user";
299 reg = <0x00500000 0x07a00000>;
300 };
301 partition@7f00000 {
302 label = "env1";
303 reg = <0x07f00000 0x00040000>;
304 };
305 partition@7f40000 {
306 label = "env2";
307 reg = <0x07f40000 0x00040000>;
308 };
309 partition@7f80000 {
310 label = "u-boot";
311 reg = <0x07f80000 0x00080000>;
312 read-only;
313 };
314 };
315
316 /* Note: CAN support needs be enabled in U-Boot */
317 can0@2,0 {
318 compatible = "intel,82527"; // Bosch CC770
319 reg = <2 0x0 0x100>;
320 interrupts = <4 0>;
321 interrupt-parent = <&mpic>;
322 };
323
324 can1@2,100 {
325 compatible = "intel,82527"; // Bosch CC770
326 reg = <2 0x100 0x100>;
327 interrupts = <4 0>;
328 interrupt-parent = <&mpic>;
329 };
330 };
331
224 pci0: pci@e0008000 { 332 pci0: pci@e0008000 {
225 cell-index = <0>; 333 cell-index = <0>;
226 #interrupt-cells = <1>; 334 #interrupt-cells = <1>;
diff --git a/arch/powerpc/boot/dts/virtex440-ml507.dts b/arch/powerpc/boot/dts/virtex440-ml507.dts
new file mode 100644
index 000000000000..dc8e78e2dceb
--- /dev/null
+++ b/arch/powerpc/boot/dts/virtex440-ml507.dts
@@ -0,0 +1,296 @@
1/*
2 * This file supports the Xilinx ML507 board with the 440 processor.
3 * A reference design for the FPGA is provided at http://git.xilinx.com.
4 *
5 * (C) Copyright 2008 Xilinx, Inc.
6 *
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
10 */
11
12/dts-v1/;
13
14/ {
15 #address-cells = <1>;
16 #size-cells = <1>;
17 compatible = "xlnx,virtex440";
18 dcr-parent = <&ppc440_0>;
19 model = "testing";
20 DDR2_SDRAM: memory@0 {
21 device_type = "memory";
22 reg = < 0 0x10000000 >;
23 } ;
24 chosen {
25 bootargs = "console=ttyS0 ip=on root=/dev/ram";
26 linux,stdout-path = "/plb@0/serial@83e00000";
27 } ;
28 cpus {
29 #address-cells = <1>;
30 #cpus = <1>;
31 #size-cells = <0>;
32 ppc440_0: cpu@0 {
33 clock-frequency = <400000000>;
34 compatible = "PowerPC,440", "ibm,ppc440";
35 d-cache-line-size = <0x20>;
36 d-cache-size = <0x8000>;
37 dcr-access-method = "native";
38 dcr-controller ;
39 device_type = "cpu";
40 i-cache-line-size = <0x20>;
41 i-cache-size = <0x8000>;
42 model = "PowerPC,440";
43 reg = <0>;
44 timebase-frequency = <400000000>;
45 xlnx,apu-control = <1>;
46 xlnx,apu-udi-0 = <0>;
47 xlnx,apu-udi-1 = <0>;
48 xlnx,apu-udi-10 = <0>;
49 xlnx,apu-udi-11 = <0>;
50 xlnx,apu-udi-12 = <0>;
51 xlnx,apu-udi-13 = <0>;
52 xlnx,apu-udi-14 = <0>;
53 xlnx,apu-udi-15 = <0>;
54 xlnx,apu-udi-2 = <0>;
55 xlnx,apu-udi-3 = <0>;
56 xlnx,apu-udi-4 = <0>;
57 xlnx,apu-udi-5 = <0>;
58 xlnx,apu-udi-6 = <0>;
59 xlnx,apu-udi-7 = <0>;
60 xlnx,apu-udi-8 = <0>;
61 xlnx,apu-udi-9 = <0>;
62 xlnx,dcr-autolock-enable = <1>;
63 xlnx,dcu-rd-ld-cache-plb-prio = <0>;
64 xlnx,dcu-rd-noncache-plb-prio = <0>;
65 xlnx,dcu-rd-touch-plb-prio = <0>;
66 xlnx,dcu-rd-urgent-plb-prio = <0>;
67 xlnx,dcu-wr-flush-plb-prio = <0>;
68 xlnx,dcu-wr-store-plb-prio = <0>;
69 xlnx,dcu-wr-urgent-plb-prio = <0>;
70 xlnx,dma0-control = <0>;
71 xlnx,dma0-plb-prio = <0>;
72 xlnx,dma0-rxchannelctrl = <0x1010000>;
73 xlnx,dma0-rxirqtimer = <0x3ff>;
74 xlnx,dma0-txchannelctrl = <0x1010000>;
75 xlnx,dma0-txirqtimer = <0x3ff>;
76 xlnx,dma1-control = <0>;
77 xlnx,dma1-plb-prio = <0>;
78 xlnx,dma1-rxchannelctrl = <0x1010000>;
79 xlnx,dma1-rxirqtimer = <0x3ff>;
80 xlnx,dma1-txchannelctrl = <0x1010000>;
81 xlnx,dma1-txirqtimer = <0x3ff>;
82 xlnx,dma2-control = <0>;
83 xlnx,dma2-plb-prio = <0>;
84 xlnx,dma2-rxchannelctrl = <0x1010000>;
85 xlnx,dma2-rxirqtimer = <0x3ff>;
86 xlnx,dma2-txchannelctrl = <0x1010000>;
87 xlnx,dma2-txirqtimer = <0x3ff>;
88 xlnx,dma3-control = <0>;
89 xlnx,dma3-plb-prio = <0>;
90 xlnx,dma3-rxchannelctrl = <0x1010000>;
91 xlnx,dma3-rxirqtimer = <0x3ff>;
92 xlnx,dma3-txchannelctrl = <0x1010000>;
93 xlnx,dma3-txirqtimer = <0x3ff>;
94 xlnx,endian-reset = <0>;
95 xlnx,generate-plb-timespecs = <1>;
96 xlnx,icu-rd-fetch-plb-prio = <0>;
97 xlnx,icu-rd-spec-plb-prio = <0>;
98 xlnx,icu-rd-touch-plb-prio = <0>;
99 xlnx,interconnect-imask = <0xffffffff>;
100 xlnx,mplb-allow-lock-xfer = <1>;
101 xlnx,mplb-arb-mode = <0>;
102 xlnx,mplb-awidth = <0x20>;
103 xlnx,mplb-counter = <0x500>;
104 xlnx,mplb-dwidth = <0x80>;
105 xlnx,mplb-max-burst = <8>;
106 xlnx,mplb-native-dwidth = <0x80>;
107 xlnx,mplb-p2p = <0>;
108 xlnx,mplb-prio-dcur = <2>;
109 xlnx,mplb-prio-dcuw = <3>;
110 xlnx,mplb-prio-icu = <4>;
111 xlnx,mplb-prio-splb0 = <1>;
112 xlnx,mplb-prio-splb1 = <0>;
113 xlnx,mplb-read-pipe-enable = <1>;
114 xlnx,mplb-sync-tattribute = <0>;
115 xlnx,mplb-wdog-enable = <1>;
116 xlnx,mplb-write-pipe-enable = <1>;
117 xlnx,mplb-write-post-enable = <1>;
118 xlnx,num-dma = <1>;
119 xlnx,pir = <0xf>;
120 xlnx,ppc440mc-addr-base = <0>;
121 xlnx,ppc440mc-addr-high = <0xfffffff>;
122 xlnx,ppc440mc-arb-mode = <0>;
123 xlnx,ppc440mc-bank-conflict-mask = <0xc00000>;
124 xlnx,ppc440mc-control = <0xf810008f>;
125 xlnx,ppc440mc-max-burst = <8>;
126 xlnx,ppc440mc-prio-dcur = <2>;
127 xlnx,ppc440mc-prio-dcuw = <3>;
128 xlnx,ppc440mc-prio-icu = <4>;
129 xlnx,ppc440mc-prio-splb0 = <1>;
130 xlnx,ppc440mc-prio-splb1 = <0>;
131 xlnx,ppc440mc-row-conflict-mask = <0x3ffe00>;
132 xlnx,ppcdm-asyncmode = <0>;
133 xlnx,ppcds-asyncmode = <0>;
134 xlnx,user-reset = <0>;
135 DMA0: sdma@80 {
136 compatible = "xlnx,ll-dma-1.00.a";
137 dcr-reg = < 0x80 0x11 >;
138 interrupt-parent = <&xps_intc_0>;
139 interrupts = < 9 2 0xa 2 >;
140 } ;
141 } ;
142 } ;
143 plb_v46_0: plb@0 {
144 #address-cells = <1>;
145 #size-cells = <1>;
146 compatible = "xlnx,plb-v46-1.02.a", "simple-bus";
147 ranges ;
148 DIP_Switches_8Bit: gpio@81460000 {
149 compatible = "xlnx,xps-gpio-1.00.a";
150 interrupt-parent = <&xps_intc_0>;
151 interrupts = < 6 2 >;
152 reg = < 0x81460000 0x10000 >;
153 xlnx,all-inputs = <1>;
154 xlnx,all-inputs-2 = <0>;
155 xlnx,dout-default = <0>;
156 xlnx,dout-default-2 = <0>;
157 xlnx,family = "virtex5";
158 xlnx,gpio-width = <8>;
159 xlnx,interrupt-present = <1>;
160 xlnx,is-bidir = <1>;
161 xlnx,is-bidir-2 = <1>;
162 xlnx,is-dual = <0>;
163 xlnx,tri-default = <0xffffffff>;
164 xlnx,tri-default-2 = <0xffffffff>;
165 } ;
166 Hard_Ethernet_MAC: xps-ll-temac@81c00000 {
167 #address-cells = <1>;
168 #size-cells = <1>;
169 compatible = "xlnx,compound";
170 ethernet@81c00000 {
171 compatible = "xlnx,xps-ll-temac-1.01.b";
172 device_type = "network";
173 interrupt-parent = <&xps_intc_0>;
174 interrupts = < 5 2 >;
175 llink-connected = <&DMA0>;
176 local-mac-address = [ 02 00 00 00 00 00 ];
177 reg = < 0x81c00000 0x40 >;
178 xlnx,bus2core-clk-ratio = <1>;
179 xlnx,phy-type = <1>;
180 xlnx,phyaddr = <1>;
181 xlnx,rxcsum = <1>;
182 xlnx,rxfifo = <0x1000>;
183 xlnx,temac-type = <0>;
184 xlnx,txcsum = <1>;
185 xlnx,txfifo = <0x1000>;
186 } ;
187 } ;
188 LEDs_8Bit: gpio@81400000 {
189 compatible = "xlnx,xps-gpio-1.00.a";
190 reg = < 0x81400000 0x10000 >;
191 xlnx,all-inputs = <0>;
192 xlnx,all-inputs-2 = <0>;
193 xlnx,dout-default = <0>;
194 xlnx,dout-default-2 = <0>;
195 xlnx,family = "virtex5";
196 xlnx,gpio-width = <8>;
197 xlnx,interrupt-present = <0>;
198 xlnx,is-bidir = <1>;
199 xlnx,is-bidir-2 = <1>;
200 xlnx,is-dual = <0>;
201 xlnx,tri-default = <0xffffffff>;
202 xlnx,tri-default-2 = <0xffffffff>;
203 } ;
204 LEDs_Positions: gpio@81420000 {
205 compatible = "xlnx,xps-gpio-1.00.a";
206 reg = < 0x81420000 0x10000 >;
207 xlnx,all-inputs = <0>;
208 xlnx,all-inputs-2 = <0>;
209 xlnx,dout-default = <0>;
210 xlnx,dout-default-2 = <0>;
211 xlnx,family = "virtex5";
212 xlnx,gpio-width = <5>;
213 xlnx,interrupt-present = <0>;
214 xlnx,is-bidir = <1>;
215 xlnx,is-bidir-2 = <1>;
216 xlnx,is-dual = <0>;
217 xlnx,tri-default = <0xffffffff>;
218 xlnx,tri-default-2 = <0xffffffff>;
219 } ;
220 Push_Buttons_5Bit: gpio@81440000 {
221 compatible = "xlnx,xps-gpio-1.00.a";
222 interrupt-parent = <&xps_intc_0>;
223 interrupts = < 7 2 >;
224 reg = < 0x81440000 0x10000 >;
225 xlnx,all-inputs = <1>;
226 xlnx,all-inputs-2 = <0>;
227 xlnx,dout-default = <0>;
228 xlnx,dout-default-2 = <0>;
229 xlnx,family = "virtex5";
230 xlnx,gpio-width = <5>;
231 xlnx,interrupt-present = <1>;
232 xlnx,is-bidir = <1>;
233 xlnx,is-bidir-2 = <1>;
234 xlnx,is-dual = <0>;
235 xlnx,tri-default = <0xffffffff>;
236 xlnx,tri-default-2 = <0xffffffff>;
237 } ;
238 RS232_Uart_1: serial@83e00000 {
239 clock-frequency = <100000000>;
240 compatible = "xlnx,xps-uart16550-2.00.a", "ns16550";
241 current-speed = <0x2580>;
242 device_type = "serial";
243 interrupt-parent = <&xps_intc_0>;
244 interrupts = < 8 2 >;
245 reg = < 0x83e00000 0x10000 >;
246 reg-offset = <3>;
247 reg-shift = <2>;
248 xlnx,family = "virtex5";
249 xlnx,has-external-rclk = <0>;
250 xlnx,has-external-xin = <0>;
251 xlnx,is-a-16550 = <1>;
252 } ;
253 SysACE_CompactFlash: sysace@83600000 {
254 compatible = "xlnx,xps-sysace-1.00.a";
255 interrupt-parent = <&xps_intc_0>;
256 interrupts = < 4 2 >;
257 reg = < 0x83600000 0x10000 >;
258 xlnx,family = "virtex5";
259 xlnx,mem-width = <0x10>;
260 } ;
261 xps_bram_if_cntlr_1: xps-bram-if-cntlr@ffff0000 {
262 compatible = "xlnx,xps-bram-if-cntlr-1.00.a";
263 reg = < 0xffff0000 0x10000 >;
264 xlnx,family = "virtex5";
265 } ;
266 xps_intc_0: interrupt-controller@81800000 {
267 #interrupt-cells = <2>;
268 compatible = "xlnx,xps-intc-1.00.a";
269 interrupt-controller ;
270 reg = < 0x81800000 0x10000 >;
271 xlnx,num-intr-inputs = <0xb>;
272 } ;
273 xps_timebase_wdt_1: xps-timebase-wdt@83a00000 {
274 compatible = "xlnx,xps-timebase-wdt-1.00.b";
275 interrupt-parent = <&xps_intc_0>;
276 interrupts = < 2 0 1 2 >;
277 reg = < 0x83a00000 0x10000 >;
278 xlnx,family = "virtex5";
279 xlnx,wdt-enable-once = <0>;
280 xlnx,wdt-interval = <0x1e>;
281 } ;
282 xps_timer_1: timer@83c00000 {
283 compatible = "xlnx,xps-timer-1.00.a";
284 interrupt-parent = <&xps_intc_0>;
285 interrupts = < 3 2 >;
286 reg = < 0x83c00000 0x10000 >;
287 xlnx,count-width = <0x20>;
288 xlnx,family = "virtex5";
289 xlnx,gen0-assert = <1>;
290 xlnx,gen1-assert = <1>;
291 xlnx,one-timer-only = <1>;
292 xlnx,trig0-assert = <1>;
293 xlnx,trig1-assert = <1>;
294 } ;
295 } ;
296} ;
diff --git a/arch/powerpc/boot/dts/walnut.dts b/arch/powerpc/boot/dts/walnut.dts
index a328607c8f84..4a9f726ada13 100644
--- a/arch/powerpc/boot/dts/walnut.dts
+++ b/arch/powerpc/boot/dts/walnut.dts
@@ -9,12 +9,14 @@
9 * any warranty of any kind, whether express or implied. 9 * any warranty of any kind, whether express or implied.
10 */ 10 */
11 11
12/dts-v1/;
13
12/ { 14/ {
13 #address-cells = <1>; 15 #address-cells = <1>;
14 #size-cells = <1>; 16 #size-cells = <1>;
15 model = "ibm,walnut"; 17 model = "ibm,walnut";
16 compatible = "ibm,walnut"; 18 compatible = "ibm,walnut";
17 dcr-parent = <&/cpus/cpu@0>; 19 dcr-parent = <&{/cpus/cpu@0}>;
18 20
19 aliases { 21 aliases {
20 ethernet0 = &EMAC; 22 ethernet0 = &EMAC;
@@ -29,13 +31,13 @@
29 cpu@0 { 31 cpu@0 {
30 device_type = "cpu"; 32 device_type = "cpu";
31 model = "PowerPC,405GP"; 33 model = "PowerPC,405GP";
32 reg = <0>; 34 reg = <0x00000000>;
33 clock-frequency = <bebc200>; /* Filled in by zImage */ 35 clock-frequency = <200000000>; /* Filled in by zImage */
34 timebase-frequency = <0>; /* Filled in by zImage */ 36 timebase-frequency = <0>; /* Filled in by zImage */
35 i-cache-line-size = <20>; 37 i-cache-line-size = <32>;
36 d-cache-line-size = <20>; 38 d-cache-line-size = <32>;
37 i-cache-size = <4000>; 39 i-cache-size = <16384>;
38 d-cache-size = <4000>; 40 d-cache-size = <16384>;
39 dcr-controller; 41 dcr-controller;
40 dcr-access-method = "native"; 42 dcr-access-method = "native";
41 }; 43 };
@@ -43,14 +45,14 @@
43 45
44 memory { 46 memory {
45 device_type = "memory"; 47 device_type = "memory";
46 reg = <0 0>; /* Filled in by zImage */ 48 reg = <0x00000000 0x00000000>; /* Filled in by zImage */
47 }; 49 };
48 50
49 UIC0: interrupt-controller { 51 UIC0: interrupt-controller {
50 compatible = "ibm,uic"; 52 compatible = "ibm,uic";
51 interrupt-controller; 53 interrupt-controller;
52 cell-index = <0>; 54 cell-index = <0>;
53 dcr-reg = <0c0 9>; 55 dcr-reg = <0x0c0 0x009>;
54 #address-cells = <0>; 56 #address-cells = <0>;
55 #size-cells = <0>; 57 #size-cells = <0>;
56 #interrupt-cells = <2>; 58 #interrupt-cells = <2>;
@@ -65,63 +67,63 @@
65 67
66 SDRAM0: memory-controller { 68 SDRAM0: memory-controller {
67 compatible = "ibm,sdram-405gp"; 69 compatible = "ibm,sdram-405gp";
68 dcr-reg = <010 2>; 70 dcr-reg = <0x010 0x002>;
69 }; 71 };
70 72
71 MAL: mcmal { 73 MAL: mcmal {
72 compatible = "ibm,mcmal-405gp", "ibm,mcmal"; 74 compatible = "ibm,mcmal-405gp", "ibm,mcmal";
73 dcr-reg = <180 62>; 75 dcr-reg = <0x180 0x062>;
74 num-tx-chans = <1>; 76 num-tx-chans = <1>;
75 num-rx-chans = <1>; 77 num-rx-chans = <1>;
76 interrupt-parent = <&UIC0>; 78 interrupt-parent = <&UIC0>;
77 interrupts = < 79 interrupts = <
78 b 4 /* TXEOB */ 80 0xb 0x4 /* TXEOB */
79 c 4 /* RXEOB */ 81 0xc 0x4 /* RXEOB */
80 a 4 /* SERR */ 82 0xa 0x4 /* SERR */
81 d 4 /* TXDE */ 83 0xd 0x4 /* TXDE */
82 e 4 /* RXDE */>; 84 0xe 0x4 /* RXDE */>;
83 }; 85 };
84 86
85 POB0: opb { 87 POB0: opb {
86 compatible = "ibm,opb-405gp", "ibm,opb"; 88 compatible = "ibm,opb-405gp", "ibm,opb";
87 #address-cells = <1>; 89 #address-cells = <1>;
88 #size-cells = <1>; 90 #size-cells = <1>;
89 ranges = <ef600000 ef600000 a00000>; 91 ranges = <0xef600000 0xef600000 0x00a00000>;
90 dcr-reg = <0a0 5>; 92 dcr-reg = <0x0a0 0x005>;
91 clock-frequency = <0>; /* Filled in by zImage */ 93 clock-frequency = <0>; /* Filled in by zImage */
92 94
93 UART0: serial@ef600300 { 95 UART0: serial@ef600300 {
94 device_type = "serial"; 96 device_type = "serial";
95 compatible = "ns16550"; 97 compatible = "ns16550";
96 reg = <ef600300 8>; 98 reg = <0xef600300 0x00000008>;
97 virtual-reg = <ef600300>; 99 virtual-reg = <0xef600300>;
98 clock-frequency = <0>; /* Filled in by zImage */ 100 clock-frequency = <0>; /* Filled in by zImage */
99 current-speed = <2580>; 101 current-speed = <9600>;
100 interrupt-parent = <&UIC0>; 102 interrupt-parent = <&UIC0>;
101 interrupts = <0 4>; 103 interrupts = <0x0 0x4>;
102 }; 104 };
103 105
104 UART1: serial@ef600400 { 106 UART1: serial@ef600400 {
105 device_type = "serial"; 107 device_type = "serial";
106 compatible = "ns16550"; 108 compatible = "ns16550";
107 reg = <ef600400 8>; 109 reg = <0xef600400 0x00000008>;
108 virtual-reg = <ef600400>; 110 virtual-reg = <0xef600400>;
109 clock-frequency = <0>; /* Filled in by zImage */ 111 clock-frequency = <0>; /* Filled in by zImage */
110 current-speed = <2580>; 112 current-speed = <9600>;
111 interrupt-parent = <&UIC0>; 113 interrupt-parent = <&UIC0>;
112 interrupts = <1 4>; 114 interrupts = <0x1 0x4>;
113 }; 115 };
114 116
115 IIC: i2c@ef600500 { 117 IIC: i2c@ef600500 {
116 compatible = "ibm,iic-405gp", "ibm,iic"; 118 compatible = "ibm,iic-405gp", "ibm,iic";
117 reg = <ef600500 11>; 119 reg = <0xef600500 0x00000011>;
118 interrupt-parent = <&UIC0>; 120 interrupt-parent = <&UIC0>;
119 interrupts = <2 4>; 121 interrupts = <0x2 0x4>;
120 }; 122 };
121 123
122 GPIO: gpio@ef600700 { 124 GPIO: gpio@ef600700 {
123 compatible = "ibm,gpio-405gp"; 125 compatible = "ibm,gpio-405gp";
124 reg = <ef600700 20>; 126 reg = <0xef600700 0x00000020>;
125 }; 127 };
126 128
127 EMAC: ethernet@ef600800 { 129 EMAC: ethernet@ef600800 {
@@ -129,26 +131,26 @@
129 compatible = "ibm,emac-405gp", "ibm,emac"; 131 compatible = "ibm,emac-405gp", "ibm,emac";
130 interrupt-parent = <&UIC0>; 132 interrupt-parent = <&UIC0>;
131 interrupts = < 133 interrupts = <
132 f 4 /* Ethernet */ 134 0xf 0x4 /* Ethernet */
133 9 4 /* Ethernet Wake Up */>; 135 0x9 0x4 /* Ethernet Wake Up */>;
134 local-mac-address = [000000000000]; /* Filled in by zImage */ 136 local-mac-address = [000000000000]; /* Filled in by zImage */
135 reg = <ef600800 70>; 137 reg = <0xef600800 0x00000070>;
136 mal-device = <&MAL>; 138 mal-device = <&MAL>;
137 mal-tx-channel = <0>; 139 mal-tx-channel = <0>;
138 mal-rx-channel = <0>; 140 mal-rx-channel = <0>;
139 cell-index = <0>; 141 cell-index = <0>;
140 max-frame-size = <5dc>; 142 max-frame-size = <1500>;
141 rx-fifo-size = <1000>; 143 rx-fifo-size = <4096>;
142 tx-fifo-size = <800>; 144 tx-fifo-size = <2048>;
143 phy-mode = "rmii"; 145 phy-mode = "rmii";
144 phy-map = <00000001>; 146 phy-map = <0x00000001>;
145 }; 147 };
146 148
147 }; 149 };
148 150
149 EBC0: ebc { 151 EBC0: ebc {
150 compatible = "ibm,ebc-405gp", "ibm,ebc"; 152 compatible = "ibm,ebc-405gp", "ibm,ebc";
151 dcr-reg = <012 2>; 153 dcr-reg = <0x012 0x002>;
152 #address-cells = <2>; 154 #address-cells = <2>;
153 #size-cells = <1>; 155 #size-cells = <1>;
154 /* The ranges property is supplied by the bootwrapper 156 /* The ranges property is supplied by the bootwrapper
@@ -158,18 +160,18 @@
158 clock-frequency = <0>; /* Filled in by zImage */ 160 clock-frequency = <0>; /* Filled in by zImage */
159 161
160 sram@0,0 { 162 sram@0,0 {
161 reg = <0 0 80000>; 163 reg = <0x00000000 0x00000000 0x00080000>;
162 }; 164 };
163 165
164 flash@0,80000 { 166 flash@0,80000 {
165 compatible = "jedec-flash"; 167 compatible = "jedec-flash";
166 bank-width = <1>; 168 bank-width = <1>;
167 reg = <0 80000 80000>; 169 reg = <0x00000000 0x00080000 0x00080000>;
168 #address-cells = <1>; 170 #address-cells = <1>;
169 #size-cells = <1>; 171 #size-cells = <1>;
170 partition@0 { 172 partition@0 {
171 label = "OpenBIOS"; 173 label = "OpenBIOS";
172 reg = <0 80000>; 174 reg = <0x00000000 0x00080000>;
173 read-only; 175 read-only;
174 }; 176 };
175 }; 177 };
@@ -177,24 +179,24 @@
177 nvram@1,0 { 179 nvram@1,0 {
178 /* NVRAM and RTC */ 180 /* NVRAM and RTC */
179 compatible = "ds1743-nvram"; 181 compatible = "ds1743-nvram";
180 #bytes = <2000>; 182 #bytes = <0x2000>;
181 reg = <1 0 2000>; 183 reg = <0x00000001 0x00000000 0x00002000>;
182 }; 184 };
183 185
184 keyboard@2,0 { 186 keyboard@2,0 {
185 compatible = "intel,82C42PC"; 187 compatible = "intel,82C42PC";
186 reg = <2 0 2>; 188 reg = <0x00000002 0x00000000 0x00000002>;
187 }; 189 };
188 190
189 ir@3,0 { 191 ir@3,0 {
190 compatible = "ti,TIR2000PAG"; 192 compatible = "ti,TIR2000PAG";
191 reg = <3 0 10>; 193 reg = <0x00000003 0x00000000 0x00000010>;
192 }; 194 };
193 195
194 fpga@7,0 { 196 fpga@7,0 {
195 compatible = "Walnut-FPGA"; 197 compatible = "Walnut-FPGA";
196 reg = <7 0 10>; 198 reg = <0x00000007 0x00000000 0x00000010>;
197 virtual-reg = <f0300005>; 199 virtual-reg = <0xf0300005>;
198 }; 200 };
199 }; 201 };
200 202
@@ -205,35 +207,35 @@
205 #address-cells = <3>; 207 #address-cells = <3>;
206 compatible = "ibm,plb405gp-pci", "ibm,plb-pci"; 208 compatible = "ibm,plb405gp-pci", "ibm,plb-pci";
207 primary; 209 primary;
208 reg = <eec00000 8 /* Config space access */ 210 reg = <0xeec00000 0x00000008 /* Config space access */
209 eed80000 4 /* IACK */ 211 0xeed80000 0x00000004 /* IACK */
210 eed80000 4 /* Special cycle */ 212 0xeed80000 0x00000004 /* Special cycle */
211 ef480000 40>; /* Internal registers */ 213 0xef480000 0x00000040>; /* Internal registers */
212 214
213 /* Outbound ranges, one memory and one IO, 215 /* Outbound ranges, one memory and one IO,
214 * later cannot be changed. Chip supports a second 216 * later cannot be changed. Chip supports a second
215 * IO range but we don't use it for now 217 * IO range but we don't use it for now
216 */ 218 */
217 ranges = <02000000 0 80000000 80000000 0 20000000 219 ranges = <0x02000000 0x00000000 0x80000000 0x80000000 0x00000000 0x20000000
218 01000000 0 00000000 e8000000 0 00010000>; 220 0x01000000 0x00000000 0x00000000 0xe8000000 0x00000000 0x00010000>;
219 221
220 /* Inbound 2GB range starting at 0 */ 222 /* Inbound 2GB range starting at 0 */
221 dma-ranges = <42000000 0 0 0 0 80000000>; 223 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>;
222 224
223 /* Walnut has all 4 IRQ pins tied together per slot */ 225 /* Walnut has all 4 IRQ pins tied together per slot */
224 interrupt-map-mask = <f800 0 0 0>; 226 interrupt-map-mask = <0xf800 0x0 0x0 0x0>;
225 interrupt-map = < 227 interrupt-map = <
226 /* IDSEL 1 */ 228 /* IDSEL 1 */
227 0800 0 0 0 &UIC0 1c 8 229 0x800 0x0 0x0 0x0 &UIC0 0x1c 0x8
228 230
229 /* IDSEL 2 */ 231 /* IDSEL 2 */
230 1000 0 0 0 &UIC0 1d 8 232 0x1000 0x0 0x0 0x0 &UIC0 0x1d 0x8
231 233
232 /* IDSEL 3 */ 234 /* IDSEL 3 */
233 1800 0 0 0 &UIC0 1e 8 235 0x1800 0x0 0x0 0x0 &UIC0 0x1e 0x8
234 236
235 /* IDSEL 4 */ 237 /* IDSEL 4 */
236 2000 0 0 0 &UIC0 1f 8 238 0x2000 0x0 0x0 0x0 &UIC0 0x1f 0x8
237 >; 239 >;
238 }; 240 };
239 }; 241 };
diff --git a/arch/powerpc/boot/dts/warp.dts b/arch/powerpc/boot/dts/warp.dts
index b04a52e22bf5..340018cf16b7 100644
--- a/arch/powerpc/boot/dts/warp.dts
+++ b/arch/powerpc/boot/dts/warp.dts
@@ -9,12 +9,14 @@
9 * any warranty of any kind, whether express or implied. 9 * any warranty of any kind, whether express or implied.
10 */ 10 */
11 11
12/dts-v1/;
13
12/ { 14/ {
13 #address-cells = <2>; 15 #address-cells = <2>;
14 #size-cells = <1>; 16 #size-cells = <1>;
15 model = "pika,warp"; 17 model = "pika,warp";
16 compatible = "pika,warp"; 18 compatible = "pika,warp";
17 dcr-parent = <&/cpus/cpu@0>; 19 dcr-parent = <&{/cpus/cpu@0}>;
18 20
19 aliases { 21 aliases {
20 ethernet0 = &EMAC0; 22 ethernet0 = &EMAC0;
@@ -28,13 +30,13 @@
28 cpu@0 { 30 cpu@0 {
29 device_type = "cpu"; 31 device_type = "cpu";
30 model = "PowerPC,440EP"; 32 model = "PowerPC,440EP";
31 reg = <0>; 33 reg = <0x00000000>;
32 clock-frequency = <0>; /* Filled in by zImage */ 34 clock-frequency = <0>; /* Filled in by zImage */
33 timebase-frequency = <0>; /* Filled in by zImage */ 35 timebase-frequency = <0>; /* Filled in by zImage */
34 i-cache-line-size = <20>; 36 i-cache-line-size = <32>;
35 d-cache-line-size = <20>; 37 d-cache-line-size = <32>;
36 i-cache-size = <8000>; 38 i-cache-size = <32768>;
37 d-cache-size = <8000>; 39 d-cache-size = <32768>;
38 dcr-controller; 40 dcr-controller;
39 dcr-access-method = "native"; 41 dcr-access-method = "native";
40 }; 42 };
@@ -42,14 +44,14 @@
42 44
43 memory { 45 memory {
44 device_type = "memory"; 46 device_type = "memory";
45 reg = <0 0 0>; /* Filled in by zImage */ 47 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by zImage */
46 }; 48 };
47 49
48 UIC0: interrupt-controller0 { 50 UIC0: interrupt-controller0 {
49 compatible = "ibm,uic-440ep","ibm,uic"; 51 compatible = "ibm,uic-440ep","ibm,uic";
50 interrupt-controller; 52 interrupt-controller;
51 cell-index = <0>; 53 cell-index = <0>;
52 dcr-reg = <0c0 009>; 54 dcr-reg = <0x0c0 0x009>;
53 #address-cells = <0>; 55 #address-cells = <0>;
54 #size-cells = <0>; 56 #size-cells = <0>;
55 #interrupt-cells = <2>; 57 #interrupt-cells = <2>;
@@ -59,22 +61,22 @@
59 compatible = "ibm,uic-440ep","ibm,uic"; 61 compatible = "ibm,uic-440ep","ibm,uic";
60 interrupt-controller; 62 interrupt-controller;
61 cell-index = <1>; 63 cell-index = <1>;
62 dcr-reg = <0d0 009>; 64 dcr-reg = <0x0d0 0x009>;
63 #address-cells = <0>; 65 #address-cells = <0>;
64 #size-cells = <0>; 66 #size-cells = <0>;
65 #interrupt-cells = <2>; 67 #interrupt-cells = <2>;
66 interrupts = <1e 4 1f 4>; /* cascade */ 68 interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
67 interrupt-parent = <&UIC0>; 69 interrupt-parent = <&UIC0>;
68 }; 70 };
69 71
70 SDR0: sdr { 72 SDR0: sdr {
71 compatible = "ibm,sdr-440ep"; 73 compatible = "ibm,sdr-440ep";
72 dcr-reg = <00e 002>; 74 dcr-reg = <0x00e 0x002>;
73 }; 75 };
74 76
75 CPR0: cpr { 77 CPR0: cpr {
76 compatible = "ibm,cpr-440ep"; 78 compatible = "ibm,cpr-440ep";
77 dcr-reg = <00c 002>; 79 dcr-reg = <0x00c 0x002>;
78 }; 80 };
79 81
80 plb { 82 plb {
@@ -86,86 +88,79 @@
86 88
87 SDRAM0: sdram { 89 SDRAM0: sdram {
88 compatible = "ibm,sdram-440ep", "ibm,sdram-405gp"; 90 compatible = "ibm,sdram-440ep", "ibm,sdram-405gp";
89 dcr-reg = <010 2>; 91 dcr-reg = <0x010 0x002>;
90 }; 92 };
91 93
92 DMA0: dma { 94 DMA0: dma {
93 compatible = "ibm,dma-440ep", "ibm,dma-440gp"; 95 compatible = "ibm,dma-440ep", "ibm,dma-440gp";
94 dcr-reg = <100 027>; 96 dcr-reg = <0x100 0x027>;
95 }; 97 };
96 98
97 MAL0: mcmal { 99 MAL0: mcmal {
98 compatible = "ibm,mcmal-440ep", "ibm,mcmal-440gp", "ibm,mcmal"; 100 compatible = "ibm,mcmal-440ep", "ibm,mcmal-440gp", "ibm,mcmal";
99 dcr-reg = <180 62>; 101 dcr-reg = <0x180 0x062>;
100 num-tx-chans = <4>; 102 num-tx-chans = <4>;
101 num-rx-chans = <2>; 103 num-rx-chans = <2>;
102 interrupt-parent = <&MAL0>; 104 interrupt-parent = <&MAL0>;
103 interrupts = <0 1 2 3 4>; 105 interrupts = <0x0 0x1 0x2 0x3 0x4>;
104 #interrupt-cells = <1>; 106 #interrupt-cells = <1>;
105 #address-cells = <0>; 107 #address-cells = <0>;
106 #size-cells = <0>; 108 #size-cells = <0>;
107 interrupt-map = </*TXEOB*/ 0 &UIC0 a 4 109 interrupt-map = </*TXEOB*/ 0x0 &UIC0 0xa 0x4
108 /*RXEOB*/ 1 &UIC0 b 4 110 /*RXEOB*/ 0x1 &UIC0 0xb 0x4
109 /*SERR*/ 2 &UIC1 0 4 111 /*SERR*/ 0x2 &UIC1 0x0 0x4
110 /*TXDE*/ 3 &UIC1 1 4 112 /*TXDE*/ 0x3 &UIC1 0x1 0x4
111 /*RXDE*/ 4 &UIC1 2 4>; 113 /*RXDE*/ 0x4 &UIC1 0x2 0x4>;
112 }; 114 };
113 115
114 POB0: opb { 116 POB0: opb {
115 compatible = "ibm,opb-440ep", "ibm,opb-440gp", "ibm,opb"; 117 compatible = "ibm,opb-440ep", "ibm,opb-440gp", "ibm,opb";
116 #address-cells = <1>; 118 #address-cells = <1>;
117 #size-cells = <1>; 119 #size-cells = <1>;
118 ranges = <00000000 0 00000000 80000000 120 ranges = <0x00000000 0x00000000 0x00000000 0x80000000
119 80000000 0 80000000 80000000>; 121 0x80000000 0x00000000 0x80000000 0x80000000>;
120 interrupt-parent = <&UIC1>; 122 interrupt-parent = <&UIC1>;
121 interrupts = <7 4>; 123 interrupts = <0x7 0x4>;
122 clock-frequency = <0>; /* Filled in by zImage */ 124 clock-frequency = <0>; /* Filled in by zImage */
123 125
124 EBC0: ebc { 126 EBC0: ebc {
125 compatible = "ibm,ebc-440ep", "ibm,ebc-440gp", "ibm,ebc"; 127 compatible = "ibm,ebc-440ep", "ibm,ebc-440gp", "ibm,ebc";
126 dcr-reg = <012 2>; 128 dcr-reg = <0x012 0x002>;
127 #address-cells = <2>; 129 #address-cells = <2>;
128 #size-cells = <1>; 130 #size-cells = <1>;
129 clock-frequency = <0>; /* Filled in by zImage */ 131 clock-frequency = <0>; /* Filled in by zImage */
130 interrupts = <5 1>; 132 interrupts = <0x5 0x1>;
131 interrupt-parent = <&UIC1>; 133 interrupt-parent = <&UIC1>;
132 134
133 fpga@2,0 { 135 fpga@2,0 {
134 compatible = "pika,fpga"; 136 compatible = "pika,fpga";
135 reg = <2 0 2200>; 137 reg = <0x00000002 0x00000000 0x00001000>;
136 interrupts = <18 8>; 138 interrupts = <0x18 0x8>;
137 interrupt-parent = <&UIC0>; 139 interrupt-parent = <&UIC0>;
138 }; 140 };
139 141
142 fpga@2,4000 {
143 compatible = "pika,fpga-sd";
144 reg = <0x00000002 0x00004000 0x00000A00>;
145 };
146
140 nor_flash@0,0 { 147 nor_flash@0,0 {
141 compatible = "amd,s29gl512n", "cfi-flash"; 148 compatible = "amd,s29gl032a", "cfi-flash";
142 bank-width = <2>; 149 bank-width = <2>;
143 reg = <0 0 4000000>; 150 reg = <0x00000000 0x00000000 0x00400000>;
144 #address-cells = <1>; 151 #address-cells = <1>;
145 #size-cells = <1>; 152 #size-cells = <1>;
146 partition@0 { 153 partition@300000 {
147 label = "kernel";
148 reg = <0 180000>;
149 };
150 partition@180000 {
151 label = "root";
152 reg = <180000 3480000>;
153 };
154 partition@3600000 {
155 label = "user";
156 reg = <3600000 900000>;
157 };
158 partition@3f00000 {
159 label = "fpga"; 154 label = "fpga";
160 reg = <3f00000 40000>; 155 reg = <0x0030000 0x00040000>;
161 }; 156 };
162 partition@3f40000 { 157 partition@340000 {
163 label = "env"; 158 label = "env";
164 reg = <3f40000 40000>; 159 reg = <0x0340000 0x00040000>;
165 }; 160 };
166 partition@3f80000 { 161 partition@380000 {
167 label = "u-boot"; 162 label = "u-boot";
168 reg = <3f80000 80000>; 163 reg = <0x0380000 0x00080000>;
169 }; 164 };
170 }; 165 };
171 }; 166 };
@@ -173,60 +168,80 @@
173 UART0: serial@ef600300 { 168 UART0: serial@ef600300 {
174 device_type = "serial"; 169 device_type = "serial";
175 compatible = "ns16550"; 170 compatible = "ns16550";
176 reg = <ef600300 8>; 171 reg = <0xef600300 0x00000008>;
177 virtual-reg = <ef600300>; 172 virtual-reg = <0xef600300>;
178 clock-frequency = <0>; /* Filled in by zImage */ 173 clock-frequency = <0>; /* Filled in by zImage */
179 current-speed = <1c200>; 174 current-speed = <115200>;
180 interrupt-parent = <&UIC0>; 175 interrupt-parent = <&UIC0>;
181 interrupts = <0 4>; 176 interrupts = <0x0 0x4>;
182 }; 177 };
183 178
184 IIC0: i2c@ef600700 { 179 IIC0: i2c@ef600700 {
185 compatible = "ibm,iic-440ep", "ibm,iic-440gp", "ibm,iic"; 180 compatible = "ibm,iic-440ep", "ibm,iic-440gp", "ibm,iic";
186 reg = <ef600700 14>; 181 reg = <0xef600700 0x00000014>;
187 interrupt-parent = <&UIC0>; 182 interrupt-parent = <&UIC0>;
188 interrupts = <2 4>; 183 interrupts = <0x2 0x4>;
184 index = <0x0>;
185 #address-cells = <1>;
186 #size-cells = <0>;
187
188 ad7414@4a {
189 compatible = "adi,ad7414";
190 reg = <0x4a>;
191 interrupts = <0x19 0x8>;
192 interrupt-parent = <&UIC0>;
193 };
189 }; 194 };
190 195
191 GPIO0: gpio@ef600b00 { 196 GPIO0: gpio@ef600b00 {
192 compatible = "ibm,gpio-440ep"; 197 compatible = "ibm,gpio-440ep";
193 reg = <ef600b00 48>; 198 reg = <0xef600b00 0x00000048>;
199 #gpio-cells = <2>;
200 gpio-controller;
194 }; 201 };
195 202
196 GPIO1: gpio@ef600c00 { 203 GPIO1: gpio@ef600c00 {
197 compatible = "ibm,gpio-440ep"; 204 compatible = "ibm,gpio-440ep";
198 reg = <ef600c00 48>; 205 reg = <0xef600c00 0x00000048>;
206 #gpio-cells = <2>;
207 gpio-controller;
208
209 led@31 {
210 compatible = "linux,gpio-led";
211 linux,name = ":green:";
212 gpios = <&GPIO1 0x30 0>;
213 };
199 }; 214 };
200 215
201 ZMII0: emac-zmii@ef600d00 { 216 ZMII0: emac-zmii@ef600d00 {
202 compatible = "ibm,zmii-440ep", "ibm,zmii-440gp", "ibm,zmii"; 217 compatible = "ibm,zmii-440ep", "ibm,zmii-440gp", "ibm,zmii";
203 reg = <ef600d00 c>; 218 reg = <0xef600d00 0x0000000c>;
204 }; 219 };
205 220
206 EMAC0: ethernet@ef600e00 { 221 EMAC0: ethernet@ef600e00 {
207 device_type = "network"; 222 device_type = "network";
208 compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac"; 223 compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac";
209 interrupt-parent = <&UIC1>; 224 interrupt-parent = <&UIC1>;
210 interrupts = <1c 4 1d 4>; 225 interrupts = <0x1c 0x4 0x1d 0x4>;
211 reg = <ef600e00 70>; 226 reg = <0xef600e00 0x00000070>;
212 local-mac-address = [000000000000]; 227 local-mac-address = [000000000000];
213 mal-device = <&MAL0>; 228 mal-device = <&MAL0>;
214 mal-tx-channel = <0 1>; 229 mal-tx-channel = <0 1>;
215 mal-rx-channel = <0>; 230 mal-rx-channel = <0>;
216 cell-index = <0>; 231 cell-index = <0>;
217 max-frame-size = <5dc>; 232 max-frame-size = <1500>;
218 rx-fifo-size = <1000>; 233 rx-fifo-size = <4096>;
219 tx-fifo-size = <800>; 234 tx-fifo-size = <2048>;
220 phy-mode = "rmii"; 235 phy-mode = "rmii";
221 phy-map = <00000000>; 236 phy-map = <0x00000000>;
222 zmii-device = <&ZMII0>; 237 zmii-device = <&ZMII0>;
223 zmii-channel = <0>; 238 zmii-channel = <0>;
224 }; 239 };
225 240
226 usb@ef601000 { 241 usb@ef601000 {
227 compatible = "ohci-be"; 242 compatible = "ohci-be";
228 reg = <ef601000 80>; 243 reg = <0xef601000 0x00000080>;
229 interrupts = <8 1 9 1>; 244 interrupts = <0x8 0x1 0x9 0x1>;
230 interrupt-parent = < &UIC1 >; 245 interrupt-parent = < &UIC1 >;
231 }; 246 };
232 }; 247 };
diff --git a/arch/powerpc/boot/dts/yosemite.dts b/arch/powerpc/boot/dts/yosemite.dts
index 0d6d332814e0..e39422aa0d85 100644
--- a/arch/powerpc/boot/dts/yosemite.dts
+++ b/arch/powerpc/boot/dts/yosemite.dts
@@ -9,12 +9,14 @@
9 * any warranty of any kind, whether express or implied. 9 * any warranty of any kind, whether express or implied.
10 */ 10 */
11 11
12/dts-v1/;
13
12/ { 14/ {
13 #address-cells = <2>; 15 #address-cells = <2>;
14 #size-cells = <1>; 16 #size-cells = <1>;
15 model = "amcc,yosemite"; 17 model = "amcc,yosemite";
16 compatible = "amcc,yosemite","amcc,bamboo"; 18 compatible = "amcc,yosemite","amcc,bamboo";
17 dcr-parent = <&/cpus/cpu@0>; 19 dcr-parent = <&{/cpus/cpu@0}>;
18 20
19 aliases { 21 aliases {
20 ethernet0 = &EMAC0; 22 ethernet0 = &EMAC0;
@@ -32,13 +34,13 @@
32 cpu@0 { 34 cpu@0 {
33 device_type = "cpu"; 35 device_type = "cpu";
34 model = "PowerPC,440EP"; 36 model = "PowerPC,440EP";
35 reg = <0>; 37 reg = <0x00000000>;
36 clock-frequency = <0>; /* Filled in by zImage */ 38 clock-frequency = <0>; /* Filled in by zImage */
37 timebase-frequency = <0>; /* Filled in by zImage */ 39 timebase-frequency = <0>; /* Filled in by zImage */
38 i-cache-line-size = <20>; 40 i-cache-line-size = <32>;
39 d-cache-line-size = <20>; 41 d-cache-line-size = <32>;
40 i-cache-size = <8000>; 42 i-cache-size = <32768>;
41 d-cache-size = <8000>; 43 d-cache-size = <32768>;
42 dcr-controller; 44 dcr-controller;
43 dcr-access-method = "native"; 45 dcr-access-method = "native";
44 }; 46 };
@@ -46,14 +48,14 @@
46 48
47 memory { 49 memory {
48 device_type = "memory"; 50 device_type = "memory";
49 reg = <0 0 0>; /* Filled in by zImage */ 51 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by zImage */
50 }; 52 };
51 53
52 UIC0: interrupt-controller0 { 54 UIC0: interrupt-controller0 {
53 compatible = "ibm,uic-440ep","ibm,uic"; 55 compatible = "ibm,uic-440ep","ibm,uic";
54 interrupt-controller; 56 interrupt-controller;
55 cell-index = <0>; 57 cell-index = <0>;
56 dcr-reg = <0c0 009>; 58 dcr-reg = <0x0c0 0x009>;
57 #address-cells = <0>; 59 #address-cells = <0>;
58 #size-cells = <0>; 60 #size-cells = <0>;
59 #interrupt-cells = <2>; 61 #interrupt-cells = <2>;
@@ -63,22 +65,22 @@
63 compatible = "ibm,uic-440ep","ibm,uic"; 65 compatible = "ibm,uic-440ep","ibm,uic";
64 interrupt-controller; 66 interrupt-controller;
65 cell-index = <1>; 67 cell-index = <1>;
66 dcr-reg = <0d0 009>; 68 dcr-reg = <0x0d0 0x009>;
67 #address-cells = <0>; 69 #address-cells = <0>;
68 #size-cells = <0>; 70 #size-cells = <0>;
69 #interrupt-cells = <2>; 71 #interrupt-cells = <2>;
70 interrupts = <1e 4 1f 4>; /* cascade */ 72 interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
71 interrupt-parent = <&UIC0>; 73 interrupt-parent = <&UIC0>;
72 }; 74 };
73 75
74 SDR0: sdr { 76 SDR0: sdr {
75 compatible = "ibm,sdr-440ep"; 77 compatible = "ibm,sdr-440ep";
76 dcr-reg = <00e 002>; 78 dcr-reg = <0x00e 0x002>;
77 }; 79 };
78 80
79 CPR0: cpr { 81 CPR0: cpr {
80 compatible = "ibm,cpr-440ep"; 82 compatible = "ibm,cpr-440ep";
81 dcr-reg = <00c 002>; 83 dcr-reg = <0x00c 0x002>;
82 }; 84 };
83 85
84 plb { 86 plb {
@@ -90,29 +92,29 @@
90 92
91 SDRAM0: sdram { 93 SDRAM0: sdram {
92 compatible = "ibm,sdram-440ep", "ibm,sdram-405gp"; 94 compatible = "ibm,sdram-440ep", "ibm,sdram-405gp";
93 dcr-reg = <010 2>; 95 dcr-reg = <0x010 0x002>;
94 }; 96 };
95 97
96 DMA0: dma { 98 DMA0: dma {
97 compatible = "ibm,dma-440ep", "ibm,dma-440gp"; 99 compatible = "ibm,dma-440ep", "ibm,dma-440gp";
98 dcr-reg = <100 027>; 100 dcr-reg = <0x100 0x027>;
99 }; 101 };
100 102
101 MAL0: mcmal { 103 MAL0: mcmal {
102 compatible = "ibm,mcmal-440ep", "ibm,mcmal-440gp", "ibm,mcmal"; 104 compatible = "ibm,mcmal-440ep", "ibm,mcmal-440gp", "ibm,mcmal";
103 dcr-reg = <180 62>; 105 dcr-reg = <0x180 0x062>;
104 num-tx-chans = <4>; 106 num-tx-chans = <4>;
105 num-rx-chans = <2>; 107 num-rx-chans = <2>;
106 interrupt-parent = <&MAL0>; 108 interrupt-parent = <&MAL0>;
107 interrupts = <0 1 2 3 4>; 109 interrupts = <0x0 0x1 0x2 0x3 0x4>;
108 #interrupt-cells = <1>; 110 #interrupt-cells = <1>;
109 #address-cells = <0>; 111 #address-cells = <0>;
110 #size-cells = <0>; 112 #size-cells = <0>;
111 interrupt-map = </*TXEOB*/ 0 &UIC0 a 4 113 interrupt-map = </*TXEOB*/ 0x0 &UIC0 0xa 0x4
112 /*RXEOB*/ 1 &UIC0 b 4 114 /*RXEOB*/ 0x1 &UIC0 0xb 0x4
113 /*SERR*/ 2 &UIC1 0 4 115 /*SERR*/ 0x2 &UIC1 0x0 0x4
114 /*TXDE*/ 3 &UIC1 1 4 116 /*TXDE*/ 0x3 &UIC1 0x1 0x4
115 /*RXDE*/ 4 &UIC1 2 4>; 117 /*RXDE*/ 0x4 &UIC1 0x2 0x4>;
116 }; 118 };
117 119
118 POB0: opb { 120 POB0: opb {
@@ -122,110 +124,110 @@
122 /* Bamboo is oddball in the 44x world and doesn't use the ERPN 124 /* Bamboo is oddball in the 44x world and doesn't use the ERPN
123 * bits. 125 * bits.
124 */ 126 */
125 ranges = <00000000 0 00000000 80000000 127 ranges = <0x00000000 0x00000000 0x00000000 0x80000000
126 80000000 0 80000000 80000000>; 128 0x80000000 0x00000000 0x80000000 0x80000000>;
127 interrupt-parent = <&UIC1>; 129 interrupt-parent = <&UIC1>;
128 interrupts = <7 4>; 130 interrupts = <0x7 0x4>;
129 clock-frequency = <0>; /* Filled in by zImage */ 131 clock-frequency = <0>; /* Filled in by zImage */
130 132
131 EBC0: ebc { 133 EBC0: ebc {
132 compatible = "ibm,ebc-440ep", "ibm,ebc-440gp", "ibm,ebc"; 134 compatible = "ibm,ebc-440ep", "ibm,ebc-440gp", "ibm,ebc";
133 dcr-reg = <012 2>; 135 dcr-reg = <0x012 0x002>;
134 #address-cells = <2>; 136 #address-cells = <2>;
135 #size-cells = <1>; 137 #size-cells = <1>;
136 clock-frequency = <0>; /* Filled in by zImage */ 138 clock-frequency = <0>; /* Filled in by zImage */
137 interrupts = <5 1>; 139 interrupts = <0x5 0x1>;
138 interrupt-parent = <&UIC1>; 140 interrupt-parent = <&UIC1>;
139 }; 141 };
140 142
141 UART0: serial@ef600300 { 143 UART0: serial@ef600300 {
142 device_type = "serial"; 144 device_type = "serial";
143 compatible = "ns16550"; 145 compatible = "ns16550";
144 reg = <ef600300 8>; 146 reg = <0xef600300 0x00000008>;
145 virtual-reg = <ef600300>; 147 virtual-reg = <0xef600300>;
146 clock-frequency = <0>; /* Filled in by zImage */ 148 clock-frequency = <0>; /* Filled in by zImage */
147 current-speed = <1c200>; 149 current-speed = <115200>;
148 interrupt-parent = <&UIC0>; 150 interrupt-parent = <&UIC0>;
149 interrupts = <0 4>; 151 interrupts = <0x0 0x4>;
150 }; 152 };
151 153
152 UART1: serial@ef600400 { 154 UART1: serial@ef600400 {
153 device_type = "serial"; 155 device_type = "serial";
154 compatible = "ns16550"; 156 compatible = "ns16550";
155 reg = <ef600400 8>; 157 reg = <0xef600400 0x00000008>;
156 virtual-reg = <ef600400>; 158 virtual-reg = <0xef600400>;
157 clock-frequency = <0>; 159 clock-frequency = <0>;
158 current-speed = <0>; 160 current-speed = <0>;
159 interrupt-parent = <&UIC0>; 161 interrupt-parent = <&UIC0>;
160 interrupts = <1 4>; 162 interrupts = <0x1 0x4>;
161 }; 163 };
162 164
163 UART2: serial@ef600500 { 165 UART2: serial@ef600500 {
164 device_type = "serial"; 166 device_type = "serial";
165 compatible = "ns16550"; 167 compatible = "ns16550";
166 reg = <ef600500 8>; 168 reg = <0xef600500 0x00000008>;
167 virtual-reg = <ef600500>; 169 virtual-reg = <0xef600500>;
168 clock-frequency = <0>; 170 clock-frequency = <0>;
169 current-speed = <0>; 171 current-speed = <0>;
170 interrupt-parent = <&UIC0>; 172 interrupt-parent = <&UIC0>;
171 interrupts = <3 4>; 173 interrupts = <0x3 0x4>;
172 status = "disabled"; 174 status = "disabled";
173 }; 175 };
174 176
175 UART3: serial@ef600600 { 177 UART3: serial@ef600600 {
176 device_type = "serial"; 178 device_type = "serial";
177 compatible = "ns16550"; 179 compatible = "ns16550";
178 reg = <ef600600 8>; 180 reg = <0xef600600 0x00000008>;
179 virtual-reg = <ef600600>; 181 virtual-reg = <0xef600600>;
180 clock-frequency = <0>; 182 clock-frequency = <0>;
181 current-speed = <0>; 183 current-speed = <0>;
182 interrupt-parent = <&UIC0>; 184 interrupt-parent = <&UIC0>;
183 interrupts = <4 4>; 185 interrupts = <0x4 0x4>;
184 status = "disabled"; 186 status = "disabled";
185 }; 187 };
186 188
187 IIC0: i2c@ef600700 { 189 IIC0: i2c@ef600700 {
188 compatible = "ibm,iic-440ep", "ibm,iic-440gp", "ibm,iic"; 190 compatible = "ibm,iic-440ep", "ibm,iic-440gp", "ibm,iic";
189 reg = <ef600700 14>; 191 reg = <0xef600700 0x00000014>;
190 interrupt-parent = <&UIC0>; 192 interrupt-parent = <&UIC0>;
191 interrupts = <2 4>; 193 interrupts = <0x2 0x4>;
192 }; 194 };
193 195
194 IIC1: i2c@ef600800 { 196 IIC1: i2c@ef600800 {
195 compatible = "ibm,iic-440ep", "ibm,iic-440gp", "ibm,iic"; 197 compatible = "ibm,iic-440ep", "ibm,iic-440gp", "ibm,iic";
196 reg = <ef600800 14>; 198 reg = <0xef600800 0x00000014>;
197 interrupt-parent = <&UIC0>; 199 interrupt-parent = <&UIC0>;
198 interrupts = <7 4>; 200 interrupts = <0x7 0x4>;
199 }; 201 };
200 202
201 spi@ef600900 { 203 spi@ef600900 {
202 compatible = "amcc,spi-440ep"; 204 compatible = "amcc,spi-440ep";
203 reg = <ef600900 6>; 205 reg = <0xef600900 0x00000006>;
204 interrupts = <8 4>; 206 interrupts = <0x8 0x4>;
205 interrupt-parent = <&UIC0>; 207 interrupt-parent = <&UIC0>;
206 }; 208 };
207 209
208 ZMII0: emac-zmii@ef600d00 { 210 ZMII0: emac-zmii@ef600d00 {
209 compatible = "ibm,zmii-440ep", "ibm,zmii-440gp", "ibm,zmii"; 211 compatible = "ibm,zmii-440ep", "ibm,zmii-440gp", "ibm,zmii";
210 reg = <ef600d00 c>; 212 reg = <0xef600d00 0x0000000c>;
211 }; 213 };
212 214
213 EMAC0: ethernet@ef600e00 { 215 EMAC0: ethernet@ef600e00 {
214 device_type = "network"; 216 device_type = "network";
215 compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac"; 217 compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac";
216 interrupt-parent = <&UIC1>; 218 interrupt-parent = <&UIC1>;
217 interrupts = <1c 4 1d 4>; 219 interrupts = <0x1c 0x4 0x1d 0x4>;
218 reg = <ef600e00 70>; 220 reg = <0xef600e00 0x00000070>;
219 local-mac-address = [000000000000]; 221 local-mac-address = [000000000000];
220 mal-device = <&MAL0>; 222 mal-device = <&MAL0>;
221 mal-tx-channel = <0 1>; 223 mal-tx-channel = <0 1>;
222 mal-rx-channel = <0>; 224 mal-rx-channel = <0>;
223 cell-index = <0>; 225 cell-index = <0>;
224 max-frame-size = <5dc>; 226 max-frame-size = <1500>;
225 rx-fifo-size = <1000>; 227 rx-fifo-size = <4096>;
226 tx-fifo-size = <800>; 228 tx-fifo-size = <2048>;
227 phy-mode = "rmii"; 229 phy-mode = "rmii";
228 phy-map = <00000000>; 230 phy-map = <0x00000000>;
229 zmii-device = <&ZMII0>; 231 zmii-device = <&ZMII0>;
230 zmii-channel = <0>; 232 zmii-channel = <0>;
231 }; 233 };
@@ -234,26 +236,26 @@
234 device_type = "network"; 236 device_type = "network";
235 compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac"; 237 compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac";
236 interrupt-parent = <&UIC1>; 238 interrupt-parent = <&UIC1>;
237 interrupts = <1e 4 1f 4>; 239 interrupts = <0x1e 0x4 0x1f 0x4>;
238 reg = <ef600f00 70>; 240 reg = <0xef600f00 0x00000070>;
239 local-mac-address = [000000000000]; 241 local-mac-address = [000000000000];
240 mal-device = <&MAL0>; 242 mal-device = <&MAL0>;
241 mal-tx-channel = <2 3>; 243 mal-tx-channel = <2 3>;
242 mal-rx-channel = <1>; 244 mal-rx-channel = <1>;
243 cell-index = <1>; 245 cell-index = <1>;
244 max-frame-size = <5dc>; 246 max-frame-size = <1500>;
245 rx-fifo-size = <1000>; 247 rx-fifo-size = <4096>;
246 tx-fifo-size = <800>; 248 tx-fifo-size = <2048>;
247 phy-mode = "rmii"; 249 phy-mode = "rmii";
248 phy-map = <00000000>; 250 phy-map = <0x00000000>;
249 zmii-device = <&ZMII0>; 251 zmii-device = <&ZMII0>;
250 zmii-channel = <1>; 252 zmii-channel = <1>;
251 }; 253 };
252 254
253 usb@ef601000 { 255 usb@ef601000 {
254 compatible = "ohci-be"; 256 compatible = "ohci-be";
255 reg = <ef601000 80>; 257 reg = <0xef601000 0x00000080>;
256 interrupts = <8 4 9 4>; 258 interrupts = <0x8 0x4 0x9 0x4>;
257 interrupt-parent = < &UIC1 >; 259 interrupt-parent = < &UIC1 >;
258 }; 260 };
259 }; 261 };
@@ -265,35 +267,35 @@
265 #address-cells = <3>; 267 #address-cells = <3>;
266 compatible = "ibm,plb440ep-pci", "ibm,plb-pci"; 268 compatible = "ibm,plb440ep-pci", "ibm,plb-pci";
267 primary; 269 primary;
268 reg = <0 eec00000 8 /* Config space access */ 270 reg = <0x00000000 0xeec00000 0x00000008 /* Config space access */
269 0 eed00000 4 /* IACK */ 271 0x00000000 0xeed00000 0x00000004 /* IACK */
270 0 eed00000 4 /* Special cycle */ 272 0x00000000 0xeed00000 0x00000004 /* Special cycle */
271 0 ef400000 40>; /* Internal registers */ 273 0x00000000 0xef400000 0x00000040>; /* Internal registers */
272 274
273 /* Outbound ranges, one memory and one IO, 275 /* Outbound ranges, one memory and one IO,
274 * later cannot be changed. Chip supports a second 276 * later cannot be changed. Chip supports a second
275 * IO range but we don't use it for now 277 * IO range but we don't use it for now
276 */ 278 */
277 ranges = <02000000 0 a0000000 0 a0000000 0 20000000 279 ranges = <0x02000000 0x00000000 0xa0000000 0x00000000 0xa0000000 0x00000000 0x20000000
278 01000000 0 00000000 0 e8000000 0 00010000>; 280 0x01000000 0x00000000 0x00000000 0x00000000 0xe8000000 0x00000000 0x00010000>;
279 281
280 /* Inbound 2GB range starting at 0 */ 282 /* Inbound 2GB range starting at 0 */
281 dma-ranges = <42000000 0 0 0 0 0 80000000>; 283 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
282 284
283 /* Bamboo has all 4 IRQ pins tied together per slot */ 285 /* Bamboo has all 4 IRQ pins tied together per slot */
284 interrupt-map-mask = <f800 0 0 0>; 286 interrupt-map-mask = <0xf800 0x0 0x0 0x0>;
285 interrupt-map = < 287 interrupt-map = <
286 /* IDSEL 1 */ 288 /* IDSEL 1 */
287 0800 0 0 0 &UIC0 1c 8 289 0x800 0x0 0x0 0x0 &UIC0 0x1c 0x8
288 290
289 /* IDSEL 2 */ 291 /* IDSEL 2 */
290 1000 0 0 0 &UIC0 1b 8 292 0x1000 0x0 0x0 0x0 &UIC0 0x1b 0x8
291 293
292 /* IDSEL 3 */ 294 /* IDSEL 3 */
293 1800 0 0 0 &UIC0 1a 8 295 0x1800 0x0 0x0 0x0 &UIC0 0x1a 0x8
294 296
295 /* IDSEL 4 */ 297 /* IDSEL 4 */
296 2000 0 0 0 &UIC0 19 8 298 0x2000 0x0 0x0 0x0 &UIC0 0x19 0x8
297 >; 299 >;
298 }; 300 };
299 }; 301 };
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-25 02:25:36 -0500