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-rw-r--r--arch/powerpc/boot/dts/bamboo.dts244
-rw-r--r--arch/powerpc/boot/dts/ebony.dts35
-rw-r--r--arch/powerpc/boot/dts/ep88xc.dts214
-rw-r--r--arch/powerpc/boot/dts/holly.dts5
-rw-r--r--arch/powerpc/boot/dts/kilauea.dts252
-rw-r--r--arch/powerpc/boot/dts/kuroboxHD.dts9
-rw-r--r--arch/powerpc/boot/dts/kuroboxHG.dts9
-rw-r--r--arch/powerpc/boot/dts/lite5200.dts59
-rw-r--r--arch/powerpc/boot/dts/lite5200b.dts119
-rw-r--r--arch/powerpc/boot/dts/mpc7448hpc2.dts9
-rw-r--r--arch/powerpc/boot/dts/mpc8272ads.dts431
-rw-r--r--arch/powerpc/boot/dts/mpc8313erdb.dts67
-rw-r--r--arch/powerpc/boot/dts/mpc832x_mds.dts122
-rw-r--r--arch/powerpc/boot/dts/mpc832x_rdb.dts72
-rw-r--r--arch/powerpc/boot/dts/mpc8349emitx.dts104
-rw-r--r--arch/powerpc/boot/dts/mpc8349emitxgp.dts52
-rw-r--r--arch/powerpc/boot/dts/mpc834x_mds.dts249
-rw-r--r--arch/powerpc/boot/dts/mpc836x_mds.dts123
-rw-r--r--arch/powerpc/boot/dts/mpc8540ads.dts175
-rw-r--r--arch/powerpc/boot/dts/mpc8541cds.dts228
-rw-r--r--arch/powerpc/boot/dts/mpc8544ds.dts377
-rw-r--r--arch/powerpc/boot/dts/mpc8548cds.dts404
-rw-r--r--arch/powerpc/boot/dts/mpc8555cds.dts228
-rw-r--r--arch/powerpc/boot/dts/mpc8560ads.dts267
-rw-r--r--arch/powerpc/boot/dts/mpc8568mds.dts160
-rw-r--r--arch/powerpc/boot/dts/mpc8572ds.dts404
-rw-r--r--arch/powerpc/boot/dts/mpc8610_hpcd.dts191
-rw-r--r--arch/powerpc/boot/dts/mpc8641_hpcn.dts289
-rw-r--r--arch/powerpc/boot/dts/mpc866ads.dts5
-rw-r--r--arch/powerpc/boot/dts/mpc885ads.dts211
-rw-r--r--arch/powerpc/boot/dts/pq2fads.dts240
-rw-r--r--arch/powerpc/boot/dts/prpmc2800.dts5
-rw-r--r--arch/powerpc/boot/dts/sequoia.dts302
-rw-r--r--arch/powerpc/boot/dts/walnut.dts190
34 files changed, 4011 insertions, 1840 deletions
diff --git a/arch/powerpc/boot/dts/bamboo.dts b/arch/powerpc/boot/dts/bamboo.dts
new file mode 100644
index 000000000000..a88ae3d218a5
--- /dev/null
+++ b/arch/powerpc/boot/dts/bamboo.dts
@@ -0,0 +1,244 @@
1/*
2 * Device Tree Source for AMCC Bamboo
3 *
4 * Copyright (c) 2006, 2007 IBM Corp.
5 * Josh Boyer <jwboyer@linux.vnet.ibm.com>
6 *
7 * FIXME: Draft only!
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without
11 * any warranty of any kind, whether express or implied.
12 */
13
14/ {
15 #address-cells = <2>;
16 #size-cells = <1>;
17 model = "amcc,bamboo";
18 compatible = "amcc,bamboo";
19 dcr-parent = <&/cpus/PowerPC,440EP@0>;
20
21 cpus {
22 #address-cells = <1>;
23 #size-cells = <0>;
24
25 PowerPC,440EP@0 {
26 device_type = "cpu";
27 reg = <0>;
28 clock-frequency = <0>; /* Filled in by zImage */
29 timebase-frequency = <0>; /* Filled in by zImage */
30 i-cache-line-size = <20>;
31 d-cache-line-size = <20>;
32 i-cache-size = <8000>;
33 d-cache-size = <8000>;
34 dcr-controller;
35 dcr-access-method = "native";
36 };
37 };
38
39 memory {
40 device_type = "memory";
41 reg = <0 0 0>; /* Filled in by zImage */
42 };
43
44 UIC0: interrupt-controller0 {
45 compatible = "ibm,uic-440ep","ibm,uic";
46 interrupt-controller;
47 cell-index = <0>;
48 dcr-reg = <0c0 009>;
49 #address-cells = <0>;
50 #size-cells = <0>;
51 #interrupt-cells = <2>;
52 };
53
54 UIC1: interrupt-controller1 {
55 compatible = "ibm,uic-440ep","ibm,uic";
56 interrupt-controller;
57 cell-index = <1>;
58 dcr-reg = <0d0 009>;
59 #address-cells = <0>;
60 #size-cells = <0>;
61 #interrupt-cells = <2>;
62 interrupts = <1e 4 1f 4>; /* cascade */
63 interrupt-parent = <&UIC0>;
64 };
65
66 SDR0: sdr {
67 compatible = "ibm,sdr-440ep";
68 dcr-reg = <00e 002>;
69 };
70
71 CPR0: cpr {
72 compatible = "ibm,cpr-440ep";
73 dcr-reg = <00c 002>;
74 };
75
76 plb {
77 compatible = "ibm,plb-440ep", "ibm,plb-440gp", "ibm,plb4";
78 #address-cells = <2>;
79 #size-cells = <1>;
80 ranges;
81 clock-frequency = <0>; /* Filled in by zImage */
82
83 SDRAM0: sdram {
84 compatible = "ibm,sdram-440ep", "ibm,sdram-405gp";
85 dcr-reg = <010 2>;
86 };
87
88 DMA0: dma {
89 compatible = "ibm,dma-440ep", "ibm,dma-440gp";
90 dcr-reg = <100 027>;
91 };
92
93 MAL0: mcmal {
94 compatible = "ibm,mcmal-440ep", "ibm,mcmal-440gp", "ibm,mcmal";
95 dcr-reg = <180 62>;
96 num-tx-chans = <4>;
97 num-rx-chans = <2>;
98 interrupt-parent = <&MAL0>;
99 interrupts = <0 1 2 3 4>;
100 #interrupt-cells = <1>;
101 interrupt-map = </*TXEOB*/ 0 &UIC0 a 4
102 /*RXEOB*/ 1 &UIC0 b 4
103 /*SERR*/ 2 &UIC1 0 4
104 /*TXDE*/ 3 &UIC1 1 4
105 /*RXDE*/ 4 &UIC1 3 4>;
106 };
107
108 POB0: opb {
109 compatible = "ibm,opb-440ep", "ibm,opb-440gp", "ibm,opb";
110 #address-cells = <1>;
111 #size-cells = <1>;
112 /* Bamboo is oddball in the 44x world and doesn't use the ERPN
113 * bits.
114 */
115 ranges = <00000000 0 00000000 80000000
116 80000000 0 80000000 80000000>;
117 interrupt-parent = <&UIC1>;
118 interrupts = <7 4>;
119 clock-frequency = <0>; /* Filled in by zImage */
120
121 EBC0: ebc {
122 compatible = "ibm,ebc-440ep", "ibm,ebc-440gp", "ibm,ebc";
123 dcr-reg = <012 2>;
124 #address-cells = <2>;
125 #size-cells = <1>;
126 clock-frequency = <0>; /* Filled in by zImage */
127 ranges;
128 interrupts = <5 1>;
129 interrupt-parent = <&UIC1>;
130 };
131
132 UART0: serial@ef600300 {
133 device_type = "serial";
134 compatible = "ns16550";
135 reg = <ef600300 8>;
136 virtual-reg = <ef600300>;
137 clock-frequency = <0>; /* Filled in by zImage */
138 current-speed = <1c200>;
139 interrupt-parent = <&UIC0>;
140 interrupts = <0 4>;
141 };
142
143 UART1: serial@ef600400 {
144 device_type = "serial";
145 compatible = "ns16550";
146 reg = <ef600400 8>;
147 virtual-reg = <ef600400>;
148 clock-frequency = <0>;
149 current-speed = <0>;
150 interrupt-parent = <&UIC0>;
151 interrupts = <1 4>;
152 };
153
154 UART2: serial@ef600500 {
155 device_type = "serial";
156 compatible = "ns16550";
157 reg = <ef600500 8>;
158 virtual-reg = <ef600500>;
159 clock-frequency = <0>;
160 current-speed = <0>;
161 interrupt-parent = <&UIC0>;
162 interrupts = <3 4>;
163 };
164
165 UART3: serial@ef600600 {
166 device_type = "serial";
167 compatible = "ns16550";
168 reg = <ef600600 8>;
169 virtual-reg = <ef600600>;
170 clock-frequency = <0>;
171 current-speed = <0>;
172 interrupt-parent = <&UIC0>;
173 interrupts = <4 4>;
174 };
175
176 IIC0: i2c@ef600700 {
177 device_type = "i2c";
178 compatible = "ibm,iic-440ep", "ibm,iic-440gp", "ibm,iic";
179 reg = <ef600700 14>;
180 interrupt-parent = <&UIC0>;
181 interrupts = <2 4>;
182 };
183
184 IIC1: i2c@ef600800 {
185 device_type = "i2c";
186 compatible = "ibm,iic-440ep", "ibm,iic-440gp", "ibm,iic";
187 reg = <ef600800 14>;
188 interrupt-parent = <&UIC0>;
189 interrupts = <7 4>;
190 };
191
192 ZMII0: emac-zmii@ef600d00 {
193 device_type = "zmii-interface";
194 compatible = "ibm,zmii-440ep", "ibm,zmii-440gp", "ibm,zmii";
195 reg = <ef600d00 c>;
196 };
197
198 EMAC0: ethernet@ef600e00 {
199 device_type = "network";
200 compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac";
201 interrupt-parent = <&UIC1>;
202 interrupts = <1c 4 1d 4>;
203 reg = <ef600e00 70>;
204 local-mac-address = [000000000000];
205 mal-device = <&MAL0>;
206 mal-tx-channel = <0 1>;
207 mal-rx-channel = <0>;
208 cell-index = <0>;
209 max-frame-size = <5dc>;
210 rx-fifo-size = <1000>;
211 tx-fifo-size = <800>;
212 phy-mode = "rmii";
213 phy-map = <00000001>;
214 zmii-device = <&ZMII0>;
215 zmii-channel = <0>;
216 };
217
218 EMAC1: ethernet@ef600f00 {
219 device_type = "network";
220 compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac";
221 interrupt-parent = <&UIC1>;
222 interrupts = <1e 4 1f 4>;
223 reg = <ef600f00 70>;
224 local-mac-address = [000000000000];
225 mal-device = <&MAL0>;
226 mal-tx-channel = <2 3>;
227 mal-rx-channel = <1>;
228 cell-index = <1>;
229 max-frame-size = <5dc>;
230 rx-fifo-size = <1000>;
231 tx-fifo-size = <800>;
232 phy-mode = "rmii";
233 phy-map = <00000001>;
234 zmii-device = <&ZMII0>;
235 zmii-channel = <1>;
236 };
237 };
238 };
239
240 chosen {
241 linux,stdout-path = "/plb/opb/serial@ef600300";
242 bootargs = "console=ttyS0,115200";
243 };
244};
diff --git a/arch/powerpc/boot/dts/ebony.dts b/arch/powerpc/boot/dts/ebony.dts
index c5f99613fc7b..bc259972aaa0 100644
--- a/arch/powerpc/boot/dts/ebony.dts
+++ b/arch/powerpc/boot/dts/ebony.dts
@@ -9,10 +9,6 @@
9 * This file is licensed under the terms of the GNU General Public 9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without 10 * License version 2. This program is licensed "as is" without
11 * any warranty of any kind, whether express or implied. 11 * any warranty of any kind, whether express or implied.
12 *
13 * To build:
14 * dtc -I dts -O asm -o ebony.S -b 0 ebony.dts
15 * dtc -I dts -O dtb -o ebony.dtb -b 0 ebony.dts
16 */ 12 */
17 13
18/ { 14/ {
@@ -142,13 +138,16 @@
142 interrupt-parent = <&UIC1>; 138 interrupt-parent = <&UIC1>;
143 139
144 small-flash@0,80000 { 140 small-flash@0,80000 {
145 device_type = "rom"; 141 compatible = "jedec-flash";
146 compatible = "direct-mapped";
147 probe-type = "JEDEC";
148 bank-width = <1>; 142 bank-width = <1>;
149 partitions = <0 80000>;
150 partition-names = "OpenBIOS";
151 reg = <0 80000 80000>; 143 reg = <0 80000 80000>;
144 #address-cells = <1>;
145 #size-cells = <1>;
146 partition@0 {
147 label = "OpenBIOS";
148 reg = <0 80000>;
149 read-only;
150 };
152 }; 151 };
153 152
154 ds1743@1,0 { 153 ds1743@1,0 {
@@ -158,14 +157,19 @@
158 }; 157 };
159 158
160 large-flash@2,0 { 159 large-flash@2,0 {
161 device_type = "rom"; 160 compatible = "jedec-flash";
162 compatible = "direct-mapped";
163 probe-type = "JEDEC";
164 bank-width = <1>; 161 bank-width = <1>;
165 partitions = <0 380000
166 380000 80000>;
167 partition-names = "fs", "firmware";
168 reg = <2 0 400000>; 162 reg = <2 0 400000>;
163 #address-cells = <1>;
164 #size-cells = <1>;
165 partition@0 {
166 label = "fs";
167 reg = <0 380000>;
168 };
169 partition@380000 {
170 label = "firmware";
171 reg = <380000 80000>;
172 };
169 }; 173 };
170 174
171 ir@3,0 { 175 ir@3,0 {
@@ -175,6 +179,7 @@
175 fpga@7,0 { 179 fpga@7,0 {
176 compatible = "Ebony-FPGA"; 180 compatible = "Ebony-FPGA";
177 reg = <7 0 10>; 181 reg = <7 0 10>;
182 virtual-reg = <e8300000>;
178 }; 183 };
179 }; 184 };
180 185
diff --git a/arch/powerpc/boot/dts/ep88xc.dts b/arch/powerpc/boot/dts/ep88xc.dts
new file mode 100644
index 000000000000..02705f299790
--- /dev/null
+++ b/arch/powerpc/boot/dts/ep88xc.dts
@@ -0,0 +1,214 @@
1/*
2 * EP88xC Device Tree Source
3 *
4 * Copyright 2006 MontaVista Software, Inc.
5 * Copyright 2007 Freescale Semiconductor, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13
14/ {
15 model = "EP88xC";
16 compatible = "fsl,ep88xc";
17 #address-cells = <1>;
18 #size-cells = <1>;
19
20 cpus {
21 #address-cells = <1>;
22 #size-cells = <0>;
23
24 PowerPC,885@0 {
25 device_type = "cpu";
26 reg = <0>;
27 d-cache-line-size = <d#16>;
28 i-cache-line-size = <d#16>;
29 d-cache-size = <d#8192>;
30 i-cache-size = <d#8192>;
31 timebase-frequency = <0>;
32 bus-frequency = <0>;
33 clock-frequency = <0>;
34 interrupts = <f 2>; // decrementer interrupt
35 interrupt-parent = <&PIC>;
36 };
37 };
38
39 memory {
40 device_type = "memory";
41 reg = <0 0>;
42 };
43
44 localbus@fa200100 {
45 compatible = "fsl,mpc885-localbus", "fsl,pq1-localbus";
46 #address-cells = <2>;
47 #size-cells = <1>;
48 reg = <fa200100 40>;
49
50 ranges = <
51 0 0 fc000000 04000000
52 3 0 fa000000 01000000
53 >;
54
55 flash@0,2000000 {
56 compatible = "cfi-flash";
57 reg = <0 2000000 2000000>;
58 bank-width = <4>;
59 device-width = <2>;
60 };
61
62 board-control@3,400000 {
63 reg = <3 400000 10>;
64 compatible = "fsl,ep88xc-bcsr";
65 };
66 };
67
68 soc@fa200000 {
69 compatible = "fsl,mpc885", "fsl,pq1-soc";
70 #address-cells = <1>;
71 #size-cells = <1>;
72 device_type = "soc";
73 ranges = <0 fa200000 00004000>;
74 bus-frequency = <0>;
75
76 // Temporary -- will go away once kernel uses ranges for get_immrbase().
77 reg = <fa200000 4000>;
78
79 mdio@e00 {
80 compatible = "fsl,mpc885-fec-mdio", "fsl,pq1-fec-mdio";
81 reg = <e00 188>;
82 #address-cells = <1>;
83 #size-cells = <0>;
84
85 PHY0: ethernet-phy@0 {
86 reg = <0>;
87 device_type = "ethernet-phy";
88 };
89
90 PHY1: ethernet-phy@1 {
91 reg = <1>;
92 device_type = "ethernet-phy";
93 };
94 };
95
96 ethernet@e00 {
97 device_type = "network";
98 compatible = "fsl,mpc885-fec-enet",
99 "fsl,pq1-fec-enet";
100 reg = <e00 188>;
101 local-mac-address = [ 00 00 00 00 00 00 ];
102 interrupts = <3 1>;
103 interrupt-parent = <&PIC>;
104 phy-handle = <&PHY0>;
105 linux,network-index = <0>;
106 };
107
108 ethernet@1e00 {
109 device_type = "network";
110 compatible = "fsl,mpc885-fec-enet",
111 "fsl,pq1-fec-enet";
112 reg = <1e00 188>;
113 local-mac-address = [ 00 00 00 00 00 00 ];
114 interrupts = <7 1>;
115 interrupt-parent = <&PIC>;
116 phy-handle = <&PHY1>;
117 linux,network-index = <1>;
118 };
119
120 PIC: interrupt-controller@0 {
121 interrupt-controller;
122 #interrupt-cells = <2>;
123 reg = <0 24>;
124 compatible = "fsl,mpc885-pic", "fsl,pq1-pic";
125 };
126
127 pcmcia@80 {
128 #address-cells = <3>;
129 #interrupt-cells = <1>;
130 #size-cells = <2>;
131 compatible = "fsl,pq-pcmcia";
132 device_type = "pcmcia";
133 reg = <80 80>;
134 interrupt-parent = <&PIC>;
135 interrupts = <d 1>;
136 };
137
138 cpm@9c0 {
139 #address-cells = <1>;
140 #size-cells = <1>;
141 compatible = "fsl,mpc885-cpm", "fsl,cpm1";
142 command-proc = <9c0>;
143 interrupts = <0>; // cpm error interrupt
144 interrupt-parent = <&CPM_PIC>;
145 reg = <9c0 40>;
146 ranges;
147
148 muram@2000 {
149 #address-cells = <1>;
150 #size-cells = <1>;
151 ranges = <0 2000 2000>;
152
153 data@0 {
154 compatible = "fsl,cpm-muram-data";
155 reg = <0 1c00>;
156 };
157 };
158
159 brg@9f0 {
160 compatible = "fsl,mpc885-brg",
161 "fsl,cpm1-brg",
162 "fsl,cpm-brg";
163 reg = <9f0 10>;
164 };
165
166 CPM_PIC: interrupt-controller@930 {
167 interrupt-controller;
168 #interrupt-cells = <1>;
169 interrupts = <5 2 0 2>;
170 interrupt-parent = <&PIC>;
171 reg = <930 20>;
172 compatible = "fsl,mpc885-cpm-pic",
173 "fsl,cpm1-pic";
174 };
175
176 // MON-1
177 serial@a80 {
178 device_type = "serial";
179 compatible = "fsl,mpc885-smc-uart",
180 "fsl,cpm1-smc-uart";
181 reg = <a80 10 3e80 40>;
182 interrupts = <4>;
183 interrupt-parent = <&CPM_PIC>;
184 fsl,cpm-brg = <1>;
185 fsl,cpm-command = <0090>;
186 linux,planetcore-label = "SMC1";
187 };
188
189 // SER-1
190 serial@a20 {
191 device_type = "serial";
192 compatible = "fsl,mpc885-scc-uart",
193 "fsl,cpm1-scc-uart";
194 reg = <a20 20 3d00 80>;
195 interrupts = <1d>;
196 interrupt-parent = <&CPM_PIC>;
197 fsl,cpm-brg = <2>;
198 fsl,cpm-command = <0040>;
199 linux,planetcore-label = "SCC2";
200 };
201
202 usb@a00 {
203 #address-cells = <1>;
204 #size-cells = <0>;
205 compatible = "fsl,mpc885-usb",
206 "fsl,cpm1-usb";
207 reg = <a00 18 1c00 80>;
208 interrupt-parent = <&CPM_PIC>;
209 interrupts = <1e>;
210 fsl,cpm-command = <0000>;
211 };
212 };
213 };
214};
diff --git a/arch/powerpc/boot/dts/holly.dts b/arch/powerpc/boot/dts/holly.dts
index 80a4fab8ee37..b5d87895fe06 100644
--- a/arch/powerpc/boot/dts/holly.dts
+++ b/arch/powerpc/boot/dts/holly.dts
@@ -8,10 +8,6 @@
8 * This file is licensed under the terms of the GNU General Public 8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without 9 * License version 2. This program is licensed "as is" without
10 * any warranty of any kind, whether express or implied. 10 * any warranty of any kind, whether express or implied.
11 *
12 * To build:
13 * dtc -I dts -O asm -o holly.S -b 0 holly.dts
14 * dtc -I dts -O dtb -o holly.dtb -b 0 holly.dts
15 */ 11 */
16 12
17/ { 13/ {
@@ -35,7 +31,6 @@
35 timebase-frequency = <2faf080>; 31 timebase-frequency = <2faf080>;
36 clock-frequency = <23c34600>; 32 clock-frequency = <23c34600>;
37 bus-frequency = <bebc200>; 33 bus-frequency = <bebc200>;
38 32-bit;
39 }; 34 };
40 }; 35 };
41 36
diff --git a/arch/powerpc/boot/dts/kilauea.dts b/arch/powerpc/boot/dts/kilauea.dts
new file mode 100644
index 000000000000..c824e8f06454
--- /dev/null
+++ b/arch/powerpc/boot/dts/kilauea.dts
@@ -0,0 +1,252 @@
1/*
2 * Device Tree Source for AMCC Kilauea (405EX)
3 *
4 * Copyright 2007 DENX Software Engineering, Stefan Roese <sr@denx.de>
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without
8 * any warranty of any kind, whether express or implied.
9 */
10
11/ {
12 #address-cells = <1>;
13 #size-cells = <1>;
14 model = "amcc,kilauea";
15 compatible = "amcc,kilauea";
16 dcr-parent = <&/cpus/PowerPC,405EX@0>;
17
18 cpus {
19 #address-cells = <1>;
20 #size-cells = <0>;
21
22 PowerPC,405EX@0 {
23 device_type = "cpu";
24 reg = <0>;
25 clock-frequency = <0>; /* Filled in by U-Boot */
26 timebase-frequency = <0>; /* Filled in by U-Boot */
27 i-cache-line-size = <20>;
28 d-cache-line-size = <20>;
29 i-cache-size = <4000>; /* 16 kB */
30 d-cache-size = <4000>; /* 16 kB */
31 dcr-controller;
32 dcr-access-method = "native";
33 };
34 };
35
36 memory {
37 device_type = "memory";
38 reg = <0 0>; /* Filled in by U-Boot */
39 };
40
41 UIC0: interrupt-controller {
42 compatible = "ibm,uic-405ex", "ibm,uic";
43 interrupt-controller;
44 cell-index = <0>;
45 dcr-reg = <0c0 009>;
46 #address-cells = <0>;
47 #size-cells = <0>;
48 #interrupt-cells = <2>;
49 };
50
51 UIC1: interrupt-controller1 {
52 compatible = "ibm,uic-405ex","ibm,uic";
53 interrupt-controller;
54 cell-index = <1>;
55 dcr-reg = <0d0 009>;
56 #address-cells = <0>;
57 #size-cells = <0>;
58 #interrupt-cells = <2>;
59 interrupts = <1e 4 1f 4>; /* cascade */
60 interrupt-parent = <&UIC0>;
61 };
62
63 UIC2: interrupt-controller2 {
64 compatible = "ibm,uic-405ex","ibm,uic";
65 interrupt-controller;
66 cell-index = <2>;
67 dcr-reg = <0e0 009>;
68 #address-cells = <0>;
69 #size-cells = <0>;
70 #interrupt-cells = <2>;
71 interrupts = <1c 4 1d 4>; /* cascade */
72 interrupt-parent = <&UIC0>;
73 };
74
75 plb {
76 compatible = "ibm,plb-405ex", "ibm,plb4";
77 #address-cells = <1>;
78 #size-cells = <1>;
79 ranges;
80 clock-frequency = <0>; /* Filled in by U-Boot */
81
82 SDRAM0: memory-controller {
83 compatible = "ibm,sdram-405ex";
84 dcr-reg = <010 2>;
85 };
86
87 MAL0: mcmal {
88 compatible = "ibm,mcmal-405ex", "ibm,mcmal2";
89 dcr-reg = <180 62>;
90 num-tx-chans = <2>;
91 num-rx-chans = <2>;
92 interrupt-parent = <&MAL0>;
93 interrupts = <0 1 2 3 4>;
94 #interrupt-cells = <1>;
95 #address-cells = <0>;
96 #size-cells = <0>;
97 interrupt-map = </*TXEOB*/ 0 &UIC0 a 4
98 /*RXEOB*/ 1 &UIC0 b 4
99 /*SERR*/ 2 &UIC1 0 4
100 /*TXDE*/ 3 &UIC1 1 4
101 /*RXDE*/ 4 &UIC1 2 4>;
102 interrupt-map-mask = <ffffffff>;
103 };
104
105 POB0: opb {
106 compatible = "ibm,opb-405ex", "ibm,opb";
107 #address-cells = <1>;
108 #size-cells = <1>;
109 ranges = <80000000 80000000 10000000
110 ef600000 ef600000 a00000
111 f0000000 f0000000 10000000>;
112 dcr-reg = <0a0 5>;
113 clock-frequency = <0>; /* Filled in by U-Boot */
114
115 EBC0: ebc {
116 compatible = "ibm,ebc-405ex", "ibm,ebc";
117 dcr-reg = <012 2>;
118 #address-cells = <2>;
119 #size-cells = <1>;
120 clock-frequency = <0>; /* Filled in by U-Boot */
121 /* ranges property is supplied by U-Boot */
122 interrupts = <5 1>;
123 interrupt-parent = <&UIC1>;
124
125 nor_flash@0,0 {
126 compatible = "amd,s29gl512n", "cfi-flash";
127 bank-width = <2>;
128 reg = <0 000000 4000000>;
129 #address-cells = <1>;
130 #size-cells = <1>;
131 partition@0 {
132 label = "kernel";
133 reg = <0 200000>;
134 };
135 partition@200000 {
136 label = "root";
137 reg = <200000 200000>;
138 };
139 partition@400000 {
140 label = "user";
141 reg = <400000 3b60000>;
142 };
143 partition@3f60000 {
144 label = "env";
145 reg = <3f60000 40000>;
146 };
147 partition@3fa0000 {
148 label = "u-boot";
149 reg = <3fa0000 60000>;
150 };
151 };
152 };
153
154 UART0: serial@ef600200 {
155 device_type = "serial";
156 compatible = "ns16550";
157 reg = <ef600200 8>;
158 virtual-reg = <ef600200>;
159 clock-frequency = <0>; /* Filled in by U-Boot */
160 current-speed = <0>;
161 interrupt-parent = <&UIC0>;
162 interrupts = <1a 4>;
163 };
164
165 UART1: serial@ef600300 {
166 device_type = "serial";
167 compatible = "ns16550";
168 reg = <ef600300 8>;
169 virtual-reg = <ef600300>;
170 clock-frequency = <0>; /* Filled in by U-Boot */
171 current-speed = <0>;
172 interrupt-parent = <&UIC0>;
173 interrupts = <1 4>;
174 };
175
176 IIC0: i2c@ef600400 {
177 device_type = "i2c";
178 compatible = "ibm,iic-405ex", "ibm,iic";
179 reg = <ef600400 14>;
180 interrupt-parent = <&UIC0>;
181 interrupts = <2 4>;
182 };
183
184 IIC1: i2c@ef600500 {
185 device_type = "i2c";
186 compatible = "ibm,iic-405ex", "ibm,iic";
187 reg = <ef600500 14>;
188 interrupt-parent = <&UIC0>;
189 interrupts = <7 4>;
190 };
191
192
193 RGMII0: emac-rgmii@ef600b00 {
194 device_type = "rgmii-interface";
195 compatible = "ibm,rgmii-405ex", "ibm,rgmii";
196 reg = <ef600b00 104>;
197 };
198
199 EMAC0: ethernet@ef600900 {
200 linux,network-index = <0>;
201 device_type = "network";
202 compatible = "ibm,emac-405ex", "ibm,emac4";
203 interrupt-parent = <&EMAC0>;
204 interrupts = <0 1>;
205 #interrupt-cells = <1>;
206 #address-cells = <0>;
207 #size-cells = <0>;
208 interrupt-map = </*Status*/ 0 &UIC0 18 4
209 /*Wake*/ 1 &UIC1 1d 4>;
210 reg = <ef600900 70>;
211 local-mac-address = [000000000000]; /* Filled in by U-Boot */
212 mal-device = <&MAL0>;
213 mal-tx-channel = <0>;
214 mal-rx-channel = <0>;
215 cell-index = <0>;
216 max-frame-size = <5dc>;
217 rx-fifo-size = <1000>;
218 tx-fifo-size = <800>;
219 phy-mode = "rgmii";
220 phy-map = <00000000>;
221 rgmii-device = <&RGMII0>;
222 rgmii-channel = <0>;
223 };
224
225 EMAC1: ethernet@ef600a00 {
226 linux,network-index = <1>;
227 device_type = "network";
228 compatible = "ibm,emac-405ex", "ibm,emac4";
229 interrupt-parent = <&EMAC1>;
230 interrupts = <0 1>;
231 #interrupt-cells = <1>;
232 #address-cells = <0>;
233 #size-cells = <0>;
234 interrupt-map = </*Status*/ 0 &UIC0 19 4
235 /*Wake*/ 1 &UIC1 1f 4>;
236 reg = <ef600a00 70>;
237 local-mac-address = [000000000000]; /* Filled in by U-Boot */
238 mal-device = <&MAL0>;
239 mal-tx-channel = <1>;
240 mal-rx-channel = <1>;
241 cell-index = <1>;
242 max-frame-size = <5dc>;
243 rx-fifo-size = <1000>;
244 tx-fifo-size = <800>;
245 phy-mode = "rgmii";
246 phy-map = <00000000>;
247 rgmii-device = <&RGMII0>;
248 rgmii-channel = <1>;
249 };
250 };
251 };
252};
diff --git a/arch/powerpc/boot/dts/kuroboxHD.dts b/arch/powerpc/boot/dts/kuroboxHD.dts
index 122537419d9f..ec71ab819fee 100644
--- a/arch/powerpc/boot/dts/kuroboxHD.dts
+++ b/arch/powerpc/boot/dts/kuroboxHD.dts
@@ -15,9 +15,6 @@
15 15
16XXXX add flash parts, rtc, ?? 16XXXX add flash parts, rtc, ??
17 17
18build with: "dtc -f -I dts -O dtb -o kuroboxHD.dtb -V 16 kuroboxHD.dts"
19
20
21 */ 18 */
22 19
23/ { 20/ {
@@ -50,7 +47,6 @@ build with: "dtc -f -I dts -O dtb -o kuroboxHD.dtb -V 16 kuroboxHD.dts"
50 soc10x { /* AFAICT need to make soc for 8245's uarts to be defined */ 47 soc10x { /* AFAICT need to make soc for 8245's uarts to be defined */
51 #address-cells = <1>; 48 #address-cells = <1>;
52 #size-cells = <1>; 49 #size-cells = <1>;
53 #interrupt-cells = <2>;
54 device_type = "soc"; 50 device_type = "soc";
55 compatible = "mpc10x"; 51 compatible = "mpc10x";
56 store-gathering = <0>; /* 0 == off, !0 == on */ 52 store-gathering = <0>; /* 0 == off, !0 == on */
@@ -72,7 +68,7 @@ build with: "dtc -f -I dts -O dtb -o kuroboxHD.dtb -V 16 kuroboxHD.dts"
72 68
73 rtc@32 { 69 rtc@32 {
74 device_type = "rtc"; 70 device_type = "rtc";
75 compatible = "ricoh,rs5c372b"; 71 compatible = "ricoh,rs5c372a";
76 reg = <32>; 72 reg = <32>;
77 }; 73 };
78 }; 74 };
@@ -83,7 +79,7 @@ build with: "dtc -f -I dts -O dtb -o kuroboxHD.dtb -V 16 kuroboxHD.dts"
83 reg = <80004500 8>; 79 reg = <80004500 8>;
84 clock-frequency = <5d08d88>; 80 clock-frequency = <5d08d88>;
85 current-speed = <2580>; 81 current-speed = <2580>;
86 interrupts = <9 2>; 82 interrupts = <9 0>;
87 interrupt-parent = <&mpic>; 83 interrupt-parent = <&mpic>;
88 }; 84 };
89 85
@@ -104,7 +100,6 @@ build with: "dtc -f -I dts -O dtb -o kuroboxHD.dtb -V 16 kuroboxHD.dts"
104 compatible = "chrp,open-pic"; 100 compatible = "chrp,open-pic";
105 interrupt-controller; 101 interrupt-controller;
106 reg = <80040000 40000>; 102 reg = <80040000 40000>;
107 built-in;
108 }; 103 };
109 104
110 pci@fec00000 { 105 pci@fec00000 {
diff --git a/arch/powerpc/boot/dts/kuroboxHG.dts b/arch/powerpc/boot/dts/kuroboxHG.dts
index 579aa8b967d9..32ecd2319928 100644
--- a/arch/powerpc/boot/dts/kuroboxHG.dts
+++ b/arch/powerpc/boot/dts/kuroboxHG.dts
@@ -15,9 +15,6 @@
15 15
16XXXX add flash parts, rtc, ?? 16XXXX add flash parts, rtc, ??
17 17
18build with: "dtc -f -I dts -O dtb -o kuroboxHG.dtb -V 16 kuroboxHG.dts"
19
20
21 */ 18 */
22 19
23/ { 20/ {
@@ -50,7 +47,6 @@ build with: "dtc -f -I dts -O dtb -o kuroboxHG.dtb -V 16 kuroboxHG.dts"
50 soc10x { /* AFAICT need to make soc for 8245's uarts to be defined */ 47 soc10x { /* AFAICT need to make soc for 8245's uarts to be defined */
51 #address-cells = <1>; 48 #address-cells = <1>;
52 #size-cells = <1>; 49 #size-cells = <1>;
53 #interrupt-cells = <2>;
54 device_type = "soc"; 50 device_type = "soc";
55 compatible = "mpc10x"; 51 compatible = "mpc10x";
56 store-gathering = <0>; /* 0 == off, !0 == on */ 52 store-gathering = <0>; /* 0 == off, !0 == on */
@@ -72,7 +68,7 @@ build with: "dtc -f -I dts -O dtb -o kuroboxHG.dtb -V 16 kuroboxHG.dts"
72 68
73 rtc@32 { 69 rtc@32 {
74 device_type = "rtc"; 70 device_type = "rtc";
75 compatible = "ricoh,rs5c372b"; 71 compatible = "ricoh,rs5c372a";
76 reg = <32>; 72 reg = <32>;
77 }; 73 };
78 }; 74 };
@@ -83,7 +79,7 @@ build with: "dtc -f -I dts -O dtb -o kuroboxHG.dtb -V 16 kuroboxHG.dts"
83 reg = <80004500 8>; 79 reg = <80004500 8>;
84 clock-frequency = <7c044a8>; 80 clock-frequency = <7c044a8>;
85 current-speed = <2580>; 81 current-speed = <2580>;
86 interrupts = <9 2>; 82 interrupts = <9 0>;
87 interrupt-parent = <&mpic>; 83 interrupt-parent = <&mpic>;
88 }; 84 };
89 85
@@ -104,7 +100,6 @@ build with: "dtc -f -I dts -O dtb -o kuroboxHG.dtb -V 16 kuroboxHG.dts"
104 compatible = "chrp,open-pic"; 100 compatible = "chrp,open-pic";
105 interrupt-controller; 101 interrupt-controller;
106 reg = <80040000 40000>; 102 reg = <80040000 40000>;
107 built-in;
108 }; 103 };
109 104
110 pci@fec00000 { 105 pci@fec00000 {
diff --git a/arch/powerpc/boot/dts/lite5200.dts b/arch/powerpc/boot/dts/lite5200.dts
index d29308fe4c24..bc45f5fbb060 100644
--- a/arch/powerpc/boot/dts/lite5200.dts
+++ b/arch/powerpc/boot/dts/lite5200.dts
@@ -19,7 +19,7 @@
19/ { 19/ {
20 model = "fsl,lite5200"; 20 model = "fsl,lite5200";
21 // revision = "1.0"; 21 // revision = "1.0";
22 compatible = "fsl,lite5200\0generic-mpc5200"; 22 compatible = "fsl,lite5200","generic-mpc5200";
23 #address-cells = <1>; 23 #address-cells = <1>;
24 #size-cells = <1>; 24 #size-cells = <1>;
25 25
@@ -37,7 +37,6 @@
37 timebase-frequency = <0>; // from bootloader 37 timebase-frequency = <0>; // from bootloader
38 bus-frequency = <0>; // from bootloader 38 bus-frequency = <0>; // from bootloader
39 clock-frequency = <0>; // from bootloader 39 clock-frequency = <0>; // from bootloader
40 32-bit;
41 }; 40 };
42 }; 41 };
43 42
@@ -50,10 +49,9 @@
50 model = "fsl,mpc5200"; 49 model = "fsl,mpc5200";
51 compatible = "mpc5200"; 50 compatible = "mpc5200";
52 revision = ""; // from bootloader 51 revision = ""; // from bootloader
53 #interrupt-cells = <3>;
54 device_type = "soc"; 52 device_type = "soc";
55 ranges = <0 f0000000 f0010000>; 53 ranges = <0 f0000000 0000c000>;
56 reg = <f0000000 00010000>; 54 reg = <f0000000 00000100>;
57 bus-frequency = <0>; // from bootloader 55 bus-frequency = <0>; // from bootloader
58 system-frequency = <0>; // from bootloader 56 system-frequency = <0>; // from bootloader
59 57
@@ -69,7 +67,6 @@
69 device_type = "interrupt-controller"; 67 device_type = "interrupt-controller";
70 compatible = "mpc5200-pic"; 68 compatible = "mpc5200-pic";
71 reg = <500 80>; 69 reg = <500 80>;
72 built-in;
73 }; 70 };
74 71
75 gpt@600 { // General Purpose Timer 72 gpt@600 { // General Purpose Timer
@@ -185,27 +182,6 @@
185 interrupt-parent = <&mpc5200_pic>; 182 interrupt-parent = <&mpc5200_pic>;
186 }; 183 };
187 184
188 pci@0d00 {
189 #interrupt-cells = <1>;
190 #size-cells = <2>;
191 #address-cells = <3>;
192 device_type = "pci";
193 compatible = "mpc5200-pci";
194 reg = <d00 100>;
195 interrupt-map-mask = <f800 0 0 7>;
196 interrupt-map = <c000 0 0 1 &mpc5200_pic 0 0 3
197 c000 0 0 2 &mpc5200_pic 0 0 3
198 c000 0 0 3 &mpc5200_pic 0 0 3
199 c000 0 0 4 &mpc5200_pic 0 0 3>;
200 clock-frequency = <0>; // From boot loader
201 interrupts = <2 8 0 2 9 0 2 a 0>;
202 interrupt-parent = <&mpc5200_pic>;
203 bus-range = <0 0>;
204 ranges = <42000000 0 80000000 80000000 0 20000000
205 02000000 0 a0000000 a0000000 0 10000000
206 01000000 0 00000000 b0000000 0 01000000>;
207 };
208
209 spi@f00 { 185 spi@f00 {
210 device_type = "spi"; 186 device_type = "spi";
211 compatible = "mpc5200-spi"; 187 compatible = "mpc5200-spi";
@@ -216,7 +192,7 @@
216 192
217 usb@1000 { 193 usb@1000 {
218 device_type = "usb-ohci-be"; 194 device_type = "usb-ohci-be";
219 compatible = "mpc5200-ohci\0ohci-be"; 195 compatible = "mpc5200-ohci","ohci-be";
220 reg = <1000 ff>; 196 reg = <1000 ff>;
221 interrupts = <2 6 0>; 197 interrupts = <2 6 0>;
222 interrupt-parent = <&mpc5200_pic>; 198 interrupt-parent = <&mpc5200_pic>;
@@ -317,7 +293,7 @@
317 293
318 i2c@3d00 { 294 i2c@3d00 {
319 device_type = "i2c"; 295 device_type = "i2c";
320 compatible = "mpc5200-i2c\0fsl-i2c"; 296 compatible = "mpc5200-i2c","fsl-i2c";
321 cell-index = <0>; 297 cell-index = <0>;
322 reg = <3d00 40>; 298 reg = <3d00 40>;
323 interrupts = <2 f 0>; 299 interrupts = <2 f 0>;
@@ -327,7 +303,7 @@
327 303
328 i2c@3d40 { 304 i2c@3d40 {
329 device_type = "i2c"; 305 device_type = "i2c";
330 compatible = "mpc5200-i2c\0fsl-i2c"; 306 compatible = "mpc5200-i2c","fsl-i2c";
331 cell-index = <1>; 307 cell-index = <1>;
332 reg = <3d40 40>; 308 reg = <3d40 40>;
333 interrupts = <2 10 0>; 309 interrupts = <2 10 0>;
@@ -336,8 +312,29 @@
336 }; 312 };
337 sram@8000 { 313 sram@8000 {
338 device_type = "sram"; 314 device_type = "sram";
339 compatible = "mpc5200-sram\0sram"; 315 compatible = "mpc5200-sram","sram";
340 reg = <8000 4000>; 316 reg = <8000 4000>;
341 }; 317 };
342 }; 318 };
319
320 pci@f0000d00 {
321 #interrupt-cells = <1>;
322 #size-cells = <2>;
323 #address-cells = <3>;
324 device_type = "pci";
325 compatible = "mpc5200-pci";
326 reg = <f0000d00 100>;
327 interrupt-map-mask = <f800 0 0 7>;
328 interrupt-map = <c000 0 0 1 &mpc5200_pic 0 0 3
329 c000 0 0 2 &mpc5200_pic 0 0 3
330 c000 0 0 3 &mpc5200_pic 0 0 3
331 c000 0 0 4 &mpc5200_pic 0 0 3>;
332 clock-frequency = <0>; // From boot loader
333 interrupts = <2 8 0 2 9 0 2 a 0>;
334 interrupt-parent = <&mpc5200_pic>;
335 bus-range = <0 0>;
336 ranges = <42000000 0 80000000 80000000 0 20000000
337 02000000 0 a0000000 a0000000 0 10000000
338 01000000 0 00000000 b0000000 0 01000000>;
339 };
343}; 340};
diff --git a/arch/powerpc/boot/dts/lite5200b.dts b/arch/powerpc/boot/dts/lite5200b.dts
index f242531f0451..a6bb1d0558ef 100644
--- a/arch/powerpc/boot/dts/lite5200b.dts
+++ b/arch/powerpc/boot/dts/lite5200b.dts
@@ -19,7 +19,7 @@
19/ { 19/ {
20 model = "fsl,lite5200b"; 20 model = "fsl,lite5200b";
21 // revision = "1.0"; 21 // revision = "1.0";
22 compatible = "fsl,lite5200b\0generic-mpc5200"; 22 compatible = "fsl,lite5200b","generic-mpc5200";
23 #address-cells = <1>; 23 #address-cells = <1>;
24 #size-cells = <1>; 24 #size-cells = <1>;
25 25
@@ -37,7 +37,6 @@
37 timebase-frequency = <0>; // from bootloader 37 timebase-frequency = <0>; // from bootloader
38 bus-frequency = <0>; // from bootloader 38 bus-frequency = <0>; // from bootloader
39 clock-frequency = <0>; // from bootloader 39 clock-frequency = <0>; // from bootloader
40 32-bit;
41 }; 40 };
42 }; 41 };
43 42
@@ -50,15 +49,14 @@
50 model = "fsl,mpc5200b"; 49 model = "fsl,mpc5200b";
51 compatible = "mpc5200"; 50 compatible = "mpc5200";
52 revision = ""; // from bootloader 51 revision = ""; // from bootloader
53 #interrupt-cells = <3>;
54 device_type = "soc"; 52 device_type = "soc";
55 ranges = <0 f0000000 f0010000>; 53 ranges = <0 f0000000 0000c000>;
56 reg = <f0000000 00010000>; 54 reg = <f0000000 00000100>;
57 bus-frequency = <0>; // from bootloader 55 bus-frequency = <0>; // from bootloader
58 system-frequency = <0>; // from bootloader 56 system-frequency = <0>; // from bootloader
59 57
60 cdm@200 { 58 cdm@200 {
61 compatible = "mpc5200b-cdm\0mpc5200-cdm"; 59 compatible = "mpc5200b-cdm","mpc5200-cdm";
62 reg = <200 38>; 60 reg = <200 38>;
63 }; 61 };
64 62
@@ -67,13 +65,12 @@
67 interrupt-controller; 65 interrupt-controller;
68 #interrupt-cells = <3>; 66 #interrupt-cells = <3>;
69 device_type = "interrupt-controller"; 67 device_type = "interrupt-controller";
70 compatible = "mpc5200b-pic\0mpc5200-pic"; 68 compatible = "mpc5200b-pic","mpc5200-pic";
71 reg = <500 80>; 69 reg = <500 80>;
72 built-in;
73 }; 70 };
74 71
75 gpt@600 { // General Purpose Timer 72 gpt@600 { // General Purpose Timer
76 compatible = "mpc5200b-gpt\0mpc5200-gpt"; 73 compatible = "mpc5200b-gpt","mpc5200-gpt";
77 device_type = "gpt"; 74 device_type = "gpt";
78 cell-index = <0>; 75 cell-index = <0>;
79 reg = <600 10>; 76 reg = <600 10>;
@@ -83,7 +80,7 @@
83 }; 80 };
84 81
85 gpt@610 { // General Purpose Timer 82 gpt@610 { // General Purpose Timer
86 compatible = "mpc5200b-gpt\0mpc5200-gpt"; 83 compatible = "mpc5200b-gpt","mpc5200-gpt";
87 device_type = "gpt"; 84 device_type = "gpt";
88 cell-index = <1>; 85 cell-index = <1>;
89 reg = <610 10>; 86 reg = <610 10>;
@@ -92,7 +89,7 @@
92 }; 89 };
93 90
94 gpt@620 { // General Purpose Timer 91 gpt@620 { // General Purpose Timer
95 compatible = "mpc5200b-gpt\0mpc5200-gpt"; 92 compatible = "mpc5200b-gpt","mpc5200-gpt";
96 device_type = "gpt"; 93 device_type = "gpt";
97 cell-index = <2>; 94 cell-index = <2>;
98 reg = <620 10>; 95 reg = <620 10>;
@@ -101,7 +98,7 @@
101 }; 98 };
102 99
103 gpt@630 { // General Purpose Timer 100 gpt@630 { // General Purpose Timer
104 compatible = "mpc5200b-gpt\0mpc5200-gpt"; 101 compatible = "mpc5200b-gpt","mpc5200-gpt";
105 device_type = "gpt"; 102 device_type = "gpt";
106 cell-index = <3>; 103 cell-index = <3>;
107 reg = <630 10>; 104 reg = <630 10>;
@@ -110,7 +107,7 @@
110 }; 107 };
111 108
112 gpt@640 { // General Purpose Timer 109 gpt@640 { // General Purpose Timer
113 compatible = "mpc5200b-gpt\0mpc5200-gpt"; 110 compatible = "mpc5200b-gpt","mpc5200-gpt";
114 device_type = "gpt"; 111 device_type = "gpt";
115 cell-index = <4>; 112 cell-index = <4>;
116 reg = <640 10>; 113 reg = <640 10>;
@@ -119,7 +116,7 @@
119 }; 116 };
120 117
121 gpt@650 { // General Purpose Timer 118 gpt@650 { // General Purpose Timer
122 compatible = "mpc5200b-gpt\0mpc5200-gpt"; 119 compatible = "mpc5200b-gpt","mpc5200-gpt";
123 device_type = "gpt"; 120 device_type = "gpt";
124 cell-index = <5>; 121 cell-index = <5>;
125 reg = <650 10>; 122 reg = <650 10>;
@@ -128,7 +125,7 @@
128 }; 125 };
129 126
130 gpt@660 { // General Purpose Timer 127 gpt@660 { // General Purpose Timer
131 compatible = "mpc5200b-gpt\0mpc5200-gpt"; 128 compatible = "mpc5200b-gpt","mpc5200-gpt";
132 device_type = "gpt"; 129 device_type = "gpt";
133 cell-index = <6>; 130 cell-index = <6>;
134 reg = <660 10>; 131 reg = <660 10>;
@@ -137,7 +134,7 @@
137 }; 134 };
138 135
139 gpt@670 { // General Purpose Timer 136 gpt@670 { // General Purpose Timer
140 compatible = "mpc5200b-gpt\0mpc5200-gpt"; 137 compatible = "mpc5200b-gpt","mpc5200-gpt";
141 device_type = "gpt"; 138 device_type = "gpt";
142 cell-index = <7>; 139 cell-index = <7>;
143 reg = <670 10>; 140 reg = <670 10>;
@@ -146,7 +143,7 @@
146 }; 143 };
147 144
148 rtc@800 { // Real time clock 145 rtc@800 { // Real time clock
149 compatible = "mpc5200b-rtc\0mpc5200-rtc"; 146 compatible = "mpc5200b-rtc","mpc5200-rtc";
150 device_type = "rtc"; 147 device_type = "rtc";
151 reg = <800 100>; 148 reg = <800 100>;
152 interrupts = <1 5 0 1 6 0>; 149 interrupts = <1 5 0 1 6 0>;
@@ -155,7 +152,7 @@
155 152
156 mscan@900 { 153 mscan@900 {
157 device_type = "mscan"; 154 device_type = "mscan";
158 compatible = "mpc5200b-mscan\0mpc5200-mscan"; 155 compatible = "mpc5200b-mscan","mpc5200-mscan";
159 cell-index = <0>; 156 cell-index = <0>;
160 interrupts = <2 11 0>; 157 interrupts = <2 11 0>;
161 interrupt-parent = <&mpc5200_pic>; 158 interrupt-parent = <&mpc5200_pic>;
@@ -164,7 +161,7 @@
164 161
165 mscan@980 { 162 mscan@980 {
166 device_type = "mscan"; 163 device_type = "mscan";
167 compatible = "mpc5200b-mscan\0mpc5200-mscan"; 164 compatible = "mpc5200b-mscan","mpc5200-mscan";
168 cell-index = <1>; 165 cell-index = <1>;
169 interrupts = <2 12 0>; 166 interrupts = <2 12 0>;
170 interrupt-parent = <&mpc5200_pic>; 167 interrupt-parent = <&mpc5200_pic>;
@@ -172,48 +169,22 @@
172 }; 169 };
173 170
174 gpio@b00 { 171 gpio@b00 {
175 compatible = "mpc5200b-gpio\0mpc5200-gpio"; 172 compatible = "mpc5200b-gpio","mpc5200-gpio";
176 reg = <b00 40>; 173 reg = <b00 40>;
177 interrupts = <1 7 0>; 174 interrupts = <1 7 0>;
178 interrupt-parent = <&mpc5200_pic>; 175 interrupt-parent = <&mpc5200_pic>;
179 }; 176 };
180 177
181 gpio-wkup@c00 { 178 gpio-wkup@c00 {
182 compatible = "mpc5200b-gpio-wkup\0mpc5200-gpio-wkup"; 179 compatible = "mpc5200b-gpio-wkup","mpc5200-gpio-wkup";
183 reg = <c00 40>; 180 reg = <c00 40>;
184 interrupts = <1 8 0 0 3 0>; 181 interrupts = <1 8 0 0 3 0>;
185 interrupt-parent = <&mpc5200_pic>; 182 interrupt-parent = <&mpc5200_pic>;
186 }; 183 };
187 184
188 pci@0d00 {
189 #interrupt-cells = <1>;
190 #size-cells = <2>;
191 #address-cells = <3>;
192 device_type = "pci";
193 compatible = "mpc5200b-pci\0mpc5200-pci";
194 reg = <d00 100>;
195 interrupt-map-mask = <f800 0 0 7>;
196 interrupt-map = <c000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
197 c000 0 0 2 &mpc5200_pic 1 1 3
198 c000 0 0 3 &mpc5200_pic 1 2 3
199 c000 0 0 4 &mpc5200_pic 1 3 3
200
201 c800 0 0 1 &mpc5200_pic 1 1 3 // 2nd slot
202 c800 0 0 2 &mpc5200_pic 1 2 3
203 c800 0 0 3 &mpc5200_pic 1 3 3
204 c800 0 0 4 &mpc5200_pic 0 0 3>;
205 clock-frequency = <0>; // From boot loader
206 interrupts = <2 8 0 2 9 0 2 a 0>;
207 interrupt-parent = <&mpc5200_pic>;
208 bus-range = <0 0>;
209 ranges = <42000000 0 80000000 80000000 0 20000000
210 02000000 0 a0000000 a0000000 0 10000000
211 01000000 0 00000000 b0000000 0 01000000>;
212 };
213
214 spi@f00 { 185 spi@f00 {
215 device_type = "spi"; 186 device_type = "spi";
216 compatible = "mpc5200b-spi\0mpc5200-spi"; 187 compatible = "mpc5200b-spi","mpc5200-spi";
217 reg = <f00 20>; 188 reg = <f00 20>;
218 interrupts = <2 d 0 2 e 0>; 189 interrupts = <2 d 0 2 e 0>;
219 interrupt-parent = <&mpc5200_pic>; 190 interrupt-parent = <&mpc5200_pic>;
@@ -221,7 +192,7 @@
221 192
222 usb@1000 { 193 usb@1000 {
223 device_type = "usb-ohci-be"; 194 device_type = "usb-ohci-be";
224 compatible = "mpc5200b-ohci\0mpc5200-ohci\0ohci-be"; 195 compatible = "mpc5200b-ohci","mpc5200-ohci","ohci-be";
225 reg = <1000 ff>; 196 reg = <1000 ff>;
226 interrupts = <2 6 0>; 197 interrupts = <2 6 0>;
227 interrupt-parent = <&mpc5200_pic>; 198 interrupt-parent = <&mpc5200_pic>;
@@ -229,7 +200,7 @@
229 200
230 bestcomm@1200 { 201 bestcomm@1200 {
231 device_type = "dma-controller"; 202 device_type = "dma-controller";
232 compatible = "mpc5200b-bestcomm\0mpc5200-bestcomm"; 203 compatible = "mpc5200b-bestcomm","mpc5200-bestcomm";
233 reg = <1200 80>; 204 reg = <1200 80>;
234 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0 205 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
235 3 4 0 3 5 0 3 6 0 3 7 0 206 3 4 0 3 5 0 3 6 0 3 7 0
@@ -239,13 +210,13 @@
239 }; 210 };
240 211
241 xlb@1f00 { 212 xlb@1f00 {
242 compatible = "mpc5200b-xlb\0mpc5200-xlb"; 213 compatible = "mpc5200b-xlb","mpc5200-xlb";
243 reg = <1f00 100>; 214 reg = <1f00 100>;
244 }; 215 };
245 216
246 serial@2000 { // PSC1 217 serial@2000 { // PSC1
247 device_type = "serial"; 218 device_type = "serial";
248 compatible = "mpc5200b-psc-uart\0mpc5200-psc-uart"; 219 compatible = "mpc5200b-psc-uart","mpc5200-psc-uart";
249 port-number = <0>; // Logical port assignment 220 port-number = <0>; // Logical port assignment
250 cell-index = <0>; 221 cell-index = <0>;
251 reg = <2000 100>; 222 reg = <2000 100>;
@@ -256,7 +227,7 @@
256 // PSC2 in ac97 mode example 227 // PSC2 in ac97 mode example
257 //ac97@2200 { // PSC2 228 //ac97@2200 { // PSC2
258 // device_type = "sound"; 229 // device_type = "sound";
259 // compatible = "mpc5200b-psc-ac97\0mpc5200-psc-ac97"; 230 // compatible = "mpc5200b-psc-ac97","mpc5200-psc-ac97";
260 // cell-index = <1>; 231 // cell-index = <1>;
261 // reg = <2200 100>; 232 // reg = <2200 100>;
262 // interrupts = <2 2 0>; 233 // interrupts = <2 2 0>;
@@ -276,7 +247,7 @@
276 // PSC4 in uart mode example 247 // PSC4 in uart mode example
277 //serial@2600 { // PSC4 248 //serial@2600 { // PSC4
278 // device_type = "serial"; 249 // device_type = "serial";
279 // compatible = "mpc5200b-psc-uart\0mpc5200-psc-uart"; 250 // compatible = "mpc5200b-psc-uart","mpc5200-psc-uart";
280 // cell-index = <3>; 251 // cell-index = <3>;
281 // reg = <2600 100>; 252 // reg = <2600 100>;
282 // interrupts = <2 b 0>; 253 // interrupts = <2 b 0>;
@@ -286,7 +257,7 @@
286 // PSC5 in uart mode example 257 // PSC5 in uart mode example
287 //serial@2800 { // PSC5 258 //serial@2800 { // PSC5
288 // device_type = "serial"; 259 // device_type = "serial";
289 // compatible = "mpc5200b-psc-uart\0mpc5200-psc-uart"; 260 // compatible = "mpc5200b-psc-uart","mpc5200-psc-uart";
290 // cell-index = <4>; 261 // cell-index = <4>;
291 // reg = <2800 100>; 262 // reg = <2800 100>;
292 // interrupts = <2 c 0>; 263 // interrupts = <2 c 0>;
@@ -296,7 +267,7 @@
296 // PSC6 in spi mode example 267 // PSC6 in spi mode example
297 //spi@2c00 { // PSC6 268 //spi@2c00 { // PSC6
298 // device_type = "spi"; 269 // device_type = "spi";
299 // compatible = "mpc5200b-psc-spi\0mpc5200-psc-spi"; 270 // compatible = "mpc5200b-psc-spi","mpc5200-psc-spi";
300 // cell-index = <5>; 271 // cell-index = <5>;
301 // reg = <2c00 100>; 272 // reg = <2c00 100>;
302 // interrupts = <2 4 0>; 273 // interrupts = <2 4 0>;
@@ -305,7 +276,7 @@
305 276
306 ethernet@3000 { 277 ethernet@3000 {
307 device_type = "network"; 278 device_type = "network";
308 compatible = "mpc5200b-fec\0mpc5200-fec"; 279 compatible = "mpc5200b-fec","mpc5200-fec";
309 reg = <3000 800>; 280 reg = <3000 800>;
310 mac-address = [ 02 03 04 05 06 07 ]; // Bad! 281 mac-address = [ 02 03 04 05 06 07 ]; // Bad!
311 interrupts = <2 5 0>; 282 interrupts = <2 5 0>;
@@ -314,7 +285,7 @@
314 285
315 ata@3a00 { 286 ata@3a00 {
316 device_type = "ata"; 287 device_type = "ata";
317 compatible = "mpc5200b-ata\0mpc5200-ata"; 288 compatible = "mpc5200b-ata","mpc5200-ata";
318 reg = <3a00 100>; 289 reg = <3a00 100>;
319 interrupts = <2 7 0>; 290 interrupts = <2 7 0>;
320 interrupt-parent = <&mpc5200_pic>; 291 interrupt-parent = <&mpc5200_pic>;
@@ -322,7 +293,7 @@
322 293
323 i2c@3d00 { 294 i2c@3d00 {
324 device_type = "i2c"; 295 device_type = "i2c";
325 compatible = "mpc5200b-i2c\0mpc5200-i2c\0fsl-i2c"; 296 compatible = "mpc5200b-i2c","mpc5200-i2c","fsl-i2c";
326 cell-index = <0>; 297 cell-index = <0>;
327 reg = <3d00 40>; 298 reg = <3d00 40>;
328 interrupts = <2 f 0>; 299 interrupts = <2 f 0>;
@@ -332,7 +303,7 @@
332 303
333 i2c@3d40 { 304 i2c@3d40 {
334 device_type = "i2c"; 305 device_type = "i2c";
335 compatible = "mpc5200b-i2c\0mpc5200-i2c\0fsl-i2c"; 306 compatible = "mpc5200b-i2c","mpc5200-i2c","fsl-i2c";
336 cell-index = <1>; 307 cell-index = <1>;
337 reg = <3d40 40>; 308 reg = <3d40 40>;
338 interrupts = <2 10 0>; 309 interrupts = <2 10 0>;
@@ -341,8 +312,34 @@
341 }; 312 };
342 sram@8000 { 313 sram@8000 {
343 device_type = "sram"; 314 device_type = "sram";
344 compatible = "mpc5200b-sram\0mpc5200-sram\0sram"; 315 compatible = "mpc5200b-sram","mpc5200-sram","sram";
345 reg = <8000 4000>; 316 reg = <8000 4000>;
346 }; 317 };
347 }; 318 };
319
320 pci@f0000d00 {
321 #interrupt-cells = <1>;
322 #size-cells = <2>;
323 #address-cells = <3>;
324 device_type = "pci";
325 compatible = "mpc5200b-pci","mpc5200-pci";
326 reg = <f0000d00 100>;
327 interrupt-map-mask = <f800 0 0 7>;
328 interrupt-map = <c000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
329 c000 0 0 2 &mpc5200_pic 1 1 3
330 c000 0 0 3 &mpc5200_pic 1 2 3
331 c000 0 0 4 &mpc5200_pic 1 3 3
332
333 c800 0 0 1 &mpc5200_pic 1 1 3 // 2nd slot
334 c800 0 0 2 &mpc5200_pic 1 2 3
335 c800 0 0 3 &mpc5200_pic 1 3 3
336 c800 0 0 4 &mpc5200_pic 0 0 3>;
337 clock-frequency = <0>; // From boot loader
338 interrupts = <2 8 0 2 9 0 2 a 0>;
339 interrupt-parent = <&mpc5200_pic>;
340 bus-range = <0 0>;
341 ranges = <42000000 0 80000000 80000000 0 20000000
342 02000000 0 a0000000 a0000000 0 10000000
343 01000000 0 00000000 b0000000 0 01000000>;
344 };
348}; 345};
diff --git a/arch/powerpc/boot/dts/mpc7448hpc2.dts b/arch/powerpc/boot/dts/mpc7448hpc2.dts
index b9158eb2797e..8fb542387436 100644
--- a/arch/powerpc/boot/dts/mpc7448hpc2.dts
+++ b/arch/powerpc/boot/dts/mpc7448hpc2.dts
@@ -31,7 +31,6 @@
31 timebase-frequency = <0>; // 33 MHz, from uboot 31 timebase-frequency = <0>; // 33 MHz, from uboot
32 clock-frequency = <0>; // From U-Boot 32 clock-frequency = <0>; // From U-Boot
33 bus-frequency = <0>; // From U-Boot 33 bus-frequency = <0>; // From U-Boot
34 32-bit;
35 }; 34 };
36 }; 35 };
37 36
@@ -44,7 +43,6 @@
44 tsi108@c0000000 { 43 tsi108@c0000000 {
45 #address-cells = <1>; 44 #address-cells = <1>;
46 #size-cells = <1>; 45 #size-cells = <1>;
47 #interrupt-cells = <2>;
48 device_type = "tsi-bridge"; 46 device_type = "tsi-bridge";
49 ranges = <00000000 c0000000 00010000>; 47 ranges = <00000000 c0000000 00010000>;
50 reg = <c0000000 00010000>; 48 reg = <c0000000 00010000>;
@@ -80,6 +78,7 @@
80 }; 78 };
81 79
82 ethernet@6200 { 80 ethernet@6200 {
81 linux,network-index = <0>;
83 #size-cells = <0>; 82 #size-cells = <0>;
84 device_type = "network"; 83 device_type = "network";
85 compatible = "tsi108-ethernet"; 84 compatible = "tsi108-ethernet";
@@ -92,6 +91,7 @@
92 }; 91 };
93 92
94 ethernet@6600 { 93 ethernet@6600 {
94 linux,network-index = <1>;
95 #address-cells = <1>; 95 #address-cells = <1>;
96 #size-cells = <0>; 96 #size-cells = <0>;
97 device_type = "network"; 97 device_type = "network";
@@ -128,7 +128,6 @@
128 #address-cells = <0>; 128 #address-cells = <0>;
129 #interrupt-cells = <2>; 129 #interrupt-cells = <2>;
130 reg = <7400 400>; 130 reg = <7400 400>;
131 built-in;
132 compatible = "chrp,open-pic"; 131 compatible = "chrp,open-pic";
133 device_type = "open-pic"; 132 device_type = "open-pic";
134 big-endian; 133 big-endian;
@@ -180,12 +179,14 @@
180 device_type = "pic-router"; 179 device_type = "pic-router";
181 #address-cells = <0>; 180 #address-cells = <0>;
182 #interrupt-cells = <2>; 181 #interrupt-cells = <2>;
183 built-in;
184 big-endian; 182 big-endian;
185 interrupts = <17 2>; 183 interrupts = <17 2>;
186 interrupt-parent = <&mpic>; 184 interrupt-parent = <&mpic>;
187 }; 185 };
188 }; 186 };
189 }; 187 };
188 chosen {
189 linux,stdout-path = "/tsi108@c0000000/serial@7808";
190 };
190 191
191}; 192};
diff --git a/arch/powerpc/boot/dts/mpc8272ads.dts b/arch/powerpc/boot/dts/mpc8272ads.dts
index 1934b800278e..7285ca1325fd 100644
--- a/arch/powerpc/boot/dts/mpc8272ads.dts
+++ b/arch/powerpc/boot/dts/mpc8272ads.dts
@@ -10,207 +10,240 @@
10 */ 10 */
11 11
12/ { 12/ {
13 model = "MPC8272ADS"; 13 model = "MPC8272ADS";
14 compatible = "MPC8260ADS"; 14 compatible = "fsl,mpc8272ads";
15 #address-cells = <1>; 15 #address-cells = <1>;
16 #size-cells = <1>; 16 #size-cells = <1>;
17 17
18 cpus { 18 cpus {
19 #address-cells = <1>; 19 #address-cells = <1>;
20 #size-cells = <0>; 20 #size-cells = <0>;
21 21
22 PowerPC,8272@0 { 22 PowerPC,8272@0 {
23 device_type = "cpu"; 23 device_type = "cpu";
24 reg = <0>; 24 reg = <0>;
25 d-cache-line-size = <20>; // 32 bytes 25 d-cache-line-size = <d#32>;
26 i-cache-line-size = <20>; // 32 bytes 26 i-cache-line-size = <d#32>;
27 d-cache-size = <4000>; // L1, 16K 27 d-cache-size = <d#16384>;
28 i-cache-size = <4000>; // L1, 16K 28 i-cache-size = <d#16384>;
29 timebase-frequency = <0>; 29 timebase-frequency = <0>;
30 bus-frequency = <0>; 30 bus-frequency = <0>;
31 clock-frequency = <0>; 31 clock-frequency = <0>;
32 32-bit; 32 };
33 }; 33 };
34 }; 34
35 35 memory {
36 pci_pic: interrupt-controller@f8200000 { 36 device_type = "memory";
37 #address-cells = <0>; 37 reg = <0 0>;
38 #interrupt-cells = <2>; 38 };
39 interrupt-controller; 39
40 reg = <f8200000 f8200004>; 40 localbus@f0010100 {
41 built-in; 41 compatible = "fsl,mpc8272-localbus",
42 device_type = "pci-pic"; 42 "fsl,pq2-localbus";
43 }; 43 #address-cells = <2>;
44 memory { 44 #size-cells = <1>;
45 device_type = "memory"; 45 reg = <f0010100 40>;
46 reg = <00000000 4000000 f4500000 00000020>; 46
47 }; 47 ranges = <0 0 fe000000 02000000
48 48 1 0 f4500000 00008000
49 chosen { 49 3 0 f8200000 00008000>;
50 name = "chosen"; 50
51 linux,platform = <0>; 51 flash@0,0 {
52 interrupt-controller = <&Cpm_pic>; 52 compatible = "jedec-flash";
53 }; 53 reg = <0 0 2000000>;
54 54 bank-width = <4>;
55 soc8272@f0000000 { 55 device-width = <1>;
56 #address-cells = <1>; 56 };
57 #size-cells = <1>; 57
58 #interrupt-cells = <2>; 58 board-control@1,0 {
59 device_type = "soc"; 59 reg = <1 0 20>;
60 ranges = <00000000 f0000000 00053000>; 60 compatible = "fsl,mpc8272ads-bcsr";
61 reg = <f0000000 10000>; 61 };
62 62
63 mdio@0 { 63 PCI_PIC: interrupt-controller@3,0 {
64 device_type = "mdio"; 64 compatible = "fsl,mpc8272ads-pci-pic",
65 compatible = "fs_enet"; 65 "fsl,pq2ads-pci-pic";
66 reg = <0 0>; 66 #interrupt-cells = <1>;
67 #address-cells = <1>; 67 interrupt-controller;
68 #size-cells = <0>; 68 reg = <3 0 8>;
69 phy0:ethernet-phy@0 { 69 interrupt-parent = <&PIC>;
70 interrupt-parent = <&Cpm_pic>; 70 interrupts = <14 8>;
71 interrupts = <17 4>; 71 };
72 reg = <0>; 72 };
73 bitbang = [ 12 12 13 02 02 01 ]; 73
74 device_type = "ethernet-phy"; 74
75 }; 75 pci@f0010800 {
76 phy1:ethernet-phy@1 { 76 device_type = "pci";
77 interrupt-parent = <&Cpm_pic>; 77 reg = <f0010800 10c f00101ac 8 f00101c4 8>;
78 interrupts = <17 4>; 78 compatible = "fsl,mpc8272-pci", "fsl,pq2-pci";
79 bitbang = [ 12 12 13 02 02 01 ]; 79 #interrupt-cells = <1>;
80 reg = <3>; 80 #size-cells = <2>;
81 device_type = "ethernet-phy"; 81 #address-cells = <3>;
82 }; 82 clock-frequency = <d#66666666>;
83 }; 83 interrupt-map-mask = <f800 0 0 7>;
84 84 interrupt-map = <
85 ethernet@24000 { 85 /* IDSEL 0x16 */
86 #address-cells = <1>; 86 b000 0 0 1 &PCI_PIC 0
87 #size-cells = <0>; 87 b000 0 0 2 &PCI_PIC 1
88 device_type = "network"; 88 b000 0 0 3 &PCI_PIC 2
89 device-id = <1>; 89 b000 0 0 4 &PCI_PIC 3
90 compatible = "fs_enet"; 90
91 model = "FCC"; 91 /* IDSEL 0x17 */
92 reg = <11300 20 8400 100 11380 30>; 92 b800 0 0 1 &PCI_PIC 4
93 mac-address = [ 00 11 2F 99 43 54 ]; 93 b800 0 0 2 &PCI_PIC 5
94 interrupts = <20 2>; 94 b800 0 0 3 &PCI_PIC 6
95 interrupt-parent = <&Cpm_pic>; 95 b800 0 0 4 &PCI_PIC 7
96 phy-handle = <&Phy0>; 96
97 rx-clock = <13>; 97 /* IDSEL 0x18 */
98 tx-clock = <12>; 98 c000 0 0 1 &PCI_PIC 8
99 }; 99 c000 0 0 2 &PCI_PIC 9
100 100 c000 0 0 3 &PCI_PIC a
101 ethernet@25000 { 101 c000 0 0 4 &PCI_PIC b>;
102 device_type = "network"; 102
103 device-id = <2>; 103 interrupt-parent = <&PIC>;
104 compatible = "fs_enet"; 104 interrupts = <12 8>;
105 model = "FCC"; 105 ranges = <42000000 0 80000000 80000000 0 20000000
106 reg = <11320 20 8500 100 113b0 30>; 106 02000000 0 a0000000 a0000000 0 20000000
107 mac-address = [ 00 11 2F 99 44 54 ]; 107 01000000 0 00000000 f6000000 0 02000000>;
108 interrupts = <21 2>; 108 };
109 interrupt-parent = <&Cpm_pic>; 109
110 phy-handle = <&Phy1>; 110 soc@f0000000 {
111 rx-clock = <17>; 111 #address-cells = <1>;
112 tx-clock = <18>; 112 #size-cells = <1>;
113 }; 113 device_type = "soc";
114 114 compatible = "fsl,mpc8272", "fsl,pq2-soc";
115 cpm@f0000000 { 115 ranges = <00000000 f0000000 00053000>;
116 #address-cells = <1>; 116
117 #size-cells = <1>; 117 // Temporary -- will go away once kernel uses ranges for get_immrbase().
118 #interrupt-cells = <2>; 118 reg = <f0000000 00053000>;
119 device_type = "cpm"; 119
120 model = "CPM2"; 120 cpm@119c0 {
121 ranges = <00000000 00000000 20000>; 121 #address-cells = <1>;
122 reg = <0 20000>; 122 #size-cells = <1>;
123 command-proc = <119c0>; 123 compatible = "fsl,mpc8272-cpm", "fsl,cpm2";
124 brg-frequency = <17D7840>; 124 reg = <119c0 30>;
125 cpm_clk = <BEBC200>; 125 ranges;
126 126
127 scc@11a00 { 127 muram@0 {
128 device_type = "serial"; 128 #address-cells = <1>;
129 compatible = "cpm_uart"; 129 #size-cells = <1>;
130 model = "SCC"; 130 ranges = <0 0 10000>;
131 device-id = <1>; 131
132 reg = <11a00 20 8000 100>; 132 data@0 {
133 current-speed = <1c200>; 133 compatible = "fsl,cpm-muram-data";
134 interrupts = <28 2>; 134 reg = <0 2000 9800 800>;
135 interrupt-parent = <&Cpm_pic>; 135 };
136 clock-setup = <0 00ffffff>; 136 };
137 rx-clock = <1>; 137
138 tx-clock = <1>; 138 brg@119f0 {
139 }; 139 compatible = "fsl,mpc8272-brg",
140 140 "fsl,cpm2-brg",
141 scc@11a60 { 141 "fsl,cpm-brg";
142 device_type = "serial"; 142 reg = <119f0 10 115f0 10>;
143 compatible = "cpm_uart"; 143 };
144 model = "SCC"; 144
145 device-id = <4>; 145 serial@11a00 {
146 reg = <11a60 20 8300 100>; 146 device_type = "serial";
147 current-speed = <1c200>; 147 compatible = "fsl,mpc8272-scc-uart",
148 interrupts = <2b 2>; 148 "fsl,cpm2-scc-uart";
149 interrupt-parent = <&Cpm_pic>; 149 reg = <11a00 20 8000 100>;
150 clock-setup = <1b ffffff00>; 150 interrupts = <28 8>;
151 rx-clock = <4>; 151 interrupt-parent = <&PIC>;
152 tx-clock = <4>; 152 fsl,cpm-brg = <1>;
153 }; 153 fsl,cpm-command = <00800000>;
154 154 };
155 }; 155
156 cpm_pic:interrupt-controller@10c00 { 156 serial@11a60 {
157 #address-cells = <0>; 157 device_type = "serial";
158 #interrupt-cells = <2>; 158 compatible = "fsl,mpc8272-scc-uart",
159 interrupt-controller; 159 "fsl,cpm2-scc-uart";
160 reg = <10c00 80>; 160 reg = <11a60 20 8300 100>;
161 built-in; 161 interrupts = <2b 8>;
162 device_type = "cpm-pic"; 162 interrupt-parent = <&PIC>;
163 compatible = "CPM2"; 163 fsl,cpm-brg = <4>;
164 }; 164 fsl,cpm-command = <0ce00000>;
165 pci@0500 { 165 };
166 #interrupt-cells = <1>; 166
167 #size-cells = <2>; 167 mdio@10d40 {
168 #address-cells = <3>; 168 device_type = "mdio";
169 compatible = "8272"; 169 compatible = "fsl,mpc8272ads-mdio-bitbang",
170 device_type = "pci"; 170 "fsl,mpc8272-mdio-bitbang",
171 reg = <10430 4dc>; 171 "fsl,cpm2-mdio-bitbang";
172 clock-frequency = <3f940aa>; 172 reg = <10d40 14>;
173 interrupt-map-mask = <f800 0 0 7>; 173 #address-cells = <1>;
174 interrupt-map = < 174 #size-cells = <0>;
175 175 fsl,mdio-pin = <12>;
176 /* IDSEL 0x16 */ 176 fsl,mdc-pin = <13>;
177 b000 0 0 1 f8200000 40 8 177
178 b000 0 0 2 f8200000 41 8 178 PHY0: ethernet-phy@0 {
179 b000 0 0 3 f8200000 42 8 179 interrupt-parent = <&PIC>;
180 b000 0 0 4 f8200000 43 8 180 interrupts = <17 8>;
181 181 reg = <0>;
182 /* IDSEL 0x17 */ 182 device_type = "ethernet-phy";
183 b800 0 0 1 f8200000 43 8 183 };
184 b800 0 0 2 f8200000 40 8 184
185 b800 0 0 3 f8200000 41 8 185 PHY1: ethernet-phy@1 {
186 b800 0 0 4 f8200000 42 8 186 interrupt-parent = <&PIC>;
187 187 interrupts = <17 8>;
188 /* IDSEL 0x18 */ 188 reg = <3>;
189 c000 0 0 1 f8200000 42 8 189 device_type = "ethernet-phy";
190 c000 0 0 2 f8200000 43 8 190 };
191 c000 0 0 3 f8200000 40 8 191 };
192 c000 0 0 4 f8200000 41 8>; 192
193 interrupt-parent = <&Cpm_pic>; 193 ethernet@11300 {
194 interrupts = <14 8>; 194 device_type = "network";
195 bus-range = <0 0>; 195 compatible = "fsl,mpc8272-fcc-enet",
196 ranges = <02000000 0 80000000 80000000 0 40000000 196 "fsl,cpm2-fcc-enet";
197 01000000 0 00000000 f6000000 0 02000000>; 197 reg = <11300 20 8400 100 11390 1>;
198 }; 198 local-mac-address = [ 00 00 00 00 00 00 ];
199 interrupts = <20 8>;
200 interrupt-parent = <&PIC>;
201 phy-handle = <&PHY0>;
202 linux,network-index = <0>;
203 fsl,cpm-command = <12000300>;
204 };
205
206 ethernet@11320 {
207 device_type = "network";
208 compatible = "fsl,mpc8272-fcc-enet",
209 "fsl,cpm2-fcc-enet";
210 reg = <11320 20 8500 100 113b0 1>;
211 local-mac-address = [ 00 00 00 00 00 00 ];
212 interrupts = <21 8>;
213 interrupt-parent = <&PIC>;
214 phy-handle = <&PHY1>;
215 linux,network-index = <1>;
216 fsl,cpm-command = <16200300>;
217 };
218 };
219
220 PIC: interrupt-controller@10c00 {
221 #interrupt-cells = <2>;
222 interrupt-controller;
223 reg = <10c00 80>;
224 compatible = "fsl,mpc8272-pic", "fsl,cpm2-pic";
225 };
199 226
200/* May need to remove if on a part without crypto engine */ 227/* May need to remove if on a part without crypto engine */
201 crypto@30000 { 228 crypto@30000 {
202 device_type = "crypto"; 229 device_type = "crypto";
203 model = "SEC2"; 230 model = "SEC2";
204 compatible = "talitos"; 231 compatible = "fsl,mpc8272-talitos-sec2",
205 reg = <30000 10000>; 232 "fsl,talitos-sec2",
206 interrupts = <b 2>; 233 "fsl,talitos",
207 interrupt-parent = <&Cpm_pic>; 234 "talitos";
208 num-channels = <4>; 235 reg = <30000 10000>;
209 channel-fifo-len = <18>; 236 interrupts = <b 8>;
210 exec-units-mask = <0000007e>; 237 interrupt-parent = <&PIC>;
238 num-channels = <4>;
239 channel-fifo-len = <18>;
240 exec-units-mask = <0000007e>;
211/* desc mask is for rev1.x, we need runtime fixup for >=2.x */ 241/* desc mask is for rev1.x, we need runtime fixup for >=2.x */
212 descriptor-types-mask = <01010ebf>; 242 descriptor-types-mask = <01010ebf>;
213 }; 243 };
244 };
214 245
215 }; 246 chosen {
247 linux,stdout-path = "/soc/cpm/serial@11a00";
248 };
216}; 249};
diff --git a/arch/powerpc/boot/dts/mpc8313erdb.dts b/arch/powerpc/boot/dts/mpc8313erdb.dts
index c5adbe40364e..9e7eba973262 100644
--- a/arch/powerpc/boot/dts/mpc8313erdb.dts
+++ b/arch/powerpc/boot/dts/mpc8313erdb.dts
@@ -29,7 +29,6 @@
29 timebase-frequency = <0>; // from bootloader 29 timebase-frequency = <0>; // from bootloader
30 bus-frequency = <0>; // from bootloader 30 bus-frequency = <0>; // from bootloader
31 clock-frequency = <0>; // from bootloader 31 clock-frequency = <0>; // from bootloader
32 32-bit;
33 }; 32 };
34 }; 33 };
35 34
@@ -41,7 +40,6 @@
41 soc8313@e0000000 { 40 soc8313@e0000000 {
42 #address-cells = <1>; 41 #address-cells = <1>;
43 #size-cells = <1>; 42 #size-cells = <1>;
44 #interrupt-cells = <2>;
45 device_type = "soc"; 43 device_type = "soc";
46 ranges = <0 e0000000 00100000>; 44 ranges = <0 e0000000 00100000>;
47 reg = <e0000000 00000200>; 45 reg = <e0000000 00000200>;
@@ -73,11 +71,11 @@
73 71
74 spi@7000 { 72 spi@7000 {
75 device_type = "spi"; 73 device_type = "spi";
76 compatible = "mpc83xx_spi"; 74 compatible = "fsl_spi";
77 reg = <7000 1000>; 75 reg = <7000 1000>;
78 interrupts = <10 8>; 76 interrupts = <10 8>;
79 interrupt-parent = < &ipic >; 77 interrupt-parent = < &ipic >;
80 mode = <0>; 78 mode = "cpu";
81 }; 79 };
82 80
83 /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */ 81 /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
@@ -152,36 +150,6 @@
152 interrupt-parent = < &ipic >; 150 interrupt-parent = < &ipic >;
153 }; 151 };
154 152
155 pci@8500 {
156 interrupt-map-mask = <f800 0 0 7>;
157 interrupt-map = <
158
159 /* IDSEL 0x0E -mini PCI */
160 7000 0 0 1 &ipic 12 8
161 7000 0 0 2 &ipic 12 8
162 7000 0 0 3 &ipic 12 8
163 7000 0 0 4 &ipic 12 8
164
165 /* IDSEL 0x0F - PCI slot */
166 7800 0 0 1 &ipic 11 8
167 7800 0 0 2 &ipic 12 8
168 7800 0 0 3 &ipic 11 8
169 7800 0 0 4 &ipic 12 8>;
170 interrupt-parent = < &ipic >;
171 interrupts = <42 8>;
172 bus-range = <0 0>;
173 ranges = <02000000 0 90000000 90000000 0 10000000
174 42000000 0 80000000 80000000 0 10000000
175 01000000 0 00000000 e2000000 0 00100000>;
176 clock-frequency = <3f940aa>;
177 #interrupt-cells = <1>;
178 #size-cells = <2>;
179 #address-cells = <3>;
180 reg = <8500 100>;
181 compatible = "fsl,mpc8349-pci";
182 device_type = "pci";
183 };
184
185 crypto@30000 { 153 crypto@30000 {
186 device_type = "crypto"; 154 device_type = "crypto";
187 model = "SEC2"; 155 model = "SEC2";
@@ -207,8 +175,37 @@
207 #address-cells = <0>; 175 #address-cells = <0>;
208 #interrupt-cells = <2>; 176 #interrupt-cells = <2>;
209 reg = <700 100>; 177 reg = <700 100>;
210 built-in;
211 device_type = "ipic"; 178 device_type = "ipic";
212 }; 179 };
213 }; 180 };
181
182 pci@e0008500 {
183 interrupt-map-mask = <f800 0 0 7>;
184 interrupt-map = <
185
186 /* IDSEL 0x0E -mini PCI */
187 7000 0 0 1 &ipic 12 8
188 7000 0 0 2 &ipic 12 8
189 7000 0 0 3 &ipic 12 8
190 7000 0 0 4 &ipic 12 8
191
192 /* IDSEL 0x0F - PCI slot */
193 7800 0 0 1 &ipic 11 8
194 7800 0 0 2 &ipic 12 8
195 7800 0 0 3 &ipic 11 8
196 7800 0 0 4 &ipic 12 8>;
197 interrupt-parent = < &ipic >;
198 interrupts = <42 8>;
199 bus-range = <0 0>;
200 ranges = <02000000 0 90000000 90000000 0 10000000
201 42000000 0 80000000 80000000 0 10000000
202 01000000 0 00000000 e2000000 0 00100000>;
203 clock-frequency = <3f940aa>;
204 #interrupt-cells = <1>;
205 #size-cells = <2>;
206 #address-cells = <3>;
207 reg = <e0008500 100>;
208 compatible = "fsl,mpc8349-pci";
209 device_type = "pci";
210 };
214}; 211};
diff --git a/arch/powerpc/boot/dts/mpc832x_mds.dts b/arch/powerpc/boot/dts/mpc832x_mds.dts
index f158ed781ba8..fcd333c391ec 100644
--- a/arch/powerpc/boot/dts/mpc832x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc832x_mds.dts
@@ -29,7 +29,6 @@
29 timebase-frequency = <0>; 29 timebase-frequency = <0>;
30 bus-frequency = <0>; 30 bus-frequency = <0>;
31 clock-frequency = <0>; 31 clock-frequency = <0>;
32 32-bit;
33 }; 32 };
34 }; 33 };
35 34
@@ -46,7 +45,6 @@
46 soc8323@e0000000 { 45 soc8323@e0000000 {
47 #address-cells = <1>; 46 #address-cells = <1>;
48 #size-cells = <1>; 47 #size-cells = <1>;
49 #interrupt-cells = <2>;
50 device_type = "soc"; 48 device_type = "soc";
51 ranges = <0 e0000000 00100000>; 49 ranges = <0 e0000000 00100000>;
52 reg = <e0000000 00000200>; 50 reg = <e0000000 00000200>;
@@ -99,71 +97,11 @@
99 descriptor-types-mask = <0122003f>; 97 descriptor-types-mask = <0122003f>;
100 }; 98 };
101 99
102 pci@8500 {
103 interrupt-map-mask = <f800 0 0 7>;
104 interrupt-map = <
105 /* IDSEL 0x11 AD17 */
106 8800 0 0 1 &ipic 14 8
107 8800 0 0 2 &ipic 15 8
108 8800 0 0 3 &ipic 16 8
109 8800 0 0 4 &ipic 17 8
110
111 /* IDSEL 0x12 AD18 */
112 9000 0 0 1 &ipic 16 8
113 9000 0 0 2 &ipic 17 8
114 9000 0 0 3 &ipic 14 8
115 9000 0 0 4 &ipic 15 8
116
117 /* IDSEL 0x13 AD19 */
118 9800 0 0 1 &ipic 17 8
119 9800 0 0 2 &ipic 14 8
120 9800 0 0 3 &ipic 15 8
121 9800 0 0 4 &ipic 16 8
122
123 /* IDSEL 0x15 AD21*/
124 a800 0 0 1 &ipic 14 8
125 a800 0 0 2 &ipic 15 8
126 a800 0 0 3 &ipic 16 8
127 a800 0 0 4 &ipic 17 8
128
129 /* IDSEL 0x16 AD22*/
130 b000 0 0 1 &ipic 17 8
131 b000 0 0 2 &ipic 14 8
132 b000 0 0 3 &ipic 15 8
133 b000 0 0 4 &ipic 16 8
134
135 /* IDSEL 0x17 AD23*/
136 b800 0 0 1 &ipic 16 8
137 b800 0 0 2 &ipic 17 8
138 b800 0 0 3 &ipic 14 8
139 b800 0 0 4 &ipic 15 8
140
141 /* IDSEL 0x18 AD24*/
142 c000 0 0 1 &ipic 15 8
143 c000 0 0 2 &ipic 16 8
144 c000 0 0 3 &ipic 17 8
145 c000 0 0 4 &ipic 14 8>;
146 interrupt-parent = < &ipic >;
147 interrupts = <42 8>;
148 bus-range = <0 0>;
149 ranges = <02000000 0 90000000 90000000 0 10000000
150 42000000 0 80000000 80000000 0 10000000
151 01000000 0 00000000 d0000000 0 00100000>;
152 clock-frequency = <0>;
153 #interrupt-cells = <1>;
154 #size-cells = <2>;
155 #address-cells = <3>;
156 reg = <8500 100>;
157 compatible = "fsl,mpc8349-pci";
158 device_type = "pci";
159 };
160
161 ipic: pic@700 { 100 ipic: pic@700 {
162 interrupt-controller; 101 interrupt-controller;
163 #address-cells = <0>; 102 #address-cells = <0>;
164 #interrupt-cells = <2>; 103 #interrupt-cells = <2>;
165 reg = <700 100>; 104 reg = <700 100>;
166 built-in;
167 device_type = "ipic"; 105 device_type = "ipic";
168 }; 106 };
169 107
@@ -333,10 +271,68 @@
333 #address-cells = <0>; 271 #address-cells = <0>;
334 #interrupt-cells = <1>; 272 #interrupt-cells = <1>;
335 reg = <80 80>; 273 reg = <80 80>;
336 built-in;
337 big-endian; 274 big-endian;
338 interrupts = <20 8 21 8>; //high:32 low:33 275 interrupts = <20 8 21 8>; //high:32 low:33
339 interrupt-parent = < &ipic >; 276 interrupt-parent = < &ipic >;
340 }; 277 };
341 }; 278 };
279
280 pci@e0008500 {
281 interrupt-map-mask = <f800 0 0 7>;
282 interrupt-map = <
283 /* IDSEL 0x11 AD17 */
284 8800 0 0 1 &ipic 14 8
285 8800 0 0 2 &ipic 15 8
286 8800 0 0 3 &ipic 16 8
287 8800 0 0 4 &ipic 17 8
288
289 /* IDSEL 0x12 AD18 */
290 9000 0 0 1 &ipic 16 8
291 9000 0 0 2 &ipic 17 8
292 9000 0 0 3 &ipic 14 8
293 9000 0 0 4 &ipic 15 8
294
295 /* IDSEL 0x13 AD19 */
296 9800 0 0 1 &ipic 17 8
297 9800 0 0 2 &ipic 14 8
298 9800 0 0 3 &ipic 15 8
299 9800 0 0 4 &ipic 16 8
300
301 /* IDSEL 0x15 AD21*/
302 a800 0 0 1 &ipic 14 8
303 a800 0 0 2 &ipic 15 8
304 a800 0 0 3 &ipic 16 8
305 a800 0 0 4 &ipic 17 8
306
307 /* IDSEL 0x16 AD22*/
308 b000 0 0 1 &ipic 17 8
309 b000 0 0 2 &ipic 14 8
310 b000 0 0 3 &ipic 15 8
311 b000 0 0 4 &ipic 16 8
312
313 /* IDSEL 0x17 AD23*/
314 b800 0 0 1 &ipic 16 8
315 b800 0 0 2 &ipic 17 8
316 b800 0 0 3 &ipic 14 8
317 b800 0 0 4 &ipic 15 8
318
319 /* IDSEL 0x18 AD24*/
320 c000 0 0 1 &ipic 15 8
321 c000 0 0 2 &ipic 16 8
322 c000 0 0 3 &ipic 17 8
323 c000 0 0 4 &ipic 14 8>;
324 interrupt-parent = < &ipic >;
325 interrupts = <42 8>;
326 bus-range = <0 0>;
327 ranges = <02000000 0 90000000 90000000 0 10000000
328 42000000 0 80000000 80000000 0 10000000
329 01000000 0 00000000 d0000000 0 00100000>;
330 clock-frequency = <0>;
331 #interrupt-cells = <1>;
332 #size-cells = <2>;
333 #address-cells = <3>;
334 reg = <e0008500 100>;
335 compatible = "fsl,mpc8349-pci";
336 device_type = "pci";
337 };
342}; 338};
diff --git a/arch/powerpc/boot/dts/mpc832x_rdb.dts b/arch/powerpc/boot/dts/mpc832x_rdb.dts
index 7c4beff3e200..388c8a7012e1 100644
--- a/arch/powerpc/boot/dts/mpc832x_rdb.dts
+++ b/arch/powerpc/boot/dts/mpc832x_rdb.dts
@@ -29,7 +29,6 @@
29 timebase-frequency = <0>; 29 timebase-frequency = <0>;
30 bus-frequency = <0>; 30 bus-frequency = <0>;
31 clock-frequency = <0>; 31 clock-frequency = <0>;
32 32-bit;
33 }; 32 };
34 }; 33 };
35 34
@@ -41,7 +40,6 @@
41 soc8323@e0000000 { 40 soc8323@e0000000 {
42 #address-cells = <1>; 41 #address-cells = <1>;
43 #size-cells = <1>; 42 #size-cells = <1>;
44 #interrupt-cells = <2>;
45 device_type = "soc"; 43 device_type = "soc";
46 ranges = <0 e0000000 00100000>; 44 ranges = <0 e0000000 00100000>;
47 reg = <e0000000 00000200>; 45 reg = <e0000000 00000200>;
@@ -94,45 +92,11 @@
94 descriptor-types-mask = <0122003f>; 92 descriptor-types-mask = <0122003f>;
95 }; 93 };
96 94
97 pci@8500 {
98 interrupt-map-mask = <f800 0 0 7>;
99 interrupt-map = <
100 /* IDSEL 0x10 AD16 (USB) */
101 8000 0 0 1 &pic 11 8
102
103 /* IDSEL 0x11 AD17 (Mini1)*/
104 8800 0 0 1 &pic 12 8
105 8800 0 0 2 &pic 13 8
106 8800 0 0 3 &pic 14 8
107 8800 0 0 4 &pic 30 8
108
109 /* IDSEL 0x12 AD18 (PCI/Mini2) */
110 9000 0 0 1 &pic 13 8
111 9000 0 0 2 &pic 14 8
112 9000 0 0 3 &pic 30 8
113 9000 0 0 4 &pic 11 8>;
114
115 interrupt-parent = <&pic>;
116 interrupts = <42 8>;
117 bus-range = <0 0>;
118 ranges = <42000000 0 80000000 80000000 0 10000000
119 02000000 0 90000000 90000000 0 10000000
120 01000000 0 d0000000 d0000000 0 04000000>;
121 clock-frequency = <0>;
122 #interrupt-cells = <1>;
123 #size-cells = <2>;
124 #address-cells = <3>;
125 reg = <8500 100>;
126 compatible = "fsl,mpc8349-pci";
127 device_type = "pci";
128 };
129
130 pic:pic@700 { 95 pic:pic@700 {
131 interrupt-controller; 96 interrupt-controller;
132 #address-cells = <0>; 97 #address-cells = <0>;
133 #interrupt-cells = <2>; 98 #interrupt-cells = <2>;
134 reg = <700 100>; 99 reg = <700 100>;
135 built-in;
136 device_type = "ipic"; 100 device_type = "ipic";
137 }; 101 };
138 102
@@ -211,7 +175,7 @@
211 reg = <4c0 40>; 175 reg = <4c0 40>;
212 interrupts = <2>; 176 interrupts = <2>;
213 interrupt-parent = <&qeic>; 177 interrupt-parent = <&qeic>;
214 mode = "cpu"; 178 mode = "cpu-qe";
215 }; 179 };
216 180
217 spi@500 { 181 spi@500 {
@@ -292,10 +256,42 @@
292 #address-cells = <0>; 256 #address-cells = <0>;
293 #interrupt-cells = <1>; 257 #interrupt-cells = <1>;
294 reg = <80 80>; 258 reg = <80 80>;
295 built-in;
296 big-endian; 259 big-endian;
297 interrupts = <20 8 21 8>; //high:32 low:33 260 interrupts = <20 8 21 8>; //high:32 low:33
298 interrupt-parent = <&pic>; 261 interrupt-parent = <&pic>;
299 }; 262 };
300 }; 263 };
264
265 pci@e0008500 {
266 interrupt-map-mask = <f800 0 0 7>;
267 interrupt-map = <
268 /* IDSEL 0x10 AD16 (USB) */
269 8000 0 0 1 &pic 11 8
270
271 /* IDSEL 0x11 AD17 (Mini1)*/
272 8800 0 0 1 &pic 12 8
273 8800 0 0 2 &pic 13 8
274 8800 0 0 3 &pic 14 8
275 8800 0 0 4 &pic 30 8
276
277 /* IDSEL 0x12 AD18 (PCI/Mini2) */
278 9000 0 0 1 &pic 13 8
279 9000 0 0 2 &pic 14 8
280 9000 0 0 3 &pic 30 8
281 9000 0 0 4 &pic 11 8>;
282
283 interrupt-parent = <&pic>;
284 interrupts = <42 8>;
285 bus-range = <0 0>;
286 ranges = <42000000 0 80000000 80000000 0 10000000
287 02000000 0 90000000 90000000 0 10000000
288 01000000 0 d0000000 d0000000 0 04000000>;
289 clock-frequency = <0>;
290 #interrupt-cells = <1>;
291 #size-cells = <2>;
292 #address-cells = <3>;
293 reg = <e0008500 100>;
294 compatible = "fsl,mpc8349-pci";
295 device_type = "pci";
296 };
301}; 297};
diff --git a/arch/powerpc/boot/dts/mpc8349emitx.dts b/arch/powerpc/boot/dts/mpc8349emitx.dts
index 44c065a6b5e7..5072f6d0a46d 100644
--- a/arch/powerpc/boot/dts/mpc8349emitx.dts
+++ b/arch/powerpc/boot/dts/mpc8349emitx.dts
@@ -28,7 +28,6 @@
28 timebase-frequency = <0>; // from bootloader 28 timebase-frequency = <0>; // from bootloader
29 bus-frequency = <0>; // from bootloader 29 bus-frequency = <0>; // from bootloader
30 clock-frequency = <0>; // from bootloader 30 clock-frequency = <0>; // from bootloader
31 32-bit;
32 }; 31 };
33 }; 32 };
34 33
@@ -40,7 +39,6 @@
40 soc8349@e0000000 { 39 soc8349@e0000000 {
41 #address-cells = <1>; 40 #address-cells = <1>;
42 #size-cells = <1>; 41 #size-cells = <1>;
43 #interrupt-cells = <2>;
44 device_type = "soc"; 42 device_type = "soc";
45 ranges = <0 e0000000 00100000>; 43 ranges = <0 e0000000 00100000>;
46 reg = <e0000000 00000200>; 44 reg = <e0000000 00000200>;
@@ -72,11 +70,11 @@
72 70
73 spi@7000 { 71 spi@7000 {
74 device_type = "spi"; 72 device_type = "spi";
75 compatible = "mpc83xx_spi"; 73 compatible = "fsl_spi";
76 reg = <7000 1000>; 74 reg = <7000 1000>;
77 interrupts = <10 8>; 75 interrupts = <10 8>;
78 interrupt-parent = < &ipic >; 76 interrupt-parent = < &ipic >;
79 mode = <0>; 77 mode = "cpu";
80 }; 78 };
81 79
82 usb@22000 { 80 usb@22000 {
@@ -142,6 +140,7 @@
142 interrupts = <20 8 21 8 22 8>; 140 interrupts = <20 8 21 8 22 8>;
143 interrupt-parent = < &ipic >; 141 interrupt-parent = < &ipic >;
144 phy-handle = < &phy1c >; 142 phy-handle = < &phy1c >;
143 linux,network-index = <0>;
145 }; 144 };
146 145
147 ethernet@25000 { 146 ethernet@25000 {
@@ -161,6 +160,7 @@
161 interrupts = <23 8 24 8 25 8>; 160 interrupts = <23 8 24 8 25 8>;
162 interrupt-parent = < &ipic >; 161 interrupt-parent = < &ipic >;
163 phy-handle = < &phy1f >; 162 phy-handle = < &phy1f >;
163 linux,network-index = <1>;
164 }; 164 };
165 165
166 serial@4500 { 166 serial@4500 {
@@ -181,52 +181,6 @@
181 interrupt-parent = < &ipic >; 181 interrupt-parent = < &ipic >;
182 }; 182 };
183 183
184 pci@8500 {
185 interrupt-map-mask = <f800 0 0 7>;
186 interrupt-map = <
187 /* IDSEL 0x10 - SATA */
188 8000 0 0 1 &ipic 16 8 /* SATA_INTA */
189 >;
190 interrupt-parent = < &ipic >;
191 interrupts = <42 8>;
192 bus-range = <0 0>;
193 ranges = <42000000 0 80000000 80000000 0 10000000
194 02000000 0 90000000 90000000 0 10000000
195 01000000 0 00000000 e2000000 0 01000000>;
196 clock-frequency = <3f940aa>;
197 #interrupt-cells = <1>;
198 #size-cells = <2>;
199 #address-cells = <3>;
200 reg = <8500 100>;
201 compatible = "fsl,mpc8349-pci";
202 device_type = "pci";
203 };
204
205 pci@8600 {
206 interrupt-map-mask = <f800 0 0 7>;
207 interrupt-map = <
208 /* IDSEL 0x0E - MiniPCI Slot */
209 7000 0 0 1 &ipic 15 8 /* PCI_INTA */
210
211 /* IDSEL 0x0F - PCI Slot */
212 7800 0 0 1 &ipic 14 8 /* PCI_INTA */
213 7800 0 0 2 &ipic 15 8 /* PCI_INTB */
214 >;
215 interrupt-parent = < &ipic >;
216 interrupts = <43 8>;
217 bus-range = <1 1>;
218 ranges = <42000000 0 a0000000 a0000000 0 10000000
219 02000000 0 b0000000 b0000000 0 10000000
220 01000000 0 00000000 e3000000 0 01000000>;
221 clock-frequency = <3f940aa>;
222 #interrupt-cells = <1>;
223 #size-cells = <2>;
224 #address-cells = <3>;
225 reg = <8600 100>;
226 compatible = "fsl,mpc8349-pci";
227 device_type = "pci";
228 };
229
230 crypto@30000 { 184 crypto@30000 {
231 device_type = "crypto"; 185 device_type = "crypto";
232 model = "SEC2"; 186 model = "SEC2";
@@ -245,8 +199,56 @@
245 #address-cells = <0>; 199 #address-cells = <0>;
246 #interrupt-cells = <2>; 200 #interrupt-cells = <2>;
247 reg = <700 100>; 201 reg = <700 100>;
248 built-in;
249 device_type = "ipic"; 202 device_type = "ipic";
250 }; 203 };
251 }; 204 };
205
206 pci@e0008500 {
207 interrupt-map-mask = <f800 0 0 7>;
208 interrupt-map = <
209 /* IDSEL 0x10 - SATA */
210 8000 0 0 1 &ipic 16 8 /* SATA_INTA */
211 >;
212 interrupt-parent = < &ipic >;
213 interrupts = <42 8>;
214 bus-range = <0 0>;
215 ranges = <42000000 0 80000000 80000000 0 10000000
216 02000000 0 90000000 90000000 0 10000000
217 01000000 0 00000000 e2000000 0 01000000>;
218 clock-frequency = <3f940aa>;
219 #interrupt-cells = <1>;
220 #size-cells = <2>;
221 #address-cells = <3>;
222 reg = <e0008500 100>;
223 compatible = "fsl,mpc8349-pci";
224 device_type = "pci";
225 };
226
227 pci@e0008600 {
228 interrupt-map-mask = <f800 0 0 7>;
229 interrupt-map = <
230 /* IDSEL 0x0E - MiniPCI Slot */
231 7000 0 0 1 &ipic 15 8 /* PCI_INTA */
232
233 /* IDSEL 0x0F - PCI Slot */
234 7800 0 0 1 &ipic 14 8 /* PCI_INTA */
235 7800 0 0 2 &ipic 15 8 /* PCI_INTB */
236 >;
237 interrupt-parent = < &ipic >;
238 interrupts = <43 8>;
239 bus-range = <0 0>;
240 ranges = <42000000 0 a0000000 a0000000 0 10000000
241 02000000 0 b0000000 b0000000 0 10000000
242 01000000 0 00000000 e3000000 0 01000000>;
243 clock-frequency = <3f940aa>;
244 #interrupt-cells = <1>;
245 #size-cells = <2>;
246 #address-cells = <3>;
247 reg = <e0008600 100>;
248 compatible = "fsl,mpc8349-pci";
249 device_type = "pci";
250 };
251
252
253
252}; 254};
diff --git a/arch/powerpc/boot/dts/mpc8349emitxgp.dts b/arch/powerpc/boot/dts/mpc8349emitxgp.dts
index 0b8387141d88..074f7a2ab7e4 100644
--- a/arch/powerpc/boot/dts/mpc8349emitxgp.dts
+++ b/arch/powerpc/boot/dts/mpc8349emitxgp.dts
@@ -28,7 +28,6 @@
28 timebase-frequency = <0>; // from bootloader 28 timebase-frequency = <0>; // from bootloader
29 bus-frequency = <0>; // from bootloader 29 bus-frequency = <0>; // from bootloader
30 clock-frequency = <0>; // from bootloader 30 clock-frequency = <0>; // from bootloader
31 32-bit;
32 }; 31 };
33 }; 32 };
34 33
@@ -40,7 +39,6 @@
40 soc8349@e0000000 { 39 soc8349@e0000000 {
41 #address-cells = <1>; 40 #address-cells = <1>;
42 #size-cells = <1>; 41 #size-cells = <1>;
43 #interrupt-cells = <2>;
44 device_type = "soc"; 42 device_type = "soc";
45 ranges = <0 e0000000 00100000>; 43 ranges = <0 e0000000 00100000>;
46 reg = <e0000000 00000200>; 44 reg = <e0000000 00000200>;
@@ -72,11 +70,11 @@
72 70
73 spi@7000 { 71 spi@7000 {
74 device_type = "spi"; 72 device_type = "spi";
75 compatible = "mpc83xx_spi"; 73 compatible = "fsl_spi";
76 reg = <7000 1000>; 74 reg = <7000 1000>;
77 interrupts = <10 8>; 75 interrupts = <10 8>;
78 interrupt-parent = < &ipic >; 76 interrupt-parent = < &ipic >;
79 mode = <0>; 77 mode = "cpu";
80 }; 78 };
81 79
82 usb@23000 { 80 usb@23000 {
@@ -116,6 +114,7 @@
116 interrupts = <20 8 21 8 22 8>; 114 interrupts = <20 8 21 8 22 8>;
117 interrupt-parent = < &ipic >; 115 interrupt-parent = < &ipic >;
118 phy-handle = < &phy1c >; 116 phy-handle = < &phy1c >;
117 linux,network-index = <0>;
119 }; 118 };
120 119
121 serial@4500 { 120 serial@4500 {
@@ -136,28 +135,6 @@
136 interrupt-parent = < &ipic >; 135 interrupt-parent = < &ipic >;
137 }; 136 };
138 137
139 pci@8600 {
140 interrupt-map-mask = <f800 0 0 7>;
141 interrupt-map = <
142 /* IDSEL 0x0F - PCI Slot */
143 7800 0 0 1 &ipic 14 8 /* PCI_INTA */
144 7800 0 0 2 &ipic 15 8 /* PCI_INTB */
145 >;
146 interrupt-parent = < &ipic >;
147 interrupts = <43 8>;
148 bus-range = <1 1>;
149 ranges = <42000000 0 a0000000 a0000000 0 10000000
150 02000000 0 b0000000 b0000000 0 10000000
151 01000000 0 00000000 e3000000 0 01000000>;
152 clock-frequency = <3f940aa>;
153 #interrupt-cells = <1>;
154 #size-cells = <2>;
155 #address-cells = <3>;
156 reg = <8600 100>;
157 compatible = "fsl,mpc8349-pci";
158 device_type = "pci";
159 };
160
161 crypto@30000 { 138 crypto@30000 {
162 device_type = "crypto"; 139 device_type = "crypto";
163 model = "SEC2"; 140 model = "SEC2";
@@ -176,8 +153,29 @@
176 #address-cells = <0>; 153 #address-cells = <0>;
177 #interrupt-cells = <2>; 154 #interrupt-cells = <2>;
178 reg = <700 100>; 155 reg = <700 100>;
179 built-in;
180 device_type = "ipic"; 156 device_type = "ipic";
181 }; 157 };
182 }; 158 };
159
160 pci@e0008600 {
161 interrupt-map-mask = <f800 0 0 7>;
162 interrupt-map = <
163 /* IDSEL 0x0F - PCI Slot */
164 7800 0 0 1 &ipic 14 8 /* PCI_INTA */
165 7800 0 0 2 &ipic 15 8 /* PCI_INTB */
166 >;
167 interrupt-parent = < &ipic >;
168 interrupts = <43 8>;
169 bus-range = <1 1>;
170 ranges = <42000000 0 a0000000 a0000000 0 10000000
171 02000000 0 b0000000 b0000000 0 10000000
172 01000000 0 00000000 e3000000 0 01000000>;
173 clock-frequency = <3f940aa>;
174 #interrupt-cells = <1>;
175 #size-cells = <2>;
176 #address-cells = <3>;
177 reg = <e0008600 100>;
178 compatible = "fsl,mpc8349-pci";
179 device_type = "pci";
180 };
183}; 181};
diff --git a/arch/powerpc/boot/dts/mpc834x_mds.dts b/arch/powerpc/boot/dts/mpc834x_mds.dts
index 481099756e44..e5a84ef9f4b0 100644
--- a/arch/powerpc/boot/dts/mpc834x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc834x_mds.dts
@@ -29,7 +29,6 @@
29 timebase-frequency = <0>; // from bootloader 29 timebase-frequency = <0>; // from bootloader
30 bus-frequency = <0>; // from bootloader 30 bus-frequency = <0>; // from bootloader
31 clock-frequency = <0>; // from bootloader 31 clock-frequency = <0>; // from bootloader
32 32-bit;
33 }; 32 };
34 }; 33 };
35 34
@@ -46,7 +45,6 @@
46 soc8349@e0000000 { 45 soc8349@e0000000 {
47 #address-cells = <1>; 46 #address-cells = <1>;
48 #size-cells = <1>; 47 #size-cells = <1>;
49 #interrupt-cells = <2>;
50 device_type = "soc"; 48 device_type = "soc";
51 ranges = <0 e0000000 00100000>; 49 ranges = <0 e0000000 00100000>;
52 reg = <e0000000 00000200>; 50 reg = <e0000000 00000200>;
@@ -78,11 +76,11 @@
78 76
79 spi@7000 { 77 spi@7000 {
80 device_type = "spi"; 78 device_type = "spi";
81 compatible = "mpc83xx_spi"; 79 compatible = "fsl_spi";
82 reg = <7000 1000>; 80 reg = <7000 1000>;
83 interrupts = <10 8>; 81 interrupts = <10 8>;
84 interrupt-parent = < &ipic >; 82 interrupt-parent = < &ipic >;
85 mode = <0>; 83 mode = "cpu";
86 }; 84 };
87 85
88 /* phy type (ULPI or SERIAL) are only types supportted for MPH */ 86 /* phy type (ULPI or SERIAL) are only types supportted for MPH */
@@ -146,6 +144,7 @@
146 interrupts = <20 8 21 8 22 8>; 144 interrupts = <20 8 21 8 22 8>;
147 interrupt-parent = < &ipic >; 145 interrupt-parent = < &ipic >;
148 phy-handle = < &phy0 >; 146 phy-handle = < &phy0 >;
147 linux,network-index = <0>;
149 }; 148 };
150 149
151 ethernet@25000 { 150 ethernet@25000 {
@@ -165,6 +164,7 @@
165 interrupts = <23 8 24 8 25 8>; 164 interrupts = <23 8 24 8 25 8>;
166 interrupt-parent = < &ipic >; 165 interrupt-parent = < &ipic >;
167 phy-handle = < &phy1 >; 166 phy-handle = < &phy1 >;
167 linux,network-index = <1>;
168 }; 168 };
169 169
170 serial@4500 { 170 serial@4500 {
@@ -185,126 +185,6 @@
185 interrupt-parent = < &ipic >; 185 interrupt-parent = < &ipic >;
186 }; 186 };
187 187
188 pci@8500 {
189 interrupt-map-mask = <f800 0 0 7>;
190 interrupt-map = <
191
192 /* IDSEL 0x11 */
193 8800 0 0 1 &ipic 14 8
194 8800 0 0 2 &ipic 15 8
195 8800 0 0 3 &ipic 16 8
196 8800 0 0 4 &ipic 17 8
197
198 /* IDSEL 0x12 */
199 9000 0 0 1 &ipic 16 8
200 9000 0 0 2 &ipic 17 8
201 9000 0 0 3 &ipic 14 8
202 9000 0 0 4 &ipic 15 8
203
204 /* IDSEL 0x13 */
205 9800 0 0 1 &ipic 17 8
206 9800 0 0 2 &ipic 14 8
207 9800 0 0 3 &ipic 15 8
208 9800 0 0 4 &ipic 16 8
209
210 /* IDSEL 0x15 */
211 a800 0 0 1 &ipic 14 8
212 a800 0 0 2 &ipic 15 8
213 a800 0 0 3 &ipic 16 8
214 a800 0 0 4 &ipic 17 8
215
216 /* IDSEL 0x16 */
217 b000 0 0 1 &ipic 17 8
218 b000 0 0 2 &ipic 14 8
219 b000 0 0 3 &ipic 15 8
220 b000 0 0 4 &ipic 16 8
221
222 /* IDSEL 0x17 */
223 b800 0 0 1 &ipic 16 8
224 b800 0 0 2 &ipic 17 8
225 b800 0 0 3 &ipic 14 8
226 b800 0 0 4 &ipic 15 8
227
228 /* IDSEL 0x18 */
229 c000 0 0 1 &ipic 15 8
230 c000 0 0 2 &ipic 16 8
231 c000 0 0 3 &ipic 17 8
232 c000 0 0 4 &ipic 14 8>;
233 interrupt-parent = < &ipic >;
234 interrupts = <42 8>;
235 bus-range = <0 0>;
236 ranges = <02000000 0 90000000 90000000 0 10000000
237 42000000 0 80000000 80000000 0 10000000
238 01000000 0 00000000 e2000000 0 00100000>;
239 clock-frequency = <3f940aa>;
240 #interrupt-cells = <1>;
241 #size-cells = <2>;
242 #address-cells = <3>;
243 reg = <8500 100>;
244 compatible = "fsl,mpc8349-pci";
245 device_type = "pci";
246 };
247
248 pci@8600 {
249 interrupt-map-mask = <f800 0 0 7>;
250 interrupt-map = <
251
252 /* IDSEL 0x11 */
253 8800 0 0 1 &ipic 14 8
254 8800 0 0 2 &ipic 15 8
255 8800 0 0 3 &ipic 16 8
256 8800 0 0 4 &ipic 17 8
257
258 /* IDSEL 0x12 */
259 9000 0 0 1 &ipic 16 8
260 9000 0 0 2 &ipic 17 8
261 9000 0 0 3 &ipic 14 8
262 9000 0 0 4 &ipic 15 8
263
264 /* IDSEL 0x13 */
265 9800 0 0 1 &ipic 17 8
266 9800 0 0 2 &ipic 14 8
267 9800 0 0 3 &ipic 15 8
268 9800 0 0 4 &ipic 16 8
269
270 /* IDSEL 0x15 */
271 a800 0 0 1 &ipic 14 8
272 a800 0 0 2 &ipic 15 8
273 a800 0 0 3 &ipic 16 8
274 a800 0 0 4 &ipic 17 8
275
276 /* IDSEL 0x16 */
277 b000 0 0 1 &ipic 17 8
278 b000 0 0 2 &ipic 14 8
279 b000 0 0 3 &ipic 15 8
280 b000 0 0 4 &ipic 16 8
281
282 /* IDSEL 0x17 */
283 b800 0 0 1 &ipic 16 8
284 b800 0 0 2 &ipic 17 8
285 b800 0 0 3 &ipic 14 8
286 b800 0 0 4 &ipic 15 8
287
288 /* IDSEL 0x18 */
289 c000 0 0 1 &ipic 15 8
290 c000 0 0 2 &ipic 16 8
291 c000 0 0 3 &ipic 17 8
292 c000 0 0 4 &ipic 14 8>;
293 interrupt-parent = < &ipic >;
294 interrupts = <42 8>;
295 bus-range = <0 0>;
296 ranges = <02000000 0 b0000000 b0000000 0 10000000
297 42000000 0 a0000000 a0000000 0 10000000
298 01000000 0 00000000 e2100000 0 00100000>;
299 clock-frequency = <3f940aa>;
300 #interrupt-cells = <1>;
301 #size-cells = <2>;
302 #address-cells = <3>;
303 reg = <8600 100>;
304 compatible = "fsl,mpc8349-pci";
305 device_type = "pci";
306 };
307
308 /* May need to remove if on a part without crypto engine */ 188 /* May need to remove if on a part without crypto engine */
309 crypto@30000 { 189 crypto@30000 {
310 device_type = "crypto"; 190 device_type = "crypto";
@@ -332,8 +212,127 @@
332 #address-cells = <0>; 212 #address-cells = <0>;
333 #interrupt-cells = <2>; 213 #interrupt-cells = <2>;
334 reg = <700 100>; 214 reg = <700 100>;
335 built-in;
336 device_type = "ipic"; 215 device_type = "ipic";
337 }; 216 };
338 }; 217 };
218
219 pci@e0008500 {
220 interrupt-map-mask = <f800 0 0 7>;
221 interrupt-map = <
222
223 /* IDSEL 0x11 */
224 8800 0 0 1 &ipic 14 8
225 8800 0 0 2 &ipic 15 8
226 8800 0 0 3 &ipic 16 8
227 8800 0 0 4 &ipic 17 8
228
229 /* IDSEL 0x12 */
230 9000 0 0 1 &ipic 16 8
231 9000 0 0 2 &ipic 17 8
232 9000 0 0 3 &ipic 14 8
233 9000 0 0 4 &ipic 15 8
234
235 /* IDSEL 0x13 */
236 9800 0 0 1 &ipic 17 8
237 9800 0 0 2 &ipic 14 8
238 9800 0 0 3 &ipic 15 8
239 9800 0 0 4 &ipic 16 8
240
241 /* IDSEL 0x15 */
242 a800 0 0 1 &ipic 14 8
243 a800 0 0 2 &ipic 15 8
244 a800 0 0 3 &ipic 16 8
245 a800 0 0 4 &ipic 17 8
246
247 /* IDSEL 0x16 */
248 b000 0 0 1 &ipic 17 8
249 b000 0 0 2 &ipic 14 8
250 b000 0 0 3 &ipic 15 8
251 b000 0 0 4 &ipic 16 8
252
253 /* IDSEL 0x17 */
254 b800 0 0 1 &ipic 16 8
255 b800 0 0 2 &ipic 17 8
256 b800 0 0 3 &ipic 14 8
257 b800 0 0 4 &ipic 15 8
258
259 /* IDSEL 0x18 */
260 c000 0 0 1 &ipic 15 8
261 c000 0 0 2 &ipic 16 8
262 c000 0 0 3 &ipic 17 8
263 c000 0 0 4 &ipic 14 8>;
264 interrupt-parent = < &ipic >;
265 interrupts = <42 8>;
266 bus-range = <0 0>;
267 ranges = <02000000 0 90000000 90000000 0 10000000
268 42000000 0 80000000 80000000 0 10000000
269 01000000 0 00000000 e2000000 0 00100000>;
270 clock-frequency = <3f940aa>;
271 #interrupt-cells = <1>;
272 #size-cells = <2>;
273 #address-cells = <3>;
274 reg = <e0008500 100>;
275 compatible = "fsl,mpc8349-pci";
276 device_type = "pci";
277 };
278
279 pci@e0008600 {
280 interrupt-map-mask = <f800 0 0 7>;
281 interrupt-map = <
282
283 /* IDSEL 0x11 */
284 8800 0 0 1 &ipic 14 8
285 8800 0 0 2 &ipic 15 8
286 8800 0 0 3 &ipic 16 8
287 8800 0 0 4 &ipic 17 8
288
289 /* IDSEL 0x12 */
290 9000 0 0 1 &ipic 16 8
291 9000 0 0 2 &ipic 17 8
292 9000 0 0 3 &ipic 14 8
293 9000 0 0 4 &ipic 15 8
294
295 /* IDSEL 0x13 */
296 9800 0 0 1 &ipic 17 8
297 9800 0 0 2 &ipic 14 8
298 9800 0 0 3 &ipic 15 8
299 9800 0 0 4 &ipic 16 8
300
301 /* IDSEL 0x15 */
302 a800 0 0 1 &ipic 14 8
303 a800 0 0 2 &ipic 15 8
304 a800 0 0 3 &ipic 16 8
305 a800 0 0 4 &ipic 17 8
306
307 /* IDSEL 0x16 */
308 b000 0 0 1 &ipic 17 8
309 b000 0 0 2 &ipic 14 8
310 b000 0 0 3 &ipic 15 8
311 b000 0 0 4 &ipic 16 8
312
313 /* IDSEL 0x17 */
314 b800 0 0 1 &ipic 16 8
315 b800 0 0 2 &ipic 17 8
316 b800 0 0 3 &ipic 14 8
317 b800 0 0 4 &ipic 15 8
318
319 /* IDSEL 0x18 */
320 c000 0 0 1 &ipic 15 8
321 c000 0 0 2 &ipic 16 8
322 c000 0 0 3 &ipic 17 8
323 c000 0 0 4 &ipic 14 8>;
324 interrupt-parent = < &ipic >;
325 interrupts = <42 8>;
326 bus-range = <0 0>;
327 ranges = <02000000 0 b0000000 b0000000 0 10000000
328 42000000 0 a0000000 a0000000 0 10000000
329 01000000 0 00000000 e2100000 0 00100000>;
330 clock-frequency = <3f940aa>;
331 #interrupt-cells = <1>;
332 #size-cells = <2>;
333 #address-cells = <3>;
334 reg = <e0008600 100>;
335 compatible = "fsl,mpc8349-pci";
336 device_type = "pci";
337 };
339}; 338};
diff --git a/arch/powerpc/boot/dts/mpc836x_mds.dts b/arch/powerpc/boot/dts/mpc836x_mds.dts
index e3f7c1282068..fbd1573c348b 100644
--- a/arch/powerpc/boot/dts/mpc836x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc836x_mds.dts
@@ -34,7 +34,6 @@
34 timebase-frequency = <3EF1480>; 34 timebase-frequency = <3EF1480>;
35 bus-frequency = <FBC5200>; 35 bus-frequency = <FBC5200>;
36 clock-frequency = <1F78A400>; 36 clock-frequency = <1F78A400>;
37 32-bit;
38 }; 37 };
39 }; 38 };
40 39
@@ -51,7 +50,6 @@
51 soc8360@e0000000 { 50 soc8360@e0000000 {
52 #address-cells = <1>; 51 #address-cells = <1>;
53 #size-cells = <1>; 52 #size-cells = <1>;
54 #interrupt-cells = <2>;
55 device_type = "soc"; 53 device_type = "soc";
56 ranges = <0 e0000000 00100000>; 54 ranges = <0 e0000000 00100000>;
57 reg = <e0000000 00000200>; 55 reg = <e0000000 00000200>;
@@ -113,72 +111,11 @@
113 descriptor-types-mask = <01010ebf>; 111 descriptor-types-mask = <01010ebf>;
114 }; 112 };
115 113
116 pci@8500 {
117 interrupt-map-mask = <f800 0 0 7>;
118 interrupt-map = <
119
120 /* IDSEL 0x11 AD17 */
121 8800 0 0 1 &ipic 14 8
122 8800 0 0 2 &ipic 15 8
123 8800 0 0 3 &ipic 16 8
124 8800 0 0 4 &ipic 17 8
125
126 /* IDSEL 0x12 AD18 */
127 9000 0 0 1 &ipic 16 8
128 9000 0 0 2 &ipic 17 8
129 9000 0 0 3 &ipic 14 8
130 9000 0 0 4 &ipic 15 8
131
132 /* IDSEL 0x13 AD19 */
133 9800 0 0 1 &ipic 17 8
134 9800 0 0 2 &ipic 14 8
135 9800 0 0 3 &ipic 15 8
136 9800 0 0 4 &ipic 16 8
137
138 /* IDSEL 0x15 AD21*/
139 a800 0 0 1 &ipic 14 8
140 a800 0 0 2 &ipic 15 8
141 a800 0 0 3 &ipic 16 8
142 a800 0 0 4 &ipic 17 8
143
144 /* IDSEL 0x16 AD22*/
145 b000 0 0 1 &ipic 17 8
146 b000 0 0 2 &ipic 14 8
147 b000 0 0 3 &ipic 15 8
148 b000 0 0 4 &ipic 16 8
149
150 /* IDSEL 0x17 AD23*/
151 b800 0 0 1 &ipic 16 8
152 b800 0 0 2 &ipic 17 8
153 b800 0 0 3 &ipic 14 8
154 b800 0 0 4 &ipic 15 8
155
156 /* IDSEL 0x18 AD24*/
157 c000 0 0 1 &ipic 15 8
158 c000 0 0 2 &ipic 16 8
159 c000 0 0 3 &ipic 17 8
160 c000 0 0 4 &ipic 14 8>;
161 interrupt-parent = < &ipic >;
162 interrupts = <42 8>;
163 bus-range = <0 0>;
164 ranges = <02000000 0 a0000000 a0000000 0 10000000
165 42000000 0 80000000 80000000 0 10000000
166 01000000 0 00000000 e2000000 0 00100000>;
167 clock-frequency = <3f940aa>;
168 #interrupt-cells = <1>;
169 #size-cells = <2>;
170 #address-cells = <3>;
171 reg = <8500 100>;
172 compatible = "fsl,mpc8349-pci";
173 device_type = "pci";
174 };
175
176 ipic: pic@700 { 114 ipic: pic@700 {
177 interrupt-controller; 115 interrupt-controller;
178 #address-cells = <0>; 116 #address-cells = <0>;
179 #interrupt-cells = <2>; 117 #interrupt-cells = <2>;
180 reg = <700 100>; 118 reg = <700 100>;
181 built-in;
182 device_type = "ipic"; 119 device_type = "ipic";
183 }; 120 };
184 121
@@ -364,11 +301,69 @@
364 #address-cells = <0>; 301 #address-cells = <0>;
365 #interrupt-cells = <1>; 302 #interrupt-cells = <1>;
366 reg = <80 80>; 303 reg = <80 80>;
367 built-in;
368 big-endian; 304 big-endian;
369 interrupts = <20 8 21 8>; //high:32 low:33 305 interrupts = <20 8 21 8>; //high:32 low:33
370 interrupt-parent = < &ipic >; 306 interrupt-parent = < &ipic >;
371 }; 307 };
308 };
372 309
310 pci@e0008500 {
311 interrupt-map-mask = <f800 0 0 7>;
312 interrupt-map = <
313
314 /* IDSEL 0x11 AD17 */
315 8800 0 0 1 &ipic 14 8
316 8800 0 0 2 &ipic 15 8
317 8800 0 0 3 &ipic 16 8
318 8800 0 0 4 &ipic 17 8
319
320 /* IDSEL 0x12 AD18 */
321 9000 0 0 1 &ipic 16 8
322 9000 0 0 2 &ipic 17 8
323 9000 0 0 3 &ipic 14 8
324 9000 0 0 4 &ipic 15 8
325
326 /* IDSEL 0x13 AD19 */
327 9800 0 0 1 &ipic 17 8
328 9800 0 0 2 &ipic 14 8
329 9800 0 0 3 &ipic 15 8
330 9800 0 0 4 &ipic 16 8
331
332 /* IDSEL 0x15 AD21*/
333 a800 0 0 1 &ipic 14 8
334 a800 0 0 2 &ipic 15 8
335 a800 0 0 3 &ipic 16 8
336 a800 0 0 4 &ipic 17 8
337
338 /* IDSEL 0x16 AD22*/
339 b000 0 0 1 &ipic 17 8
340 b000 0 0 2 &ipic 14 8
341 b000 0 0 3 &ipic 15 8
342 b000 0 0 4 &ipic 16 8
343
344 /* IDSEL 0x17 AD23*/
345 b800 0 0 1 &ipic 16 8
346 b800 0 0 2 &ipic 17 8
347 b800 0 0 3 &ipic 14 8
348 b800 0 0 4 &ipic 15 8
349
350 /* IDSEL 0x18 AD24*/
351 c000 0 0 1 &ipic 15 8
352 c000 0 0 2 &ipic 16 8
353 c000 0 0 3 &ipic 17 8
354 c000 0 0 4 &ipic 14 8>;
355 interrupt-parent = < &ipic >;
356 interrupts = <42 8>;
357 bus-range = <0 0>;
358 ranges = <02000000 0 a0000000 a0000000 0 10000000
359 42000000 0 80000000 80000000 0 10000000
360 01000000 0 00000000 e2000000 0 00100000>;
361 clock-frequency = <3f940aa>;
362 #interrupt-cells = <1>;
363 #size-cells = <2>;
364 #address-cells = <3>;
365 reg = <e0008500 100>;
366 compatible = "fsl,mpc8349-pci";
367 device_type = "pci";
373 }; 368 };
374}; 369};
diff --git a/arch/powerpc/boot/dts/mpc8540ads.dts b/arch/powerpc/boot/dts/mpc8540ads.dts
index fc8dff9f6201..6442a717ec3b 100644
--- a/arch/powerpc/boot/dts/mpc8540ads.dts
+++ b/arch/powerpc/boot/dts/mpc8540ads.dts
@@ -30,7 +30,6 @@
30 timebase-frequency = <0>; // 33 MHz, from uboot 30 timebase-frequency = <0>; // 33 MHz, from uboot
31 bus-frequency = <0>; // 166 MHz 31 bus-frequency = <0>; // 166 MHz
32 clock-frequency = <0>; // 825 MHz, from uboot 32 clock-frequency = <0>; // 825 MHz, from uboot
33 32-bit;
34 }; 33 };
35 }; 34 };
36 35
@@ -42,7 +41,6 @@
42 soc8540@e0000000 { 41 soc8540@e0000000 {
43 #address-cells = <1>; 42 #address-cells = <1>;
44 #size-cells = <1>; 43 #size-cells = <1>;
45 #interrupt-cells = <2>;
46 device_type = "soc"; 44 device_type = "soc";
47 ranges = <0 e0000000 00100000>; 45 ranges = <0 e0000000 00100000>;
48 reg = <e0000000 00100000>; // CCSRBAR 1M 46 reg = <e0000000 00100000>; // CCSRBAR 1M
@@ -173,105 +171,104 @@
173 interrupts = <2a 2>; 171 interrupts = <2a 2>;
174 interrupt-parent = <&mpic>; 172 interrupt-parent = <&mpic>;
175 }; 173 };
176 pci@8000 { 174 mpic: pic@40000 {
177 interrupt-map-mask = <f800 0 0 7>; 175 clock-frequency = <0>;
178 interrupt-map = < 176 interrupt-controller;
177 #address-cells = <0>;
178 #interrupt-cells = <2>;
179 reg = <40000 40000>;
180 compatible = "chrp,open-pic";
181 device_type = "open-pic";
182 big-endian;
183 };
184 };
179 185
180 /* IDSEL 0x02 */ 186 pci@e0008000 {
181 1000 0 0 1 &mpic 1 1 187 interrupt-map-mask = <f800 0 0 7>;
182 1000 0 0 2 &mpic 2 1 188 interrupt-map = <
183 1000 0 0 3 &mpic 3 1
184 1000 0 0 4 &mpic 4 1
185 189
186 /* IDSEL 0x03 */ 190 /* IDSEL 0x02 */
187 1800 0 0 1 &mpic 4 1 191 1000 0 0 1 &mpic 1 1
188 1800 0 0 2 &mpic 1 1 192 1000 0 0 2 &mpic 2 1
189 1800 0 0 3 &mpic 2 1 193 1000 0 0 3 &mpic 3 1
190 1800 0 0 4 &mpic 3 1 194 1000 0 0 4 &mpic 4 1
191 195
192 /* IDSEL 0x04 */ 196 /* IDSEL 0x03 */
193 2000 0 0 1 &mpic 3 1 197 1800 0 0 1 &mpic 4 1
194 2000 0 0 2 &mpic 4 1 198 1800 0 0 2 &mpic 1 1
195 2000 0 0 3 &mpic 1 1 199 1800 0 0 3 &mpic 2 1
196 2000 0 0 4 &mpic 2 1 200 1800 0 0 4 &mpic 3 1
197 201
198 /* IDSEL 0x05 */ 202 /* IDSEL 0x04 */
199 2800 0 0 1 &mpic 2 1 203 2000 0 0 1 &mpic 3 1
200 2800 0 0 2 &mpic 3 1 204 2000 0 0 2 &mpic 4 1
201 2800 0 0 3 &mpic 4 1 205 2000 0 0 3 &mpic 1 1
202 2800 0 0 4 &mpic 1 1 206 2000 0 0 4 &mpic 2 1
203 207
204 /* IDSEL 0x0c */ 208 /* IDSEL 0x05 */
205 6000 0 0 1 &mpic 1 1 209 2800 0 0 1 &mpic 2 1
206 6000 0 0 2 &mpic 2 1 210 2800 0 0 2 &mpic 3 1
207 6000 0 0 3 &mpic 3 1 211 2800 0 0 3 &mpic 4 1
208 6000 0 0 4 &mpic 4 1 212 2800 0 0 4 &mpic 1 1
209 213
210 /* IDSEL 0x0d */ 214 /* IDSEL 0x0c */
211 6800 0 0 1 &mpic 4 1 215 6000 0 0 1 &mpic 1 1
212 6800 0 0 2 &mpic 1 1 216 6000 0 0 2 &mpic 2 1
213 6800 0 0 3 &mpic 2 1 217 6000 0 0 3 &mpic 3 1
214 6800 0 0 4 &mpic 3 1 218 6000 0 0 4 &mpic 4 1
215 219
216 /* IDSEL 0x0e */ 220 /* IDSEL 0x0d */
217 7000 0 0 1 &mpic 3 1 221 6800 0 0 1 &mpic 4 1
218 7000 0 0 2 &mpic 4 1 222 6800 0 0 2 &mpic 1 1
219 7000 0 0 3 &mpic 1 1 223 6800 0 0 3 &mpic 2 1
220 7000 0 0 4 &mpic 2 1 224 6800 0 0 4 &mpic 3 1
221 225
222 /* IDSEL 0x0f */ 226 /* IDSEL 0x0e */
223 7800 0 0 1 &mpic 2 1 227 7000 0 0 1 &mpic 3 1
224 7800 0 0 2 &mpic 3 1 228 7000 0 0 2 &mpic 4 1
225 7800 0 0 3 &mpic 4 1 229 7000 0 0 3 &mpic 1 1
226 7800 0 0 4 &mpic 1 1 230 7000 0 0 4 &mpic 2 1
227 231
228 /* IDSEL 0x12 */ 232 /* IDSEL 0x0f */
229 9000 0 0 1 &mpic 1 1 233 7800 0 0 1 &mpic 2 1
230 9000 0 0 2 &mpic 2 1 234 7800 0 0 2 &mpic 3 1
231 9000 0 0 3 &mpic 3 1 235 7800 0 0 3 &mpic 4 1
232 9000 0 0 4 &mpic 4 1 236 7800 0 0 4 &mpic 1 1
233 237
234 /* IDSEL 0x13 */ 238 /* IDSEL 0x12 */
235 9800 0 0 1 &mpic 4 1 239 9000 0 0 1 &mpic 1 1
236 9800 0 0 2 &mpic 1 1 240 9000 0 0 2 &mpic 2 1
237 9800 0 0 3 &mpic 2 1 241 9000 0 0 3 &mpic 3 1
238 9800 0 0 4 &mpic 3 1 242 9000 0 0 4 &mpic 4 1
239 243
240 /* IDSEL 0x14 */ 244 /* IDSEL 0x13 */
241 a000 0 0 1 &mpic 3 1 245 9800 0 0 1 &mpic 4 1
242 a000 0 0 2 &mpic 4 1 246 9800 0 0 2 &mpic 1 1
243 a000 0 0 3 &mpic 1 1 247 9800 0 0 3 &mpic 2 1
244 a000 0 0 4 &mpic 2 1 248 9800 0 0 4 &mpic 3 1
245 249
246 /* IDSEL 0x15 */ 250 /* IDSEL 0x14 */
247 a800 0 0 1 &mpic 2 1 251 a000 0 0 1 &mpic 3 1
248 a800 0 0 2 &mpic 3 1 252 a000 0 0 2 &mpic 4 1
249 a800 0 0 3 &mpic 4 1 253 a000 0 0 3 &mpic 1 1
250 a800 0 0 4 &mpic 1 1>; 254 a000 0 0 4 &mpic 2 1
251 interrupt-parent = <&mpic>;
252 interrupts = <18 2>;
253 bus-range = <0 0>;
254 ranges = <02000000 0 80000000 80000000 0 20000000
255 01000000 0 00000000 e2000000 0 00100000>;
256 clock-frequency = <3f940aa>;
257 #interrupt-cells = <1>;
258 #size-cells = <2>;
259 #address-cells = <3>;
260 reg = <8000 1000>;
261 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
262 device_type = "pci";
263 };
264 255
265 mpic: pic@40000 { 256 /* IDSEL 0x15 */
266 clock-frequency = <0>; 257 a800 0 0 1 &mpic 2 1
267 interrupt-controller; 258 a800 0 0 2 &mpic 3 1
268 #address-cells = <0>; 259 a800 0 0 3 &mpic 4 1
269 #interrupt-cells = <2>; 260 a800 0 0 4 &mpic 1 1>;
270 reg = <40000 40000>; 261 interrupt-parent = <&mpic>;
271 built-in; 262 interrupts = <18 2>;
272 compatible = "chrp,open-pic"; 263 bus-range = <0 0>;
273 device_type = "open-pic"; 264 ranges = <02000000 0 80000000 80000000 0 20000000
274 big-endian; 265 01000000 0 00000000 e2000000 0 00100000>;
275 }; 266 clock-frequency = <3f940aa>;
267 #interrupt-cells = <1>;
268 #size-cells = <2>;
269 #address-cells = <3>;
270 reg = <e0008000 1000>;
271 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
272 device_type = "pci";
276 }; 273 };
277}; 274};
diff --git a/arch/powerpc/boot/dts/mpc8541cds.dts b/arch/powerpc/boot/dts/mpc8541cds.dts
index fb0b647f8c2a..f3f4d79deb63 100644
--- a/arch/powerpc/boot/dts/mpc8541cds.dts
+++ b/arch/powerpc/boot/dts/mpc8541cds.dts
@@ -30,7 +30,6 @@
30 timebase-frequency = <0>; // 33 MHz, from uboot 30 timebase-frequency = <0>; // 33 MHz, from uboot
31 bus-frequency = <0>; // 166 MHz 31 bus-frequency = <0>; // 166 MHz
32 clock-frequency = <0>; // 825 MHz, from uboot 32 clock-frequency = <0>; // 825 MHz, from uboot
33 32-bit;
34 }; 33 };
35 }; 34 };
36 35
@@ -42,10 +41,9 @@
42 soc8541@e0000000 { 41 soc8541@e0000000 {
43 #address-cells = <1>; 42 #address-cells = <1>;
44 #size-cells = <1>; 43 #size-cells = <1>;
45 #interrupt-cells = <2>;
46 device_type = "soc"; 44 device_type = "soc";
47 ranges = <0 e0000000 00100000>; 45 ranges = <0 e0000000 00100000>;
48 reg = <e0000000 00100000>; // CCSRBAR 1M 46 reg = <e0000000 00001000>; // CCSRBAR 1M
49 bus-frequency = <0>; 47 bus-frequency = <0>;
50 48
51 memory-controller@2000 { 49 memory-controller@2000 {
@@ -137,113 +135,145 @@
137 interrupt-parent = <&mpic>; 135 interrupt-parent = <&mpic>;
138 }; 136 };
139 137
140 pci1: pci@8000 { 138 mpic: pic@40000 {
141 interrupt-map-mask = <1f800 0 0 7>; 139 clock-frequency = <0>;
142 interrupt-map = < 140 interrupt-controller;
143 141 #address-cells = <0>;
144 /* IDSEL 0x10 */ 142 #interrupt-cells = <2>;
145 08000 0 0 1 &mpic 0 1 143 reg = <40000 40000>;
146 08000 0 0 2 &mpic 1 1 144 compatible = "chrp,open-pic";
147 08000 0 0 3 &mpic 2 1 145 device_type = "open-pic";
148 08000 0 0 4 &mpic 3 1 146 big-endian;
149 147 };
150 /* IDSEL 0x11 */ 148
151 08800 0 0 1 &mpic 0 1 149 cpm@919c0 {
152 08800 0 0 2 &mpic 1 1 150 #address-cells = <1>;
153 08800 0 0 3 &mpic 2 1 151 #size-cells = <1>;
154 08800 0 0 4 &mpic 3 1 152 compatible = "fsl,mpc8541-cpm", "fsl,cpm2";
155 153 reg = <919c0 30>;
156 /* IDSEL 0x12 (Slot 1) */ 154 ranges;
157 09000 0 0 1 &mpic 0 1 155
158 09000 0 0 2 &mpic 1 1 156 muram@80000 {
159 09000 0 0 3 &mpic 2 1 157 #address-cells = <1>;
160 09000 0 0 4 &mpic 3 1 158 #size-cells = <1>;
161 159 ranges = <0 80000 10000>;
162 /* IDSEL 0x13 (Slot 2) */ 160
163 09800 0 0 1 &mpic 1 1 161 data@0 {
164 09800 0 0 2 &mpic 2 1 162 compatible = "fsl,cpm-muram-data";
165 09800 0 0 3 &mpic 3 1 163 reg = <0 2000 9000 1000>;
166 09800 0 0 4 &mpic 0 1 164 };
167 165 };
168 /* IDSEL 0x14 (Slot 3) */ 166
169 0a000 0 0 1 &mpic 2 1 167 brg@919f0 {
170 0a000 0 0 2 &mpic 3 1 168 compatible = "fsl,mpc8541-brg",
171 0a000 0 0 3 &mpic 0 1 169 "fsl,cpm2-brg",
172 0a000 0 0 4 &mpic 1 1 170 "fsl,cpm-brg";
173 171 reg = <919f0 10 915f0 10>;
174 /* IDSEL 0x15 (Slot 4) */ 172 };
175 0a800 0 0 1 &mpic 3 1 173
176 0a800 0 0 2 &mpic 0 1 174 cpmpic: pic@90c00 {
177 0a800 0 0 3 &mpic 1 1
178 0a800 0 0 4 &mpic 2 1
179
180 /* Bus 1 (Tundra Bridge) */
181 /* IDSEL 0x12 (ISA bridge) */
182 19000 0 0 1 &mpic 0 1
183 19000 0 0 2 &mpic 1 1
184 19000 0 0 3 &mpic 2 1
185 19000 0 0 4 &mpic 3 1>;
186 interrupt-parent = <&mpic>;
187 interrupts = <18 2>;
188 bus-range = <0 0>;
189 ranges = <02000000 0 80000000 80000000 0 20000000
190 01000000 0 00000000 e2000000 0 00100000>;
191 clock-frequency = <3f940aa>;
192 #interrupt-cells = <1>;
193 #size-cells = <2>;
194 #address-cells = <3>;
195 reg = <8000 1000>;
196 compatible = "fsl,mpc8540-pci";
197 device_type = "pci";
198
199 i8259@19000 {
200 clock-frequency = <0>;
201 interrupt-controller; 175 interrupt-controller;
202 device_type = "interrupt-controller";
203 reg = <19000 0 0 0 1>;
204 #address-cells = <0>; 176 #address-cells = <0>;
205 #interrupt-cells = <2>; 177 #interrupt-cells = <2>;
206 built-in; 178 interrupts = <2e 2>;
207 compatible = "chrp,iic"; 179 interrupt-parent = <&mpic>;
208 big-endian; 180 reg = <90c00 80>;
209 interrupts = <1>; 181 compatible = "fsl,mpc8541-cpm-pic", "fsl,cpm2-pic";
210 interrupt-parent = <&pci1>;
211 }; 182 };
212 }; 183 };
184 };
213 185
214 pci@9000 { 186 pci1: pci@e0008000 {
215 interrupt-map-mask = <f800 0 0 7>; 187 interrupt-map-mask = <1f800 0 0 7>;
216 interrupt-map = < 188 interrupt-map = <
217 189
218 /* IDSEL 0x15 */ 190 /* IDSEL 0x10 */
219 a800 0 0 1 &mpic b 1 191 08000 0 0 1 &mpic 0 1
220 a800 0 0 2 &mpic b 1 192 08000 0 0 2 &mpic 1 1
221 a800 0 0 3 &mpic b 1 193 08000 0 0 3 &mpic 2 1
222 a800 0 0 4 &mpic b 1>; 194 08000 0 0 4 &mpic 3 1
223 interrupt-parent = <&mpic>;
224 interrupts = <19 2>;
225 bus-range = <0 0>;
226 ranges = <02000000 0 a0000000 a0000000 0 20000000
227 01000000 0 00000000 e3000000 0 00100000>;
228 clock-frequency = <3f940aa>;
229 #interrupt-cells = <1>;
230 #size-cells = <2>;
231 #address-cells = <3>;
232 reg = <9000 1000>;
233 compatible = "fsl,mpc8540-pci";
234 device_type = "pci";
235 };
236 195
237 mpic: pic@40000 { 196 /* IDSEL 0x11 */
238 clock-frequency = <0>; 197 08800 0 0 1 &mpic 0 1
198 08800 0 0 2 &mpic 1 1
199 08800 0 0 3 &mpic 2 1
200 08800 0 0 4 &mpic 3 1
201
202 /* IDSEL 0x12 (Slot 1) */
203 09000 0 0 1 &mpic 0 1
204 09000 0 0 2 &mpic 1 1
205 09000 0 0 3 &mpic 2 1
206 09000 0 0 4 &mpic 3 1
207
208 /* IDSEL 0x13 (Slot 2) */
209 09800 0 0 1 &mpic 1 1
210 09800 0 0 2 &mpic 2 1
211 09800 0 0 3 &mpic 3 1
212 09800 0 0 4 &mpic 0 1
213
214 /* IDSEL 0x14 (Slot 3) */
215 0a000 0 0 1 &mpic 2 1
216 0a000 0 0 2 &mpic 3 1
217 0a000 0 0 3 &mpic 0 1
218 0a000 0 0 4 &mpic 1 1
219
220 /* IDSEL 0x15 (Slot 4) */
221 0a800 0 0 1 &mpic 3 1
222 0a800 0 0 2 &mpic 0 1
223 0a800 0 0 3 &mpic 1 1
224 0a800 0 0 4 &mpic 2 1
225
226 /* Bus 1 (Tundra Bridge) */
227 /* IDSEL 0x12 (ISA bridge) */
228 19000 0 0 1 &mpic 0 1
229 19000 0 0 2 &mpic 1 1
230 19000 0 0 3 &mpic 2 1
231 19000 0 0 4 &mpic 3 1>;
232 interrupt-parent = <&mpic>;
233 interrupts = <18 2>;
234 bus-range = <0 0>;
235 ranges = <02000000 0 80000000 80000000 0 20000000
236 01000000 0 00000000 e2000000 0 00100000>;
237 clock-frequency = <3f940aa>;
238 #interrupt-cells = <1>;
239 #size-cells = <2>;
240 #address-cells = <3>;
241 reg = <e0008000 1000>;
242 compatible = "fsl,mpc8540-pci";
243 device_type = "pci";
244
245 i8259@19000 {
239 interrupt-controller; 246 interrupt-controller;
247 device_type = "interrupt-controller";
248 reg = <19000 0 0 0 1>;
240 #address-cells = <0>; 249 #address-cells = <0>;
241 #interrupt-cells = <2>; 250 #interrupt-cells = <2>;
242 reg = <40000 40000>; 251 compatible = "chrp,iic";
243 built-in; 252 interrupts = <1>;
244 compatible = "chrp,open-pic"; 253 interrupt-parent = <&pci1>;
245 device_type = "open-pic";
246 big-endian;
247 }; 254 };
248 }; 255 };
256
257 pci@e0009000 {
258 interrupt-map-mask = <f800 0 0 7>;
259 interrupt-map = <
260
261 /* IDSEL 0x15 */
262 a800 0 0 1 &mpic b 1
263 a800 0 0 2 &mpic b 1
264 a800 0 0 3 &mpic b 1
265 a800 0 0 4 &mpic b 1>;
266 interrupt-parent = <&mpic>;
267 interrupts = <19 2>;
268 bus-range = <0 0>;
269 ranges = <02000000 0 a0000000 a0000000 0 20000000
270 01000000 0 00000000 e3000000 0 00100000>;
271 clock-frequency = <3f940aa>;
272 #interrupt-cells = <1>;
273 #size-cells = <2>;
274 #address-cells = <3>;
275 reg = <e0009000 1000>;
276 compatible = "fsl,mpc8540-pci";
277 device_type = "pci";
278 };
249}; 279};
diff --git a/arch/powerpc/boot/dts/mpc8544ds.dts b/arch/powerpc/boot/dts/mpc8544ds.dts
index 3e79bf0a3159..3f9d15cf13e0 100644
--- a/arch/powerpc/boot/dts/mpc8544ds.dts
+++ b/arch/powerpc/boot/dts/mpc8544ds.dts
@@ -30,7 +30,6 @@
30 timebase-frequency = <0>; 30 timebase-frequency = <0>;
31 bus-frequency = <0>; 31 bus-frequency = <0>;
32 clock-frequency = <0>; 32 clock-frequency = <0>;
33 32-bit;
34 }; 33 };
35 }; 34 };
36 35
@@ -42,19 +41,9 @@
42 soc8544@e0000000 { 41 soc8544@e0000000 {
43 #address-cells = <1>; 42 #address-cells = <1>;
44 #size-cells = <1>; 43 #size-cells = <1>;
45 #interrupt-cells = <2>;
46 device_type = "soc"; 44 device_type = "soc";
47 45
48 46 ranges = <00000000 e0000000 00100000>;
49 ranges = <00001000 e0001000 000ff000
50 80000000 80000000 20000000
51 a0000000 a0000000 10000000
52 b0000000 b0000000 00100000
53 c0000000 c0000000 20000000
54 b0100000 b0100000 00100000
55 e1000000 e1000000 00010000
56 e1010000 e1010000 00010000
57 e1020000 e1020000 00010000>;
58 reg = <e0000000 00001000>; // CCSRBAR 1M 47 reg = <e0000000 00001000>; // CCSRBAR 1M
59 bus-frequency = <0>; // Filled out by uboot. 48 bus-frequency = <0>; // Filled out by uboot.
60 49
@@ -149,115 +138,173 @@
149 interrupt-parent = <&mpic>; 138 interrupt-parent = <&mpic>;
150 }; 139 };
151 140
152 pci@8000 { 141 global-utilities@e0000 { //global utilities block
153 compatible = "fsl,mpc8540-pci"; 142 compatible = "fsl,mpc8548-guts";
154 device_type = "pci"; 143 reg = <e0000 1000>;
155 interrupt-map-mask = <f800 0 0 7>; 144 fsl,has-rstcr;
156 interrupt-map = < 145 };
157
158 /* IDSEL 0x11 J17 Slot 1 */
159 8800 0 0 1 &mpic 2 1
160 8800 0 0 2 &mpic 3 1
161 8800 0 0 3 &mpic 4 1
162 8800 0 0 4 &mpic 1 1
163 146
164 /* IDSEL 0x12 J16 Slot 2 */ 147 mpic: pic@40000 {
148 clock-frequency = <0>;
149 interrupt-controller;
150 #address-cells = <0>;
151 #interrupt-cells = <2>;
152 reg = <40000 40000>;
153 compatible = "chrp,open-pic";
154 device_type = "open-pic";
155 big-endian;
156 };
157 };
165 158
166 9000 0 0 1 &mpic 3 1 159 pci@e0008000 {
167 9000 0 0 2 &mpic 4 1 160 compatible = "fsl,mpc8540-pci";
168 9000 0 0 3 &mpic 2 1 161 device_type = "pci";
169 9000 0 0 4 &mpic 1 1>; 162 interrupt-map-mask = <f800 0 0 7>;
163 interrupt-map = <
164
165 /* IDSEL 0x11 J17 Slot 1 */
166 8800 0 0 1 &mpic 2 1
167 8800 0 0 2 &mpic 3 1
168 8800 0 0 3 &mpic 4 1
169 8800 0 0 4 &mpic 1 1
170
171 /* IDSEL 0x12 J16 Slot 2 */
172
173 9000 0 0 1 &mpic 3 1
174 9000 0 0 2 &mpic 4 1
175 9000 0 0 3 &mpic 2 1
176 9000 0 0 4 &mpic 1 1>;
177
178 interrupt-parent = <&mpic>;
179 interrupts = <18 2>;
180 bus-range = <0 ff>;
181 ranges = <02000000 0 c0000000 c0000000 0 20000000
182 01000000 0 00000000 e1000000 0 00010000>;
183 clock-frequency = <3f940aa>;
184 #interrupt-cells = <1>;
185 #size-cells = <2>;
186 #address-cells = <3>;
187 reg = <e0008000 1000>;
188 };
170 189
171 interrupt-parent = <&mpic>; 190 pcie@e0009000 {
172 interrupts = <18 2>; 191 compatible = "fsl,mpc8548-pcie";
173 bus-range = <0 ff>; 192 device_type = "pci";
174 ranges = <02000000 0 c0000000 c0000000 0 20000000 193 #interrupt-cells = <1>;
175 01000000 0 00000000 e1000000 0 00010000>; 194 #size-cells = <2>;
176 clock-frequency = <3f940aa>; 195 #address-cells = <3>;
177 #interrupt-cells = <1>; 196 reg = <e0009000 1000>;
197 bus-range = <0 ff>;
198 ranges = <02000000 0 80000000 80000000 0 20000000
199 01000000 0 00000000 e1010000 0 00010000>;
200 clock-frequency = <1fca055>;
201 interrupt-parent = <&mpic>;
202 interrupts = <1a 2>;
203 interrupt-map-mask = <f800 0 0 7>;
204 interrupt-map = <
205 /* IDSEL 0x0 */
206 0000 0 0 1 &mpic 4 1
207 0000 0 0 2 &mpic 5 1
208 0000 0 0 3 &mpic 6 1
209 0000 0 0 4 &mpic 7 1
210 >;
211 pcie@0 {
212 reg = <0 0 0 0 0>;
178 #size-cells = <2>; 213 #size-cells = <2>;
179 #address-cells = <3>; 214 #address-cells = <3>;
180 reg = <8000 1000>;
181 };
182
183 pcie@9000 {
184 compatible = "fsl,mpc8548-pcie";
185 device_type = "pci"; 215 device_type = "pci";
186 #interrupt-cells = <1>; 216 ranges = <02000000 0 80000000
187 #size-cells = <2>; 217 02000000 0 80000000
188 #address-cells = <3>; 218 0 20000000
189 reg = <9000 1000>; 219
190 bus-range = <0 ff>; 220 01000000 0 00000000
191 ranges = <02000000 0 80000000 80000000 0 20000000 221 01000000 0 00000000
192 01000000 0 00000000 e1010000 0 00010000>; 222 0 00010000>;
193 clock-frequency = <1fca055>;
194 interrupt-parent = <&mpic>;
195 interrupts = <1a 2>;
196 interrupt-map-mask = <f800 0 0 7>;
197 interrupt-map = <
198 /* IDSEL 0x0 */
199 0000 0 0 1 &mpic 4 1
200 0000 0 0 2 &mpic 5 1
201 0000 0 0 3 &mpic 6 1
202 0000 0 0 4 &mpic 7 1
203 >;
204 }; 223 };
224 };
205 225
206 pcie@a000 { 226 pcie@e000a000 {
207 compatible = "fsl,mpc8548-pcie"; 227 compatible = "fsl,mpc8548-pcie";
208 device_type = "pci"; 228 device_type = "pci";
209 #interrupt-cells = <1>; 229 #interrupt-cells = <1>;
230 #size-cells = <2>;
231 #address-cells = <3>;
232 reg = <e000a000 1000>;
233 bus-range = <0 ff>;
234 ranges = <02000000 0 a0000000 a0000000 0 10000000
235 01000000 0 00000000 e1020000 0 00010000>;
236 clock-frequency = <1fca055>;
237 interrupt-parent = <&mpic>;
238 interrupts = <19 2>;
239 interrupt-map-mask = <f800 0 0 7>;
240 interrupt-map = <
241 /* IDSEL 0x0 */
242 0000 0 0 1 &mpic 0 1
243 0000 0 0 2 &mpic 1 1
244 0000 0 0 3 &mpic 2 1
245 0000 0 0 4 &mpic 3 1
246 >;
247 pcie@0 {
248 reg = <0 0 0 0 0>;
210 #size-cells = <2>; 249 #size-cells = <2>;
211 #address-cells = <3>; 250 #address-cells = <3>;
212 reg = <a000 1000>; 251 device_type = "pci";
213 bus-range = <0 ff>; 252 ranges = <02000000 0 a0000000
214 ranges = <02000000 0 a0000000 a0000000 0 10000000 253 02000000 0 a0000000
215 01000000 0 00000000 e1020000 0 00010000>; 254 0 10000000
216 clock-frequency = <1fca055>; 255
217 interrupt-parent = <&mpic>; 256 01000000 0 00000000
218 interrupts = <19 2>; 257 01000000 0 00000000
219 interrupt-map-mask = <f800 0 0 7>; 258 0 00010000>;
220 interrupt-map = <
221 /* IDSEL 0x0 */
222 0000 0 0 1 &mpic 0 1
223 0000 0 0 2 &mpic 1 1
224 0000 0 0 3 &mpic 2 1
225 0000 0 0 4 &mpic 3 1
226 >;
227 }; 259 };
260 };
228 261
229 pcie@b000 { 262 pcie@e000b000 {
230 compatible = "fsl,mpc8548-pcie"; 263 compatible = "fsl,mpc8548-pcie";
231 device_type = "pci"; 264 device_type = "pci";
232 #interrupt-cells = <1>; 265 #interrupt-cells = <1>;
266 #size-cells = <2>;
267 #address-cells = <3>;
268 reg = <e000b000 1000>;
269 bus-range = <0 ff>;
270 ranges = <02000000 0 b0000000 b0000000 0 00100000
271 01000000 0 00000000 b0100000 0 00100000>;
272 clock-frequency = <1fca055>;
273 interrupt-parent = <&mpic>;
274 interrupts = <1b 2>;
275 interrupt-map-mask = <fb00 0 0 0>;
276 interrupt-map = <
277 // IDSEL 0x1c USB
278 e000 0 0 0 &i8259 c 2
279 e100 0 0 0 &i8259 9 2
280 e200 0 0 0 &i8259 a 2
281 e300 0 0 0 &i8259 b 2
282
283 // IDSEL 0x1d Audio
284 e800 0 0 0 &i8259 6 2
285
286 // IDSEL 0x1e Legacy
287 f000 0 0 0 &i8259 7 2
288 f100 0 0 0 &i8259 7 2
289
290 // IDSEL 0x1f IDE/SATA
291 f800 0 0 0 &i8259 e 2
292 f900 0 0 0 &i8259 5 2
293 >;
294
295 pcie@0 {
296 reg = <0 0 0 0 0>;
233 #size-cells = <2>; 297 #size-cells = <2>;
234 #address-cells = <3>; 298 #address-cells = <3>;
235 reg = <b000 1000>; 299 device_type = "pci";
236 bus-range = <0 ff>; 300 ranges = <02000000 0 b0000000
237 ranges = <02000000 0 b0000000 b0000000 0 00100000 301 02000000 0 b0000000
238 01000000 0 00000000 b0100000 0 00100000>; 302 0 00100000
239 clock-frequency = <1fca055>; 303
240 interrupt-parent = <&mpic>; 304 01000000 0 00000000
241 interrupts = <1b 2>; 305 01000000 0 00000000
242 interrupt-map-mask = <fb00 0 0 0>; 306 0 00100000>;
243 interrupt-map = < 307
244 // IDSEL 0x1c USB
245 e000 0 0 0 &i8259 c 2
246 e100 0 0 0 &i8259 9 2
247 e200 0 0 0 &i8259 a 2
248 e300 0 0 0 &i8259 b 2
249
250 // IDSEL 0x1d Audio
251 e800 0 0 0 &i8259 6 2
252
253 // IDSEL 0x1e Legacy
254 f000 0 0 0 &i8259 7 2
255 f100 0 0 0 &i8259 7 2
256
257 // IDSEL 0x1f IDE/SATA
258 f800 0 0 0 &i8259 e 2
259 f900 0 0 0 &i8259 5 2
260 >;
261 uli1575@0 { 308 uli1575@0 {
262 reg = <0 0 0 0 0>; 309 reg = <0 0 0 0 0>;
263 #size-cells = <2>; 310 #size-cells = <2>;
@@ -265,95 +312,63 @@
265 ranges = <02000000 0 b0000000 312 ranges = <02000000 0 b0000000
266 02000000 0 b0000000 313 02000000 0 b0000000
267 0 00100000 314 0 00100000
315
268 01000000 0 00000000 316 01000000 0 00000000
269 01000000 0 00000000 317 01000000 0 00000000
270 0 00100000>; 318 0 00100000>;
271 319 isa@1e {
272 pci_bridge@0 { 320 device_type = "isa";
273 reg = <0 0 0 0 0>; 321 #interrupt-cells = <2>;
274 #size-cells = <2>; 322 #size-cells = <1>;
275 #address-cells = <3>; 323 #address-cells = <2>;
276 ranges = <02000000 0 b0000000 324 reg = <f000 0 0 0 0>;
277 02000000 0 b0000000 325 ranges = <1 0
278 0 00100000 326 01000000 0 0
279 01000000 0 00000000 327 00001000>;
280 01000000 0 00000000 328 interrupt-parent = <&i8259>;
281 0 00100000>; 329
282 330 i8259: interrupt-controller@20 {
283 isa@1e { 331 reg = <1 20 2
284 device_type = "isa"; 332 1 a0 2
333 1 4d0 2>;
334 interrupt-controller;
335 device_type = "interrupt-controller";
336 #address-cells = <0>;
285 #interrupt-cells = <2>; 337 #interrupt-cells = <2>;
286 #size-cells = <1>; 338 compatible = "chrp,iic";
287 #address-cells = <2>; 339 interrupts = <9 2>;
288 reg = <f000 0 0 0 0>; 340 interrupt-parent = <&mpic>;
289 ranges = <1 0 341 };
290 01000000 0 0 342
291 00001000>; 343 i8042@60 {
344 #size-cells = <0>;
345 #address-cells = <1>;
346 reg = <1 60 1 1 64 1>;
347 interrupts = <1 3 c 3>;
292 interrupt-parent = <&i8259>; 348 interrupt-parent = <&i8259>;
293 349
294 i8259: interrupt-controller@20 { 350 keyboard@0 {
295 reg = <1 20 2 351 reg = <0>;
296 1 a0 2 352 compatible = "pnpPNP,303";
297 1 4d0 2>;
298 clock-frequency = <0>;
299 interrupt-controller;
300 device_type = "interrupt-controller";
301 #address-cells = <0>;
302 #interrupt-cells = <2>;
303 built-in;
304 compatible = "chrp,iic";
305 interrupts = <9 2>;
306 interrupt-parent = <&mpic>;
307 }; 353 };
308 354
309 i8042@60 { 355 mouse@1 {
310 #size-cells = <0>; 356 reg = <1>;
311 #address-cells = <1>; 357 compatible = "pnpPNP,f03";
312 reg = <1 60 1 1 64 1>;
313 interrupts = <1 3 c 3>;
314 interrupt-parent = <&i8259>;
315
316 keyboard@0 {
317 reg = <0>;
318 compatible = "pnpPNP,303";
319 };
320
321 mouse@1 {
322 reg = <1>;
323 compatible = "pnpPNP,f03";
324 };
325 }; 358 };
359 };
326 360
327 rtc@70 { 361 rtc@70 {
328 compatible = "pnpPNP,b00"; 362 compatible = "pnpPNP,b00";
329 reg = <1 70 2>; 363 reg = <1 70 2>;
330 }; 364 };
331 365
332 gpio@400 { 366 gpio@400 {
333 reg = <1 400 80>; 367 reg = <1 400 80>;
334 };
335 }; 368 };
336 }; 369 };
337 }; 370 };
338
339 }; 371 };
340 372
341 global-utilities@e0000 { //global utilities block
342 compatible = "fsl,mpc8548-guts";
343 reg = <e0000 1000>;
344 fsl,has-rstcr;
345 };
346
347 mpic: pic@40000 {
348 clock-frequency = <0>;
349 interrupt-controller;
350 #address-cells = <0>;
351 #interrupt-cells = <2>;
352 reg = <40000 40000>;
353 built-in;
354 compatible = "chrp,open-pic";
355 device_type = "open-pic";
356 big-endian;
357 };
358 }; 373 };
359}; 374};
diff --git a/arch/powerpc/boot/dts/mpc8548cds.dts b/arch/powerpc/boot/dts/mpc8548cds.dts
index d215d21fff42..69ca5025d972 100644
--- a/arch/powerpc/boot/dts/mpc8548cds.dts
+++ b/arch/powerpc/boot/dts/mpc8548cds.dts
@@ -30,7 +30,6 @@
30 timebase-frequency = <0>; // 33 MHz, from uboot 30 timebase-frequency = <0>; // 33 MHz, from uboot
31 bus-frequency = <0>; // 166 MHz 31 bus-frequency = <0>; // 166 MHz
32 clock-frequency = <0>; // 825 MHz, from uboot 32 clock-frequency = <0>; // 825 MHz, from uboot
33 32-bit;
34 }; 33 };
35 }; 34 };
36 35
@@ -42,15 +41,8 @@
42 soc8548@e0000000 { 41 soc8548@e0000000 {
43 #address-cells = <1>; 42 #address-cells = <1>;
44 #size-cells = <1>; 43 #size-cells = <1>;
45 #interrupt-cells = <2>;
46 device_type = "soc"; 44 device_type = "soc";
47 ranges = <00001000 e0001000 000ff000 45 ranges = <00000000 e0000000 00100000>;
48 80000000 80000000 10000000
49 e2000000 e2000000 00800000
50 90000000 90000000 10000000
51 e2800000 e2800000 00800000
52 a0000000 a0000000 20000000
53 e3000000 e3000000 01000000>;
54 reg = <e0000000 00001000>; // CCSRBAR 46 reg = <e0000000 00001000>; // CCSRBAR
55 bus-frequency = <0>; 47 bus-frequency = <0>;
56 48
@@ -189,215 +181,225 @@
189 fsl,has-rstcr; 181 fsl,has-rstcr;
190 }; 182 };
191 183
192 pci@8000 { 184 mpic: pic@40000 {
185 clock-frequency = <0>;
186 interrupt-controller;
187 #address-cells = <0>;
188 #interrupt-cells = <2>;
189 reg = <40000 40000>;
190 compatible = "chrp,open-pic";
191 device_type = "open-pic";
192 big-endian;
193 };
194 };
195
196 pci@e0008000 {
197 interrupt-map-mask = <f800 0 0 7>;
198 interrupt-map = <
199 /* IDSEL 0x4 (PCIX Slot 2) */
200 02000 0 0 1 &mpic 0 1
201 02000 0 0 2 &mpic 1 1
202 02000 0 0 3 &mpic 2 1
203 02000 0 0 4 &mpic 3 1
204
205 /* IDSEL 0x5 (PCIX Slot 3) */
206 02800 0 0 1 &mpic 1 1
207 02800 0 0 2 &mpic 2 1
208 02800 0 0 3 &mpic 3 1
209 02800 0 0 4 &mpic 0 1
210
211 /* IDSEL 0x6 (PCIX Slot 4) */
212 03000 0 0 1 &mpic 2 1
213 03000 0 0 2 &mpic 3 1
214 03000 0 0 3 &mpic 0 1
215 03000 0 0 4 &mpic 1 1
216
217 /* IDSEL 0x8 (PCIX Slot 5) */
218 04000 0 0 1 &mpic 0 1
219 04000 0 0 2 &mpic 1 1
220 04000 0 0 3 &mpic 2 1
221 04000 0 0 4 &mpic 3 1
222
223 /* IDSEL 0xC (Tsi310 bridge) */
224 06000 0 0 1 &mpic 0 1
225 06000 0 0 2 &mpic 1 1
226 06000 0 0 3 &mpic 2 1
227 06000 0 0 4 &mpic 3 1
228
229 /* IDSEL 0x14 (Slot 2) */
230 0a000 0 0 1 &mpic 0 1
231 0a000 0 0 2 &mpic 1 1
232 0a000 0 0 3 &mpic 2 1
233 0a000 0 0 4 &mpic 3 1
234
235 /* IDSEL 0x15 (Slot 3) */
236 0a800 0 0 1 &mpic 1 1
237 0a800 0 0 2 &mpic 2 1
238 0a800 0 0 3 &mpic 3 1
239 0a800 0 0 4 &mpic 0 1
240
241 /* IDSEL 0x16 (Slot 4) */
242 0b000 0 0 1 &mpic 2 1
243 0b000 0 0 2 &mpic 3 1
244 0b000 0 0 3 &mpic 0 1
245 0b000 0 0 4 &mpic 1 1
246
247 /* IDSEL 0x18 (Slot 5) */
248 0c000 0 0 1 &mpic 0 1
249 0c000 0 0 2 &mpic 1 1
250 0c000 0 0 3 &mpic 2 1
251 0c000 0 0 4 &mpic 3 1
252
253 /* IDSEL 0x1C (Tsi310 bridge PCI primary) */
254 0E000 0 0 1 &mpic 0 1
255 0E000 0 0 2 &mpic 1 1
256 0E000 0 0 3 &mpic 2 1
257 0E000 0 0 4 &mpic 3 1>;
258
259 interrupt-parent = <&mpic>;
260 interrupts = <18 2>;
261 bus-range = <0 0>;
262 ranges = <02000000 0 80000000 80000000 0 10000000
263 01000000 0 00000000 e2000000 0 00800000>;
264 clock-frequency = <3f940aa>;
265 #interrupt-cells = <1>;
266 #size-cells = <2>;
267 #address-cells = <3>;
268 reg = <e0008000 1000>;
269 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
270 device_type = "pci";
271
272 pci_bridge@1c {
193 interrupt-map-mask = <f800 0 0 7>; 273 interrupt-map-mask = <f800 0 0 7>;
194 interrupt-map = < 274 interrupt-map = <
195 /* IDSEL 0x4 (PCIX Slot 2) */
196 02000 0 0 1 &mpic 0 1
197 02000 0 0 2 &mpic 1 1
198 02000 0 0 3 &mpic 2 1
199 02000 0 0 4 &mpic 3 1
200
201 /* IDSEL 0x5 (PCIX Slot 3) */
202 02800 0 0 1 &mpic 1 1
203 02800 0 0 2 &mpic 2 1
204 02800 0 0 3 &mpic 3 1
205 02800 0 0 4 &mpic 0 1
206
207 /* IDSEL 0x6 (PCIX Slot 4) */
208 03000 0 0 1 &mpic 2 1
209 03000 0 0 2 &mpic 3 1
210 03000 0 0 3 &mpic 0 1
211 03000 0 0 4 &mpic 1 1
212
213 /* IDSEL 0x8 (PCIX Slot 5) */
214 04000 0 0 1 &mpic 0 1
215 04000 0 0 2 &mpic 1 1
216 04000 0 0 3 &mpic 2 1
217 04000 0 0 4 &mpic 3 1
218
219 /* IDSEL 0xC (Tsi310 bridge) */
220 06000 0 0 1 &mpic 0 1
221 06000 0 0 2 &mpic 1 1
222 06000 0 0 3 &mpic 2 1
223 06000 0 0 4 &mpic 3 1
224
225 /* IDSEL 0x14 (Slot 2) */
226 0a000 0 0 1 &mpic 0 1
227 0a000 0 0 2 &mpic 1 1
228 0a000 0 0 3 &mpic 2 1
229 0a000 0 0 4 &mpic 3 1
230
231 /* IDSEL 0x15 (Slot 3) */
232 0a800 0 0 1 &mpic 1 1
233 0a800 0 0 2 &mpic 2 1
234 0a800 0 0 3 &mpic 3 1
235 0a800 0 0 4 &mpic 0 1
236
237 /* IDSEL 0x16 (Slot 4) */
238 0b000 0 0 1 &mpic 2 1
239 0b000 0 0 2 &mpic 3 1
240 0b000 0 0 3 &mpic 0 1
241 0b000 0 0 4 &mpic 1 1
242
243 /* IDSEL 0x18 (Slot 5) */
244 0c000 0 0 1 &mpic 0 1
245 0c000 0 0 2 &mpic 1 1
246 0c000 0 0 3 &mpic 2 1
247 0c000 0 0 4 &mpic 3 1
248
249 /* IDSEL 0x1C (Tsi310 bridge PCI primary) */
250 0E000 0 0 1 &mpic 0 1
251 0E000 0 0 2 &mpic 1 1
252 0E000 0 0 3 &mpic 2 1
253 0E000 0 0 4 &mpic 3 1>;
254 275
255 interrupt-parent = <&mpic>; 276 /* IDSEL 0x00 (PrPMC Site) */
256 interrupts = <18 2>; 277 0000 0 0 1 &mpic 0 1
257 bus-range = <0 0>; 278 0000 0 0 2 &mpic 1 1
258 ranges = <02000000 0 80000000 80000000 0 10000000 279 0000 0 0 3 &mpic 2 1
259 01000000 0 00000000 e2000000 0 00800000>; 280 0000 0 0 4 &mpic 3 1
260 clock-frequency = <3f940aa>; 281
282 /* IDSEL 0x04 (VIA chip) */
283 2000 0 0 1 &mpic 0 1
284 2000 0 0 2 &mpic 1 1
285 2000 0 0 3 &mpic 2 1
286 2000 0 0 4 &mpic 3 1
287
288 /* IDSEL 0x05 (8139) */
289 2800 0 0 1 &mpic 1 1
290
291 /* IDSEL 0x06 (Slot 6) */
292 3000 0 0 1 &mpic 2 1
293 3000 0 0 2 &mpic 3 1
294 3000 0 0 3 &mpic 0 1
295 3000 0 0 4 &mpic 1 1
296
297 /* IDESL 0x07 (Slot 7) */
298 3800 0 0 1 &mpic 3 1
299 3800 0 0 2 &mpic 0 1
300 3800 0 0 3 &mpic 1 1
301 3800 0 0 4 &mpic 2 1>;
302
303 reg = <e000 0 0 0 0>;
261 #interrupt-cells = <1>; 304 #interrupt-cells = <1>;
262 #size-cells = <2>; 305 #size-cells = <2>;
263 #address-cells = <3>; 306 #address-cells = <3>;
264 reg = <8000 1000>; 307 ranges = <02000000 0 80000000
265 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; 308 02000000 0 80000000
266 device_type = "pci"; 309 0 20000000
310 01000000 0 00000000
311 01000000 0 00000000
312 0 00080000>;
313 clock-frequency = <1fca055>;
267 314
268 pci_bridge@1c { 315 isa@4 {
269 interrupt-map-mask = <f800 0 0 7>; 316 device_type = "isa";
270 interrupt-map = < 317 #interrupt-cells = <2>;
271 318 #size-cells = <1>;
272 /* IDSEL 0x00 (PrPMC Site) */ 319 #address-cells = <2>;
273 0000 0 0 1 &mpic 0 1 320 reg = <2000 0 0 0 0>;
274 0000 0 0 2 &mpic 1 1 321 ranges = <1 0 01000000 0 0 00001000>;
275 0000 0 0 3 &mpic 2 1 322 interrupt-parent = <&i8259>;
276 0000 0 0 4 &mpic 3 1 323
277 324 i8259: interrupt-controller@20 {
278 /* IDSEL 0x04 (VIA chip) */ 325 interrupt-controller;
279 2000 0 0 1 &mpic 0 1 326 device_type = "interrupt-controller";
280 2000 0 0 2 &mpic 1 1 327 reg = <1 20 2
281 2000 0 0 3 &mpic 2 1 328 1 a0 2
282 2000 0 0 4 &mpic 3 1 329 1 4d0 2>;
283 330 #address-cells = <0>;
284 /* IDSEL 0x05 (8139) */
285 2800 0 0 1 &mpic 1 1
286
287 /* IDSEL 0x06 (Slot 6) */
288 3000 0 0 1 &mpic 2 1
289 3000 0 0 2 &mpic 3 1
290 3000 0 0 3 &mpic 0 1
291 3000 0 0 4 &mpic 1 1
292
293 /* IDESL 0x07 (Slot 7) */
294 3800 0 0 1 &mpic 3 1
295 3800 0 0 2 &mpic 0 1
296 3800 0 0 3 &mpic 1 1
297 3800 0 0 4 &mpic 2 1>;
298
299 reg = <e000 0 0 0 0>;
300 #interrupt-cells = <1>;
301 #size-cells = <2>;
302 #address-cells = <3>;
303 ranges = <02000000 0 80000000
304 02000000 0 80000000
305 0 20000000
306 01000000 0 00000000
307 01000000 0 00000000
308 0 00080000>;
309 clock-frequency = <1fca055>;
310
311 isa@4 {
312 device_type = "isa";
313 #interrupt-cells = <2>; 331 #interrupt-cells = <2>;
314 #size-cells = <1>; 332 compatible = "chrp,iic";
315 #address-cells = <2>; 333 interrupts = <0 1>;
316 reg = <2000 0 0 0 0>; 334 interrupt-parent = <&mpic>;
317 ranges = <1 0 01000000 0 0 00001000>;
318 interrupt-parent = <&i8259>;
319
320 i8259: interrupt-controller@20 {
321 clock-frequency = <0>;
322 interrupt-controller;
323 device_type = "interrupt-controller";
324 reg = <1 20 2
325 1 a0 2
326 1 4d0 2>;
327 #address-cells = <0>;
328 #interrupt-cells = <2>;
329 built-in;
330 compatible = "chrp,iic";
331 interrupts = <0 1>;
332 interrupt-parent = <&mpic>;
333 };
334
335 rtc@70 {
336 compatible = "pnpPNP,b00";
337 reg = <1 70 2>;
338 };
339 }; 335 };
340 };
341 };
342 336
343 pci@9000 { 337 rtc@70 {
344 interrupt-map-mask = <f800 0 0 7>; 338 compatible = "pnpPNP,b00";
345 interrupt-map = < 339 reg = <1 70 2>;
346 340 };
347 /* IDSEL 0x15 */ 341 };
348 a800 0 0 1 &mpic b 1
349 a800 0 0 2 &mpic 1 1
350 a800 0 0 3 &mpic 2 1
351 a800 0 0 4 &mpic 3 1>;
352
353 interrupt-parent = <&mpic>;
354 interrupts = <19 2>;
355 bus-range = <0 0>;
356 ranges = <02000000 0 90000000 90000000 0 10000000
357 01000000 0 00000000 e2800000 0 00800000>;
358 clock-frequency = <3f940aa>;
359 #interrupt-cells = <1>;
360 #size-cells = <2>;
361 #address-cells = <3>;
362 reg = <9000 1000>;
363 compatible = "fsl,mpc8540-pci";
364 device_type = "pci";
365 }; 342 };
366 /* PCI Express */ 343 };
367 pcie@a000 {
368 interrupt-map-mask = <f800 0 0 7>;
369 interrupt-map = <
370 344
371 /* IDSEL 0x0 (PEX) */ 345 pci@e0009000 {
372 00000 0 0 1 &mpic 0 1 346 interrupt-map-mask = <f800 0 0 7>;
373 00000 0 0 2 &mpic 1 1 347 interrupt-map = <
374 00000 0 0 3 &mpic 2 1 348
375 00000 0 0 4 &mpic 3 1>; 349 /* IDSEL 0x15 */
350 a800 0 0 1 &mpic b 1
351 a800 0 0 2 &mpic 1 1
352 a800 0 0 3 &mpic 2 1
353 a800 0 0 4 &mpic 3 1>;
354
355 interrupt-parent = <&mpic>;
356 interrupts = <19 2>;
357 bus-range = <0 0>;
358 ranges = <02000000 0 90000000 90000000 0 10000000
359 01000000 0 00000000 e2800000 0 00800000>;
360 clock-frequency = <3f940aa>;
361 #interrupt-cells = <1>;
362 #size-cells = <2>;
363 #address-cells = <3>;
364 reg = <e0009000 1000>;
365 compatible = "fsl,mpc8540-pci";
366 device_type = "pci";
367 };
376 368
377 interrupt-parent = <&mpic>; 369 pcie@e000a000 {
378 interrupts = <1a 2>; 370 interrupt-map-mask = <f800 0 0 7>;
379 bus-range = <0 ff>; 371 interrupt-map = <
380 ranges = <02000000 0 a0000000 a0000000 0 20000000 372
381 01000000 0 00000000 e3000000 0 08000000>; 373 /* IDSEL 0x0 (PEX) */
382 clock-frequency = <1fca055>; 374 00000 0 0 1 &mpic 0 1
383 #interrupt-cells = <1>; 375 00000 0 0 2 &mpic 1 1
376 00000 0 0 3 &mpic 2 1
377 00000 0 0 4 &mpic 3 1>;
378
379 interrupt-parent = <&mpic>;
380 interrupts = <1a 2>;
381 bus-range = <0 ff>;
382 ranges = <02000000 0 a0000000 a0000000 0 20000000
383 01000000 0 00000000 e3000000 0 08000000>;
384 clock-frequency = <1fca055>;
385 #interrupt-cells = <1>;
386 #size-cells = <2>;
387 #address-cells = <3>;
388 reg = <e000a000 1000>;
389 compatible = "fsl,mpc8548-pcie";
390 device_type = "pci";
391 pcie@0 {
392 reg = <0 0 0 0 0>;
384 #size-cells = <2>; 393 #size-cells = <2>;
385 #address-cells = <3>; 394 #address-cells = <3>;
386 reg = <a000 1000>;
387 compatible = "fsl,mpc8548-pcie";
388 device_type = "pci"; 395 device_type = "pci";
389 }; 396 ranges = <02000000 0 a0000000
397 02000000 0 a0000000
398 0 20000000
390 399
391 mpic: pic@40000 { 400 01000000 0 00000000
392 clock-frequency = <0>; 401 01000000 0 00000000
393 interrupt-controller; 402 0 08000000>;
394 #address-cells = <0>;
395 #interrupt-cells = <2>;
396 reg = <40000 40000>;
397 built-in;
398 compatible = "chrp,open-pic";
399 device_type = "open-pic";
400 big-endian;
401 }; 403 };
402 }; 404 };
403}; 405};
diff --git a/arch/powerpc/boot/dts/mpc8555cds.dts b/arch/powerpc/boot/dts/mpc8555cds.dts
index c3c888252121..57029cca32b2 100644
--- a/arch/powerpc/boot/dts/mpc8555cds.dts
+++ b/arch/powerpc/boot/dts/mpc8555cds.dts
@@ -30,7 +30,6 @@
30 timebase-frequency = <0>; // 33 MHz, from uboot 30 timebase-frequency = <0>; // 33 MHz, from uboot
31 bus-frequency = <0>; // 166 MHz 31 bus-frequency = <0>; // 166 MHz
32 clock-frequency = <0>; // 825 MHz, from uboot 32 clock-frequency = <0>; // 825 MHz, from uboot
33 32-bit;
34 }; 33 };
35 }; 34 };
36 35
@@ -42,10 +41,9 @@
42 soc8555@e0000000 { 41 soc8555@e0000000 {
43 #address-cells = <1>; 42 #address-cells = <1>;
44 #size-cells = <1>; 43 #size-cells = <1>;
45 #interrupt-cells = <2>;
46 device_type = "soc"; 44 device_type = "soc";
47 ranges = <0 e0000000 00100000>; 45 ranges = <0 e0000000 00100000>;
48 reg = <e0000000 00100000>; // CCSRBAR 1M 46 reg = <e0000000 00001000>; // CCSRBAR 1M
49 bus-frequency = <0>; 47 bus-frequency = <0>;
50 48
51 memory-controller@2000 { 49 memory-controller@2000 {
@@ -137,113 +135,145 @@
137 interrupt-parent = <&mpic>; 135 interrupt-parent = <&mpic>;
138 }; 136 };
139 137
140 pci1: pci@8000 { 138 mpic: pic@40000 {
141 interrupt-map-mask = <1f800 0 0 7>; 139 clock-frequency = <0>;
142 interrupt-map = < 140 interrupt-controller;
143 141 #address-cells = <0>;
144 /* IDSEL 0x10 */ 142 #interrupt-cells = <2>;
145 08000 0 0 1 &mpic 0 1 143 reg = <40000 40000>;
146 08000 0 0 2 &mpic 1 1 144 compatible = "chrp,open-pic";
147 08000 0 0 3 &mpic 2 1 145 device_type = "open-pic";
148 08000 0 0 4 &mpic 3 1 146 big-endian;
149 147 };
150 /* IDSEL 0x11 */ 148
151 08800 0 0 1 &mpic 0 1 149 cpm@919c0 {
152 08800 0 0 2 &mpic 1 1 150 #address-cells = <1>;
153 08800 0 0 3 &mpic 2 1 151 #size-cells = <1>;
154 08800 0 0 4 &mpic 3 1 152 compatible = "fsl,mpc8555-cpm", "fsl,cpm2";
155 153 reg = <919c0 30>;
156 /* IDSEL 0x12 (Slot 1) */ 154 ranges;
157 09000 0 0 1 &mpic 0 1 155
158 09000 0 0 2 &mpic 1 1 156 muram@80000 {
159 09000 0 0 3 &mpic 2 1 157 #address-cells = <1>;
160 09000 0 0 4 &mpic 3 1 158 #size-cells = <1>;
161 159 ranges = <0 80000 10000>;
162 /* IDSEL 0x13 (Slot 2) */ 160
163 09800 0 0 1 &mpic 1 1 161 data@0 {
164 09800 0 0 2 &mpic 2 1 162 compatible = "fsl,cpm-muram-data";
165 09800 0 0 3 &mpic 3 1 163 reg = <0 2000 9000 1000>;
166 09800 0 0 4 &mpic 0 1 164 };
167 165 };
168 /* IDSEL 0x14 (Slot 3) */ 166
169 0a000 0 0 1 &mpic 2 1 167 brg@919f0 {
170 0a000 0 0 2 &mpic 3 1 168 compatible = "fsl,mpc8555-brg",
171 0a000 0 0 3 &mpic 0 1 169 "fsl,cpm2-brg",
172 0a000 0 0 4 &mpic 1 1 170 "fsl,cpm-brg";
173 171 reg = <919f0 10 915f0 10>;
174 /* IDSEL 0x15 (Slot 4) */ 172 };
175 0a800 0 0 1 &mpic 3 1 173
176 0a800 0 0 2 &mpic 0 1 174 cpmpic: pic@90c00 {
177 0a800 0 0 3 &mpic 1 1
178 0a800 0 0 4 &mpic 2 1
179
180 /* Bus 1 (Tundra Bridge) */
181 /* IDSEL 0x12 (ISA bridge) */
182 19000 0 0 1 &mpic 0 1
183 19000 0 0 2 &mpic 1 1
184 19000 0 0 3 &mpic 2 1
185 19000 0 0 4 &mpic 3 1>;
186 interrupt-parent = <&mpic>;
187 interrupts = <18 2>;
188 bus-range = <0 0>;
189 ranges = <02000000 0 80000000 80000000 0 20000000
190 01000000 0 00000000 e2000000 0 00100000>;
191 clock-frequency = <3f940aa>;
192 #interrupt-cells = <1>;
193 #size-cells = <2>;
194 #address-cells = <3>;
195 reg = <8000 1000>;
196 compatible = "fsl,mpc8540-pci";
197 device_type = "pci";
198
199 i8259@19000 {
200 clock-frequency = <0>;
201 interrupt-controller; 175 interrupt-controller;
202 device_type = "interrupt-controller";
203 reg = <19000 0 0 0 1>;
204 #address-cells = <0>; 176 #address-cells = <0>;
205 #interrupt-cells = <2>; 177 #interrupt-cells = <2>;
206 built-in; 178 interrupts = <2e 2>;
207 compatible = "chrp,iic"; 179 interrupt-parent = <&mpic>;
208 big-endian; 180 reg = <90c00 80>;
209 interrupts = <1>; 181 compatible = "fsl,mpc8555-cpm-pic", "fsl,cpm2-pic";
210 interrupt-parent = <&pci1>;
211 }; 182 };
212 }; 183 };
184 };
213 185
214 pci@9000 { 186 pci1: pci@e0008000 {
215 interrupt-map-mask = <f800 0 0 7>; 187 interrupt-map-mask = <1f800 0 0 7>;
216 interrupt-map = < 188 interrupt-map = <
217 189
218 /* IDSEL 0x15 */ 190 /* IDSEL 0x10 */
219 a800 0 0 1 &mpic b 1 191 08000 0 0 1 &mpic 0 1
220 a800 0 0 2 &mpic b 1 192 08000 0 0 2 &mpic 1 1
221 a800 0 0 3 &mpic b 1 193 08000 0 0 3 &mpic 2 1
222 a800 0 0 4 &mpic b 1>; 194 08000 0 0 4 &mpic 3 1
223 interrupt-parent = <&mpic>;
224 interrupts = <19 2>;
225 bus-range = <0 0>;
226 ranges = <02000000 0 a0000000 a0000000 0 20000000
227 01000000 0 00000000 e3000000 0 00100000>;
228 clock-frequency = <3f940aa>;
229 #interrupt-cells = <1>;
230 #size-cells = <2>;
231 #address-cells = <3>;
232 reg = <9000 1000>;
233 compatible = "fsl,mpc8540-pci";
234 device_type = "pci";
235 };
236 195
237 mpic: pic@40000 { 196 /* IDSEL 0x11 */
238 clock-frequency = <0>; 197 08800 0 0 1 &mpic 0 1
198 08800 0 0 2 &mpic 1 1
199 08800 0 0 3 &mpic 2 1
200 08800 0 0 4 &mpic 3 1
201
202 /* IDSEL 0x12 (Slot 1) */
203 09000 0 0 1 &mpic 0 1
204 09000 0 0 2 &mpic 1 1
205 09000 0 0 3 &mpic 2 1
206 09000 0 0 4 &mpic 3 1
207
208 /* IDSEL 0x13 (Slot 2) */
209 09800 0 0 1 &mpic 1 1
210 09800 0 0 2 &mpic 2 1
211 09800 0 0 3 &mpic 3 1
212 09800 0 0 4 &mpic 0 1
213
214 /* IDSEL 0x14 (Slot 3) */
215 0a000 0 0 1 &mpic 2 1
216 0a000 0 0 2 &mpic 3 1
217 0a000 0 0 3 &mpic 0 1
218 0a000 0 0 4 &mpic 1 1
219
220 /* IDSEL 0x15 (Slot 4) */
221 0a800 0 0 1 &mpic 3 1
222 0a800 0 0 2 &mpic 0 1
223 0a800 0 0 3 &mpic 1 1
224 0a800 0 0 4 &mpic 2 1
225
226 /* Bus 1 (Tundra Bridge) */
227 /* IDSEL 0x12 (ISA bridge) */
228 19000 0 0 1 &mpic 0 1
229 19000 0 0 2 &mpic 1 1
230 19000 0 0 3 &mpic 2 1
231 19000 0 0 4 &mpic 3 1>;
232 interrupt-parent = <&mpic>;
233 interrupts = <18 2>;
234 bus-range = <0 0>;
235 ranges = <02000000 0 80000000 80000000 0 20000000
236 01000000 0 00000000 e2000000 0 00100000>;
237 clock-frequency = <3f940aa>;
238 #interrupt-cells = <1>;
239 #size-cells = <2>;
240 #address-cells = <3>;
241 reg = <e0008000 1000>;
242 compatible = "fsl,mpc8540-pci";
243 device_type = "pci";
244
245 i8259@19000 {
239 interrupt-controller; 246 interrupt-controller;
247 device_type = "interrupt-controller";
248 reg = <19000 0 0 0 1>;
240 #address-cells = <0>; 249 #address-cells = <0>;
241 #interrupt-cells = <2>; 250 #interrupt-cells = <2>;
242 reg = <40000 40000>; 251 compatible = "chrp,iic";
243 built-in; 252 interrupts = <1>;
244 compatible = "chrp,open-pic"; 253 interrupt-parent = <&pci1>;
245 device_type = "open-pic";
246 big-endian;
247 }; 254 };
248 }; 255 };
256
257 pci@e0009000 {
258 interrupt-map-mask = <f800 0 0 7>;
259 interrupt-map = <
260
261 /* IDSEL 0x15 */
262 a800 0 0 1 &mpic b 1
263 a800 0 0 2 &mpic b 1
264 a800 0 0 3 &mpic b 1
265 a800 0 0 4 &mpic b 1>;
266 interrupt-parent = <&mpic>;
267 interrupts = <19 2>;
268 bus-range = <0 0>;
269 ranges = <02000000 0 a0000000 a0000000 0 20000000
270 01000000 0 00000000 e3000000 0 00100000>;
271 clock-frequency = <3f940aa>;
272 #interrupt-cells = <1>;
273 #size-cells = <2>;
274 #address-cells = <3>;
275 reg = <e0009000 1000>;
276 compatible = "fsl,mpc8540-pci";
277 device_type = "pci";
278 };
249}; 279};
diff --git a/arch/powerpc/boot/dts/mpc8560ads.dts b/arch/powerpc/boot/dts/mpc8560ads.dts
index 16dbe848cecf..6b362f8222c1 100644
--- a/arch/powerpc/boot/dts/mpc8560ads.dts
+++ b/arch/powerpc/boot/dts/mpc8560ads.dts
@@ -30,7 +30,6 @@
30 timebase-frequency = <04ead9a0>; 30 timebase-frequency = <04ead9a0>;
31 bus-frequency = <13ab6680>; 31 bus-frequency = <13ab6680>;
32 clock-frequency = <312c8040>; 32 clock-frequency = <312c8040>;
33 32-bit;
34 }; 33 };
35 }; 34 };
36 35
@@ -42,7 +41,6 @@
42 soc8560@e0000000 { 41 soc8560@e0000000 {
43 #address-cells = <1>; 42 #address-cells = <1>;
44 #size-cells = <1>; 43 #size-cells = <1>;
45 #interrupt-cells = <2>;
46 device_type = "soc"; 44 device_type = "soc";
47 ranges = <0 e0000000 00100000>; 45 ranges = <0 e0000000 00100000>;
48 reg = <e0000000 00000200>; 46 reg = <e0000000 00000200>;
@@ -132,115 +130,39 @@
132 phy-handle = <&phy1>; 130 phy-handle = <&phy1>;
133 }; 131 };
134 132
135 pci@8000 {
136 #interrupt-cells = <1>;
137 #size-cells = <2>;
138 #address-cells = <3>;
139 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
140 device_type = "pci";
141 reg = <8000 1000>;
142 clock-frequency = <3f940aa>;
143 interrupt-map-mask = <f800 0 0 7>;
144 interrupt-map = <
145
146 /* IDSEL 0x2 */
147 1000 0 0 1 &mpic 1 1
148 1000 0 0 2 &mpic 2 1
149 1000 0 0 3 &mpic 3 1
150 1000 0 0 4 &mpic 4 1
151
152 /* IDSEL 0x3 */
153 1800 0 0 1 &mpic 4 1
154 1800 0 0 2 &mpic 1 1
155 1800 0 0 3 &mpic 2 1
156 1800 0 0 4 &mpic 3 1
157
158 /* IDSEL 0x4 */
159 2000 0 0 1 &mpic 3 1
160 2000 0 0 2 &mpic 4 1
161 2000 0 0 3 &mpic 1 1
162 2000 0 0 4 &mpic 2 1
163
164 /* IDSEL 0x5 */
165 2800 0 0 1 &mpic 2 1
166 2800 0 0 2 &mpic 3 1
167 2800 0 0 3 &mpic 4 1
168 2800 0 0 4 &mpic 1 1
169
170 /* IDSEL 12 */
171 6000 0 0 1 &mpic 1 1
172 6000 0 0 2 &mpic 2 1
173 6000 0 0 3 &mpic 3 1
174 6000 0 0 4 &mpic 4 1
175
176 /* IDSEL 13 */
177 6800 0 0 1 &mpic 4 1
178 6800 0 0 2 &mpic 1 1
179 6800 0 0 3 &mpic 2 1
180 6800 0 0 4 &mpic 3 1
181
182 /* IDSEL 14*/
183 7000 0 0 1 &mpic 3 1
184 7000 0 0 2 &mpic 4 1
185 7000 0 0 3 &mpic 1 1
186 7000 0 0 4 &mpic 2 1
187
188 /* IDSEL 15 */
189 7800 0 0 1 &mpic 2 1
190 7800 0 0 2 &mpic 3 1
191 7800 0 0 3 &mpic 4 1
192 7800 0 0 4 &mpic 1 1
193
194 /* IDSEL 18 */
195 9000 0 0 1 &mpic 1 1
196 9000 0 0 2 &mpic 2 1
197 9000 0 0 3 &mpic 3 1
198 9000 0 0 4 &mpic 4 1
199
200 /* IDSEL 19 */
201 9800 0 0 1 &mpic 4 1
202 9800 0 0 2 &mpic 1 1
203 9800 0 0 3 &mpic 2 1
204 9800 0 0 4 &mpic 3 1
205
206 /* IDSEL 20 */
207 a000 0 0 1 &mpic 3 1
208 a000 0 0 2 &mpic 4 1
209 a000 0 0 3 &mpic 1 1
210 a000 0 0 4 &mpic 2 1
211
212 /* IDSEL 21 */
213 a800 0 0 1 &mpic 2 1
214 a800 0 0 2 &mpic 3 1
215 a800 0 0 3 &mpic 4 1
216 a800 0 0 4 &mpic 1 1>;
217
218 interrupt-parent = <&mpic>;
219 interrupts = <18 2>;
220 bus-range = <0 0>;
221 ranges = <02000000 0 80000000 80000000 0 20000000
222 01000000 0 00000000 e2000000 0 01000000>;
223 };
224
225 mpic: pic@40000 { 133 mpic: pic@40000 {
226 interrupt-controller; 134 interrupt-controller;
227 #address-cells = <0>; 135 #address-cells = <0>;
228 #interrupt-cells = <2>; 136 #interrupt-cells = <2>;
229 reg = <40000 40000>; 137 reg = <40000 40000>;
230 built-in;
231 device_type = "open-pic"; 138 device_type = "open-pic";
232 }; 139 };
233 140
234 cpm@e0000000 { 141 cpm@919c0 {
235 #address-cells = <1>; 142 #address-cells = <1>;
236 #size-cells = <1>; 143 #size-cells = <1>;
237 #interrupt-cells = <2>; 144 compatible = "fsl,mpc8560-cpm", "fsl,cpm2";
238 device_type = "cpm"; 145 reg = <919c0 30>;
239 model = "CPM2"; 146 ranges;
240 ranges = <0 0 c0000>; 147
241 reg = <80000 40000>; 148 muram@80000 {
242 command-proc = <919c0>; 149 #address-cells = <1>;
243 brg-frequency = <9d5b340>; 150 #size-cells = <1>;
151 ranges = <0 80000 10000>;
152
153 data@0 {
154 compatible = "fsl,cpm-muram-data";
155 reg = <0 4000 9000 2000>;
156 };
157 };
158
159 brg@919f0 {
160 compatible = "fsl,mpc8560-brg",
161 "fsl,cpm2-brg",
162 "fsl,cpm-brg";
163 reg = <919f0 10 915f0 10>;
164 clock-frequency = <d#165000000>;
165 };
244 166
245 cpmpic: pic@90c00 { 167 cpmpic: pic@90c00 {
246 interrupt-controller; 168 interrupt-controller;
@@ -249,44 +171,38 @@
249 interrupts = <2e 2>; 171 interrupts = <2e 2>;
250 interrupt-parent = <&mpic>; 172 interrupt-parent = <&mpic>;
251 reg = <90c00 80>; 173 reg = <90c00 80>;
252 built-in; 174 compatible = "fsl,mpc8560-cpm-pic", "fsl,cpm2-pic";
253 device_type = "cpm-pic";
254 }; 175 };
255 176
256 scc@91a00 { 177 serial@91a00 {
257 device_type = "serial"; 178 device_type = "serial";
258 compatible = "cpm_uart"; 179 compatible = "fsl,mpc8560-scc-uart",
259 model = "SCC"; 180 "fsl,cpm2-scc-uart";
260 device-id = <1>;
261 reg = <91a00 20 88000 100>; 181 reg = <91a00 20 88000 100>;
262 clock-setup = <00ffffff 0>; 182 fsl,cpm-brg = <1>;
263 rx-clock = <1>; 183 fsl,cpm-command = <00800000>;
264 tx-clock = <1>;
265 current-speed = <1c200>; 184 current-speed = <1c200>;
266 interrupts = <28 8>; 185 interrupts = <28 8>;
267 interrupt-parent = <&cpmpic>; 186 interrupt-parent = <&cpmpic>;
268 }; 187 };
269 188
270 scc@91a20 { 189 serial@91a20 {
271 device_type = "serial"; 190 device_type = "serial";
272 compatible = "cpm_uart"; 191 compatible = "fsl,mpc8560-scc-uart",
273 model = "SCC"; 192 "fsl,cpm2-scc-uart";
274 device-id = <2>;
275 reg = <91a20 20 88100 100>; 193 reg = <91a20 20 88100 100>;
276 clock-setup = <ff00ffff 90000>; 194 fsl,cpm-brg = <2>;
277 rx-clock = <2>; 195 fsl,cpm-command = <04a00000>;
278 tx-clock = <2>;
279 current-speed = <1c200>; 196 current-speed = <1c200>;
280 interrupts = <29 8>; 197 interrupts = <29 8>;
281 interrupt-parent = <&cpmpic>; 198 interrupt-parent = <&cpmpic>;
282 }; 199 };
283 200
284 fcc@91320 { 201 ethernet@91320 {
285 device_type = "network"; 202 device_type = "network";
286 compatible = "fs_enet"; 203 compatible = "fsl,mpc8560-fcc-enet",
287 model = "FCC"; 204 "fsl,cpm2-fcc-enet";
288 device-id = <2>; 205 reg = <91320 20 88500 100 913b0 1>;
289 reg = <91320 20 88500 100 913a0 30>;
290 /* 206 /*
291 * mac-address is deprecated and will be removed 207 * mac-address is deprecated and will be removed
292 * in 2.6.25. Only recent versions of 208 * in 2.6.25. Only recent versions of
@@ -294,20 +210,17 @@
294 */ 210 */
295 mac-address = [ 00 00 00 00 00 00 ]; 211 mac-address = [ 00 00 00 00 00 00 ];
296 local-mac-address = [ 00 00 00 00 00 00 ]; 212 local-mac-address = [ 00 00 00 00 00 00 ];
297 clock-setup = <ff00ffff 250000>; 213 fsl,cpm-command = <16200300>;
298 rx-clock = <15>;
299 tx-clock = <16>;
300 interrupts = <21 8>; 214 interrupts = <21 8>;
301 interrupt-parent = <&cpmpic>; 215 interrupt-parent = <&cpmpic>;
302 phy-handle = <&phy2>; 216 phy-handle = <&phy2>;
303 }; 217 };
304 218
305 fcc@91340 { 219 ethernet@91340 {
306 device_type = "network"; 220 device_type = "network";
307 compatible = "fs_enet"; 221 compatible = "fsl,mpc8560-fcc-enet",
308 model = "FCC"; 222 "fsl,cpm2-fcc-enet";
309 device-id = <3>; 223 reg = <91340 20 88600 100 913d0 1>;
310 reg = <91340 20 88600 100 913d0 30>;
311 /* 224 /*
312 * mac-address is deprecated and will be removed 225 * mac-address is deprecated and will be removed
313 * in 2.6.25. Only recent versions of 226 * in 2.6.25. Only recent versions of
@@ -315,13 +228,101 @@
315 */ 228 */
316 mac-address = [ 00 00 00 00 00 00 ]; 229 mac-address = [ 00 00 00 00 00 00 ];
317 local-mac-address = [ 00 00 00 00 00 00 ]; 230 local-mac-address = [ 00 00 00 00 00 00 ];
318 clock-setup = <ffff00ff 3700>; 231 fsl,cpm-command = <1a400300>;
319 rx-clock = <17>;
320 tx-clock = <18>;
321 interrupts = <22 8>; 232 interrupts = <22 8>;
322 interrupt-parent = <&cpmpic>; 233 interrupt-parent = <&cpmpic>;
323 phy-handle = <&phy3>; 234 phy-handle = <&phy3>;
324 }; 235 };
325 }; 236 };
326 }; 237 };
238
239 pci@e0008000 {
240 #interrupt-cells = <1>;
241 #size-cells = <2>;
242 #address-cells = <3>;
243 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
244 device_type = "pci";
245 reg = <e0008000 1000>;
246 clock-frequency = <3f940aa>;
247 interrupt-map-mask = <f800 0 0 7>;
248 interrupt-map = <
249
250 /* IDSEL 0x2 */
251 1000 0 0 1 &mpic 1 1
252 1000 0 0 2 &mpic 2 1
253 1000 0 0 3 &mpic 3 1
254 1000 0 0 4 &mpic 4 1
255
256 /* IDSEL 0x3 */
257 1800 0 0 1 &mpic 4 1
258 1800 0 0 2 &mpic 1 1
259 1800 0 0 3 &mpic 2 1
260 1800 0 0 4 &mpic 3 1
261
262 /* IDSEL 0x4 */
263 2000 0 0 1 &mpic 3 1
264 2000 0 0 2 &mpic 4 1
265 2000 0 0 3 &mpic 1 1
266 2000 0 0 4 &mpic 2 1
267
268 /* IDSEL 0x5 */
269 2800 0 0 1 &mpic 2 1
270 2800 0 0 2 &mpic 3 1
271 2800 0 0 3 &mpic 4 1
272 2800 0 0 4 &mpic 1 1
273
274 /* IDSEL 12 */
275 6000 0 0 1 &mpic 1 1
276 6000 0 0 2 &mpic 2 1
277 6000 0 0 3 &mpic 3 1
278 6000 0 0 4 &mpic 4 1
279
280 /* IDSEL 13 */
281 6800 0 0 1 &mpic 4 1
282 6800 0 0 2 &mpic 1 1
283 6800 0 0 3 &mpic 2 1
284 6800 0 0 4 &mpic 3 1
285
286 /* IDSEL 14*/
287 7000 0 0 1 &mpic 3 1
288 7000 0 0 2 &mpic 4 1
289 7000 0 0 3 &mpic 1 1
290 7000 0 0 4 &mpic 2 1
291
292 /* IDSEL 15 */
293 7800 0 0 1 &mpic 2 1
294 7800 0 0 2 &mpic 3 1
295 7800 0 0 3 &mpic 4 1
296 7800 0 0 4 &mpic 1 1
297
298 /* IDSEL 18 */
299 9000 0 0 1 &mpic 1 1
300 9000 0 0 2 &mpic 2 1
301 9000 0 0 3 &mpic 3 1
302 9000 0 0 4 &mpic 4 1
303
304 /* IDSEL 19 */
305 9800 0 0 1 &mpic 4 1
306 9800 0 0 2 &mpic 1 1
307 9800 0 0 3 &mpic 2 1
308 9800 0 0 4 &mpic 3 1
309
310 /* IDSEL 20 */
311 a000 0 0 1 &mpic 3 1
312 a000 0 0 2 &mpic 4 1
313 a000 0 0 3 &mpic 1 1
314 a000 0 0 4 &mpic 2 1
315
316 /* IDSEL 21 */
317 a800 0 0 1 &mpic 2 1
318 a800 0 0 2 &mpic 3 1
319 a800 0 0 3 &mpic 4 1
320 a800 0 0 4 &mpic 1 1>;
321
322 interrupt-parent = <&mpic>;
323 interrupts = <18 2>;
324 bus-range = <0 0>;
325 ranges = <02000000 0 80000000 80000000 0 20000000
326 01000000 0 00000000 e2000000 0 01000000>;
327 };
327}; 328};
diff --git a/arch/powerpc/boot/dts/mpc8568mds.dts b/arch/powerpc/boot/dts/mpc8568mds.dts
index b1dcfbe8c1f8..54394372b12a 100644
--- a/arch/powerpc/boot/dts/mpc8568mds.dts
+++ b/arch/powerpc/boot/dts/mpc8568mds.dts
@@ -34,7 +34,6 @@
34 timebase-frequency = <0>; 34 timebase-frequency = <0>;
35 bus-frequency = <0>; 35 bus-frequency = <0>;
36 clock-frequency = <0>; 36 clock-frequency = <0>;
37 32-bit;
38 }; 37 };
39 }; 38 };
40 39
@@ -51,10 +50,9 @@
51 soc8568@e0000000 { 50 soc8568@e0000000 {
52 #address-cells = <1>; 51 #address-cells = <1>;
53 #size-cells = <1>; 52 #size-cells = <1>;
54 #interrupt-cells = <2>;
55 device_type = "soc"; 53 device_type = "soc";
56 ranges = <0 e0000000 00100000>; 54 ranges = <0 e0000000 00100000>;
57 reg = <e0000000 00100000>; 55 reg = <e0000000 00001000>;
58 bus-frequency = <0>; 56 bus-frequency = <0>;
59 57
60 memory-controller@2000 { 58 memory-controller@2000 {
@@ -74,15 +72,24 @@
74 }; 72 };
75 73
76 i2c@3000 { 74 i2c@3000 {
75 #address-cells = <1>;
76 #size-cells = <0>;
77 device_type = "i2c"; 77 device_type = "i2c";
78 compatible = "fsl-i2c"; 78 compatible = "fsl-i2c";
79 reg = <3000 100>; 79 reg = <3000 100>;
80 interrupts = <2b 2>; 80 interrupts = <2b 2>;
81 interrupt-parent = <&mpic>; 81 interrupt-parent = <&mpic>;
82 dfsrr; 82 dfsrr;
83
84 rtc@68 {
85 compatible = "dallas,ds1374";
86 reg = <68>;
87 };
83 }; 88 };
84 89
85 i2c@3100 { 90 i2c@3100 {
91 #address-cells = <1>;
92 #size-cells = <0>;
86 device_type = "i2c"; 93 device_type = "i2c";
87 compatible = "fsl-i2c"; 94 compatible = "fsl-i2c";
88 reg = <3100 100>; 95 reg = <3100 100>;
@@ -97,10 +104,10 @@
97 device_type = "mdio"; 104 device_type = "mdio";
98 compatible = "gianfar"; 105 compatible = "gianfar";
99 reg = <24520 20>; 106 reg = <24520 20>;
100 phy0: ethernet-phy@0 { 107 phy0: ethernet-phy@7 {
101 interrupt-parent = <&mpic>; 108 interrupt-parent = <&mpic>;
102 interrupts = <1 1>; 109 interrupts = <1 1>;
103 reg = <0>; 110 reg = <7>;
104 device_type = "ethernet-phy"; 111 device_type = "ethernet-phy";
105 }; 112 };
106 phy1: ethernet-phy@1 { 113 phy1: ethernet-phy@1 {
@@ -176,60 +183,6 @@
176 fsl,has-rstcr; 183 fsl,has-rstcr;
177 }; 184 };
178 185
179 pci@8000 {
180 interrupt-map-mask = <f800 0 0 7>;
181 interrupt-map = <
182 /* IDSEL 0x12 AD18 */
183 9000 0 0 1 &mpic 5 1
184 9000 0 0 2 &mpic 6 1
185 9000 0 0 3 &mpic 7 1
186 9000 0 0 4 &mpic 4 1
187
188 /* IDSEL 0x13 AD19 */
189 9800 0 0 1 &mpic 6 1
190 9800 0 0 2 &mpic 7 1
191 9800 0 0 3 &mpic 4 1
192 9800 0 0 4 &mpic 5 1>;
193
194 interrupt-parent = <&mpic>;
195 interrupts = <18 2>;
196 bus-range = <0 ff>;
197 ranges = <02000000 0 80000000 80000000 0 20000000
198 01000000 0 00000000 e2000000 0 00800000>;
199 clock-frequency = <3f940aa>;
200 #interrupt-cells = <1>;
201 #size-cells = <2>;
202 #address-cells = <3>;
203 reg = <8000 1000>;
204 compatible = "fsl,mpc8540-pci";
205 device_type = "pci";
206 };
207
208 /* PCI Express */
209 pcie@a000 {
210 interrupt-map-mask = <f800 0 0 7>;
211 interrupt-map = <
212
213 /* IDSEL 0x0 (PEX) */
214 00000 0 0 1 &mpic 0 1
215 00000 0 0 2 &mpic 1 1
216 00000 0 0 3 &mpic 2 1
217 00000 0 0 4 &mpic 3 1>;
218
219 interrupt-parent = <&mpic>;
220 interrupts = <1a 2>;
221 bus-range = <0 ff>;
222 ranges = <02000000 0 a0000000 a0000000 0 20000000
223 01000000 0 00000000 e3000000 0 08000000>;
224 clock-frequency = <1fca055>;
225 #interrupt-cells = <1>;
226 #size-cells = <2>;
227 #address-cells = <3>;
228 reg = <a000 1000>;
229 compatible = "fsl,mpc8548-pcie";
230 device_type = "pci";
231 };
232
233 serial@4600 { 186 serial@4600 {
234 device_type = "serial"; 187 device_type = "serial";
235 compatible = "ns16550"; 188 compatible = "ns16550";
@@ -258,11 +211,11 @@
258 #address-cells = <0>; 211 #address-cells = <0>;
259 #interrupt-cells = <2>; 212 #interrupt-cells = <2>;
260 reg = <40000 40000>; 213 reg = <40000 40000>;
261 built-in;
262 compatible = "chrp,open-pic"; 214 compatible = "chrp,open-pic";
263 device_type = "open-pic"; 215 device_type = "open-pic";
264 big-endian; 216 big-endian;
265 }; 217 };
218
266 par_io@e0100 { 219 par_io@e0100 {
267 reg = <e0100 100>; 220 reg = <e0100 100>;
268 device_type = "par_io"; 221 device_type = "par_io";
@@ -289,12 +242,13 @@
289 4 1a 2 0 2 0 /* RxD7 */ 242 4 1a 2 0 2 0 /* RxD7 */
290 4 0b 1 0 2 0 /* TX_EN */ 243 4 0b 1 0 2 0 /* TX_EN */
291 4 18 1 0 2 0 /* TX_ER */ 244 4 18 1 0 2 0 /* TX_ER */
292 4 0f 2 0 2 0 /* RX_DV */ 245 4 10 2 0 2 0 /* RX_DV */
293 4 1e 2 0 2 0 /* RX_ER */ 246 4 1e 2 0 2 0 /* RX_ER */
294 4 11 2 0 2 0 /* RX_CLK */ 247 4 11 2 0 2 0 /* RX_CLK */
295 4 13 1 0 2 0 /* GTX_CLK */ 248 4 13 1 0 2 0 /* GTX_CLK */
296 1 1f 2 0 3 0>; /* GTX125 */ 249 1 1f 2 0 3 0>; /* GTX125 */
297 }; 250 };
251
298 pio2: ucc_pin@02 { 252 pio2: ucc_pin@02 {
299 pio-map = < 253 pio-map = <
300 /* port pin dir open_drain assignment has_irq */ 254 /* port pin dir open_drain assignment has_irq */
@@ -380,10 +334,10 @@
380 mac-address = [ 00 00 00 00 00 00 ]; 334 mac-address = [ 00 00 00 00 00 00 ];
381 local-mac-address = [ 00 00 00 00 00 00 ]; 335 local-mac-address = [ 00 00 00 00 00 00 ];
382 rx-clock = <0>; 336 rx-clock = <0>;
383 tx-clock = <19>; 337 tx-clock = <20>;
384 phy-handle = <&qe_phy0>;
385 phy-connection-type = "gmii";
386 pio-handle = <&pio1>; 338 pio-handle = <&pio1>;
339 phy-handle = <&phy0>;
340 phy-connection-type = "rgmii-id";
387 }; 341 };
388 342
389 ucc@3000 { 343 ucc@3000 {
@@ -402,10 +356,10 @@
402 mac-address = [ 00 00 00 00 00 00 ]; 356 mac-address = [ 00 00 00 00 00 00 ];
403 local-mac-address = [ 00 00 00 00 00 00 ]; 357 local-mac-address = [ 00 00 00 00 00 00 ];
404 rx-clock = <0>; 358 rx-clock = <0>;
405 tx-clock = <14>; 359 tx-clock = <20>;
406 phy-handle = <&qe_phy1>;
407 phy-connection-type = "gmii";
408 pio-handle = <&pio2>; 360 pio-handle = <&pio2>;
361 phy-handle = <&phy1>;
362 phy-connection-type = "rgmii-id";
409 }; 363 };
410 364
411 mdio@2120 { 365 mdio@2120 {
@@ -417,10 +371,10 @@
417 371
418 /* These are the same PHYs as on 372 /* These are the same PHYs as on
419 * gianfar's MDIO bus */ 373 * gianfar's MDIO bus */
420 qe_phy0: ethernet-phy@00 { 374 qe_phy0: ethernet-phy@07 {
421 interrupt-parent = <&mpic>; 375 interrupt-parent = <&mpic>;
422 interrupts = <1 1>; 376 interrupts = <1 1>;
423 reg = <0>; 377 reg = <7>;
424 device_type = "ethernet-phy"; 378 device_type = "ethernet-phy";
425 }; 379 };
426 qe_phy1: ethernet-phy@01 { 380 qe_phy1: ethernet-phy@01 {
@@ -449,11 +403,77 @@
449 #address-cells = <0>; 403 #address-cells = <0>;
450 #interrupt-cells = <1>; 404 #interrupt-cells = <1>;
451 reg = <80 80>; 405 reg = <80 80>;
452 built-in;
453 big-endian; 406 big-endian;
454 interrupts = <2e 2 2e 2>; //high:30 low:30 407 interrupts = <2e 2 2e 2>; //high:30 low:30
455 interrupt-parent = <&mpic>; 408 interrupt-parent = <&mpic>;
456 }; 409 };
457 410
458 }; 411 };
412
413 pci@e0008000 {
414 interrupt-map-mask = <f800 0 0 7>;
415 interrupt-map = <
416 /* IDSEL 0x12 AD18 */
417 9000 0 0 1 &mpic 5 1
418 9000 0 0 2 &mpic 6 1
419 9000 0 0 3 &mpic 7 1
420 9000 0 0 4 &mpic 4 1
421
422 /* IDSEL 0x13 AD19 */
423 9800 0 0 1 &mpic 6 1
424 9800 0 0 2 &mpic 7 1
425 9800 0 0 3 &mpic 4 1
426 9800 0 0 4 &mpic 5 1>;
427
428 interrupt-parent = <&mpic>;
429 interrupts = <18 2>;
430 bus-range = <0 ff>;
431 ranges = <02000000 0 80000000 80000000 0 20000000
432 01000000 0 00000000 e2000000 0 00800000>;
433 clock-frequency = <3f940aa>;
434 #interrupt-cells = <1>;
435 #size-cells = <2>;
436 #address-cells = <3>;
437 reg = <e0008000 1000>;
438 compatible = "fsl,mpc8540-pci";
439 device_type = "pci";
440 };
441
442 /* PCI Express */
443 pcie@e000a000 {
444 interrupt-map-mask = <f800 0 0 7>;
445 interrupt-map = <
446
447 /* IDSEL 0x0 (PEX) */
448 00000 0 0 1 &mpic 0 1
449 00000 0 0 2 &mpic 1 1
450 00000 0 0 3 &mpic 2 1
451 00000 0 0 4 &mpic 3 1>;
452
453 interrupt-parent = <&mpic>;
454 interrupts = <1a 2>;
455 bus-range = <0 ff>;
456 ranges = <02000000 0 a0000000 a0000000 0 10000000
457 01000000 0 00000000 e2800000 0 00800000>;
458 clock-frequency = <1fca055>;
459 #interrupt-cells = <1>;
460 #size-cells = <2>;
461 #address-cells = <3>;
462 reg = <e000a000 1000>;
463 compatible = "fsl,mpc8548-pcie";
464 device_type = "pci";
465 pcie@0 {
466 reg = <0 0 0 0 0>;
467 #size-cells = <2>;
468 #address-cells = <3>;
469 device_type = "pci";
470 ranges = <02000000 0 a0000000
471 02000000 0 a0000000
472 0 10000000
473
474 01000000 0 00000000
475 01000000 0 00000000
476 0 00800000>;
477 };
478 };
459}; 479};
diff --git a/arch/powerpc/boot/dts/mpc8572ds.dts b/arch/powerpc/boot/dts/mpc8572ds.dts
new file mode 100644
index 000000000000..d638deec7652
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc8572ds.dts
@@ -0,0 +1,404 @@
1/*
2 * MPC8572 DS Device Tree Source
3 *
4 * Copyright 2007 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/ {
13 model = "fsl,MPC8572DS";
14 compatible = "fsl,MPC8572DS";
15 #address-cells = <1>;
16 #size-cells = <1>;
17
18 cpus {
19 #address-cells = <1>;
20 #size-cells = <0>;
21
22 PowerPC,8572@0 {
23 device_type = "cpu";
24 reg = <0>;
25 d-cache-line-size = <20>; // 32 bytes
26 i-cache-line-size = <20>; // 32 bytes
27 d-cache-size = <8000>; // L1, 32K
28 i-cache-size = <8000>; // L1, 32K
29 timebase-frequency = <0>;
30 bus-frequency = <0>;
31 clock-frequency = <0>;
32 };
33 };
34
35 memory {
36 device_type = "memory";
37 reg = <00000000 00000000>; // Filled by U-Boot
38 };
39
40 soc8572@ffe00000 {
41 #address-cells = <1>;
42 #size-cells = <1>;
43 device_type = "soc";
44 ranges = <00000000 ffe00000 00100000>;
45 reg = <ffe00000 00001000>; // CCSRBAR & soc regs, remove once parse code for immrbase fixed
46 bus-frequency = <0>; // Filled out by uboot.
47
48 memory-controller@2000 {
49 compatible = "fsl,mpc8572-memory-controller";
50 reg = <2000 1000>;
51 interrupt-parent = <&mpic>;
52 interrupts = <12 2>;
53 };
54
55 memory-controller@6000 {
56 compatible = "fsl,mpc8572-memory-controller";
57 reg = <6000 1000>;
58 interrupt-parent = <&mpic>;
59 interrupts = <12 2>;
60 };
61
62 l2-cache-controller@20000 {
63 compatible = "fsl,mpc8572-l2-cache-controller";
64 reg = <20000 1000>;
65 cache-line-size = <20>; // 32 bytes
66 cache-size = <80000>; // L2, 512K
67 interrupt-parent = <&mpic>;
68 interrupts = <10 2>;
69 };
70
71 i2c@3000 {
72 device_type = "i2c";
73 compatible = "fsl-i2c";
74 reg = <3000 100>;
75 interrupts = <2b 2>;
76 interrupt-parent = <&mpic>;
77 dfsrr;
78 };
79
80 i2c@3100 {
81 device_type = "i2c";
82 compatible = "fsl-i2c";
83 reg = <3100 100>;
84 interrupts = <2b 2>;
85 interrupt-parent = <&mpic>;
86 dfsrr;
87 };
88
89 mdio@24520 {
90 #address-cells = <1>;
91 #size-cells = <0>;
92 device_type = "mdio";
93 compatible = "gianfar";
94 reg = <24520 20>;
95 phy0: ethernet-phy@0 {
96 interrupt-parent = <&mpic>;
97 interrupts = <a 1>;
98 reg = <0>;
99 };
100 phy1: ethernet-phy@1 {
101 interrupt-parent = <&mpic>;
102 interrupts = <a 1>;
103 reg = <1>;
104 };
105 phy2: ethernet-phy@2 {
106 interrupt-parent = <&mpic>;
107 interrupts = <a 1>;
108 reg = <2>;
109 };
110 phy3: ethernet-phy@3 {
111 interrupt-parent = <&mpic>;
112 interrupts = <a 1>;
113 reg = <3>;
114 };
115 };
116
117 ethernet@24000 {
118 #address-cells = <1>;
119 #size-cells = <0>;
120 device_type = "network";
121 model = "eTSEC";
122 compatible = "gianfar";
123 reg = <24000 1000>;
124 local-mac-address = [ 00 00 00 00 00 00 ];
125 interrupts = <1d 2 1e 2 22 2>;
126 interrupt-parent = <&mpic>;
127 phy-handle = <&phy0>;
128 phy-connection-type = "rgmii-id";
129 };
130
131 ethernet@25000 {
132 #address-cells = <1>;
133 #size-cells = <0>;
134 device_type = "network";
135 model = "eTSEC";
136 compatible = "gianfar";
137 reg = <25000 1000>;
138 local-mac-address = [ 00 00 00 00 00 00 ];
139 interrupts = <23 2 24 2 28 2>;
140 interrupt-parent = <&mpic>;
141 phy-handle = <&phy1>;
142 phy-connection-type = "rgmii-id";
143 };
144
145 ethernet@26000 {
146 #address-cells = <1>;
147 #size-cells = <0>;
148 device_type = "network";
149 model = "eTSEC";
150 compatible = "gianfar";
151 reg = <26000 1000>;
152 local-mac-address = [ 00 00 00 00 00 00 ];
153 interrupts = <1f 2 20 2 21 2>;
154 interrupt-parent = <&mpic>;
155 phy-handle = <&phy2>;
156 phy-connection-type = "rgmii-id";
157 };
158
159 ethernet@27000 {
160 #address-cells = <1>;
161 #size-cells = <0>;
162 device_type = "network";
163 model = "eTSEC";
164 compatible = "gianfar";
165 reg = <27000 1000>;
166 local-mac-address = [ 00 00 00 00 00 00 ];
167 interrupts = <25 2 26 2 27 2>;
168 interrupt-parent = <&mpic>;
169 phy-handle = <&phy3>;
170 phy-connection-type = "rgmii-id";
171 };
172
173 serial@4500 {
174 device_type = "serial";
175 compatible = "ns16550";
176 reg = <4500 100>;
177 clock-frequency = <0>;
178 interrupts = <2a 2>;
179 interrupt-parent = <&mpic>;
180 };
181
182 serial@4600 {
183 device_type = "serial";
184 compatible = "ns16550";
185 reg = <4600 100>;
186 clock-frequency = <0>;
187 interrupts = <2a 2>;
188 interrupt-parent = <&mpic>;
189 };
190
191 global-utilities@e0000 { //global utilities block
192 compatible = "fsl,mpc8572-guts";
193 reg = <e0000 1000>;
194 fsl,has-rstcr;
195 };
196
197 mpic: pic@40000 {
198 clock-frequency = <0>;
199 interrupt-controller;
200 #address-cells = <0>;
201 #interrupt-cells = <2>;
202 reg = <40000 40000>;
203 compatible = "chrp,open-pic";
204 device_type = "open-pic";
205 big-endian;
206 };
207 };
208
209 pcie@ffe08000 {
210 compatible = "fsl,mpc8548-pcie";
211 device_type = "pci";
212 #interrupt-cells = <1>;
213 #size-cells = <2>;
214 #address-cells = <3>;
215 reg = <ffe08000 1000>;
216 bus-range = <0 ff>;
217 ranges = <02000000 0 80000000 80000000 0 20000000
218 01000000 0 00000000 ffc00000 0 00010000>;
219 clock-frequency = <1fca055>;
220 interrupt-parent = <&mpic>;
221 interrupts = <18 2>;
222 interrupt-map-mask = <fb00 0 0 0>;
223 interrupt-map = <
224 /* IDSEL 0x11 - PCI slot 1 */
225 8800 0 0 1 &mpic 2 1
226 8800 0 0 2 &mpic 3 1
227 8800 0 0 3 &mpic 4 1
228 8800 0 0 4 &mpic 1 1
229
230 /* IDSEL 0x12 - PCI slot 2 */
231 9000 0 0 1 &mpic 3 1
232 9000 0 0 2 &mpic 4 1
233 9000 0 0 3 &mpic 1 1
234 9000 0 0 4 &mpic 2 1
235
236 // IDSEL 0x1c USB
237 e000 0 0 0 &i8259 c 2
238 e100 0 0 0 &i8259 9 2
239 e200 0 0 0 &i8259 a 2
240 e300 0 0 0 &i8259 b 2
241
242 // IDSEL 0x1d Audio
243 e800 0 0 0 &i8259 6 2
244
245 // IDSEL 0x1e Legacy
246 f000 0 0 0 &i8259 7 2
247 f100 0 0 0 &i8259 7 2
248
249 // IDSEL 0x1f IDE/SATA
250 f800 0 0 0 &i8259 e 2
251 f900 0 0 0 &i8259 5 2
252
253 >;
254
255 pcie@0 {
256 reg = <0 0 0 0 0>;
257 #size-cells = <2>;
258 #address-cells = <3>;
259 device_type = "pci";
260 ranges = <02000000 0 80000000
261 02000000 0 80000000
262 0 20000000
263
264 01000000 0 00000000
265 01000000 0 00000000
266 0 00100000>;
267 uli1575@0 {
268 reg = <0 0 0 0 0>;
269 #size-cells = <2>;
270 #address-cells = <3>;
271 ranges = <02000000 0 80000000
272 02000000 0 80000000
273 0 20000000
274
275 01000000 0 00000000
276 01000000 0 00000000
277 0 00100000>;
278 isa@1e {
279 device_type = "isa";
280 #interrupt-cells = <2>;
281 #size-cells = <1>;
282 #address-cells = <2>;
283 reg = <f000 0 0 0 0>;
284 ranges = <1 0 01000000 0 0
285 00001000>;
286 interrupt-parent = <&i8259>;
287
288 i8259: interrupt-controller@20 {
289 reg = <1 20 2
290 1 a0 2
291 1 4d0 2>;
292 interrupt-controller;
293 device_type = "interrupt-controller";
294 #address-cells = <0>;
295 #interrupt-cells = <2>;
296 compatible = "chrp,iic";
297 interrupts = <9 2>;
298 interrupt-parent = <&mpic>;
299 };
300
301 i8042@60 {
302 #size-cells = <0>;
303 #address-cells = <1>;
304 reg = <1 60 1 1 64 1>;
305 interrupts = <1 3 c 3>;
306 interrupt-parent =
307 <&i8259>;
308
309 keyboard@0 {
310 reg = <0>;
311 compatible = "pnpPNP,303";
312 };
313
314 mouse@1 {
315 reg = <1>;
316 compatible = "pnpPNP,f03";
317 };
318 };
319
320 rtc@70 {
321 compatible = "pnpPNP,b00";
322 reg = <1 70 2>;
323 };
324
325 gpio@400 {
326 reg = <1 400 80>;
327 };
328 };
329 };
330 };
331
332 };
333
334 pcie@ffe09000 {
335 compatible = "fsl,mpc8548-pcie";
336 device_type = "pci";
337 #interrupt-cells = <1>;
338 #size-cells = <2>;
339 #address-cells = <3>;
340 reg = <ffe09000 1000>;
341 bus-range = <0 ff>;
342 ranges = <02000000 0 a0000000 a0000000 0 20000000
343 01000000 0 00000000 ffc10000 0 00010000>;
344 clock-frequency = <1fca055>;
345 interrupt-parent = <&mpic>;
346 interrupts = <1a 2>;
347 interrupt-map-mask = <f800 0 0 7>;
348 interrupt-map = <
349 /* IDSEL 0x0 */
350 0000 0 0 1 &mpic 4 1
351 0000 0 0 2 &mpic 5 1
352 0000 0 0 3 &mpic 6 1
353 0000 0 0 4 &mpic 7 1
354 >;
355 pcie@0 {
356 reg = <0 0 0 0 0>;
357 #size-cells = <2>;
358 #address-cells = <3>;
359 device_type = "pci";
360 ranges = <02000000 0 a0000000
361 02000000 0 a0000000
362 0 20000000
363
364 01000000 0 00000000
365 01000000 0 00000000
366 0 00100000>;
367 };
368 };
369
370 pcie@ffe0a000 {
371 compatible = "fsl,mpc8548-pcie";
372 device_type = "pci";
373 #interrupt-cells = <1>;
374 #size-cells = <2>;
375 #address-cells = <3>;
376 reg = <ffe0a000 1000>;
377 bus-range = <0 ff>;
378 ranges = <02000000 0 c0000000 c0000000 0 20000000
379 01000000 0 00000000 ffc20000 0 00010000>;
380 clock-frequency = <1fca055>;
381 interrupt-parent = <&mpic>;
382 interrupts = <1b 2>;
383 interrupt-map = <
384 /* IDSEL 0x0 */
385 0000 0 0 1 &mpic 0 1
386 0000 0 0 2 &mpic 1 1
387 0000 0 0 3 &mpic 2 1
388 0000 0 0 4 &mpic 3 1
389 >;
390 pcie@0 {
391 reg = <0 0 0 0 0>;
392 #size-cells = <2>;
393 #address-cells = <3>;
394 device_type = "pci";
395 ranges = <02000000 0 c0000000
396 02000000 0 c0000000
397 0 20000000
398
399 01000000 0 00000000
400 01000000 0 00000000
401 0 00100000>;
402 };
403 };
404};
diff --git a/arch/powerpc/boot/dts/mpc8610_hpcd.dts b/arch/powerpc/boot/dts/mpc8610_hpcd.dts
new file mode 100644
index 000000000000..966edf1161a6
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc8610_hpcd.dts
@@ -0,0 +1,191 @@
1/*
2 * MPC8610 HPCD Device Tree Source
3 *
4 * Copyright 2007 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License Version 2 as published
8 * by the Free Software Foundation.
9 */
10
11
12/ {
13 model = "MPC8610HPCD";
14 compatible = "fsl,MPC8610HPCD";
15 #address-cells = <1>;
16 #size-cells = <1>;
17
18 cpus {
19 #address-cells = <1>;
20 #size-cells = <0>;
21
22 PowerPC,8610@0 {
23 device_type = "cpu";
24 reg = <0>;
25 d-cache-line-size = <d# 32>; // bytes
26 i-cache-line-size = <d# 32>; // bytes
27 d-cache-size = <8000>; // L1, 32K
28 i-cache-size = <8000>; // L1, 32K
29 timebase-frequency = <0>; // 33 MHz, from uboot
30 bus-frequency = <0>; // From uboot
31 clock-frequency = <0>; // From uboot
32 };
33 };
34
35 memory {
36 device_type = "memory";
37 reg = <00000000 20000000>; // 512M at 0x0
38 };
39
40 soc@e0000000 {
41 #address-cells = <1>;
42 #size-cells = <1>;
43 #interrupt-cells = <2>;
44 device_type = "soc";
45 ranges = <0 e0000000 00100000>;
46 reg = <e0000000 1000>;
47 bus-frequency = <0>;
48
49 i2c@3000 {
50 device_type = "i2c";
51 compatible = "fsl-i2c";
52 #address-cells = <1>;
53 #size-cells = <0>;
54 reg = <3000 100>;
55 interrupts = <2b 2>;
56 interrupt-parent = <&mpic>;
57 dfsrr;
58 };
59
60 i2c@3100 {
61 device_type = "i2c";
62 compatible = "fsl-i2c";
63 #address-cells = <1>;
64 #size-cells = <0>;
65 reg = <3100 100>;
66 interrupts = <2b 2>;
67 interrupt-parent = <&mpic>;
68 dfsrr;
69 };
70
71 serial@4500 {
72 device_type = "serial";
73 compatible = "ns16550";
74 reg = <4500 100>;
75 clock-frequency = <0>;
76 interrupts = <2a 2>;
77 interrupt-parent = <&mpic>;
78 };
79
80 serial@4600 {
81 device_type = "serial";
82 compatible = "ns16550";
83 reg = <4600 100>;
84 clock-frequency = <0>;
85 interrupts = <1c 2>;
86 interrupt-parent = <&mpic>;
87 };
88
89
90 mpic: interrupt-controller@40000 {
91 clock-frequency = <0>;
92 interrupt-controller;
93 #address-cells = <0>;
94 #interrupt-cells = <2>;
95 reg = <40000 40000>;
96 compatible = "chrp,open-pic";
97 device_type = "open-pic";
98 big-endian;
99 };
100
101 global-utilities@e0000 {
102 compatible = "fsl,mpc8610-guts";
103 reg = <e0000 1000>;
104 fsl,has-rstcr;
105 };
106 };
107
108 pci@e0008000 {
109 compatible = "fsl,mpc8610-pci";
110 device_type = "pci";
111 #interrupt-cells = <1>;
112 #size-cells = <2>;
113 #address-cells = <3>;
114 reg = <e0008000 1000>;
115 bus-range = <0 0>;
116 ranges = <02000000 0 80000000 80000000 0 10000000
117 01000000 0 00000000 e1000000 0 00100000>;
118 clock-frequency = <1fca055>;
119 interrupt-parent = <&mpic>;
120 interrupts = <18 2>;
121 interrupt-map-mask = <f800 0 0 7>;
122 interrupt-map = <
123 /* IDSEL 0x11 */
124 8800 0 0 1 &mpic 4 1
125 8800 0 0 2 &mpic 5 1
126 8800 0 0 3 &mpic 6 1
127 8800 0 0 4 &mpic 7 1
128
129 /* IDSEL 0x12 */
130 9000 0 0 1 &mpic 5 1
131 9000 0 0 2 &mpic 6 1
132 9000 0 0 3 &mpic 7 1
133 9000 0 0 4 &mpic 4 1
134 >;
135 };
136
137 pcie@e000a000 {
138 compatible = "fsl,mpc8641-pcie";
139 device_type = "pci";
140 #interrupt-cells = <1>;
141 #size-cells = <2>;
142 #address-cells = <3>;
143 reg = <e000a000 1000>;
144 bus-range = <1 3>;
145 ranges = <02000000 0 a0000000 a0000000 0 10000000
146 01000000 0 00000000 e3000000 0 00100000>;
147 clock-frequency = <1fca055>;
148 interrupt-parent = <&mpic>;
149 interrupts = <1a 2>;
150 interrupt-map-mask = <f800 0 0 7>;
151
152 interrupt-map = <
153 /* IDSEL 0x1b */
154 d800 0 0 1 &mpic 2 1
155
156 /* IDSEL 0x1c*/
157 e000 0 0 1 &mpic 1 1
158 e000 0 0 2 &mpic 1 1
159 e000 0 0 3 &mpic 1 1
160 e000 0 0 4 &mpic 1 1
161
162 /* IDSEL 0x1f */
163 f800 0 0 1 &mpic 3 0
164 f800 0 0 2 &mpic 0 1
165 >;
166
167 pcie@0 {
168 reg = <0 0 0 0 0>;
169 #size-cells = <2>;
170 #address-cells = <3>;
171 device_type = "pci";
172 ranges = <02000000 0 a0000000
173 02000000 0 a0000000
174 0 10000000
175 01000000 0 00000000
176 01000000 0 00000000
177 0 00100000>;
178 uli1575@0 {
179 reg = <0 0 0 0 0>;
180 #size-cells = <2>;
181 #address-cells = <3>;
182 ranges = <02000000 0 a0000000
183 02000000 0 a0000000
184 0 10000000
185 01000000 0 00000000
186 01000000 0 00000000
187 0 00100000>;
188 };
189 };
190 };
191};
diff --git a/arch/powerpc/boot/dts/mpc8641_hpcn.dts b/arch/powerpc/boot/dts/mpc8641_hpcn.dts
index b0166e5c177e..367765937a06 100644
--- a/arch/powerpc/boot/dts/mpc8641_hpcn.dts
+++ b/arch/powerpc/boot/dts/mpc8641_hpcn.dts
@@ -30,7 +30,6 @@
30 timebase-frequency = <0>; // 33 MHz, from uboot 30 timebase-frequency = <0>; // 33 MHz, from uboot
31 bus-frequency = <0>; // From uboot 31 bus-frequency = <0>; // From uboot
32 clock-frequency = <0>; // From uboot 32 clock-frequency = <0>; // From uboot
33 32-bit;
34 }; 33 };
35 PowerPC,8641@1 { 34 PowerPC,8641@1 {
36 device_type = "cpu"; 35 device_type = "cpu";
@@ -42,7 +41,6 @@
42 timebase-frequency = <0>; // 33 MHz, from uboot 41 timebase-frequency = <0>; // 33 MHz, from uboot
43 bus-frequency = <0>; // From uboot 42 bus-frequency = <0>; // From uboot
44 clock-frequency = <0>; // From uboot 43 clock-frequency = <0>; // From uboot
45 32-bit;
46 }; 44 };
47 }; 45 };
48 46
@@ -54,13 +52,8 @@
54 soc8641@f8000000 { 52 soc8641@f8000000 {
55 #address-cells = <1>; 53 #address-cells = <1>;
56 #size-cells = <1>; 54 #size-cells = <1>;
57 #interrupt-cells = <2>;
58 device_type = "soc"; 55 device_type = "soc";
59 ranges = <00001000 f8001000 000ff000 56 ranges = <00000000 f8000000 00100000>;
60 80000000 80000000 20000000
61 e2000000 e2000000 00100000
62 a0000000 a0000000 20000000
63 e3000000 e3000000 00100000>;
64 reg = <f8000000 00001000>; // CCSRBAR 57 reg = <f8000000 00001000>; // CCSRBAR
65 bus-frequency = <0>; 58 bus-frequency = <0>;
66 59
@@ -211,50 +204,81 @@
211 interrupt-parent = <&mpic>; 204 interrupt-parent = <&mpic>;
212 }; 205 };
213 206
214 pcie@8000 { 207 mpic: pic@40000 {
215 compatible = "fsl,mpc8641-pcie"; 208 clock-frequency = <0>;
216 device_type = "pci"; 209 interrupt-controller;
217 #interrupt-cells = <1>; 210 #address-cells = <0>;
211 #interrupt-cells = <2>;
212 reg = <40000 40000>;
213 compatible = "chrp,open-pic";
214 device_type = "open-pic";
215 big-endian;
216 };
217
218 global-utilities@e0000 {
219 compatible = "fsl,mpc8641-guts";
220 reg = <e0000 1000>;
221 fsl,has-rstcr;
222 };
223 };
224
225 pcie@f8008000 {
226 compatible = "fsl,mpc8641-pcie";
227 device_type = "pci";
228 #interrupt-cells = <1>;
229 #size-cells = <2>;
230 #address-cells = <3>;
231 reg = <f8008000 1000>;
232 bus-range = <0 ff>;
233 ranges = <02000000 0 80000000 80000000 0 20000000
234 01000000 0 00000000 e2000000 0 00100000>;
235 clock-frequency = <1fca055>;
236 interrupt-parent = <&mpic>;
237 interrupts = <18 2>;
238 interrupt-map-mask = <fb00 0 0 0>;
239 interrupt-map = <
240 /* IDSEL 0x11 */
241 8800 0 0 1 &i8259 9 2
242 8800 0 0 2 &i8259 a 2
243 8800 0 0 3 &i8259 b 2
244 8800 0 0 4 &i8259 c 2
245
246 /* IDSEL 0x12 */
247 9000 0 0 1 &i8259 a 2
248 9000 0 0 2 &i8259 b 2
249 9000 0 0 3 &i8259 c 2
250 9000 0 0 4 &i8259 9 2
251
252 // IDSEL 0x1c USB
253 e000 0 0 0 &i8259 c 2
254 e100 0 0 0 &i8259 9 2
255 e200 0 0 0 &i8259 a 2
256 e300 0 0 0 &i8259 b 2
257
258 // IDSEL 0x1d Audio
259 e800 0 0 0 &i8259 6 2
260
261 // IDSEL 0x1e Legacy
262 f000 0 0 0 &i8259 7 2
263 f100 0 0 0 &i8259 7 2
264
265 // IDSEL 0x1f IDE/SATA
266 f800 0 0 0 &i8259 e 2
267 f900 0 0 0 &i8259 5 2
268 >;
269
270 pcie@0 {
271 reg = <0 0 0 0 0>;
218 #size-cells = <2>; 272 #size-cells = <2>;
219 #address-cells = <3>; 273 #address-cells = <3>;
220 reg = <8000 1000>; 274 device_type = "pci";
221 bus-range = <0 ff>; 275 ranges = <02000000 0 80000000
222 ranges = <02000000 0 80000000 80000000 0 20000000 276 02000000 0 80000000
223 01000000 0 00000000 e2000000 0 00100000>; 277 0 20000000
224 clock-frequency = <1fca055>; 278
225 interrupt-parent = <&mpic>; 279 01000000 0 00000000
226 interrupts = <18 2>; 280 01000000 0 00000000
227 interrupt-map-mask = <fb00 0 0 0>; 281 0 00100000>;
228 interrupt-map = <
229 /* IDSEL 0x11 */
230 8800 0 0 1 &i8259 9 2
231 8800 0 0 2 &i8259 a 2
232 8800 0 0 3 &i8259 b 2
233 8800 0 0 4 &i8259 c 2
234
235 /* IDSEL 0x12 */
236 9000 0 0 1 &i8259 a 2
237 9000 0 0 2 &i8259 b 2
238 9000 0 0 3 &i8259 c 2
239 9000 0 0 4 &i8259 9 2
240
241 // IDSEL 0x1c USB
242 e000 0 0 0 &i8259 c 2
243 e100 0 0 0 &i8259 9 2
244 e200 0 0 0 &i8259 a 2
245 e300 0 0 0 &i8259 b 2
246
247 // IDSEL 0x1d Audio
248 e800 0 0 0 &i8259 6 2
249
250 // IDSEL 0x1e Legacy
251 f000 0 0 0 &i8259 7 2
252 f100 0 0 0 &i8259 7 2
253
254 // IDSEL 0x1f IDE/SATA
255 f800 0 0 0 &i8259 e 2
256 f900 0 0 0 &i8259 5 2
257 >;
258 uli1575@0 { 282 uli1575@0 {
259 reg = <0 0 0 0 0>; 283 reg = <0 0 0 0 0>;
260 #size-cells = <2>; 284 #size-cells = <2>;
@@ -265,111 +289,96 @@
265 01000000 0 00000000 289 01000000 0 00000000
266 01000000 0 00000000 290 01000000 0 00000000
267 0 00100000>; 291 0 00100000>;
292 isa@1e {
293 device_type = "isa";
294 #interrupt-cells = <2>;
295 #size-cells = <1>;
296 #address-cells = <2>;
297 reg = <f000 0 0 0 0>;
298 ranges = <1 0 01000000 0 0
299 00001000>;
300 interrupt-parent = <&i8259>;
268 301
269 pci_bridge@0 { 302 i8259: interrupt-controller@20 {
270 reg = <0 0 0 0 0>; 303 reg = <1 20 2
271 #size-cells = <2>; 304 1 a0 2
272 #address-cells = <3>; 305 1 4d0 2>;
273 ranges = <02000000 0 80000000 306 interrupt-controller;
274 02000000 0 80000000 307 device_type = "interrupt-controller";
275 0 20000000 308 #address-cells = <0>;
276 01000000 0 00000000
277 01000000 0 00000000
278 0 00100000>;
279
280 isa@1e {
281 device_type = "isa";
282 #interrupt-cells = <2>; 309 #interrupt-cells = <2>;
283 #size-cells = <1>; 310 compatible = "chrp,iic";
284 #address-cells = <2>; 311 interrupts = <9 2>;
285 reg = <f000 0 0 0 0>; 312 interrupt-parent = <&mpic>;
286 ranges = <1 0 01000000 0 0 313 };
287 00001000>;
288 interrupt-parent = <&i8259>;
289
290 i8259: interrupt-controller@20 {
291 reg = <1 20 2
292 1 a0 2
293 1 4d0 2>;
294 clock-frequency = <0>;
295 interrupt-controller;
296 device_type = "interrupt-controller";
297 #address-cells = <0>;
298 #interrupt-cells = <2>;
299 built-in;
300 compatible = "chrp,iic";
301 interrupts = <9 2>;
302 interrupt-parent =
303 <&mpic>;
304 };
305 314
306 i8042@60 { 315 i8042@60 {
307 #size-cells = <0>; 316 #size-cells = <0>;
308 #address-cells = <1>; 317 #address-cells = <1>;
309 reg = <1 60 1 1 64 1>; 318 reg = <1 60 1 1 64 1>;
310 interrupts = <1 3 c 3>; 319 interrupts = <1 3 c 3>;
311 interrupt-parent = 320 interrupt-parent =
312 <&i8259>; 321 <&i8259>;
313
314 keyboard@0 {
315 reg = <0>;
316 compatible = "pnpPNP,303";
317 };
318
319 mouse@1 {
320 reg = <1>;
321 compatible = "pnpPNP,f03";
322 };
323 };
324 322
325 rtc@70 { 323 keyboard@0 {
326 compatible = 324 reg = <0>;
327 "pnpPNP,b00"; 325 compatible = "pnpPNP,303";
328 reg = <1 70 2>;
329 }; 326 };
330 327
331 gpio@400 { 328 mouse@1 {
332 reg = <1 400 80>; 329 reg = <1>;
330 compatible = "pnpPNP,f03";
333 }; 331 };
334 }; 332 };
333
334 rtc@70 {
335 compatible =
336 "pnpPNP,b00";
337 reg = <1 70 2>;
338 };
339
340 gpio@400 {
341 reg = <1 400 80>;
342 };
335 }; 343 };
336 }; 344 };
337
338 }; 345 };
339 346
340 pcie@9000 { 347 };
341 compatible = "fsl,mpc8641-pcie"; 348
342 device_type = "pci"; 349 pcie@f8009000 {
343 #interrupt-cells = <1>; 350 compatible = "fsl,mpc8641-pcie";
351 device_type = "pci";
352 #interrupt-cells = <1>;
353 #size-cells = <2>;
354 #address-cells = <3>;
355 reg = <f8009000 1000>;
356 bus-range = <0 ff>;
357 ranges = <02000000 0 a0000000 a0000000 0 20000000
358 01000000 0 00000000 e3000000 0 00100000>;
359 clock-frequency = <1fca055>;
360 interrupt-parent = <&mpic>;
361 interrupts = <19 2>;
362 interrupt-map-mask = <f800 0 0 7>;
363 interrupt-map = <
364 /* IDSEL 0x0 */
365 0000 0 0 1 &mpic 4 1
366 0000 0 0 2 &mpic 5 1
367 0000 0 0 3 &mpic 6 1
368 0000 0 0 4 &mpic 7 1
369 >;
370 pcie@0 {
371 reg = <0 0 0 0 0>;
344 #size-cells = <2>; 372 #size-cells = <2>;
345 #address-cells = <3>; 373 #address-cells = <3>;
346 reg = <9000 1000>; 374 device_type = "pci";
347 bus-range = <0 ff>; 375 ranges = <02000000 0 a0000000
348 ranges = <02000000 0 a0000000 a0000000 0 20000000 376 02000000 0 a0000000
349 01000000 0 00000000 e3000000 0 00100000>; 377 0 20000000
350 clock-frequency = <1fca055>;
351 interrupt-parent = <&mpic>;
352 interrupts = <19 2>;
353 interrupt-map-mask = <f800 0 0 7>;
354 interrupt-map = <
355 /* IDSEL 0x0 */
356 0000 0 0 1 &mpic 4 1
357 0000 0 0 2 &mpic 5 1
358 0000 0 0 3 &mpic 6 1
359 0000 0 0 4 &mpic 7 1
360 >;
361 };
362 378
363 mpic: pic@40000 { 379 01000000 0 00000000
364 clock-frequency = <0>; 380 01000000 0 00000000
365 interrupt-controller; 381 0 00100000>;
366 #address-cells = <0>;
367 #interrupt-cells = <2>;
368 reg = <40000 40000>;
369 built-in;
370 compatible = "chrp,open-pic";
371 device_type = "open-pic";
372 big-endian;
373 }; 382 };
374 }; 383 };
375}; 384};
diff --git a/arch/powerpc/boot/dts/mpc866ads.dts b/arch/powerpc/boot/dts/mpc866ads.dts
index e5e7726ddb03..90f2293ed3cd 100644
--- a/arch/powerpc/boot/dts/mpc866ads.dts
+++ b/arch/powerpc/boot/dts/mpc866ads.dts
@@ -30,7 +30,6 @@
30 timebase-frequency = <0>; 30 timebase-frequency = <0>;
31 bus-frequency = <0>; 31 bus-frequency = <0>;
32 clock-frequency = <0>; 32 clock-frequency = <0>;
33 32-bit;
34 interrupts = <f 2>; // decrementer interrupt 33 interrupts = <f 2>; // decrementer interrupt
35 interrupt-parent = <&Mpc8xx_pic>; 34 interrupt-parent = <&Mpc8xx_pic>;
36 }; 35 };
@@ -44,7 +43,6 @@
44 soc866@ff000000 { 43 soc866@ff000000 {
45 #address-cells = <1>; 44 #address-cells = <1>;
46 #size-cells = <1>; 45 #size-cells = <1>;
47 #interrupt-cells = <2>;
48 device_type = "soc"; 46 device_type = "soc";
49 ranges = <0 ff000000 00100000>; 47 ranges = <0 ff000000 00100000>;
50 reg = <ff000000 00000200>; 48 reg = <ff000000 00000200>;
@@ -78,7 +76,6 @@
78 #address-cells = <0>; 76 #address-cells = <0>;
79 #interrupt-cells = <2>; 77 #interrupt-cells = <2>;
80 reg = <0 24>; 78 reg = <0 24>;
81 built-in;
82 device_type = "mpc8xx-pic"; 79 device_type = "mpc8xx-pic";
83 compatible = "CPM"; 80 compatible = "CPM";
84 }; 81 };
@@ -86,7 +83,6 @@
86 cpm@ff000000 { 83 cpm@ff000000 {
87 #address-cells = <1>; 84 #address-cells = <1>;
88 #size-cells = <1>; 85 #size-cells = <1>;
89 #interrupt-cells = <2>;
90 device_type = "cpm"; 86 device_type = "cpm";
91 model = "CPM"; 87 model = "CPM";
92 ranges = <0 0 4000>; 88 ranges = <0 0 4000>;
@@ -103,7 +99,6 @@
103 interrupts = <5 2 0 2>; 99 interrupts = <5 2 0 2>;
104 interrupt-parent = <&Mpc8xx_pic>; 100 interrupt-parent = <&Mpc8xx_pic>;
105 reg = <930 20>; 101 reg = <930 20>;
106 built-in;
107 device_type = "cpm-pic"; 102 device_type = "cpm-pic";
108 compatible = "CPM"; 103 compatible = "CPM";
109 }; 104 };
diff --git a/arch/powerpc/boot/dts/mpc885ads.dts b/arch/powerpc/boot/dts/mpc885ads.dts
index dc7ab9c80611..8848e637293e 100644
--- a/arch/powerpc/boot/dts/mpc885ads.dts
+++ b/arch/powerpc/boot/dts/mpc885ads.dts
@@ -2,6 +2,7 @@
2 * MPC885 ADS Device Tree Source 2 * MPC885 ADS Device Tree Source
3 * 3 *
4 * Copyright 2006 MontaVista Software, Inc. 4 * Copyright 2006 MontaVista Software, Inc.
5 * Copyright 2007 Freescale Semiconductor, Inc.
5 * 6 *
6 * This program is free software; you can redistribute it and/or modify it 7 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the 8 * under the terms of the GNU General Public License as published by the
@@ -12,7 +13,7 @@
12 13
13/ { 14/ {
14 model = "MPC885ADS"; 15 model = "MPC885ADS";
15 compatible = "mpc8xx"; 16 compatible = "fsl,mpc885ads";
16 #address-cells = <1>; 17 #address-cells = <1>;
17 #size-cells = <1>; 18 #size-cells = <1>;
18 19
@@ -23,161 +24,199 @@
23 PowerPC,885@0 { 24 PowerPC,885@0 {
24 device_type = "cpu"; 25 device_type = "cpu";
25 reg = <0>; 26 reg = <0>;
26 d-cache-line-size = <20>; // 32 bytes 27 d-cache-line-size = <d#16>;
27 i-cache-line-size = <20>; // 32 bytes 28 i-cache-line-size = <d#16>;
28 d-cache-size = <2000>; // L1, 8K 29 d-cache-size = <d#8192>;
29 i-cache-size = <2000>; // L1, 8K 30 i-cache-size = <d#8192>;
30 timebase-frequency = <0>; 31 timebase-frequency = <0>;
31 bus-frequency = <0>; 32 bus-frequency = <0>;
32 clock-frequency = <0>; 33 clock-frequency = <0>;
33 32-bit;
34 interrupts = <f 2>; // decrementer interrupt 34 interrupts = <f 2>; // decrementer interrupt
35 interrupt-parent = <&Mpc8xx_pic>; 35 interrupt-parent = <&PIC>;
36 }; 36 };
37 }; 37 };
38 38
39 memory { 39 memory {
40 device_type = "memory"; 40 device_type = "memory";
41 reg = <00000000 800000>; 41 reg = <0 0>;
42 }; 42 };
43 43
44 soc885@ff000000 { 44 localbus@ff000100 {
45 compatible = "fsl,mpc885-localbus", "fsl,pq1-localbus";
46 #address-cells = <2>;
47 #size-cells = <1>;
48 reg = <ff000100 40>;
49
50 ranges = <
51 0 0 fe000000 00800000
52 1 0 ff080000 00008000
53 5 0 ff0a0000 00008000
54 >;
55
56 flash@0,0 {
57 compatible = "jedec-flash";
58 reg = <0 0 800000>;
59 bank-width = <4>;
60 device-width = <1>;
61 };
62
63 board-control@1,0 {
64 reg = <1 0 20 5 300 4>;
65 compatible = "fsl,mpc885ads-bcsr";
66 };
67 };
68
69 soc@ff000000 {
70 compatible = "fsl,mpc885", "fsl,pq1-soc";
45 #address-cells = <1>; 71 #address-cells = <1>;
46 #size-cells = <1>; 72 #size-cells = <1>;
47 #interrupt-cells = <2>;
48 device_type = "soc"; 73 device_type = "soc";
49 ranges = <0 ff000000 00100000>; 74 ranges = <0 ff000000 00004000>;
50 reg = <ff000000 00000200>;
51 bus-frequency = <0>; 75 bus-frequency = <0>;
52 mdio@e80 { 76
53 device_type = "mdio"; 77 // Temporary -- will go away once kernel uses ranges for get_immrbase().
54 compatible = "fs_enet"; 78 reg = <ff000000 4000>;
55 reg = <e80 8>; 79
80 mdio@e00 {
81 compatible = "fsl,mpc885-fec-mdio", "fsl,pq1-fec-mdio";
82 reg = <e00 188>;
56 #address-cells = <1>; 83 #address-cells = <1>;
57 #size-cells = <0>; 84 #size-cells = <0>;
58 Phy0: ethernet-phy@0 { 85
86 PHY0: ethernet-phy@0 {
59 reg = <0>; 87 reg = <0>;
60 device_type = "ethernet-phy"; 88 device_type = "ethernet-phy";
61 }; 89 };
62 Phy1: ethernet-phy@1 { 90
91 PHY1: ethernet-phy@1 {
63 reg = <1>; 92 reg = <1>;
64 device_type = "ethernet-phy"; 93 device_type = "ethernet-phy";
65 }; 94 };
66 Phy2: ethernet-phy@2 { 95
96 PHY2: ethernet-phy@2 {
67 reg = <2>; 97 reg = <2>;
68 device_type = "ethernet-phy"; 98 device_type = "ethernet-phy";
69 }; 99 };
70 }; 100 };
71 101
72 fec@e00 { 102 ethernet@e00 {
73 device_type = "network"; 103 device_type = "network";
74 compatible = "fs_enet"; 104 compatible = "fsl,mpc885-fec-enet",
75 model = "FEC"; 105 "fsl,pq1-fec-enet";
76 device-id = <1>;
77 reg = <e00 188>; 106 reg = <e00 188>;
78 mac-address = [ 00 00 0C 00 01 FD ]; 107 local-mac-address = [ 00 00 00 00 00 00 ];
79 interrupts = <3 1>; 108 interrupts = <3 1>;
80 interrupt-parent = <&Mpc8xx_pic>; 109 interrupt-parent = <&PIC>;
81 phy-handle = <&Phy1>; 110 phy-handle = <&PHY0>;
111 linux,network-index = <0>;
82 }; 112 };
83 113
84 fec@1e00 { 114 ethernet@1e00 {
85 device_type = "network"; 115 device_type = "network";
86 compatible = "fs_enet"; 116 compatible = "fsl,mpc885-fec-enet",
87 model = "FEC"; 117 "fsl,pq1-fec-enet";
88 device-id = <2>;
89 reg = <1e00 188>; 118 reg = <1e00 188>;
90 mac-address = [ 00 00 0C 00 02 FD ]; 119 local-mac-address = [ 00 00 00 00 00 00 ];
91 interrupts = <7 1>; 120 interrupts = <7 1>;
92 interrupt-parent = <&Mpc8xx_pic>; 121 interrupt-parent = <&PIC>;
93 phy-handle = <&Phy2>; 122 phy-handle = <&PHY1>;
123 linux,network-index = <1>;
94 }; 124 };
95 125
96 Mpc8xx_pic: pic@ff000000 { 126 PIC: interrupt-controller@0 {
97 interrupt-controller; 127 interrupt-controller;
98 #address-cells = <0>;
99 #interrupt-cells = <2>; 128 #interrupt-cells = <2>;
100 reg = <0 24>; 129 reg = <0 24>;
101 built-in; 130 compatible = "fsl,mpc885-pic", "fsl,pq1-pic";
102 device_type = "mpc8xx-pic";
103 compatible = "CPM";
104 }; 131 };
105 132
106 pcmcia@0080 { 133 pcmcia@80 {
107 #address-cells = <3>; 134 #address-cells = <3>;
108 #interrupt-cells = <1>; 135 #interrupt-cells = <1>;
109 #size-cells = <2>; 136 #size-cells = <2>;
110 compatible = "fsl,pq-pcmcia"; 137 compatible = "fsl,pq-pcmcia";
111 device_type = "pcmcia"; 138 device_type = "pcmcia";
112 reg = <80 80>; 139 reg = <80 80>;
113 interrupt-parent = <&Mpc8xx_pic>; 140 interrupt-parent = <&PIC>;
114 interrupts = <d 1>; 141 interrupts = <d 1>;
115 }; 142 };
116 143
117 cpm@ff000000 { 144 cpm@9c0 {
118 #address-cells = <1>; 145 #address-cells = <1>;
119 #size-cells = <1>; 146 #size-cells = <1>;
120 #interrupt-cells = <2>; 147 compatible = "fsl,mpc885-cpm", "fsl,cpm1";
121 device_type = "cpm";
122 model = "CPM";
123 ranges = <0 0 4000>;
124 reg = <860 f0>;
125 command-proc = <9c0>; 148 command-proc = <9c0>;
126 brg-frequency = <0>; 149 interrupts = <0>; // cpm error interrupt
127 interrupts = <0 2>; // cpm error interrupt 150 interrupt-parent = <&CPM_PIC>;
128 interrupt-parent = <&Cpm_pic>; 151 reg = <9c0 40>;
152 ranges;
153
154 muram@2000 {
155 #address-cells = <1>;
156 #size-cells = <1>;
157 ranges = <0 2000 2000>;
129 158
130 Cpm_pic: pic@930 { 159 data@0 {
160 compatible = "fsl,cpm-muram-data";
161 reg = <0 1c00>;
162 };
163 };
164
165 brg@9f0 {
166 compatible = "fsl,mpc885-brg",
167 "fsl,cpm1-brg",
168 "fsl,cpm-brg";
169 reg = <9f0 10>;
170 };
171
172 CPM_PIC: interrupt-controller@930 {
131 interrupt-controller; 173 interrupt-controller;
132 #address-cells = <0>; 174 #interrupt-cells = <1>;
133 #interrupt-cells = <2>;
134 interrupts = <5 2 0 2>; 175 interrupts = <5 2 0 2>;
135 interrupt-parent = <&Mpc8xx_pic>; 176 interrupt-parent = <&PIC>;
136 reg = <930 20>; 177 reg = <930 20>;
137 built-in; 178 compatible = "fsl,mpc885-cpm-pic",
138 device_type = "cpm-pic"; 179 "fsl,cpm1-pic";
139 compatible = "CPM";
140 }; 180 };
141 181
142 smc@a80 { 182 serial@a80 {
143 device_type = "serial"; 183 device_type = "serial";
144 compatible = "cpm_uart"; 184 compatible = "fsl,mpc885-smc-uart",
145 model = "SMC"; 185 "fsl,cpm1-smc-uart";
146 device-id = <1>;
147 reg = <a80 10 3e80 40>; 186 reg = <a80 10 3e80 40>;
148 clock-setup = <00ffffff 0>; 187 interrupts = <4>;
149 rx-clock = <1>; 188 interrupt-parent = <&CPM_PIC>;
150 tx-clock = <1>; 189 fsl,cpm-brg = <1>;
151 current-speed = <0>; 190 fsl,cpm-command = <0090>;
152 interrupts = <4 3>;
153 interrupt-parent = <&Cpm_pic>;
154 }; 191 };
155 192
156 smc@a90 { 193 serial@a90 {
157 device_type = "serial"; 194 device_type = "serial";
158 compatible = "cpm_uart"; 195 compatible = "fsl,mpc885-smc-uart",
159 model = "SMC"; 196 "fsl,cpm1-smc-uart";
160 device-id = <2>; 197 reg = <a90 10 3f80 40>;
161 reg = <a90 20 3f80 40>; 198 interrupts = <3>;
162 clock-setup = <ff00ffff 90000>; 199 interrupt-parent = <&CPM_PIC>;
163 rx-clock = <2>; 200 fsl,cpm-brg = <2>;
164 tx-clock = <2>; 201 fsl,cpm-command = <00d0>;
165 current-speed = <0>;
166 interrupts = <3 3>;
167 interrupt-parent = <&Cpm_pic>;
168 }; 202 };
169 203
170 scc@a40 { 204 ethernet@a40 {
171 device_type = "network"; 205 device_type = "network";
172 compatible = "fs_enet"; 206 compatible = "fsl,mpc885-scc-enet",
173 model = "SCC"; 207 "fsl,cpm1-scc-enet";
174 device-id = <3>; 208 reg = <a40 18 3e00 100>;
175 reg = <a40 18 3e00 80>; 209 local-mac-address = [ 00 00 00 00 00 00 ];
176 mac-address = [ 00 00 0C 00 03 FD ]; 210 interrupts = <1c>;
177 interrupts = <1c 3>; 211 interrupt-parent = <&CPM_PIC>;
178 interrupt-parent = <&Cpm_pic>; 212 phy-handle = <&PHY2>;
179 phy-handle = <&Phy2>; 213 fsl,cpm-command = <0080>;
214 linux,network-index = <2>;
180 }; 215 };
181 }; 216 };
182 }; 217 };
218
219 chosen {
220 linux,stdout-path = "/soc/cpm/serial@a80";
221 };
183}; 222};
diff --git a/arch/powerpc/boot/dts/pq2fads.dts b/arch/powerpc/boot/dts/pq2fads.dts
new file mode 100644
index 000000000000..2d564921897a
--- /dev/null
+++ b/arch/powerpc/boot/dts/pq2fads.dts
@@ -0,0 +1,240 @@
1/*
2 * Device Tree for the PQ2FADS-ZU board with an MPC8280 chip.
3 *
4 * Copyright 2007 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/ {
13 model = "pq2fads";
14 compatible = "fsl,pq2fads";
15 #address-cells = <1>;
16 #size-cells = <1>;
17
18 cpus {
19 #address-cells = <1>;
20 #size-cells = <0>;
21
22 cpu@0 {
23 device_type = "cpu";
24 reg = <0>;
25 d-cache-line-size = <d#32>;
26 i-cache-line-size = <d#32>;
27 d-cache-size = <d#16384>;
28 i-cache-size = <d#16384>;
29 timebase-frequency = <0>;
30 clock-frequency = <0>;
31 };
32 };
33
34 memory {
35 device_type = "memory";
36 reg = <0 0>;
37 };
38
39 localbus@f0010100 {
40 compatible = "fsl,mpc8280-localbus",
41 "fsl,pq2-localbus";
42 #address-cells = <2>;
43 #size-cells = <1>;
44 reg = <f0010100 60>;
45
46 ranges = <0 0 fe000000 00800000
47 1 0 f4500000 00008000
48 8 0 f8200000 00008000>;
49
50 flash@0,0 {
51 compatible = "jedec-flash";
52 reg = <0 0 800000>;
53 bank-width = <4>;
54 device-width = <1>;
55 };
56
57 bcsr@1,0 {
58 reg = <1 0 20>;
59 compatible = "fsl,pq2fads-bcsr";
60 };
61
62 PCI_PIC: pic@8,0 {
63 #interrupt-cells = <1>;
64 interrupt-controller;
65 reg = <8 0 8>;
66 compatible = "fsl,pq2ads-pci-pic";
67 interrupt-parent = <&PIC>;
68 interrupts = <18 8>;
69 };
70 };
71
72 pci@f0010800 {
73 device_type = "pci";
74 reg = <f0010800 10c f00101ac 8 f00101c4 8>;
75 compatible = "fsl,mpc8280-pci", "fsl,pq2-pci";
76 #interrupt-cells = <1>;
77 #size-cells = <2>;
78 #address-cells = <3>;
79 clock-frequency = <d#66000000>;
80 interrupt-map-mask = <f800 0 0 7>;
81 interrupt-map = <
82 /* IDSEL 0x16 */
83 b000 0 0 1 &PCI_PIC 0
84 b000 0 0 2 &PCI_PIC 1
85 b000 0 0 3 &PCI_PIC 2
86 b000 0 0 4 &PCI_PIC 3
87
88 /* IDSEL 0x17 */
89 b800 0 0 1 &PCI_PIC 4
90 b800 0 0 2 &PCI_PIC 5
91 b800 0 0 3 &PCI_PIC 6
92 b800 0 0 4 &PCI_PIC 7
93
94 /* IDSEL 0x18 */
95 c000 0 0 1 &PCI_PIC 8
96 c000 0 0 2 &PCI_PIC 9
97 c000 0 0 3 &PCI_PIC a
98 c000 0 0 4 &PCI_PIC b>;
99
100 interrupt-parent = <&PIC>;
101 interrupts = <12 8>;
102 ranges = <42000000 0 80000000 80000000 0 20000000
103 02000000 0 a0000000 a0000000 0 20000000
104 01000000 0 00000000 f6000000 0 02000000>;
105 };
106
107 soc@f0000000 {
108 #address-cells = <1>;
109 #size-cells = <1>;
110 device_type = "soc";
111 compatible = "fsl,mpc8280", "fsl,pq2-soc";
112 ranges = <00000000 f0000000 00053000>;
113
114 // Temporary -- will go away once kernel uses ranges for get_immrbase().
115 reg = <f0000000 00053000>;
116
117 cpm@119c0 {
118 #address-cells = <1>;
119 #size-cells = <1>;
120 #interrupt-cells = <2>;
121 compatible = "fsl,mpc8280-cpm", "fsl,cpm2";
122 reg = <119c0 30>;
123 ranges;
124
125 muram@0 {
126 #address-cells = <1>;
127 #size-cells = <1>;
128 ranges = <0 0 10000>;
129
130 data@0 {
131 compatible = "fsl,cpm-muram-data";
132 reg = <0 2000 9800 800>;
133 };
134 };
135
136 brg@119f0 {
137 compatible = "fsl,mpc8280-brg",
138 "fsl,cpm2-brg",
139 "fsl,cpm-brg";
140 reg = <119f0 10 115f0 10>;
141 };
142
143 serial@11a00 {
144 device_type = "serial";
145 compatible = "fsl,mpc8280-scc-uart",
146 "fsl,cpm2-scc-uart";
147 reg = <11a00 20 8000 100>;
148 interrupts = <28 8>;
149 interrupt-parent = <&PIC>;
150 fsl,cpm-brg = <1>;
151 fsl,cpm-command = <00800000>;
152 };
153
154 serial@11a20 {
155 device_type = "serial";
156 compatible = "fsl,mpc8280-scc-uart",
157 "fsl,cpm2-scc-uart";
158 reg = <11a20 20 8100 100>;
159 interrupts = <29 8>;
160 interrupt-parent = <&PIC>;
161 fsl,cpm-brg = <2>;
162 fsl,cpm-command = <04a00000>;
163 };
164
165 ethernet@11320 {
166 device_type = "network";
167 compatible = "fsl,mpc8280-fcc-enet",
168 "fsl,cpm2-fcc-enet";
169 reg = <11320 20 8500 100 113b0 1>;
170 interrupts = <21 8>;
171 interrupt-parent = <&PIC>;
172 phy-handle = <&PHY0>;
173 linux,network-index = <0>;
174 fsl,cpm-command = <16200300>;
175 };
176
177 ethernet@11340 {
178 device_type = "network";
179 compatible = "fsl,mpc8280-fcc-enet",
180 "fsl,cpm2-fcc-enet";
181 reg = <11340 20 8600 100 113d0 1>;
182 interrupts = <22 8>;
183 interrupt-parent = <&PIC>;
184 phy-handle = <&PHY1>;
185 linux,network-index = <1>;
186 fsl,cpm-command = <1a400300>;
187 local-mac-address = [00 e0 0c 00 79 01];
188 };
189
190 mdio@10d40 {
191 device_type = "mdio";
192 compatible = "fsl,pq2fads-mdio-bitbang",
193 "fsl,mpc8280-mdio-bitbang",
194 "fsl,cpm2-mdio-bitbang";
195 #address-cells = <1>;
196 #size-cells = <0>;
197 reg = <10d40 14>;
198 fsl,mdio-pin = <9>;
199 fsl,mdc-pin = <a>;
200
201 PHY0: ethernet-phy@0 {
202 interrupt-parent = <&PIC>;
203 interrupts = <19 2>;
204 reg = <0>;
205 device_type = "ethernet-phy";
206 };
207
208 PHY1: ethernet-phy@1 {
209 interrupt-parent = <&PIC>;
210 interrupts = <19 2>;
211 reg = <3>;
212 device_type = "ethernet-phy";
213 };
214 };
215
216 usb@11b60 {
217 #address-cells = <1>;
218 #size-cells = <0>;
219 compatible = "fsl,mpc8280-usb",
220 "fsl,cpm2-usb";
221 reg = <11b60 18 8b00 100>;
222 interrupt-parent = <&PIC>;
223 interrupts = <b 8>;
224 fsl,cpm-command = <2e600000>;
225 };
226 };
227
228 PIC: interrupt-controller@10c00 {
229 #interrupt-cells = <2>;
230 interrupt-controller;
231 reg = <10c00 80>;
232 compatible = "fsl,mpc8280-pic", "fsl,cpm2-pic";
233 };
234
235 };
236
237 chosen {
238 linux,stdout-path = "/soc/cpm/serial@11a00";
239 };
240};
diff --git a/arch/powerpc/boot/dts/prpmc2800.dts b/arch/powerpc/boot/dts/prpmc2800.dts
index 5300b50cdc2f..297dfa53fe9e 100644
--- a/arch/powerpc/boot/dts/prpmc2800.dts
+++ b/arch/powerpc/boot/dts/prpmc2800.dts
@@ -9,10 +9,6 @@
9 * 9 *
10 * Property values that are labeled as "Default" will be updated by bootwrapper 10 * Property values that are labeled as "Default" will be updated by bootwrapper
11 * if it can determine the exact PrPMC type. 11 * if it can determine the exact PrPMC type.
12 *
13 * To build:
14 * dtc -I dts -O asm -o prpmc2800.S -b 0 prpmc2800.dts
15 * dtc -I dts -O dtb -o prpmc2800.dtb -b 0 prpmc2800.dts
16 */ 12 */
17 13
18/ { 14/ {
@@ -47,7 +43,6 @@
47 mv64x60@f1000000 { /* Marvell Discovery */ 43 mv64x60@f1000000 { /* Marvell Discovery */
48 #address-cells = <1>; 44 #address-cells = <1>;
49 #size-cells = <1>; 45 #size-cells = <1>;
50 #interrupt-cells = <1>;
51 model = "mv64360"; /* Default */ 46 model = "mv64360"; /* Default */
52 compatible = "marvell,mv64x60"; 47 compatible = "marvell,mv64x60";
53 clock-frequency = <7f28155>; /* 133.333333 MHz */ 48 clock-frequency = <7f28155>; /* 133.333333 MHz */
diff --git a/arch/powerpc/boot/dts/sequoia.dts b/arch/powerpc/boot/dts/sequoia.dts
new file mode 100644
index 000000000000..36be75b04de1
--- /dev/null
+++ b/arch/powerpc/boot/dts/sequoia.dts
@@ -0,0 +1,302 @@
1/*
2 * Device Tree Source for AMCC Sequoia
3 *
4 * Based on Bamboo code by Josh Boyer <jwboyer@linux.vnet.ibm.com>
5 * Copyright (c) 2006, 2007 IBM Corp.
6 *
7 * FIXME: Draft only!
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without
11 * any warranty of any kind, whether express or implied.
12 *
13 */
14
15/ {
16 #address-cells = <2>;
17 #size-cells = <1>;
18 model = "amcc,sequoia";
19 compatible = "amcc,sequoia";
20 dcr-parent = <&/cpus/PowerPC,440EPx@0>;
21
22 cpus {
23 #address-cells = <1>;
24 #size-cells = <0>;
25
26 PowerPC,440EPx@0 {
27 device_type = "cpu";
28 reg = <0>;
29 clock-frequency = <0>; /* Filled in by zImage */
30 timebase-frequency = <0>; /* Filled in by zImage */
31 i-cache-line-size = <20>;
32 d-cache-line-size = <20>;
33 i-cache-size = <8000>;
34 d-cache-size = <8000>;
35 dcr-controller;
36 dcr-access-method = "native";
37 };
38 };
39
40 memory {
41 device_type = "memory";
42 reg = <0 0 0>; /* Filled in by zImage */
43 };
44
45 UIC0: interrupt-controller0 {
46 compatible = "ibm,uic-440epx","ibm,uic";
47 interrupt-controller;
48 cell-index = <0>;
49 dcr-reg = <0c0 009>;
50 #address-cells = <0>;
51 #size-cells = <0>;
52 #interrupt-cells = <2>;
53 };
54
55 UIC1: interrupt-controller1 {
56 compatible = "ibm,uic-440epx","ibm,uic";
57 interrupt-controller;
58 cell-index = <1>;
59 dcr-reg = <0d0 009>;
60 #address-cells = <0>;
61 #size-cells = <0>;
62 #interrupt-cells = <2>;
63 interrupts = <1e 4 1f 4>; /* cascade */
64 interrupt-parent = <&UIC0>;
65 };
66
67 UIC2: interrupt-controller2 {
68 compatible = "ibm,uic-440epx","ibm,uic";
69 interrupt-controller;
70 cell-index = <2>;
71 dcr-reg = <0e0 009>;
72 #address-cells = <0>;
73 #size-cells = <0>;
74 #interrupt-cells = <2>;
75 interrupts = <1c 4 1d 4>; /* cascade */
76 interrupt-parent = <&UIC0>;
77 };
78
79 SDR0: sdr {
80 compatible = "ibm,sdr-440epx", "ibm,sdr-440ep";
81 dcr-reg = <00e 002>;
82 };
83
84 CPR0: cpr {
85 compatible = "ibm,cpr-440epx", "ibm,cpr-440ep";
86 dcr-reg = <00c 002>;
87 };
88
89 plb {
90 compatible = "ibm,plb-440epx", "ibm,plb4";
91 #address-cells = <2>;
92 #size-cells = <1>;
93 ranges;
94 clock-frequency = <0>; /* Filled in by zImage */
95
96 SDRAM0: sdram {
97 device_type = "memory-controller";
98 compatible = "ibm,sdram-440epx", "ibm,sdram-44x-ddr2denali";
99 dcr-reg = <010 2>;
100 };
101
102 DMA0: dma {
103 compatible = "ibm,dma-440epx", "ibm,dma-4xx";
104 dcr-reg = <100 027>;
105 };
106
107 MAL0: mcmal {
108 compatible = "ibm,mcmal-440epx", "ibm,mcmal2";
109 dcr-reg = <180 62>;
110 num-tx-chans = <2>;
111 num-rx-chans = <2>;
112 interrupt-parent = <&MAL0>;
113 interrupts = <0 1 2 3 4>;
114 #interrupt-cells = <1>;
115 #address-cells = <0>;
116 #size-cells = <0>;
117 interrupt-map = </*TXEOB*/ 0 &UIC0 a 4
118 /*RXEOB*/ 1 &UIC0 b 4
119 /*SERR*/ 2 &UIC1 0 4
120 /*TXDE*/ 3 &UIC1 1 4
121 /*RXDE*/ 4 &UIC1 2 4>;
122 interrupt-map-mask = <ffffffff>;
123 };
124
125 POB0: opb {
126 compatible = "ibm,opb-440epx", "ibm,opb";
127 #address-cells = <1>;
128 #size-cells = <1>;
129 ranges = <00000000 1 00000000 80000000
130 80000000 1 80000000 80000000>;
131 interrupt-parent = <&UIC1>;
132 interrupts = <7 4>;
133 clock-frequency = <0>; /* Filled in by zImage */
134
135 EBC0: ebc {
136 compatible = "ibm,ebc-440epx", "ibm,ebc";
137 dcr-reg = <012 2>;
138 #address-cells = <2>;
139 #size-cells = <1>;
140 clock-frequency = <0>; /* Filled in by zImage */
141 interrupts = <5 1>;
142 interrupt-parent = <&UIC1>;
143
144 nor_flash@0,0 {
145 compatible = "amd,s29gl256n", "cfi-flash";
146 bank-width = <2>;
147 reg = <0 000000 4000000>;
148 #address-cells = <1>;
149 #size-cells = <1>;
150 partition@0 {
151 label = "Kernel";
152 reg = <0 180000>;
153 };
154 partition@180000 {
155 label = "ramdisk";
156 reg = <180000 200000>;
157 };
158 partition@380000 {
159 label = "file system";
160 reg = <380000 3aa0000>;
161 };
162 partition@3e20000 {
163 label = "kozio";
164 reg = <3e20000 140000>;
165 };
166 partition@3f60000 {
167 label = "env";
168 reg = <3f60000 40000>;
169 };
170 partition@3fa0000 {
171 label = "u-boot";
172 reg = <3fa0000 60000>;
173 };
174 };
175
176 };
177
178 UART0: serial@ef600300 {
179 device_type = "serial";
180 compatible = "ns16550";
181 reg = <ef600300 8>;
182 virtual-reg = <ef600300>;
183 clock-frequency = <0>; /* Filled in by zImage */
184 current-speed = <1c200>;
185 interrupt-parent = <&UIC0>;
186 interrupts = <0 4>;
187 };
188
189 UART1: serial@ef600400 {
190 device_type = "serial";
191 compatible = "ns16550";
192 reg = <ef600400 8>;
193 virtual-reg = <ef600400>;
194 clock-frequency = <0>;
195 current-speed = <0>;
196 interrupt-parent = <&UIC0>;
197 interrupts = <1 4>;
198 };
199
200 UART2: serial@ef600500 {
201 device_type = "serial";
202 compatible = "ns16550";
203 reg = <ef600500 8>;
204 virtual-reg = <ef600500>;
205 clock-frequency = <0>;
206 current-speed = <0>;
207 interrupt-parent = <&UIC1>;
208 interrupts = <3 4>;
209 };
210
211 UART3: serial@ef600600 {
212 device_type = "serial";
213 compatible = "ns16550";
214 reg = <ef600600 8>;
215 virtual-reg = <ef600600>;
216 clock-frequency = <0>;
217 current-speed = <0>;
218 interrupt-parent = <&UIC1>;
219 interrupts = <4 4>;
220 };
221
222 IIC0: i2c@ef600700 {
223 device_type = "i2c";
224 compatible = "ibm,iic-440epx", "ibm,iic";
225 reg = <ef600700 14>;
226 interrupt-parent = <&UIC0>;
227 interrupts = <2 4>;
228 };
229
230 IIC1: i2c@ef600800 {
231 device_type = "i2c";
232 compatible = "ibm,iic-440epx", "ibm,iic";
233 reg = <ef600800 14>;
234 interrupt-parent = <&UIC0>;
235 interrupts = <7 4>;
236 };
237
238 ZMII0: emac-zmii@ef600d00 {
239 device_type = "zmii-interface";
240 compatible = "ibm,zmii-440epx", "ibm,zmii";
241 reg = <ef600d00 c>;
242 };
243
244 EMAC0: ethernet@ef600e00 {
245 linux,network-index = <0>;
246 device_type = "network";
247 compatible = "ibm,emac-440epx", "ibm,emac4";
248 interrupt-parent = <&EMAC0>;
249 interrupts = <0 1>;
250 #interrupt-cells = <1>;
251 #address-cells = <0>;
252 #size-cells = <0>;
253 interrupt-map = </*Status*/ 0 &UIC0 18 4
254 /*Wake*/ 1 &UIC1 1d 4>;
255 reg = <ef600e00 70>;
256 local-mac-address = [000000000000];
257 mal-device = <&MAL0>;
258 mal-tx-channel = <0>;
259 mal-rx-channel = <0>;
260 cell-index = <0>;
261 max-frame-size = <5dc>;
262 rx-fifo-size = <1000>;
263 tx-fifo-size = <800>;
264 phy-mode = "rmii";
265 phy-map = <00000000>;
266 zmii-device = <&ZMII0>;
267 zmii-channel = <0>;
268 };
269
270 EMAC1: ethernet@ef600f00 {
271 linux,network-index = <1>;
272 device_type = "network";
273 compatible = "ibm,emac-440epx", "ibm,emac4";
274 interrupt-parent = <&EMAC1>;
275 interrupts = <0 1>;
276 #interrupt-cells = <1>;
277 #address-cells = <0>;
278 #size-cells = <0>;
279 interrupt-map = </*Status*/ 0 &UIC0 19 4
280 /*Wake*/ 1 &UIC1 1f 4>;
281 reg = <ef600f00 70>;
282 local-mac-address = [000000000000];
283 mal-device = <&MAL0>;
284 mal-tx-channel = <1>;
285 mal-rx-channel = <1>;
286 cell-index = <1>;
287 max-frame-size = <5dc>;
288 rx-fifo-size = <1000>;
289 tx-fifo-size = <800>;
290 phy-mode = "rmii";
291 phy-map = <00000000>;
292 zmii-device = <&ZMII0>;
293 zmii-channel = <1>;
294 };
295 };
296 };
297
298 chosen {
299 linux,stdout-path = "/plb/opb/serial@ef600300";
300 bootargs = "console=ttyS0,115200";
301 };
302};
diff --git a/arch/powerpc/boot/dts/walnut.dts b/arch/powerpc/boot/dts/walnut.dts
new file mode 100644
index 000000000000..ec54f4e04ad6
--- /dev/null
+++ b/arch/powerpc/boot/dts/walnut.dts
@@ -0,0 +1,190 @@
1/*
2 * Device Tree Source for IBM Walnut
3 *
4 * Copyright 2007 IBM Corp.
5 * Josh Boyer <jwboyer@linux.vnet.ibm.com>
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without
9 * any warranty of any kind, whether express or implied.
10 */
11
12/ {
13 #address-cells = <1>;
14 #size-cells = <1>;
15 model = "ibm,walnut";
16 compatible = "ibm,walnut";
17 dcr-parent = <&/cpus/PowerPC,405GP@0>;
18
19 cpus {
20 #address-cells = <1>;
21 #size-cells = <0>;
22
23 PowerPC,405GP@0 {
24 device_type = "cpu";
25 reg = <0>;
26 clock-frequency = <bebc200>; /* Filled in by zImage */
27 timebase-frequency = <0>; /* Filled in by zImage */
28 i-cache-line-size = <20>;
29 d-cache-line-size = <20>;
30 i-cache-size = <4000>;
31 d-cache-size = <4000>;
32 dcr-controller;
33 dcr-access-method = "native";
34 };
35 };
36
37 memory {
38 device_type = "memory";
39 reg = <0 0>; /* Filled in by zImage */
40 };
41
42 UIC0: interrupt-controller {
43 compatible = "ibm,uic";
44 interrupt-controller;
45 cell-index = <0>;
46 dcr-reg = <0c0 9>;
47 #address-cells = <0>;
48 #size-cells = <0>;
49 #interrupt-cells = <2>;
50 };
51
52 plb {
53 compatible = "ibm,plb3";
54 #address-cells = <1>;
55 #size-cells = <1>;
56 ranges;
57 clock-frequency = <0>; /* Filled in by zImage */
58
59 SDRAM0: memory-controller {
60 compatible = "ibm,sdram-405gp";
61 dcr-reg = <010 2>;
62 };
63
64 MAL: mcmal {
65 compatible = "ibm,mcmal-405gp", "ibm,mcmal";
66 dcr-reg = <180 62>;
67 num-tx-chans = <2>;
68 num-rx-chans = <1>;
69 interrupt-parent = <&UIC0>;
70 interrupts = <a 4 b 4 c 4 d 4 e 4>;
71 };
72
73 POB0: opb {
74 compatible = "ibm,opb-405gp", "ibm,opb";
75 #address-cells = <1>;
76 #size-cells = <1>;
77 ranges = <ef600000 ef600000 a00000>;
78 dcr-reg = <0a0 5>;
79 clock-frequency = <0>; /* Filled in by zImage */
80
81 UART0: serial@ef600300 {
82 device_type = "serial";
83 compatible = "ns16550";
84 reg = <ef600300 8>;
85 virtual-reg = <ef600300>;
86 clock-frequency = <0>; /* Filled in by zImage */
87 current-speed = <2580>;
88 interrupt-parent = <&UIC0>;
89 interrupts = <0 4>;
90 };
91
92 UART1: serial@ef600400 {
93 device_type = "serial";
94 compatible = "ns16550";
95 reg = <ef600400 8>;
96 virtual-reg = <ef600400>;
97 clock-frequency = <0>; /* Filled in by zImage */
98 current-speed = <2580>;
99 interrupt-parent = <&UIC0>;
100 interrupts = <1 4>;
101 };
102
103 IIC: i2c@ef600500 {
104 compatible = "ibm,iic-405gp", "ibm,iic";
105 reg = <ef600500 11>;
106 interrupt-parent = <&UIC0>;
107 interrupts = <2 4>;
108 };
109
110 GPIO: gpio@ef600700 {
111 compatible = "ibm,gpio-405gp";
112 reg = <ef600700 20>;
113 };
114
115 EMAC: ethernet@ef600800 {
116 linux,network-index = <0>;
117 device_type = "network";
118 compatible = "ibm,emac-405gp", "ibm,emac";
119 interrupt-parent = <&UIC0>;
120 interrupts = <9 4 f 4>;
121 reg = <ef600800 70>;
122 mal-device = <&MAL>;
123 mal-tx-channel = <0 1>;
124 mal-rx-channel = <0>;
125 cell-index = <0>;
126 max-frame-size = <5dc>;
127 rx-fifo-size = <1000>;
128 tx-fifo-size = <800>;
129 phy-mode = "rmii";
130 phy-map = <00000001>;
131 };
132
133 };
134
135 EBC0: ebc {
136 compatible = "ibm,ebc-405gp", "ibm,ebc";
137 dcr-reg = <012 2>;
138 #address-cells = <2>;
139 #size-cells = <1>;
140 /* The ranges property is supplied by the bootwrapper
141 * and is based on the firmware's configuration of the
142 * EBC bridge
143 */
144 clock-frequency = <0>; /* Filled in by zImage */
145
146 sram@0,0 {
147 reg = <0 0 80000>;
148 };
149
150 flash@0,80000 {
151 compatible = "jedec-flash";
152 bank-width = <1>;
153 reg = <0 80000 80000>;
154 #address-cells = <1>;
155 #size-cells = <1>;
156 partition@0 {
157 label = "OpenBIOS";
158 reg = <0 80000>;
159 read-only;
160 };
161 };
162
163 ds1743@1,0 {
164 /* NVRAM and RTC */
165 compatible = "ds1743";
166 reg = <1 0 2000>;
167 };
168
169 keyboard@2,0 {
170 compatible = "intel,82C42PC";
171 reg = <2 0 2>;
172 };
173
174 ir@3,0 {
175 compatible = "ti,TIR2000PAG";
176 reg = <3 0 10>;
177 };
178
179 fpga@7,0 {
180 compatible = "Walnut-FPGA";
181 reg = <7 0 10>;
182 virtual-reg = <f0300005>;
183 };
184 };
185 };
186
187 chosen {
188 linux,stdout-path = "/plb/opb/serial@ef600300";
189 };
190};
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-26 05:36:00 -0500