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-rw-r--r--arch/powerpc/boot/dts/bsc9131rdb.dtsi2
-rw-r--r--arch/powerpc/boot/dts/fsl/p1010si-post.dtsi4
-rw-r--r--arch/powerpc/boot/dts/fsl/p1022si-post.dtsi6
-rw-r--r--arch/powerpc/boot/dts/fsl/p2041si-post.dtsi87
-rw-r--r--arch/powerpc/boot/dts/fsl/p3041si-post.dtsi87
-rw-r--r--arch/powerpc/boot/dts/fsl/p4080si-post.dtsi74
-rw-r--r--arch/powerpc/boot/dts/fsl/p5020si-post.dtsi92
-rw-r--r--arch/powerpc/boot/dts/fsl/p5040si-post.dtsi92
-rw-r--r--arch/powerpc/boot/dts/fsl/pq3-sec4.4-0.dtsi1
-rw-r--r--arch/powerpc/boot/dts/ppa8548.dts166
-rw-r--r--arch/powerpc/boot/dts/sbc8548-altflash.dts115
-rw-r--r--arch/powerpc/boot/dts/sbc8548-post.dtsi295
-rw-r--r--arch/powerpc/boot/dts/sbc8548-pre.dtsi52
-rw-r--r--arch/powerpc/boot/dts/sbc8548.dts356
14 files changed, 1035 insertions, 394 deletions
diff --git a/arch/powerpc/boot/dts/bsc9131rdb.dtsi b/arch/powerpc/boot/dts/bsc9131rdb.dtsi
index 638adda2c218..9e6c01339ccc 100644
--- a/arch/powerpc/boot/dts/bsc9131rdb.dtsi
+++ b/arch/powerpc/boot/dts/bsc9131rdb.dtsi
@@ -126,7 +126,7 @@
126 }; 126 };
127 }; 127 };
128 128
129 sdhci@2e000 { 129 sdhc@2e000 {
130 status = "disabled"; 130 status = "disabled";
131 }; 131 };
132 132
diff --git a/arch/powerpc/boot/dts/fsl/p1010si-post.dtsi b/arch/powerpc/boot/dts/fsl/p1010si-post.dtsi
index 0bde9ee8afaf..af12ead88c5f 100644
--- a/arch/powerpc/boot/dts/fsl/p1010si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p1010si-post.dtsi
@@ -41,7 +41,7 @@
41 41
42/* controller at 0x9000 */ 42/* controller at 0x9000 */
43&pci0 { 43&pci0 {
44 compatible = "fsl,p1010-pcie", "fsl,qoriq-pcie-v2.3", "fsl,qoriq-pcie-v2.2"; 44 compatible = "fsl,p1010-pcie", "fsl,qoriq-pcie-v2.3";
45 device_type = "pci"; 45 device_type = "pci";
46 #size-cells = <2>; 46 #size-cells = <2>;
47 #address-cells = <3>; 47 #address-cells = <3>;
@@ -69,7 +69,7 @@
69 69
70/* controller at 0xa000 */ 70/* controller at 0xa000 */
71&pci1 { 71&pci1 {
72 compatible = "fsl,p1010-pcie", "fsl,qoriq-pcie-v2.3", "fsl,qoriq-pcie-v2.2"; 72 compatible = "fsl,p1010-pcie", "fsl,qoriq-pcie-v2.3";
73 device_type = "pci"; 73 device_type = "pci";
74 #size-cells = <2>; 74 #size-cells = <2>;
75 #address-cells = <3>; 75 #address-cells = <3>;
diff --git a/arch/powerpc/boot/dts/fsl/p1022si-post.dtsi b/arch/powerpc/boot/dts/fsl/p1022si-post.dtsi
index 06216b8c0af5..e179803a81ef 100644
--- a/arch/powerpc/boot/dts/fsl/p1022si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p1022si-post.dtsi
@@ -45,7 +45,7 @@
45 45
46/* controller at 0x9000 */ 46/* controller at 0x9000 */
47&pci0 { 47&pci0 {
48 compatible = "fsl,p1022-pcie"; 48 compatible = "fsl,mpc8548-pcie";
49 device_type = "pci"; 49 device_type = "pci";
50 #size-cells = <2>; 50 #size-cells = <2>;
51 #address-cells = <3>; 51 #address-cells = <3>;
@@ -73,7 +73,7 @@
73 73
74/* controller at 0xa000 */ 74/* controller at 0xa000 */
75&pci1 { 75&pci1 {
76 compatible = "fsl,p1022-pcie"; 76 compatible = "fsl,mpc8548-pcie";
77 device_type = "pci"; 77 device_type = "pci";
78 #size-cells = <2>; 78 #size-cells = <2>;
79 #address-cells = <3>; 79 #address-cells = <3>;
@@ -102,7 +102,7 @@
102 102
103/* controller at 0xb000 */ 103/* controller at 0xb000 */
104&pci2 { 104&pci2 {
105 compatible = "fsl,p1022-pcie"; 105 compatible = "fsl,mpc8548-pcie";
106 device_type = "pci"; 106 device_type = "pci";
107 #size-cells = <2>; 107 #size-cells = <2>;
108 #address-cells = <3>; 108 #address-cells = <3>;
diff --git a/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi b/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
index 531eab82c6c9..69ac1acd4349 100644
--- a/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
@@ -48,6 +48,8 @@
48 bus-range = <0x0 0xff>; 48 bus-range = <0x0 0xff>;
49 clock-frequency = <33333333>; 49 clock-frequency = <33333333>;
50 interrupts = <16 2 1 15>; 50 interrupts = <16 2 1 15>;
51 fsl,iommu-parent = <&pamu0>;
52 fsl,liodn-reg = <&guts 0x500>; /* PEX1LIODNR */
51 pcie@0 { 53 pcie@0 {
52 reg = <0 0 0 0 0>; 54 reg = <0 0 0 0 0>;
53 #interrupt-cells = <1>; 55 #interrupt-cells = <1>;
@@ -75,6 +77,8 @@
75 bus-range = <0 0xff>; 77 bus-range = <0 0xff>;
76 clock-frequency = <33333333>; 78 clock-frequency = <33333333>;
77 interrupts = <16 2 1 14>; 79 interrupts = <16 2 1 14>;
80 fsl,iommu-parent = <&pamu0>;
81 fsl,liodn-reg = <&guts 0x504>; /* PEX2LIODNR */
78 pcie@0 { 82 pcie@0 {
79 reg = <0 0 0 0 0>; 83 reg = <0 0 0 0 0>;
80 #interrupt-cells = <1>; 84 #interrupt-cells = <1>;
@@ -102,6 +106,8 @@
102 bus-range = <0x0 0xff>; 106 bus-range = <0x0 0xff>;
103 clock-frequency = <33333333>; 107 clock-frequency = <33333333>;
104 interrupts = <16 2 1 13>; 108 interrupts = <16 2 1 13>;
109 fsl,iommu-parent = <&pamu0>;
110 fsl,liodn-reg = <&guts 0x508>; /* PEX3LIODNR */
105 pcie@0 { 111 pcie@0 {
106 reg = <0 0 0 0 0>; 112 reg = <0 0 0 0 0>;
107 #interrupt-cells = <1>; 113 #interrupt-cells = <1>;
@@ -125,18 +131,21 @@
125 interrupts = <16 2 1 11>; 131 interrupts = <16 2 1 11>;
126 #address-cells = <2>; 132 #address-cells = <2>;
127 #size-cells = <2>; 133 #size-cells = <2>;
134 fsl,iommu-parent = <&pamu0>;
128 ranges; 135 ranges;
129 136
130 port1 { 137 port1 {
131 #address-cells = <2>; 138 #address-cells = <2>;
132 #size-cells = <2>; 139 #size-cells = <2>;
133 cell-index = <1>; 140 cell-index = <1>;
141 fsl,liodn-reg = <&guts 0x510>; /* RIO1LIODNR */
134 }; 142 };
135 143
136 port2 { 144 port2 {
137 #address-cells = <2>; 145 #address-cells = <2>;
138 #size-cells = <2>; 146 #size-cells = <2>;
139 cell-index = <2>; 147 cell-index = <2>;
148 fsl,liodn-reg = <&guts 0x514>; /* RIO2LIODNR */
140 }; 149 };
141}; 150};
142 151
@@ -246,10 +255,37 @@
246 255
247 iommu@20000 { 256 iommu@20000 {
248 compatible = "fsl,pamu-v1.0", "fsl,pamu"; 257 compatible = "fsl,pamu-v1.0", "fsl,pamu";
249 reg = <0x20000 0x4000>; 258 reg = <0x20000 0x4000>; /* for compatibility with older PAMU drivers */
259 ranges = <0 0x20000 0x4000>;
260 #address-cells = <1>;
261 #size-cells = <1>;
250 interrupts = < 262 interrupts = <
251 24 2 0 0 263 24 2 0 0
252 16 2 1 30>; 264 16 2 1 30>;
265
266 pamu0: pamu@0 {
267 reg = <0 0x1000>;
268 fsl,primary-cache-geometry = <32 1>;
269 fsl,secondary-cache-geometry = <128 2>;
270 };
271
272 pamu1: pamu@1000 {
273 reg = <0x1000 0x1000>;
274 fsl,primary-cache-geometry = <32 1>;
275 fsl,secondary-cache-geometry = <128 2>;
276 };
277
278 pamu2: pamu@2000 {
279 reg = <0x2000 0x1000>;
280 fsl,primary-cache-geometry = <32 1>;
281 fsl,secondary-cache-geometry = <128 2>;
282 };
283
284 pamu3: pamu@3000 {
285 reg = <0x3000 0x1000>;
286 fsl,primary-cache-geometry = <32 1>;
287 fsl,secondary-cache-geometry = <128 2>;
288 };
253 }; 289 };
254 290
255/include/ "qoriq-mpic.dtsi" 291/include/ "qoriq-mpic.dtsi"
@@ -291,7 +327,17 @@
291 }; 327 };
292 328
293/include/ "qoriq-dma-0.dtsi" 329/include/ "qoriq-dma-0.dtsi"
330 dma@100300 {
331 fsl,iommu-parent = <&pamu0>;
332 fsl,liodn-reg = <&guts 0x580>; /* DMA1LIODNR */
333 };
334
294/include/ "qoriq-dma-1.dtsi" 335/include/ "qoriq-dma-1.dtsi"
336 dma@101300 {
337 fsl,iommu-parent = <&pamu0>;
338 fsl,liodn-reg = <&guts 0x584>; /* DMA2LIODNR */
339 };
340
295/include/ "qoriq-espi-0.dtsi" 341/include/ "qoriq-espi-0.dtsi"
296 spi@110000 { 342 spi@110000 {
297 fsl,espi-num-chipselects = <4>; 343 fsl,espi-num-chipselects = <4>;
@@ -299,6 +345,8 @@
299 345
300/include/ "qoriq-esdhc-0.dtsi" 346/include/ "qoriq-esdhc-0.dtsi"
301 sdhc@114000 { 347 sdhc@114000 {
348 fsl,iommu-parent = <&pamu1>;
349 fsl,liodn-reg = <&guts 0x530>; /* eSDHCLIODNR */
302 sdhci,auto-cmd12; 350 sdhci,auto-cmd12;
303 }; 351 };
304 352
@@ -308,20 +356,37 @@
308/include/ "qoriq-duart-1.dtsi" 356/include/ "qoriq-duart-1.dtsi"
309/include/ "qoriq-gpio-0.dtsi" 357/include/ "qoriq-gpio-0.dtsi"
310/include/ "qoriq-usb2-mph-0.dtsi" 358/include/ "qoriq-usb2-mph-0.dtsi"
311 usb0: usb@210000 { 359 usb0: usb@210000 {
312 compatible = "fsl-usb2-mph-v1.6", "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph"; 360 compatible = "fsl-usb2-mph-v1.6", "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
313 phy_type = "utmi"; 361 phy_type = "utmi";
314 port0; 362 fsl,iommu-parent = <&pamu1>;
315 }; 363 fsl,liodn-reg = <&guts 0x520>; /* USB1LIODNR */
364 port0;
365 };
316 366
317/include/ "qoriq-usb2-dr-0.dtsi" 367/include/ "qoriq-usb2-dr-0.dtsi"
318 usb1: usb@211000 { 368 usb1: usb@211000 {
319 compatible = "fsl-usb2-dr-v1.6", "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr"; 369 compatible = "fsl-usb2-dr-v1.6", "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
320 dr_mode = "host"; 370 fsl,iommu-parent = <&pamu1>;
321 phy_type = "utmi"; 371 fsl,liodn-reg = <&guts 0x524>; /* USB2LIODNR */
322 }; 372 dr_mode = "host";
373 phy_type = "utmi";
374 };
323 375
324/include/ "qoriq-sata2-0.dtsi" 376/include/ "qoriq-sata2-0.dtsi"
377 sata@220000 {
378 fsl,iommu-parent = <&pamu1>;
379 fsl,liodn-reg = <&guts 0x550>; /* SATA1LIODNR */
380 };
381
325/include/ "qoriq-sata2-1.dtsi" 382/include/ "qoriq-sata2-1.dtsi"
383 sata@221000 {
384 fsl,iommu-parent = <&pamu1>;
385 fsl,liodn-reg = <&guts 0x554>; /* SATA2LIODNR */
386 };
387
326/include/ "qoriq-sec4.2-0.dtsi" 388/include/ "qoriq-sec4.2-0.dtsi"
389crypto: crypto@300000 {
390 fsl,iommu-parent = <&pamu1>;
391 };
327}; 392};
diff --git a/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi b/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
index af4ebc8009e3..9b5a81a4529c 100644
--- a/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
@@ -48,6 +48,8 @@
48 bus-range = <0x0 0xff>; 48 bus-range = <0x0 0xff>;
49 clock-frequency = <33333333>; 49 clock-frequency = <33333333>;
50 interrupts = <16 2 1 15>; 50 interrupts = <16 2 1 15>;
51 fsl,iommu-parent = <&pamu0>;
52 fsl,liodn-reg = <&guts 0x500>; /* PEX1LIODNR */
51 pcie@0 { 53 pcie@0 {
52 reg = <0 0 0 0 0>; 54 reg = <0 0 0 0 0>;
53 #interrupt-cells = <1>; 55 #interrupt-cells = <1>;
@@ -75,6 +77,8 @@
75 bus-range = <0 0xff>; 77 bus-range = <0 0xff>;
76 clock-frequency = <33333333>; 78 clock-frequency = <33333333>;
77 interrupts = <16 2 1 14>; 79 interrupts = <16 2 1 14>;
80 fsl,iommu-parent = <&pamu0>;
81 fsl,liodn-reg = <&guts 0x504>; /* PEX2LIODNR */
78 pcie@0 { 82 pcie@0 {
79 reg = <0 0 0 0 0>; 83 reg = <0 0 0 0 0>;
80 #interrupt-cells = <1>; 84 #interrupt-cells = <1>;
@@ -102,6 +106,8 @@
102 bus-range = <0x0 0xff>; 106 bus-range = <0x0 0xff>;
103 clock-frequency = <33333333>; 107 clock-frequency = <33333333>;
104 interrupts = <16 2 1 13>; 108 interrupts = <16 2 1 13>;
109 fsl,iommu-parent = <&pamu0>;
110 fsl,liodn-reg = <&guts 0x508>; /* PEX3LIODNR */
105 pcie@0 { 111 pcie@0 {
106 reg = <0 0 0 0 0>; 112 reg = <0 0 0 0 0>;
107 #interrupt-cells = <1>; 113 #interrupt-cells = <1>;
@@ -152,18 +158,21 @@
152 interrupts = <16 2 1 11>; 158 interrupts = <16 2 1 11>;
153 #address-cells = <2>; 159 #address-cells = <2>;
154 #size-cells = <2>; 160 #size-cells = <2>;
161 fsl,iommu-parent = <&pamu0>;
155 ranges; 162 ranges;
156 163
157 port1 { 164 port1 {
158 #address-cells = <2>; 165 #address-cells = <2>;
159 #size-cells = <2>; 166 #size-cells = <2>;
160 cell-index = <1>; 167 cell-index = <1>;
168 fsl,liodn-reg = <&guts 0x510>; /* RIO1LIODNR */
161 }; 169 };
162 170
163 port2 { 171 port2 {
164 #address-cells = <2>; 172 #address-cells = <2>;
165 #size-cells = <2>; 173 #size-cells = <2>;
166 cell-index = <2>; 174 cell-index = <2>;
175 fsl,liodn-reg = <&guts 0x514>; /* RIO2LIODNR */
167 }; 176 };
168}; 177};
169 178
@@ -273,10 +282,37 @@
273 282
274 iommu@20000 { 283 iommu@20000 {
275 compatible = "fsl,pamu-v1.0", "fsl,pamu"; 284 compatible = "fsl,pamu-v1.0", "fsl,pamu";
276 reg = <0x20000 0x4000>; 285 reg = <0x20000 0x4000>; /* for compatibility with older PAMU drivers */
286 ranges = <0 0x20000 0x4000>;
287 #address-cells = <1>;
288 #size-cells = <1>;
277 interrupts = < 289 interrupts = <
278 24 2 0 0 290 24 2 0 0
279 16 2 1 30>; 291 16 2 1 30>;
292
293 pamu0: pamu@0 {
294 reg = <0 0x1000>;
295 fsl,primary-cache-geometry = <32 1>;
296 fsl,secondary-cache-geometry = <128 2>;
297 };
298
299 pamu1: pamu@1000 {
300 reg = <0x1000 0x1000>;
301 fsl,primary-cache-geometry = <32 1>;
302 fsl,secondary-cache-geometry = <128 2>;
303 };
304
305 pamu2: pamu@2000 {
306 reg = <0x2000 0x1000>;
307 fsl,primary-cache-geometry = <32 1>;
308 fsl,secondary-cache-geometry = <128 2>;
309 };
310
311 pamu3: pamu@3000 {
312 reg = <0x3000 0x1000>;
313 fsl,primary-cache-geometry = <32 1>;
314 fsl,secondary-cache-geometry = <128 2>;
315 };
280 }; 316 };
281 317
282/include/ "qoriq-mpic.dtsi" 318/include/ "qoriq-mpic.dtsi"
@@ -318,7 +354,17 @@
318 }; 354 };
319 355
320/include/ "qoriq-dma-0.dtsi" 356/include/ "qoriq-dma-0.dtsi"
357 dma@100300 {
358 fsl,iommu-parent = <&pamu0>;
359 fsl,liodn-reg = <&guts 0x580>; /* DMA1LIODNR */
360 };
361
321/include/ "qoriq-dma-1.dtsi" 362/include/ "qoriq-dma-1.dtsi"
363 dma@101300 {
364 fsl,iommu-parent = <&pamu0>;
365 fsl,liodn-reg = <&guts 0x584>; /* DMA2LIODNR */
366 };
367
322/include/ "qoriq-espi-0.dtsi" 368/include/ "qoriq-espi-0.dtsi"
323 spi@110000 { 369 spi@110000 {
324 fsl,espi-num-chipselects = <4>; 370 fsl,espi-num-chipselects = <4>;
@@ -326,6 +372,8 @@
326 372
327/include/ "qoriq-esdhc-0.dtsi" 373/include/ "qoriq-esdhc-0.dtsi"
328 sdhc@114000 { 374 sdhc@114000 {
375 fsl,iommu-parent = <&pamu1>;
376 fsl,liodn-reg = <&guts 0x530>; /* eSDHCLIODNR */
329 sdhci,auto-cmd12; 377 sdhci,auto-cmd12;
330 }; 378 };
331 379
@@ -335,20 +383,37 @@
335/include/ "qoriq-duart-1.dtsi" 383/include/ "qoriq-duart-1.dtsi"
336/include/ "qoriq-gpio-0.dtsi" 384/include/ "qoriq-gpio-0.dtsi"
337/include/ "qoriq-usb2-mph-0.dtsi" 385/include/ "qoriq-usb2-mph-0.dtsi"
338 usb0: usb@210000 { 386 usb0: usb@210000 {
339 compatible = "fsl-usb2-mph-v1.6", "fsl-usb2-mph"; 387 compatible = "fsl-usb2-mph-v1.6", "fsl-usb2-mph";
340 phy_type = "utmi"; 388 phy_type = "utmi";
341 port0; 389 fsl,iommu-parent = <&pamu1>;
342 }; 390 fsl,liodn-reg = <&guts 0x520>; /* USB1LIODNR */
391 port0;
392 };
343 393
344/include/ "qoriq-usb2-dr-0.dtsi" 394/include/ "qoriq-usb2-dr-0.dtsi"
345 usb1: usb@211000 { 395 usb1: usb@211000 {
346 compatible = "fsl-usb2-dr-v1.6", "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr"; 396 compatible = "fsl-usb2-dr-v1.6", "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
347 dr_mode = "host"; 397 fsl,iommu-parent = <&pamu1>;
348 phy_type = "utmi"; 398 fsl,liodn-reg = <&guts 0x524>; /* USB2LIODNR */
349 }; 399 dr_mode = "host";
400 phy_type = "utmi";
401 };
350 402
351/include/ "qoriq-sata2-0.dtsi" 403/include/ "qoriq-sata2-0.dtsi"
404 sata@220000 {
405 fsl,iommu-parent = <&pamu1>;
406 fsl,liodn-reg = <&guts 0x550>; /* SATA1LIODNR */
407 };
408
352/include/ "qoriq-sata2-1.dtsi" 409/include/ "qoriq-sata2-1.dtsi"
410 sata@221000 {
411 fsl,iommu-parent = <&pamu1>;
412 fsl,liodn-reg = <&guts 0x554>; /* SATA2LIODNR */
413 };
414
353/include/ "qoriq-sec4.2-0.dtsi" 415/include/ "qoriq-sec4.2-0.dtsi"
416crypto: crypto@300000 {
417 fsl,iommu-parent = <&pamu1>;
418 };
354}; 419};
diff --git a/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi b/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
index 4f9c9f682ecf..19859ad851eb 100644
--- a/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
@@ -41,13 +41,15 @@
41 41
42/* controller at 0x200000 */ 42/* controller at 0x200000 */
43&pci0 { 43&pci0 {
44 compatible = "fsl,p4080-pcie"; 44 compatible = "fsl,p4080-pcie", "fsl,qoriq-pcie-v2.1";
45 device_type = "pci"; 45 device_type = "pci";
46 #size-cells = <2>; 46 #size-cells = <2>;
47 #address-cells = <3>; 47 #address-cells = <3>;
48 bus-range = <0x0 0xff>; 48 bus-range = <0x0 0xff>;
49 clock-frequency = <33333333>; 49 clock-frequency = <33333333>;
50 interrupts = <16 2 1 15>; 50 interrupts = <16 2 1 15>;
51 fsl,iommu-parent = <&pamu0>;
52 fsl,liodn-reg = <&guts 0x500>; /* PEX1LIODNR */
51 pcie@0 { 53 pcie@0 {
52 reg = <0 0 0 0 0>; 54 reg = <0 0 0 0 0>;
53 #interrupt-cells = <1>; 55 #interrupt-cells = <1>;
@@ -68,13 +70,15 @@
68 70
69/* controller at 0x201000 */ 71/* controller at 0x201000 */
70&pci1 { 72&pci1 {
71 compatible = "fsl,p4080-pcie"; 73 compatible = "fsl,p4080-pcie", "fsl,qoriq-pcie-v2.1";
72 device_type = "pci"; 74 device_type = "pci";
73 #size-cells = <2>; 75 #size-cells = <2>;
74 #address-cells = <3>; 76 #address-cells = <3>;
75 bus-range = <0 0xff>; 77 bus-range = <0 0xff>;
76 clock-frequency = <33333333>; 78 clock-frequency = <33333333>;
77 interrupts = <16 2 1 14>; 79 interrupts = <16 2 1 14>;
80 fsl,iommu-parent = <&pamu0>;
81 fsl,liodn-reg = <&guts 0x504>; /* PEX2LIODNR */
78 pcie@0 { 82 pcie@0 {
79 reg = <0 0 0 0 0>; 83 reg = <0 0 0 0 0>;
80 #interrupt-cells = <1>; 84 #interrupt-cells = <1>;
@@ -95,13 +99,15 @@
95 99
96/* controller at 0x202000 */ 100/* controller at 0x202000 */
97&pci2 { 101&pci2 {
98 compatible = "fsl,p4080-pcie"; 102 compatible = "fsl,p4080-pcie", "fsl,qoriq-pcie-v2.1";
99 device_type = "pci"; 103 device_type = "pci";
100 #size-cells = <2>; 104 #size-cells = <2>;
101 #address-cells = <3>; 105 #address-cells = <3>;
102 bus-range = <0x0 0xff>; 106 bus-range = <0x0 0xff>;
103 clock-frequency = <33333333>; 107 clock-frequency = <33333333>;
104 interrupts = <16 2 1 13>; 108 interrupts = <16 2 1 13>;
109 fsl,iommu-parent = <&pamu0>;
110 fsl,liodn-reg = <&guts 0x508>; /* PEX3LIODNR */
105 pcie@0 { 111 pcie@0 {
106 reg = <0 0 0 0 0>; 112 reg = <0 0 0 0 0>;
107 #interrupt-cells = <1>; 113 #interrupt-cells = <1>;
@@ -126,18 +132,21 @@
126 #address-cells = <2>; 132 #address-cells = <2>;
127 #size-cells = <2>; 133 #size-cells = <2>;
128 fsl,srio-rmu-handle = <&rmu>; 134 fsl,srio-rmu-handle = <&rmu>;
135 fsl,iommu-parent = <&pamu0>;
129 ranges; 136 ranges;
130 137
131 port1 { 138 port1 {
132 #address-cells = <2>; 139 #address-cells = <2>;
133 #size-cells = <2>; 140 #size-cells = <2>;
134 cell-index = <1>; 141 cell-index = <1>;
142 fsl,liodn-reg = <&guts 0x510>; /* RIO1LIODNR */
135 }; 143 };
136 144
137 port2 { 145 port2 {
138 #address-cells = <2>; 146 #address-cells = <2>;
139 #size-cells = <2>; 147 #size-cells = <2>;
140 cell-index = <2>; 148 cell-index = <2>;
149 fsl,liodn-reg = <&guts 0x514>; /* RIO2LIODNR */
141 }; 150 };
142}; 151};
143 152
@@ -281,13 +290,51 @@
281 290
282 iommu@20000 { 291 iommu@20000 {
283 compatible = "fsl,pamu-v1.0", "fsl,pamu"; 292 compatible = "fsl,pamu-v1.0", "fsl,pamu";
284 reg = <0x20000 0x5000>; 293 reg = <0x20000 0x5000>; /* for compatibility with older PAMU drivers */
294 ranges = <0 0x20000 0x5000>;
295 #address-cells = <1>;
296 #size-cells = <1>;
285 interrupts = < 297 interrupts = <
286 24 2 0 0 298 24 2 0 0
287 16 2 1 30>; 299 16 2 1 30>;
300
301 pamu0: pamu@0 {
302 reg = <0 0x1000>;
303 fsl,primary-cache-geometry = <32 1>;
304 fsl,secondary-cache-geometry = <128 2>;
305 };
306
307 pamu1: pamu@1000 {
308 reg = <0x1000 0x1000>;
309 fsl,primary-cache-geometry = <32 1>;
310 fsl,secondary-cache-geometry = <128 2>;
311 };
312
313 pamu2: pamu@2000 {
314 reg = <0x2000 0x1000>;
315 fsl,primary-cache-geometry = <32 1>;
316 fsl,secondary-cache-geometry = <128 2>;
317 };
318
319 pamu3: pamu@3000 {
320 reg = <0x3000 0x1000>;
321 fsl,primary-cache-geometry = <32 1>;
322 fsl,secondary-cache-geometry = <128 2>;
323 };
324
325 pamu4: pamu@4000 {
326 reg = <0x4000 0x1000>;
327 fsl,primary-cache-geometry = <32 1>;
328 fsl,secondary-cache-geometry = <128 2>;
329 };
288 }; 330 };
289 331
290/include/ "qoriq-rmu-0.dtsi" 332/include/ "qoriq-rmu-0.dtsi"
333 rmu@d3000 {
334 fsl,iommu-parent = <&pamu0>;
335 fsl,liodn-reg = <&guts 0x540>; /* RMULIODNR */
336 };
337
291/include/ "qoriq-mpic.dtsi" 338/include/ "qoriq-mpic.dtsi"
292 339
293 guts: global-utilities@e0000 { 340 guts: global-utilities@e0000 {
@@ -327,7 +374,17 @@
327 }; 374 };
328 375
329/include/ "qoriq-dma-0.dtsi" 376/include/ "qoriq-dma-0.dtsi"
377 dma@100300 {
378 fsl,iommu-parent = <&pamu0>;
379 fsl,liodn-reg = <&guts 0x580>; /* DMA1LIODNR */
380 };
381
330/include/ "qoriq-dma-1.dtsi" 382/include/ "qoriq-dma-1.dtsi"
383 dma@101300 {
384 fsl,iommu-parent = <&pamu0>;
385 fsl,liodn-reg = <&guts 0x584>; /* DMA2LIODNR */
386 };
387
331/include/ "qoriq-espi-0.dtsi" 388/include/ "qoriq-espi-0.dtsi"
332 spi@110000 { 389 spi@110000 {
333 fsl,espi-num-chipselects = <4>; 390 fsl,espi-num-chipselects = <4>;
@@ -335,6 +392,8 @@
335 392
336/include/ "qoriq-esdhc-0.dtsi" 393/include/ "qoriq-esdhc-0.dtsi"
337 sdhc@114000 { 394 sdhc@114000 {
395 fsl,iommu-parent = <&pamu1>;
396 fsl,liodn-reg = <&guts 0x530>; /* eSDHCLIODNR */
338 voltage-ranges = <3300 3300>; 397 voltage-ranges = <3300 3300>;
339 sdhci,auto-cmd12; 398 sdhci,auto-cmd12;
340 }; 399 };
@@ -347,11 +406,18 @@
347/include/ "qoriq-usb2-mph-0.dtsi" 406/include/ "qoriq-usb2-mph-0.dtsi"
348 usb@210000 { 407 usb@210000 {
349 compatible = "fsl-usb2-mph-v1.6", "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph"; 408 compatible = "fsl-usb2-mph-v1.6", "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
409 fsl,iommu-parent = <&pamu1>;
410 fsl,liodn-reg = <&guts 0x520>; /* USB1LIODNR */
350 port0; 411 port0;
351 }; 412 };
352/include/ "qoriq-usb2-dr-0.dtsi" 413/include/ "qoriq-usb2-dr-0.dtsi"
353 usb@211000 { 414 usb@211000 {
354 compatible = "fsl-usb2-dr-v1.6", "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr"; 415 compatible = "fsl-usb2-dr-v1.6", "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
416 fsl,iommu-parent = <&pamu1>;
417 fsl,liodn-reg = <&guts 0x524>; /* USB2LIODNR */
355 }; 418 };
356/include/ "qoriq-sec4.0-0.dtsi" 419/include/ "qoriq-sec4.0-0.dtsi"
420crypto: crypto@300000 {
421 fsl,iommu-parent = <&pamu1>;
422 };
357}; 423};
diff --git a/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi b/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
index 5d7205b7bb05..9ea77c3513f6 100644
--- a/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
@@ -48,6 +48,8 @@
48 bus-range = <0x0 0xff>; 48 bus-range = <0x0 0xff>;
49 clock-frequency = <33333333>; 49 clock-frequency = <33333333>;
50 interrupts = <16 2 1 15>; 50 interrupts = <16 2 1 15>;
51 fsl,iommu-parent = <&pamu0>;
52 fsl,liodn-reg = <&guts 0x500>; /* PEX1LIODNR */
51 pcie@0 { 53 pcie@0 {
52 reg = <0 0 0 0 0>; 54 reg = <0 0 0 0 0>;
53 #interrupt-cells = <1>; 55 #interrupt-cells = <1>;
@@ -75,6 +77,8 @@
75 bus-range = <0 0xff>; 77 bus-range = <0 0xff>;
76 clock-frequency = <33333333>; 78 clock-frequency = <33333333>;
77 interrupts = <16 2 1 14>; 79 interrupts = <16 2 1 14>;
80 fsl,iommu-parent = <&pamu0>;
81 fsl,liodn-reg = <&guts 0x504>; /* PEX2LIODNR */
78 pcie@0 { 82 pcie@0 {
79 reg = <0 0 0 0 0>; 83 reg = <0 0 0 0 0>;
80 #interrupt-cells = <1>; 84 #interrupt-cells = <1>;
@@ -102,6 +106,8 @@
102 bus-range = <0x0 0xff>; 106 bus-range = <0x0 0xff>;
103 clock-frequency = <33333333>; 107 clock-frequency = <33333333>;
104 interrupts = <16 2 1 13>; 108 interrupts = <16 2 1 13>;
109 fsl,iommu-parent = <&pamu0>;
110 fsl,liodn-reg = <&guts 0x508>; /* PEX3LIODNR */
105 pcie@0 { 111 pcie@0 {
106 reg = <0 0 0 0 0>; 112 reg = <0 0 0 0 0>;
107 #interrupt-cells = <1>; 113 #interrupt-cells = <1>;
@@ -129,6 +135,8 @@
129 bus-range = <0x0 0xff>; 135 bus-range = <0x0 0xff>;
130 clock-frequency = <33333333>; 136 clock-frequency = <33333333>;
131 interrupts = <16 2 1 12>; 137 interrupts = <16 2 1 12>;
138 fsl,iommu-parent = <&pamu0>;
139 fsl,liodn-reg = <&guts 0x50c>; /* PEX4LIODNR */
132 pcie@0 { 140 pcie@0 {
133 reg = <0 0 0 0 0>; 141 reg = <0 0 0 0 0>;
134 #interrupt-cells = <1>; 142 #interrupt-cells = <1>;
@@ -152,18 +160,21 @@
152 interrupts = <16 2 1 11>; 160 interrupts = <16 2 1 11>;
153 #address-cells = <2>; 161 #address-cells = <2>;
154 #size-cells = <2>; 162 #size-cells = <2>;
163 fsl,iommu-parent = <&pamu0>;
155 ranges; 164 ranges;
156 165
157 port1 { 166 port1 {
158 #address-cells = <2>; 167 #address-cells = <2>;
159 #size-cells = <2>; 168 #size-cells = <2>;
160 cell-index = <1>; 169 cell-index = <1>;
170 fsl,liodn-reg = <&guts 0x510>; /* RIO1LIODNR */
161 }; 171 };
162 172
163 port2 { 173 port2 {
164 #address-cells = <2>; 174 #address-cells = <2>;
165 #size-cells = <2>; 175 #size-cells = <2>;
166 cell-index = <2>; 176 cell-index = <2>;
177 fsl,liodn-reg = <&guts 0x514>; /* RIO2LIODNR */
167 }; 178 };
168}; 179};
169 180
@@ -276,10 +287,37 @@
276 287
277 iommu@20000 { 288 iommu@20000 {
278 compatible = "fsl,pamu-v1.0", "fsl,pamu"; 289 compatible = "fsl,pamu-v1.0", "fsl,pamu";
279 reg = <0x20000 0x4000>; 290 reg = <0x20000 0x4000>; /* for compatibility with older PAMU drivers */
291 ranges = <0 0x20000 0x4000>;
292 #address-cells = <1>;
293 #size-cells = <1>;
280 interrupts = < 294 interrupts = <
281 24 2 0 0 295 24 2 0 0
282 16 2 1 30>; 296 16 2 1 30>;
297
298 pamu0: pamu@0 {
299 reg = <0 0x1000>;
300 fsl,primary-cache-geometry = <32 1>;
301 fsl,secondary-cache-geometry = <128 2>;
302 };
303
304 pamu1: pamu@1000 {
305 reg = <0x1000 0x1000>;
306 fsl,primary-cache-geometry = <32 1>;
307 fsl,secondary-cache-geometry = <128 2>;
308 };
309
310 pamu2: pamu@2000 {
311 reg = <0x2000 0x1000>;
312 fsl,primary-cache-geometry = <32 1>;
313 fsl,secondary-cache-geometry = <128 2>;
314 };
315
316 pamu3: pamu@3000 {
317 reg = <0x3000 0x1000>;
318 fsl,primary-cache-geometry = <32 1>;
319 fsl,secondary-cache-geometry = <128 2>;
320 };
283 }; 321 };
284 322
285/include/ "qoriq-mpic.dtsi" 323/include/ "qoriq-mpic.dtsi"
@@ -321,7 +359,17 @@
321 }; 359 };
322 360
323/include/ "qoriq-dma-0.dtsi" 361/include/ "qoriq-dma-0.dtsi"
362 dma@100300 {
363 fsl,iommu-parent = <&pamu0>;
364 fsl,liodn-reg = <&guts 0x580>; /* DMA1LIODNR */
365 };
366
324/include/ "qoriq-dma-1.dtsi" 367/include/ "qoriq-dma-1.dtsi"
368 dma@101300 {
369 fsl,iommu-parent = <&pamu0>;
370 fsl,liodn-reg = <&guts 0x584>; /* DMA2LIODNR */
371 };
372
325/include/ "qoriq-espi-0.dtsi" 373/include/ "qoriq-espi-0.dtsi"
326 spi@110000 { 374 spi@110000 {
327 fsl,espi-num-chipselects = <4>; 375 fsl,espi-num-chipselects = <4>;
@@ -329,6 +377,8 @@
329 377
330/include/ "qoriq-esdhc-0.dtsi" 378/include/ "qoriq-esdhc-0.dtsi"
331 sdhc@114000 { 379 sdhc@114000 {
380 fsl,iommu-parent = <&pamu1>;
381 fsl,liodn-reg = <&guts 0x530>; /* eSDHCLIODNR */
332 sdhci,auto-cmd12; 382 sdhci,auto-cmd12;
333 }; 383 };
334 384
@@ -338,21 +388,41 @@
338/include/ "qoriq-duart-1.dtsi" 388/include/ "qoriq-duart-1.dtsi"
339/include/ "qoriq-gpio-0.dtsi" 389/include/ "qoriq-gpio-0.dtsi"
340/include/ "qoriq-usb2-mph-0.dtsi" 390/include/ "qoriq-usb2-mph-0.dtsi"
341 usb0: usb@210000 { 391 usb0: usb@210000 {
342 compatible = "fsl-usb2-mph-v1.6", "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph"; 392 compatible = "fsl-usb2-mph-v1.6", "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
343 phy_type = "utmi"; 393 fsl,iommu-parent = <&pamu1>;
344 port0; 394 fsl,liodn-reg = <&guts 0x520>; /* USB1LIODNR */
345 }; 395 phy_type = "utmi";
396 port0;
397 };
346 398
347/include/ "qoriq-usb2-dr-0.dtsi" 399/include/ "qoriq-usb2-dr-0.dtsi"
348 usb1: usb@211000 { 400 usb1: usb@211000 {
349 compatible = "fsl-usb2-dr-v1.6", "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr"; 401 compatible = "fsl-usb2-dr-v1.6", "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
350 dr_mode = "host"; 402 fsl,iommu-parent = <&pamu1>;
351 phy_type = "utmi"; 403 fsl,liodn-reg = <&guts 0x524>; /* USB2LIODNR */
352 }; 404 dr_mode = "host";
405 phy_type = "utmi";
406 };
353 407
354/include/ "qoriq-sata2-0.dtsi" 408/include/ "qoriq-sata2-0.dtsi"
409 sata@220000 {
410 fsl,iommu-parent = <&pamu1>;
411 fsl,liodn-reg = <&guts 0x550>; /* SATA1LIODNR */
412 };
413
355/include/ "qoriq-sata2-1.dtsi" 414/include/ "qoriq-sata2-1.dtsi"
415 sata@221000 {
416 fsl,iommu-parent = <&pamu1>;
417 fsl,liodn-reg = <&guts 0x554>; /* SATA2LIODNR */
418 };
356/include/ "qoriq-sec4.2-0.dtsi" 419/include/ "qoriq-sec4.2-0.dtsi"
420 crypto@300000 {
421 fsl,iommu-parent = <&pamu1>;
422 };
423
357/include/ "qoriq-raid1.0-0.dtsi" 424/include/ "qoriq-raid1.0-0.dtsi"
425 raideng@320000 {
426 fsl,iommu-parent = <&pamu1>;
427 };
358}; 428};
diff --git a/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi b/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
index db2c9a7b3a0e..97f8c26f9709 100644
--- a/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
@@ -48,6 +48,7 @@
48 bus-range = <0x0 0xff>; 48 bus-range = <0x0 0xff>;
49 clock-frequency = <33333333>; 49 clock-frequency = <33333333>;
50 interrupts = <16 2 1 15>; 50 interrupts = <16 2 1 15>;
51 fsl,iommu-parent = <&pamu0>;
51 pcie@0 { 52 pcie@0 {
52 reg = <0 0 0 0 0>; 53 reg = <0 0 0 0 0>;
53 #interrupt-cells = <1>; 54 #interrupt-cells = <1>;
@@ -75,6 +76,7 @@
75 bus-range = <0 0xff>; 76 bus-range = <0 0xff>;
76 clock-frequency = <33333333>; 77 clock-frequency = <33333333>;
77 interrupts = <16 2 1 14>; 78 interrupts = <16 2 1 14>;
79 fsl,iommu-parent = <&pamu0>;
78 pcie@0 { 80 pcie@0 {
79 reg = <0 0 0 0 0>; 81 reg = <0 0 0 0 0>;
80 #interrupt-cells = <1>; 82 #interrupt-cells = <1>;
@@ -102,6 +104,7 @@
102 bus-range = <0x0 0xff>; 104 bus-range = <0x0 0xff>;
103 clock-frequency = <33333333>; 105 clock-frequency = <33333333>;
104 interrupts = <16 2 1 13>; 106 interrupts = <16 2 1 13>;
107 fsl,iommu-parent = <&pamu0>;
105 pcie@0 { 108 pcie@0 {
106 reg = <0 0 0 0 0>; 109 reg = <0 0 0 0 0>;
107 #interrupt-cells = <1>; 110 #interrupt-cells = <1>;
@@ -239,10 +242,42 @@
239 242
240 iommu@20000 { 243 iommu@20000 {
241 compatible = "fsl,pamu-v1.0", "fsl,pamu"; 244 compatible = "fsl,pamu-v1.0", "fsl,pamu";
242 reg = <0x20000 0x5000>; 245 reg = <0x20000 0x5000>; /* for compatibility with older PAMU drivers */
243 interrupts = < 246 ranges = <0 0x20000 0x5000>;
244 24 2 0 0 247 #address-cells = <1>;
245 16 2 1 30>; 248 #size-cells = <1>;
249 interrupts = <24 2 0 0
250 16 2 1 30>;
251
252 pamu0: pamu@0 {
253 reg = <0 0x1000>;
254 fsl,primary-cache-geometry = <32 1>;
255 fsl,secondary-cache-geometry = <128 2>;
256 };
257
258 pamu1: pamu@1000 {
259 reg = <0x1000 0x1000>;
260 fsl,primary-cache-geometry = <32 1>;
261 fsl,secondary-cache-geometry = <128 2>;
262 };
263
264 pamu2: pamu@2000 {
265 reg = <0x2000 0x1000>;
266 fsl,primary-cache-geometry = <32 1>;
267 fsl,secondary-cache-geometry = <128 2>;
268 };
269
270 pamu3: pamu@3000 {
271 reg = <0x3000 0x1000>;
272 fsl,primary-cache-geometry = <32 1>;
273 fsl,secondary-cache-geometry = <128 2>;
274 };
275
276 pamu4: pamu@4000 {
277 reg = <0x4000 0x1000>;
278 fsl,primary-cache-geometry = <32 1>;
279 fsl,secondary-cache-geometry = <128 2>;
280 };
246 }; 281 };
247 282
248/include/ "qoriq-mpic.dtsi" 283/include/ "qoriq-mpic.dtsi"
@@ -284,7 +319,17 @@
284 }; 319 };
285 320
286/include/ "qoriq-dma-0.dtsi" 321/include/ "qoriq-dma-0.dtsi"
322 dma@100300 {
323 fsl,iommu-parent = <&pamu0>;
324 fsl,liodn-reg = <&guts 0x580>; /* DMA1LIODNR */
325 };
326
287/include/ "qoriq-dma-1.dtsi" 327/include/ "qoriq-dma-1.dtsi"
328 dma@101300 {
329 fsl,iommu-parent = <&pamu0>;
330 fsl,liodn-reg = <&guts 0x584>; /* DMA2LIODNR */
331 };
332
288/include/ "qoriq-espi-0.dtsi" 333/include/ "qoriq-espi-0.dtsi"
289 spi@110000 { 334 spi@110000 {
290 fsl,espi-num-chipselects = <4>; 335 fsl,espi-num-chipselects = <4>;
@@ -292,6 +337,8 @@
292 337
293/include/ "qoriq-esdhc-0.dtsi" 338/include/ "qoriq-esdhc-0.dtsi"
294 sdhc@114000 { 339 sdhc@114000 {
340 fsl,iommu-parent = <&pamu2>;
341 fsl,liodn-reg = <&guts 0x530>; /* eSDHCLIODNR */
295 sdhci,auto-cmd12; 342 sdhci,auto-cmd12;
296 }; 343 };
297 344
@@ -301,20 +348,37 @@
301/include/ "qoriq-duart-1.dtsi" 348/include/ "qoriq-duart-1.dtsi"
302/include/ "qoriq-gpio-0.dtsi" 349/include/ "qoriq-gpio-0.dtsi"
303/include/ "qoriq-usb2-mph-0.dtsi" 350/include/ "qoriq-usb2-mph-0.dtsi"
304 usb0: usb@210000 { 351 usb0: usb@210000 {
305 compatible = "fsl-usb2-mph-v1.6", "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph"; 352 compatible = "fsl-usb2-mph-v1.6", "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
306 phy_type = "utmi"; 353 fsl,iommu-parent = <&pamu4>;
307 port0; 354 fsl,liodn-reg = <&guts 0x520>; /* USB1LIODNR */
308 }; 355 phy_type = "utmi";
356 port0;
357 };
309 358
310/include/ "qoriq-usb2-dr-0.dtsi" 359/include/ "qoriq-usb2-dr-0.dtsi"
311 usb1: usb@211000 { 360 usb1: usb@211000 {
312 compatible = "fsl-usb2-dr-v1.6", "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr"; 361 compatible = "fsl-usb2-dr-v1.6", "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
313 dr_mode = "host"; 362 fsl,iommu-parent = <&pamu4>;
314 phy_type = "utmi"; 363 fsl,liodn-reg = <&guts 0x524>; /* USB2LIODNR */
315 }; 364 dr_mode = "host";
365 phy_type = "utmi";
366 };
316 367
317/include/ "qoriq-sata2-0.dtsi" 368/include/ "qoriq-sata2-0.dtsi"
369 sata@220000 {
370 fsl,iommu-parent = <&pamu4>;
371 fsl,liodn-reg = <&guts 0x550>; /* SATA1LIODNR */
372 };
373
318/include/ "qoriq-sata2-1.dtsi" 374/include/ "qoriq-sata2-1.dtsi"
375 sata@221000 {
376 fsl,iommu-parent = <&pamu4>;
377 fsl,liodn-reg = <&guts 0x554>; /* SATA2LIODNR */
378 };
379
319/include/ "qoriq-sec5.2-0.dtsi" 380/include/ "qoriq-sec5.2-0.dtsi"
381 crypto@300000 {
382 fsl,iommu-parent = <&pamu4>;
383 };
320}; 384};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-sec4.4-0.dtsi b/arch/powerpc/boot/dts/fsl/pq3-sec4.4-0.dtsi
index d4c9d5daab21..ffadcb563ada 100644
--- a/arch/powerpc/boot/dts/fsl/pq3-sec4.4-0.dtsi
+++ b/arch/powerpc/boot/dts/fsl/pq3-sec4.4-0.dtsi
@@ -36,6 +36,7 @@ crypto@30000 {
36 compatible = "fsl,sec-v4.4", "fsl,sec-v4.0"; 36 compatible = "fsl,sec-v4.4", "fsl,sec-v4.0";
37 #address-cells = <1>; 37 #address-cells = <1>;
38 #size-cells = <1>; 38 #size-cells = <1>;
39 ranges = <0x0 0x30000 0x10000>;
39 reg = <0x30000 0x10000>; 40 reg = <0x30000 0x10000>;
40 interrupts = <58 2 0 0>; 41 interrupts = <58 2 0 0>;
41 42
diff --git a/arch/powerpc/boot/dts/ppa8548.dts b/arch/powerpc/boot/dts/ppa8548.dts
new file mode 100644
index 000000000000..f97eceed610a
--- /dev/null
+++ b/arch/powerpc/boot/dts/ppa8548.dts
@@ -0,0 +1,166 @@
1/*
2 * PPA8548 Device Tree Source (36-bit address map)
3 * Copyright 2013 Prodrive B.V.
4 *
5 * Based on:
6 * MPC8548 CDS Device Tree Source (36-bit address map)
7 * Copyright 2012 Freescale Semiconductor Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14
15/include/ "fsl/mpc8548si-pre.dtsi"
16
17/ {
18 model = "ppa8548";
19 compatible = "ppa8548";
20 #address-cells = <2>;
21 #size-cells = <2>;
22 interrupt-parent = <&mpic>;
23
24 memory {
25 device_type = "memory";
26 reg = <0 0 0x0 0x40000000>;
27 };
28
29 lbc: localbus@fe0005000 {
30 reg = <0xf 0xe0005000 0 0x1000>;
31 ranges = <0x0 0x0 0xf 0xff800000 0x00800000>;
32 };
33
34 soc: soc8548@fe0000000 {
35 ranges = <0 0xf 0xe0000000 0x100000>;
36 };
37
38 pci0: pci@fe0008000 {
39 /* ppa8548 board doesn't support PCI */
40 status = "disabled";
41 };
42
43 pci1: pci@fe0009000 {
44 /* ppa8548 board doesn't support PCI */
45 status = "disabled";
46 };
47
48 pci2: pcie@fe000a000 {
49 /* ppa8548 board doesn't support PCI */
50 status = "disabled";
51 };
52
53 rio: rapidio@fe00c0000 {
54 reg = <0xf 0xe00c0000 0x0 0x11000>;
55 port1 {
56 ranges = <0x0 0x0 0x0 0x80000000 0x0 0x40000000>;
57 };
58 };
59};
60
61&lbc {
62 nor@0 {
63 #address-cells = <1>;
64 #size-cells = <1>;
65 compatible = "cfi-flash";
66 reg = <0x0 0x0 0x00800000>;
67 bank-width = <2>;
68 device-width = <2>;
69
70 partition@0 {
71 reg = <0x0 0x7A0000>;
72 label = "user";
73 };
74
75 partition@7A0000 {
76 reg = <0x7A0000 0x20000>;
77 label = "env";
78 read-only;
79 };
80
81 partition@7C0000 {
82 reg = <0x7C0000 0x40000>;
83 label = "u-boot";
84 read-only;
85 };
86 };
87};
88
89&soc {
90 i2c@3000 {
91 rtc@6f {
92 compatible = "intersil,isl1208";
93 reg = <0x6f>;
94 };
95 };
96
97 i2c@3100 {
98 };
99
100 /*
101 * Only ethernet controller @25000 and @26000 are used.
102 * Use alias enet2 and enet3 for the remainig controllers,
103 * to stay compatible with mpc8548si-pre.dtsi.
104 */
105 enet2: ethernet@24000 {
106 status = "disabled";
107 };
108
109 mdio@24520 {
110 phy0: ethernet-phy@0 {
111 interrupts = <7 1 0 0>;
112 reg = <0x0>;
113 device_type = "ethernet-phy";
114 };
115 phy1: ethernet-phy@1 {
116 interrupts = <8 1 0 0>;
117 reg = <0x1>;
118 device_type = "ethernet-phy";
119 };
120 tbi0: tbi-phy@11 {
121 reg = <0x11>;
122 device_type = "tbi-phy";
123 };
124 };
125
126 enet0: ethernet@25000 {
127 tbi-handle = <&tbi1>;
128 phy-handle = <&phy0>;
129 };
130
131 mdio@25520 {
132 tbi1: tbi-phy@11 {
133 reg = <0x11>;
134 device_type = "tbi-phy";
135 };
136 };
137
138 enet1: ethernet@26000 {
139 tbi-handle = <&tbi2>;
140 phy-handle = <&phy1>;
141 };
142
143 mdio@26520 {
144 tbi2: tbi-phy@11 {
145 reg = <0x11>;
146 device_type = "tbi-phy";
147 };
148 };
149
150 enet3: ethernet@27000 {
151 status = "disabled";
152 };
153
154 mdio@27520 {
155 tbi3: tbi-phy@11 {
156 reg = <0x11>;
157 device_type = "tbi-phy";
158 };
159 };
160
161 crypto@30000 {
162 status = "disabled";
163 };
164};
165
166/include/ "fsl/mpc8548si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/sbc8548-altflash.dts b/arch/powerpc/boot/dts/sbc8548-altflash.dts
new file mode 100644
index 000000000000..0b38a0defd2c
--- /dev/null
+++ b/arch/powerpc/boot/dts/sbc8548-altflash.dts
@@ -0,0 +1,115 @@
1/*
2 * SBC8548 Device Tree Source
3 *
4 * Configured for booting off the alternate (64MB SODIMM) flash.
5 * Requires switching JP12 jumpers and changing SW2.8 setting.
6 *
7 * Copyright 2013 Wind River Systems Inc.
8 *
9 * Paul Gortmaker (see MAINTAINERS for contact information)
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 */
16
17
18/dts-v1/;
19
20/include/ "sbc8548-pre.dtsi"
21
22/{
23 localbus@e0000000 {
24 #address-cells = <2>;
25 #size-cells = <1>;
26 compatible = "simple-bus";
27 reg = <0xe0000000 0x5000>;
28 interrupt-parent = <&mpic>;
29
30 ranges = <0x0 0x0 0xfc000000 0x04000000 /*64MB Flash*/
31 0x3 0x0 0xf0000000 0x04000000 /*64MB SDRAM*/
32 0x4 0x0 0xf4000000 0x04000000 /*64MB SDRAM*/
33 0x5 0x0 0xf8000000 0x00b10000 /* EPLD */
34 0x6 0x0 0xef800000 0x00800000>; /*8MB Flash*/
35
36 flash@0,0 {
37 #address-cells = <1>;
38 #size-cells = <1>;
39 reg = <0x0 0x0 0x04000000>;
40 compatible = "intel,JS28F128", "cfi-flash";
41 bank-width = <4>;
42 device-width = <1>;
43 partition@0x0 {
44 label = "space";
45 /* FC000000 -> FFEFFFFF */
46 reg = <0x00000000 0x03f00000>;
47 };
48 partition@0x03f00000 {
49 label = "bootloader";
50 /* FFF00000 -> FFFFFFFF */
51 reg = <0x03f00000 0x00100000>;
52 read-only;
53 };
54 };
55
56
57 epld@5,0 {
58 compatible = "wrs,epld-localbus";
59 #address-cells = <2>;
60 #size-cells = <1>;
61 reg = <0x5 0x0 0x00b10000>;
62 ranges = <
63 0x0 0x0 0x5 0x000000 0x1fff /* LED */
64 0x1 0x0 0x5 0x100000 0x1fff /* Switches */
65 0x3 0x0 0x5 0x300000 0x1fff /* HW Rev. */
66 0xb 0x0 0x5 0xb00000 0x1fff /* EEPROM */
67 >;
68
69 led@0,0 {
70 compatible = "led";
71 reg = <0x0 0x0 0x1fff>;
72 };
73
74 switches@1,0 {
75 compatible = "switches";
76 reg = <0x1 0x0 0x1fff>;
77 };
78
79 hw-rev@3,0 {
80 compatible = "hw-rev";
81 reg = <0x3 0x0 0x1fff>;
82 };
83
84 eeprom@b,0 {
85 compatible = "eeprom";
86 reg = <0xb 0 0x1fff>;
87 };
88
89 };
90
91 alt-flash@6,0 {
92 #address-cells = <1>;
93 #size-cells = <1>;
94 compatible = "intel,JS28F640", "cfi-flash";
95 reg = <0x6 0x0 0x800000>;
96 bank-width = <1>;
97 device-width = <1>;
98 partition@0x0 {
99 label = "space";
100 /* EF800000 -> EFF9FFFF */
101 reg = <0x00000000 0x007a0000>;
102 };
103 partition@0x7a0000 {
104 label = "bootloader";
105 /* EFFA0000 -> EFFFFFFF */
106 reg = <0x007a0000 0x00060000>;
107 read-only;
108 };
109 };
110
111
112 };
113};
114
115/include/ "sbc8548-post.dtsi"
diff --git a/arch/powerpc/boot/dts/sbc8548-post.dtsi b/arch/powerpc/boot/dts/sbc8548-post.dtsi
new file mode 100644
index 000000000000..33a47e27a11e
--- /dev/null
+++ b/arch/powerpc/boot/dts/sbc8548-post.dtsi
@@ -0,0 +1,295 @@
1/*
2 * SBC8548 Device Tree Source
3 *
4 * Copyright 2007 Wind River Systems Inc.
5 *
6 * Paul Gortmaker (see MAINTAINERS for contact information)
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14/{
15 soc8548@e0000000 {
16 #address-cells = <1>;
17 #size-cells = <1>;
18 device_type = "soc";
19 ranges = <0x00000000 0xe0000000 0x00100000>;
20 bus-frequency = <0>;
21 compatible = "simple-bus";
22
23 ecm-law@0 {
24 compatible = "fsl,ecm-law";
25 reg = <0x0 0x1000>;
26 fsl,num-laws = <10>;
27 };
28
29 ecm@1000 {
30 compatible = "fsl,mpc8548-ecm", "fsl,ecm";
31 reg = <0x1000 0x1000>;
32 interrupts = <17 2>;
33 interrupt-parent = <&mpic>;
34 };
35
36 memory-controller@2000 {
37 compatible = "fsl,mpc8548-memory-controller";
38 reg = <0x2000 0x1000>;
39 interrupt-parent = <&mpic>;
40 interrupts = <0x12 0x2>;
41 };
42
43 L2: l2-cache-controller@20000 {
44 compatible = "fsl,mpc8548-l2-cache-controller";
45 reg = <0x20000 0x1000>;
46 cache-line-size = <0x20>; // 32 bytes
47 cache-size = <0x80000>; // L2, 512K
48 interrupt-parent = <&mpic>;
49 interrupts = <0x10 0x2>;
50 };
51
52 i2c@3000 {
53 #address-cells = <1>;
54 #size-cells = <0>;
55 cell-index = <0>;
56 compatible = "fsl-i2c";
57 reg = <0x3000 0x100>;
58 interrupts = <0x2b 0x2>;
59 interrupt-parent = <&mpic>;
60 dfsrr;
61 };
62
63 i2c@3100 {
64 #address-cells = <1>;
65 #size-cells = <0>;
66 cell-index = <1>;
67 compatible = "fsl-i2c";
68 reg = <0x3100 0x100>;
69 interrupts = <0x2b 0x2>;
70 interrupt-parent = <&mpic>;
71 dfsrr;
72 };
73
74 dma@21300 {
75 #address-cells = <1>;
76 #size-cells = <1>;
77 compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma";
78 reg = <0x21300 0x4>;
79 ranges = <0x0 0x21100 0x200>;
80 cell-index = <0>;
81 dma-channel@0 {
82 compatible = "fsl,mpc8548-dma-channel",
83 "fsl,eloplus-dma-channel";
84 reg = <0x0 0x80>;
85 cell-index = <0>;
86 interrupt-parent = <&mpic>;
87 interrupts = <20 2>;
88 };
89 dma-channel@80 {
90 compatible = "fsl,mpc8548-dma-channel",
91 "fsl,eloplus-dma-channel";
92 reg = <0x80 0x80>;
93 cell-index = <1>;
94 interrupt-parent = <&mpic>;
95 interrupts = <21 2>;
96 };
97 dma-channel@100 {
98 compatible = "fsl,mpc8548-dma-channel",
99 "fsl,eloplus-dma-channel";
100 reg = <0x100 0x80>;
101 cell-index = <2>;
102 interrupt-parent = <&mpic>;
103 interrupts = <22 2>;
104 };
105 dma-channel@180 {
106 compatible = "fsl,mpc8548-dma-channel",
107 "fsl,eloplus-dma-channel";
108 reg = <0x180 0x80>;
109 cell-index = <3>;
110 interrupt-parent = <&mpic>;
111 interrupts = <23 2>;
112 };
113 };
114
115 enet0: ethernet@24000 {
116 #address-cells = <1>;
117 #size-cells = <1>;
118 cell-index = <0>;
119 device_type = "network";
120 model = "eTSEC";
121 compatible = "gianfar";
122 reg = <0x24000 0x1000>;
123 ranges = <0x0 0x24000 0x1000>;
124 local-mac-address = [ 00 00 00 00 00 00 ];
125 interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>;
126 interrupt-parent = <&mpic>;
127 tbi-handle = <&tbi0>;
128 phy-handle = <&phy0>;
129
130 mdio@520 {
131 #address-cells = <1>;
132 #size-cells = <0>;
133 compatible = "fsl,gianfar-mdio";
134 reg = <0x520 0x20>;
135
136 phy0: ethernet-phy@19 {
137 interrupt-parent = <&mpic>;
138 interrupts = <0x6 0x1>;
139 reg = <0x19>;
140 device_type = "ethernet-phy";
141 };
142 phy1: ethernet-phy@1a {
143 interrupt-parent = <&mpic>;
144 interrupts = <0x7 0x1>;
145 reg = <0x1a>;
146 device_type = "ethernet-phy";
147 };
148 tbi0: tbi-phy@11 {
149 reg = <0x11>;
150 device_type = "tbi-phy";
151 };
152 };
153 };
154
155 enet1: ethernet@25000 {
156 #address-cells = <1>;
157 #size-cells = <1>;
158 cell-index = <1>;
159 device_type = "network";
160 model = "eTSEC";
161 compatible = "gianfar";
162 reg = <0x25000 0x1000>;
163 ranges = <0x0 0x25000 0x1000>;
164 local-mac-address = [ 00 00 00 00 00 00 ];
165 interrupts = <0x23 0x2 0x24 0x2 0x28 0x2>;
166 interrupt-parent = <&mpic>;
167 tbi-handle = <&tbi1>;
168 phy-handle = <&phy1>;
169
170 mdio@520 {
171 #address-cells = <1>;
172 #size-cells = <0>;
173 compatible = "fsl,gianfar-tbi";
174 reg = <0x520 0x20>;
175
176 tbi1: tbi-phy@11 {
177 reg = <0x11>;
178 device_type = "tbi-phy";
179 };
180 };
181 };
182
183 serial0: serial@4500 {
184 cell-index = <0>;
185 device_type = "serial";
186 compatible = "fsl,ns16550", "ns16550";
187 reg = <0x4500 0x100>; // reg base, size
188 clock-frequency = <0>; // should we fill in in uboot?
189 interrupts = <0x2a 0x2>;
190 interrupt-parent = <&mpic>;
191 };
192
193 serial1: serial@4600 {
194 cell-index = <1>;
195 device_type = "serial";
196 compatible = "fsl,ns16550", "ns16550";
197 reg = <0x4600 0x100>; // reg base, size
198 clock-frequency = <0>; // should we fill in in uboot?
199 interrupts = <0x2a 0x2>;
200 interrupt-parent = <&mpic>;
201 };
202
203 global-utilities@e0000 { //global utilities reg
204 compatible = "fsl,mpc8548-guts";
205 reg = <0xe0000 0x1000>;
206 fsl,has-rstcr;
207 };
208
209 crypto@30000 {
210 compatible = "fsl,sec2.1", "fsl,sec2.0";
211 reg = <0x30000 0x10000>;
212 interrupts = <45 2>;
213 interrupt-parent = <&mpic>;
214 fsl,num-channels = <4>;
215 fsl,channel-fifo-len = <24>;
216 fsl,exec-units-mask = <0xfe>;
217 fsl,descriptor-types-mask = <0x12b0ebf>;
218 };
219
220 mpic: pic@40000 {
221 interrupt-controller;
222 #address-cells = <0>;
223 #interrupt-cells = <2>;
224 reg = <0x40000 0x40000>;
225 compatible = "chrp,open-pic";
226 device_type = "open-pic";
227 };
228 };
229
230 pci0: pci@e0008000 {
231 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
232 interrupt-map = <
233 /* IDSEL 0x01 (PCI-X slot) @66MHz */
234 0x0800 0x0 0x0 0x1 &mpic 0x2 0x1
235 0x0800 0x0 0x0 0x2 &mpic 0x3 0x1
236 0x0800 0x0 0x0 0x3 &mpic 0x4 0x1
237 0x0800 0x0 0x0 0x4 &mpic 0x1 0x1
238
239 /* IDSEL 0x11 (PCI, 3.3V 32bit) @33MHz */
240 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
241 0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
242 0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
243 0x8800 0x0 0x0 0x4 &mpic 0x1 0x1>;
244
245 interrupt-parent = <&mpic>;
246 interrupts = <0x18 0x2>;
247 bus-range = <0 0>;
248 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x10000000
249 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00800000>;
250 clock-frequency = <66000000>;
251 #interrupt-cells = <1>;
252 #size-cells = <2>;
253 #address-cells = <3>;
254 reg = <0xe0008000 0x1000>;
255 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
256 device_type = "pci";
257 };
258
259 pci1: pcie@e000a000 {
260 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
261 interrupt-map = <
262
263 /* IDSEL 0x0 (PEX) */
264 0x0000 0x0 0x0 0x1 &mpic 0x0 0x1
265 0x0000 0x0 0x0 0x2 &mpic 0x1 0x1
266 0x0000 0x0 0x0 0x3 &mpic 0x2 0x1
267 0x0000 0x0 0x0 0x4 &mpic 0x3 0x1>;
268
269 interrupt-parent = <&mpic>;
270 interrupts = <0x1a 0x2>;
271 bus-range = <0x0 0xff>;
272 ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
273 0x01000000 0x0 0x00000000 0xe2800000 0x0 0x08000000>;
274 clock-frequency = <33000000>;
275 #interrupt-cells = <1>;
276 #size-cells = <2>;
277 #address-cells = <3>;
278 reg = <0xe000a000 0x1000>;
279 compatible = "fsl,mpc8548-pcie";
280 device_type = "pci";
281 pcie@0 {
282 reg = <0x0 0x0 0x0 0x0 0x0>;
283 #size-cells = <2>;
284 #address-cells = <3>;
285 device_type = "pci";
286 ranges = <0x02000000 0x0 0xa0000000
287 0x02000000 0x0 0xa0000000
288 0x0 0x10000000
289
290 0x01000000 0x0 0x00000000
291 0x01000000 0x0 0x00000000
292 0x0 0x00800000>;
293 };
294 };
295};
diff --git a/arch/powerpc/boot/dts/sbc8548-pre.dtsi b/arch/powerpc/boot/dts/sbc8548-pre.dtsi
new file mode 100644
index 000000000000..d8c66290c5b4
--- /dev/null
+++ b/arch/powerpc/boot/dts/sbc8548-pre.dtsi
@@ -0,0 +1,52 @@
1/*
2 * SBC8548 Device Tree Source
3 *
4 * Copyright 2007 Wind River Systems Inc.
5 *
6 * Paul Gortmaker (see MAINTAINERS for contact information)
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14/{
15 model = "SBC8548";
16 compatible = "SBC8548";
17 #address-cells = <1>;
18 #size-cells = <1>;
19
20 aliases {
21 ethernet0 = &enet0;
22 ethernet1 = &enet1;
23 serial0 = &serial0;
24 serial1 = &serial1;
25 pci0 = &pci0;
26 pci1 = &pci1;
27 };
28
29 cpus {
30 #address-cells = <1>;
31 #size-cells = <0>;
32
33 PowerPC,8548@0 {
34 device_type = "cpu";
35 reg = <0>;
36 d-cache-line-size = <0x20>; // 32 bytes
37 i-cache-line-size = <0x20>; // 32 bytes
38 d-cache-size = <0x8000>; // L1, 32K
39 i-cache-size = <0x8000>; // L1, 32K
40 timebase-frequency = <0>; // From uboot
41 bus-frequency = <0>;
42 clock-frequency = <0>;
43 next-level-cache = <&L2>;
44 };
45 };
46
47 memory {
48 device_type = "memory";
49 reg = <0x00000000 0x10000000>;
50 };
51
52};
diff --git a/arch/powerpc/boot/dts/sbc8548.dts b/arch/powerpc/boot/dts/sbc8548.dts
index 77be77116c2e..1df2a0955668 100644
--- a/arch/powerpc/boot/dts/sbc8548.dts
+++ b/arch/powerpc/boot/dts/sbc8548.dts
@@ -14,44 +14,9 @@
14 14
15/dts-v1/; 15/dts-v1/;
16 16
17/ { 17/include/ "sbc8548-pre.dtsi"
18 model = "SBC8548";
19 compatible = "SBC8548";
20 #address-cells = <1>;
21 #size-cells = <1>;
22
23 aliases {
24 ethernet0 = &enet0;
25 ethernet1 = &enet1;
26 serial0 = &serial0;
27 serial1 = &serial1;
28 pci0 = &pci0;
29 pci1 = &pci1;
30 };
31
32 cpus {
33 #address-cells = <1>;
34 #size-cells = <0>;
35
36 PowerPC,8548@0 {
37 device_type = "cpu";
38 reg = <0>;
39 d-cache-line-size = <0x20>; // 32 bytes
40 i-cache-line-size = <0x20>; // 32 bytes
41 d-cache-size = <0x8000>; // L1, 32K
42 i-cache-size = <0x8000>; // L1, 32K
43 timebase-frequency = <0>; // From uboot
44 bus-frequency = <0>;
45 clock-frequency = <0>;
46 next-level-cache = <&L2>;
47 };
48 };
49
50 memory {
51 device_type = "memory";
52 reg = <0x00000000 0x10000000>;
53 };
54 18
19/{
55 localbus@e0000000 { 20 localbus@e0000000 {
56 #address-cells = <2>; 21 #address-cells = <2>;
57 #size-cells = <1>; 22 #size-cells = <1>;
@@ -63,23 +28,25 @@
63 0x3 0x0 0xf0000000 0x04000000 /*64MB SDRAM*/ 28 0x3 0x0 0xf0000000 0x04000000 /*64MB SDRAM*/
64 0x4 0x0 0xf4000000 0x04000000 /*64MB SDRAM*/ 29 0x4 0x0 0xf4000000 0x04000000 /*64MB SDRAM*/
65 0x5 0x0 0xf8000000 0x00b10000 /* EPLD */ 30 0x5 0x0 0xf8000000 0x00b10000 /* EPLD */
66 0x6 0x0 0xfb800000 0x04000000>; /*64MB Flash*/ 31 0x6 0x0 0xec000000 0x04000000>; /*64MB Flash*/
67 32
68 33
69 flash@0,0 { 34 flash@0,0 {
70 #address-cells = <1>; 35 #address-cells = <1>;
71 #size-cells = <1>; 36 #size-cells = <1>;
72 compatible = "cfi-flash"; 37 compatible = "intel,JS28F640", "cfi-flash";
73 reg = <0x0 0x0 0x800000>; 38 reg = <0x0 0x0 0x800000>;
74 bank-width = <1>; 39 bank-width = <1>;
75 device-width = <1>; 40 device-width = <1>;
76 partition@0x0 { 41 partition@0x0 {
77 label = "space"; 42 label = "space";
78 reg = <0x00000000 0x00100000>; 43 /* FF800000 -> FFF9FFFF */
44 reg = <0x00000000 0x007a0000>;
79 }; 45 };
80 partition@0x100000 { 46 partition@0x7a0000 {
81 label = "bootloader"; 47 label = "bootloader";
82 reg = <0x00100000 0x00700000>; 48 /* FFFA0000 -> FFFFFFFF */
49 reg = <0x007a0000 0x00060000>;
83 read-only; 50 read-only;
84 }; 51 };
85 }; 52 };
@@ -122,307 +89,22 @@
122 #address-cells = <1>; 89 #address-cells = <1>;
123 #size-cells = <1>; 90 #size-cells = <1>;
124 reg = <0x6 0x0 0x04000000>; 91 reg = <0x6 0x0 0x04000000>;
125 compatible = "cfi-flash"; 92 compatible = "intel,JS28F128", "cfi-flash";
126 bank-width = <4>; 93 bank-width = <4>;
127 device-width = <1>; 94 device-width = <1>;
128 partition@0x0 { 95 partition@0x0 {
96 label = "space";
97 /* EC000000 -> EFEFFFFF */
98 reg = <0x00000000 0x03f00000>;
99 };
100 partition@0x03f00000 {
129 label = "bootloader"; 101 label = "bootloader";
130 reg = <0x00000000 0x00100000>; 102 /* EFF00000 -> EFFFFFFF */
103 reg = <0x03f00000 0x00100000>;
131 read-only; 104 read-only;
132 }; 105 };
133 partition@0x00100000 {
134 label = "file-system";
135 reg = <0x00100000 0x01f00000>;
136 };
137 partition@0x02000000 {
138 label = "boot-config";
139 reg = <0x02000000 0x00100000>;
140 };
141 partition@0x02100000 {
142 label = "space";
143 reg = <0x02100000 0x01f00000>;
144 };
145 }; 106 };
146 }; 107 };
147
148 soc8548@e0000000 {
149 #address-cells = <1>;
150 #size-cells = <1>;
151 device_type = "soc";
152 ranges = <0x00000000 0xe0000000 0x00100000>;
153 bus-frequency = <0>;
154 compatible = "simple-bus";
155
156 ecm-law@0 {
157 compatible = "fsl,ecm-law";
158 reg = <0x0 0x1000>;
159 fsl,num-laws = <10>;
160 };
161
162 ecm@1000 {
163 compatible = "fsl,mpc8548-ecm", "fsl,ecm";
164 reg = <0x1000 0x1000>;
165 interrupts = <17 2>;
166 interrupt-parent = <&mpic>;
167 };
168
169 memory-controller@2000 {
170 compatible = "fsl,mpc8548-memory-controller";
171 reg = <0x2000 0x1000>;
172 interrupt-parent = <&mpic>;
173 interrupts = <0x12 0x2>;
174 };
175
176 L2: l2-cache-controller@20000 {
177 compatible = "fsl,mpc8548-l2-cache-controller";
178 reg = <0x20000 0x1000>;
179 cache-line-size = <0x20>; // 32 bytes
180 cache-size = <0x80000>; // L2, 512K
181 interrupt-parent = <&mpic>;
182 interrupts = <0x10 0x2>;
183 };
184
185 i2c@3000 {
186 #address-cells = <1>;
187 #size-cells = <0>;
188 cell-index = <0>;
189 compatible = "fsl-i2c";
190 reg = <0x3000 0x100>;
191 interrupts = <0x2b 0x2>;
192 interrupt-parent = <&mpic>;
193 dfsrr;
194 };
195
196 i2c@3100 {
197 #address-cells = <1>;
198 #size-cells = <0>;
199 cell-index = <1>;
200 compatible = "fsl-i2c";
201 reg = <0x3100 0x100>;
202 interrupts = <0x2b 0x2>;
203 interrupt-parent = <&mpic>;
204 dfsrr;
205 };
206
207 dma@21300 {
208 #address-cells = <1>;
209 #size-cells = <1>;
210 compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma";
211 reg = <0x21300 0x4>;
212 ranges = <0x0 0x21100 0x200>;
213 cell-index = <0>;
214 dma-channel@0 {
215 compatible = "fsl,mpc8548-dma-channel",
216 "fsl,eloplus-dma-channel";
217 reg = <0x0 0x80>;
218 cell-index = <0>;
219 interrupt-parent = <&mpic>;
220 interrupts = <20 2>;
221 };
222 dma-channel@80 {
223 compatible = "fsl,mpc8548-dma-channel",
224 "fsl,eloplus-dma-channel";
225 reg = <0x80 0x80>;
226 cell-index = <1>;
227 interrupt-parent = <&mpic>;
228 interrupts = <21 2>;
229 };
230 dma-channel@100 {
231 compatible = "fsl,mpc8548-dma-channel",
232 "fsl,eloplus-dma-channel";
233 reg = <0x100 0x80>;
234 cell-index = <2>;
235 interrupt-parent = <&mpic>;
236 interrupts = <22 2>;
237 };
238 dma-channel@180 {
239 compatible = "fsl,mpc8548-dma-channel",
240 "fsl,eloplus-dma-channel";
241 reg = <0x180 0x80>;
242 cell-index = <3>;
243 interrupt-parent = <&mpic>;
244 interrupts = <23 2>;
245 };
246 };
247
248 enet0: ethernet@24000 {
249 #address-cells = <1>;
250 #size-cells = <1>;
251 cell-index = <0>;
252 device_type = "network";
253 model = "eTSEC";
254 compatible = "gianfar";
255 reg = <0x24000 0x1000>;
256 ranges = <0x0 0x24000 0x1000>;
257 local-mac-address = [ 00 00 00 00 00 00 ];
258 interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>;
259 interrupt-parent = <&mpic>;
260 tbi-handle = <&tbi0>;
261 phy-handle = <&phy0>;
262
263 mdio@520 {
264 #address-cells = <1>;
265 #size-cells = <0>;
266 compatible = "fsl,gianfar-mdio";
267 reg = <0x520 0x20>;
268
269 phy0: ethernet-phy@19 {
270 interrupt-parent = <&mpic>;
271 interrupts = <0x6 0x1>;
272 reg = <0x19>;
273 device_type = "ethernet-phy";
274 };
275 phy1: ethernet-phy@1a {
276 interrupt-parent = <&mpic>;
277 interrupts = <0x7 0x1>;
278 reg = <0x1a>;
279 device_type = "ethernet-phy";
280 };
281 tbi0: tbi-phy@11 {
282 reg = <0x11>;
283 device_type = "tbi-phy";
284 };
285 };
286 };
287
288 enet1: ethernet@25000 {
289 #address-cells = <1>;
290 #size-cells = <1>;
291 cell-index = <1>;
292 device_type = "network";
293 model = "eTSEC";
294 compatible = "gianfar";
295 reg = <0x25000 0x1000>;
296 ranges = <0x0 0x25000 0x1000>;
297 local-mac-address = [ 00 00 00 00 00 00 ];
298 interrupts = <0x23 0x2 0x24 0x2 0x28 0x2>;
299 interrupt-parent = <&mpic>;
300 tbi-handle = <&tbi1>;
301 phy-handle = <&phy1>;
302
303 mdio@520 {
304 #address-cells = <1>;
305 #size-cells = <0>;
306 compatible = "fsl,gianfar-tbi";
307 reg = <0x520 0x20>;
308
309 tbi1: tbi-phy@11 {
310 reg = <0x11>;
311 device_type = "tbi-phy";
312 };
313 };
314 };
315
316 serial0: serial@4500 {
317 cell-index = <0>;
318 device_type = "serial";
319 compatible = "fsl,ns16550", "ns16550";
320 reg = <0x4500 0x100>; // reg base, size
321 clock-frequency = <0>; // should we fill in in uboot?
322 interrupts = <0x2a 0x2>;
323 interrupt-parent = <&mpic>;
324 };
325
326 serial1: serial@4600 {
327 cell-index = <1>;
328 device_type = "serial";
329 compatible = "fsl,ns16550", "ns16550";
330 reg = <0x4600 0x100>; // reg base, size
331 clock-frequency = <0>; // should we fill in in uboot?
332 interrupts = <0x2a 0x2>;
333 interrupt-parent = <&mpic>;
334 };
335
336 global-utilities@e0000 { //global utilities reg
337 compatible = "fsl,mpc8548-guts";
338 reg = <0xe0000 0x1000>;
339 fsl,has-rstcr;
340 };
341
342 crypto@30000 {
343 compatible = "fsl,sec2.1", "fsl,sec2.0";
344 reg = <0x30000 0x10000>;
345 interrupts = <45 2>;
346 interrupt-parent = <&mpic>;
347 fsl,num-channels = <4>;
348 fsl,channel-fifo-len = <24>;
349 fsl,exec-units-mask = <0xfe>;
350 fsl,descriptor-types-mask = <0x12b0ebf>;
351 };
352
353 mpic: pic@40000 {
354 interrupt-controller;
355 #address-cells = <0>;
356 #interrupt-cells = <2>;
357 reg = <0x40000 0x40000>;
358 compatible = "chrp,open-pic";
359 device_type = "open-pic";
360 };
361 };
362
363 pci0: pci@e0008000 {
364 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
365 interrupt-map = <
366 /* IDSEL 0x01 (PCI-X slot) @66MHz */
367 0x0800 0x0 0x0 0x1 &mpic 0x2 0x1
368 0x0800 0x0 0x0 0x2 &mpic 0x3 0x1
369 0x0800 0x0 0x0 0x3 &mpic 0x4 0x1
370 0x0800 0x0 0x0 0x4 &mpic 0x1 0x1
371
372 /* IDSEL 0x11 (PCI, 3.3V 32bit) @33MHz */
373 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
374 0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
375 0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
376 0x8800 0x0 0x0 0x4 &mpic 0x1 0x1>;
377
378 interrupt-parent = <&mpic>;
379 interrupts = <0x18 0x2>;
380 bus-range = <0 0>;
381 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x10000000
382 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00800000>;
383 clock-frequency = <66000000>;
384 #interrupt-cells = <1>;
385 #size-cells = <2>;
386 #address-cells = <3>;
387 reg = <0xe0008000 0x1000>;
388 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
389 device_type = "pci";
390 };
391
392 pci1: pcie@e000a000 {
393 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
394 interrupt-map = <
395
396 /* IDSEL 0x0 (PEX) */
397 0x0000 0x0 0x0 0x1 &mpic 0x0 0x1
398 0x0000 0x0 0x0 0x2 &mpic 0x1 0x1
399 0x0000 0x0 0x0 0x3 &mpic 0x2 0x1
400 0x0000 0x0 0x0 0x4 &mpic 0x3 0x1>;
401
402 interrupt-parent = <&mpic>;
403 interrupts = <0x1a 0x2>;
404 bus-range = <0x0 0xff>;
405 ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
406 0x01000000 0x0 0x00000000 0xe2800000 0x0 0x08000000>;
407 clock-frequency = <33000000>;
408 #interrupt-cells = <1>;
409 #size-cells = <2>;
410 #address-cells = <3>;
411 reg = <0xe000a000 0x1000>;
412 compatible = "fsl,mpc8548-pcie";
413 device_type = "pci";
414 pcie@0 {
415 reg = <0x0 0x0 0x0 0x0 0x0>;
416 #size-cells = <2>;
417 #address-cells = <3>;
418 device_type = "pci";
419 ranges = <0x02000000 0x0 0xa0000000
420 0x02000000 0x0 0xa0000000
421 0x0 0x10000000
422
423 0x01000000 0x0 0x00000000
424 0x01000000 0x0 0x00000000
425 0x0 0x00800000>;
426 };
427 };
428}; 108};
109
110/include/ "sbc8548-post.dtsi"
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-05 03:11:52 -0500